JP7611902B2 - Redundancy scheme for multichip stacked devices. - Google Patents

Description

Examples of the present disclosure generally relate to redundancy configurations in multi-chip stacked devices that include stacked chips.

In some multi-chip devices, field programmable gate array (FPGA) chips may be packaged to form a package, and the chips are placed on a common substrate or interposer. The chips may be mounted side-by-side on the same side of the interposer. The interposer is generally passive (e.g., does not contain active components such as transistors) and contains data paths to couple the chips together.

A manufacturing defect may cause one or more chips to be incorporated into a multi-chip device to be non-functional. In the above example of a multi-chip device, the defective chips may be identified and discarded before being attached to the interposer. In developing technologies for multi-chip stacked devices, under some circumstances, defective chips, even if identified, may be incorporated into the multi-chip stacked device, resulting in a lower yield of manufactured multi-chip stacked devices, since defective chips in the multi-chip stacked device may cause the multi-chip stacked device to fail.

Examples described herein relate to redundancy configurations in multi-chip stacked devices. A multi-chip device may be manufactured according to a device specification that includes, for example, each of the chips of the multi-chip device operable to meet the device specification. The multi-chip device may be configurable to be operable according to another device specification, for example, a device specification having fewer but common chips (or portions thereof) that are operable. In such an example, a faulty multi-chip device manufactured according to one specification can be refurbished to operate according to a different specification. Further examples describe techniques for realizing a multi-chip device based on the ability to refurbish faulty devices.

One example described herein is a multi-chip device. A multi-chip device includes a chip stack that includes chips stacked vertically. Adjacent pairs of the chips are directly connected to each other. Two or more of the chips each include a processing integrated circuit. The chip stack is configurable to operate a subset of the functionality of the processing integrated circuits of two or more of the chips when a portion of the processing integrated circuits is defective.

Another example described herein is a method of implementing a device in which a chip stack is configured to operate a subset of the functionality of multiple processing integrated circuits when some of the processing integrated circuits are faulty. The chip stack includes vertically stacked chips. Adjacent pairs of the chips are directly connected to each other. Two or more of the chips each include a respective one of the processing integrated circuits.

Another example described herein is a multi-chip device. The multi-chip device includes a chip stack with chips. Each of the chips includes an integrated circuit. At least one of the chips includes an integrated circuit with a programmable logic region. The chip stack is configurable to operate each of all chips of the chip stack in their entirety and to operate less than all chips of the chip stack in their entirety. When the chip stack is configured to operate less than all chips of the chip stack in their entirety, at least a portion of the programmable logic region of at least one of the chips having an integrated circuit with a programmable logic region is operable. The chip stack is operable to load and operate configuration data, the configuration data being operable in one or more programmable logic regions of the chip stack. The chip stack is configurable to operate the configuration data regardless of which portions of the chips of the chip stack are configured to operate.

Another example described herein is a method of implementing a device. A multi-chip device including a chip stack of chips is tested. Each of the chips includes a processing integrated circuit. The multi-chip device is manufactured according to a first device specification. It is determined whether the multi-chip device is operable according to the first device specification or a second device specification that is different from the first device specification based on testing the multi-chip device. The multi-chip device is programmed to be operable according to one of the first device specification and the second device specification based on the determination.

An additional example described herein is a method of implementing a device. A multi-chip stacked device is manufactured according to a first specification. The first specification includes a first number of chips. The first number of chips includes at least one chip with an integrated circuit with a programmable logic region. The multi-chip stacked device is tested. The multi-chip stacked device is configured to be operable according to the first specification or a second specification. The second specification includes a second number of chips that is less than the first number of chips. The second number of chips includes at least one chip with an integrated circuit with a programmable logic region.

A further example described herein is a method of manufacturing a device. A first target number of multi-chip devices to be realized according to a first specification and a second target number of multi-chip devices to be realized according to a second specification are obtained. A first manufacturing number of multi-chip devices to be manufactured according to the first specification is determined based on the first target number and a first expected yield of manufacturing according to the first specification. An expected rework number of defective multi-chip devices to be manufactured according to the first specification that are reworkable to at least partially realize the second target number is determined. A second manufacturing number of multi-chip devices to be manufactured according to the second specification is determined based on the second target number excluding the rework number and based on a second expected yield of manufacturing according to the second specification. The first manufacturing number of multi-chip devices is manufactured according to the first specification. The second manufacturing number of multi-chip devices is manufactured according to the second specification.

A further example described herein is a method of manufacturing devices. A target number of each of the multi-chip devices to be realized according to different specifications is identified. Iteratively, until each of the target numbers is satisfied, (i) a production number of the multi-chip devices to be manufactured according to the specification having the highest manufacturing cost and the remaining unmet target number of the specifications is determined, and (ii) an expected reproducible number of each of the defective multi-chip devices to be manufactured according to a reproducible specification to at least partially realize and satisfy each of the target numbers of the multi-chip devices of the other specifications of the specifications is determined. Determining the production number is based on the remaining unmet target number and the expected yield of manufacturing according to the specification. Each production number of the multi-chip devices is manufactured according to the specification.

In a manner in which the above features can be understood in detail, a more detailed description of what has been briefly summarized above can be made with reference to exemplary implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings show only typical exemplary implementations and should not be considered as limiting the scope of application thereof.

FIG. 1 illustrates a structure of a multi-chip device, according to some examples. 2 is a flowchart of a method of forming the multi-chip device of FIG. 1 according to some examples. 1 is a schematic diagram of disabling programmable logic regions of chips in a multi-chip device, according to some examples. 1 is a diagram of some example multi-chip device specifications that may enable regeneration schemes according to some examples. 1 is a schematic diagram of disabling sub-regions of a programmable logic region of a multi-chip device in accordance with some examples. 1 is a schematic diagram of disabling sub-regions of a programmable logic region of a multi-chip device in accordance with some examples. 1 is a circuit diagram of an on-chip and between-slivers inter-chip bridge in accordance with some examples. 1 is a flowchart of a method for implementing a multi-chip device according to some examples. 1 is a flowchart of a method for implementing a multi-chip device according to some examples.

For ease of understanding, identical reference numbers have been used, where possible, to designate identical elements common to several figures. It is believed that elements of one example may be beneficially incorporated in other examples.

Various features are described below with reference to the figures. It should be noted that the figures may or may not be drawn to scale, and that elements of similar structure or function are represented by similar reference numerals throughout the figures. It should be noted that the figures are intended only to facilitate the description of the features. The figures are not intended as an exhaustive description or as limitations on the scope of the claims. Furthermore, an illustrated example need not have all aspects or advantages shown. An aspect or advantage described in connection with a particular example is not necessarily limited to that example and may be implemented in other examples, even if not illustrated or explicitly described.

Examples described herein relate to redundancy configurations in multi-chip stacked devices. A multi-chip device may include a stack of chips. A multi-chip device may be manufactured according to a device specification, for example, including each of the chips of the multi-chip device operable to meet the device specification. However, as a result of manufacturing, one or more of the chips of the multi-chip device may become defective, either in whole or in part. A multi-chip device may be configurable to be operable according to another device specification, for example, a device specification having fewer but common chips (or portions thereof) that are operable. In some examples described herein, an entire chip having a defective portion may be disabled by configuring the multi-chip device. In some examples, various portions that have become defective may be disabled while other functioning portions of the chip are configured to operate by configuring the multi-chip device. In some examples, a defective multi-chip device manufactured according to one specification may be refurbished to operate according to a different specification.

Some examples describe techniques for implementing multi-chip devices based on the ability to refurbish faulty devices. As shown, because some multi-chip devices manufactured according to one device specification may be refurbished to operate according to another device specification, the refurbished multi-chip devices that are operable according to the other device specification may reduce the number of multi-chip devices manufactured according to the other device specification. Thus, by reducing the number of multi-chip devices that must be manufactured according to the other device specification, manufacturing costs may be reduced.

Various examples described herein are described in the context of chips of a multi-chip device having a programmable logic region, such as in the case of a field programmable gate array (FPGA). The concepts described herein may be extended to chips of a multi-chip device having any integrated circuit. For example, redundancy may be implemented when multiple chips have processors, memory, or any other circuitry, and may further be application specific integrated circuits (ASICs). As used herein, a "processing integrated circuit" refers to an integrated circuit with circuitry capable of, configured, and/or configurable to process or manipulate data, as opposed to simply memory that stores data, and any circuitry associated with the memory (e.g., memory controller, address decoder, etc.). A processing integrated circuit may include memory in addition to circuitry capable of, configured, and/or configurable to process or manipulate data. Examples of processing integrated circuits include integrated circuits that include programmable logic regions (e.g., FPGAs), processors (e.g., central processing units (CPUs), graphics processing units (GPUs), etc.), ASICs, etc., or combinations thereof.

Figure 1 illustrates the structure of a multi-chip device according to some examples. The multi-chip device illustrated in Figure 1 is intended to facilitate the explanation and understanding of various example aspects described herein. Various other multi-chip devices may have different structures, different numbers of chips, additional components, etc.

The multi-chip device includes a first chip 102, a second chip 104, a third chip 106, and a fourth chip 108. Typically, the chips 102-108 are stacked to form a chip stack in the multi-chip device. The chips 102-108 are stacked to form an Active Die-on-Active Die (AoA) device in some examples. In some examples, as described below, more or fewer chips may be included in the chip stack. For example, one or more of the second chip 104 and/or the third chip 106 may be removed from or added to the chip stack.

Each of the chips 102-108 includes a semiconductor substrate 112 and a front-side dielectric layer 114 on the front side of the respective semiconductor substrate 112. The front-side dielectric layer 114 includes metallization (e.g., metal lines and/or vias) (illustrated but not specifically numbered) formed therein to electrically connect various components within an integrated circuit. Each of the chips 102-106 includes a back-side dielectric layer 116 on the back side of the respective semiconductor substrate 112. The back-side dielectric layer 116 includes metallization (e.g., metal lines and/or vias) (illustrated but not specifically numbered) formed therein to electrically connect various components within an integrated circuit. Each of the semiconductor substrates 112 of the chips 102-108 includes, for example, a transistor 118 formed on and/or in the front surface of the respective semiconductor substrate 112. The transistor 118 and any other components may be connected to the metallization in the front-side dielectric layer 114. Each semiconductor substrate 112 of each chip 102-106 has a through-substrate via (TSV) 120 extending therethrough, which can electrically connect the metallization in the front dielectric layer 114 of each chip 102-106 to the metallization in the back dielectric layer 116.

A front side bond pad 122 is formed in the front side dielectric layer 114 of each of the chips 102-108 at an outer surface distal from the respective semiconductor substrate 112. The front side bond pad 122 is connected to a metallization in the respective front side dielectric layer 114. A back side bond pad 124 is formed in the back side dielectric layer 116 of each of the chips 104, 106 at an outer surface distal from the respective semiconductor substrate 112. The back side bond pad 124 is connected to a metallization in the respective back side dielectric layer 116.

The chips 102-108 are bonded together (e.g., by hybrid bonding using metal-to-metal and oxide-to-oxide bonds). The first chip 102 is bonded to the second chip 104 front-to-side such that the front bond pads 122 and outer surface of the front dielectric layer 114 of the first chip 102 are bonded to the front bond pads 122 and outer surface of the front dielectric layer 114 of the second chip 104. The second chip 104 is bonded to the third chip 106 back-to-front such that the back bond pads 124 and outer surface of the back dielectric layer 116 of the second chip 104 are bonded to the front bond pads 122 and outer surface of the front dielectric layer 114 of the third chip 106. The third chip 106 is bonded to the fourth chip 108 between its backside and frontside such that the backside bond pads 124 and outer surface of the backside dielectric layer 116 of the third chip 106 are bonded to the frontside bond pads 122 and outer surface of the frontside dielectric layer 114 of the fourth chip 108.

Other arrangements of coupling may be implemented. In other examples, the chips 102-108 may be attached to one another using external connectors (mini-bumps, solder, etc.). In some examples, some of the chips 102-108 may be attached to one another by external connectors, while other chips may be coupled to one another without the use of external connectors. Any permutation of coupling and the use of external connectors may be implemented.

Outer connector bond pads 126 (e.g., aluminum pads) are formed in the backside dielectric layer 116 of the chip 102 at an outer surface distal from the semiconductor substrate 112 of the chip 102. The outer connector bond pads 126 are connected to metallization in the backside dielectric layer 116 of the chip 102. A passivation layer 128 is formed on the outer surface distal from the semiconductor substrate 112 of the chip 102 with respective openings therethrough exposing the outer connector bond pads 126. An external connector 130 (e.g., controlled collapse chip connection (C4), mini-bumps, etc.) is formed on each outer connector bond pad 126 through an opening in the passivation layer 128.

The external connector 130 may be attached to a package substrate. The package substrate may be further attached, for example, to a printed circuit board (PCB) to attach the package substrate (and thus the multi-chip device) to the PCB. Various other components may be included in the multi-chip device. For example, an interposer, an encapsulant (such as molding compound, MUF, etc.), etc. may be included in the multi-chip device. Those skilled in the art will readily envision various modifications that may be made to the multi-chip device.

FIG. 2 is a flow chart of a method 200 for forming the multi-chip device of FIG. 1. The process of the method of FIG. 2 is generally described, and one of ordinary skill in the art will readily appreciate that more specific processes may be performed. The more specific processes may follow any semiconductor process for forming integrated circuits on a substrate to be singulated into chips.

At block 202, surface processing of the chips on each substrate (e.g., wafer) is performed. For example, surface processing of each semiconductor substrate 112 (e.g., wafer) may include forming devices (e.g., transistors 118) in and/or on the surface of the semiconductor substrate 112 and forming a front-side dielectric layer 114 having metallization and front-side bond pads 122 on the surface of the semiconductor substrate 112. A plurality of first chips 102 may be formed on the first substrate. A plurality of second chips 104 may be formed on the second substrate. A plurality of third chips 106 may be formed on the third substrate. A plurality of fourth chips 108 may be formed on the fourth substrate.

At block 204, the respective substrates (e.g., the first substrate and the second substrate) of the first chip and the second chip are bonded together, such as by front-side to front-side bonding as shown in FIG. 1. The bonding can be at the substrate (e.g., wafer) level. The bonding can be a hybrid bond, such as bonding the front-side bond pads 122 of the first substrate to the front-side bond pads 122 of the second substrate and bonding the outer surface of the front-side dielectric layer 114 of the first substrate to the outer surface of the front-side dielectric layer 114 of the second substrate.

At block 206, the semiconductor substrate 112 of the second chip (e.g., the semiconductor substrate 112 of the second substrate) is thinned from the backside. The thinning can be by chemical mechanical polishing (CMP) or other suitable process. At block 208, backside processing of the second chip on the second substrate is performed. The backside processing can include forming backside TSVs 120 through the semiconductor substrate 112 of the second substrate and connecting to the metallization in the frontside dielectric layer 114 of the second substrate. The backside processing can further include forming a backside dielectric layer 116 having metallization and backside bond pads 124 on the backside of the semiconductor substrate 112. The metallization in the backside dielectric layer 116 can be connected to the metallization in the frontside dielectric layer 114 of the second substrate through the backside TSVs 120.

At block 210, the respective substrates (e.g., the second substrate and the third substrate) of the second and third chips are bonded together, such as the backside (of the second substrate) to frontside (of the third substrate) bonding shown in FIG. 1. The bonding can be at the substrate (e.g., wafer) level. The bonding can be a hybrid bond, such as bonding the backside bond pads 124 of the second substrate to the frontside bond pads 122 of the third substrate and bonding the outer surface of the backside dielectric layer 116 of the second substrate to the outer surface of the frontside dielectric layer 114 of the third substrate.

In block 212, the semiconductor substrate 112 of the third chip (e.g., the semiconductor substrate 112 of the third substrate) is thinned from the backside, similar to block 206. In block 214, backside processing of the third chip on the third substrate is performed, similar to block 208. In block 216, the respective substrates (e.g., the third substrate and the fourth substrate) of the third chip and the fourth chip are bonded to each other, similar to the bonding of the backside (of the third substrate) and the front side (of the fourth substrate) shown in FIG. 1, similar to block 210.

At block 218, the semiconductor substrate 112 of the first chip (e.g., the semiconductor substrate 112 of the first substrate) is thinned from the backside, similar to block 206. At block 220, backside processing of the first chip on the first substrate is performed, similar to block 208. Backside processing of the first chip may further include forming outer connector bond pads 126, a passivation layer 128, and an external connector 130. At block 222, the bonded substrates are singulated (e.g., by sawing) to separate the individual multi-chip devices formed. Each of the multi-chip devices may be as shown in FIG. 1.

In some examples, multiple of the chips 102-108 have the same integrated circuit (IC) (e.g., the same processing IC) formed on each chip 102-108. Thus, the multiple of the chips 102-108 may in some cases form a larger collective IC than each chip individually, and/or one or more of the chips 102-108 may in some cases be redundant for device refurbishment. For example, if the second chip 104, the third chip 106, and the fourth chip 108 have the same IC, any one or more of the chips may enable a redundant configuration within a multi-chip device. For example, if one of the multiple of the chips 102-108 is faulty, a redundant other one of the multiple of the chips 102-108 may be used or enabled in place of the failed chip, for example, by power gating, switching, and/or configuration data. Furthermore, even if multiple of the chips 102-108 do not have the same ICs, the multi-chip device may be configurable to operate a subset of the functionality of the ICs of the chips 102-108 when any portion of the ICs is defective.

As an example, the first chip 102 can have an interconnect IC, and each of the chips 104-108 can have the same programmable IC. Each of the chips 102-106 can include TSVs that penetrate the semiconductor substrate 112 of each of the chips 102-106 to accommodate signal and power transfer vertically within the chip stack. The interconnect IC on the first chip 102 can distribute and transfer signals and power horizontally and vertically within the chip stack. The interconnect IC can further include various subsystems and can be a system-on-chip (SoC). For example, the interconnect IC can include a processing system that can, among other things, control the configuration or programming of the programmable ICs of the chips 104-108 (e.g., by a controller (e.g., which can include any control logic) of the processing system). In addition, interconnect ICs are being developed for a wide range of applications including network-on-chip (NoC), eXtreme Performance Input/Output (XPIO), multi-gigabit transceiver (MGT), high bandwidth memory (HBM) interfaces, peripheral component interconnect express (PCIe) interfaces, cache coherent interconnect for accelerators (CCIX), and more. It may have input/output blocks (such as digital accelerators interfaces, analog-to-digital converters (ADC), digital-to-analog converters (DAC), etc.), and/or any intellectual property (IP) hard blocks (such as memory controllers (such as double data rate (DDR) memory controllers, high bandwidth memory (HBM) memory controllers, etc.), PCIe blocks, CCIX blocks, Ethernet cores, forward error correction (FEC) blocks, etc.).

The programmable ICs of chips 104-108 may include programmable logic regions. The programmable logic regions may include programmable logic elements including configurable logic blocks (CLBs), look-up tables (LUTs), random access memory blocks (BRAMs), ultraRAMs (URAMs), input/output blocks (IOBs), digital signal processing blocks (DSPs), clock managers, and/or delay-locked loops (DLLs). In some architectures, the programmable logic regions may include columns of programmable logic elements, each column including a single type of programmable logic element (e.g., a column of CLBs, a column of BRAMs, etc.). The programmable logic elements may have one or more associated programmable interconnect elements. For example, in some architectures, the programmable logic regions include columns of programmable interconnect elements associated with and adjacent to each column of programmable logic elements. In such an example, each programmable interconnect element is connected to an associated programmable logic element in an adjacent column, and to adjacent programmable interconnect elements in the same column. The interconnected columns of programmable interconnect elements may form a global routing network within the programmable logic region. In some examples, the programmable ICs may include a controller (having a boot read-only memory (ROM)) and an NoC. The controller reads the ROM to configure each programmable IC in a base configuration, allowing the programmable ICs to receive configuration data, for example, from the interconnect ICs of the first chip 102 for system-level configuration.

According to some examples, if one or more chips, or portions thereof, are defective, the multi-chip device can still be operational by disabling any of the defective chips, or portions thereof, and allowing the remaining chips, or portions thereof, to operate. For example, when multiple chips in a multi-chip device each have a programmable logic region, and when any of the programmable logic regions is defective or faulty, the entire programmable logic region of that chip can be disabled, while the programmable logic regions of the other chips can be operational. In some examples, when multiple chips in a multi-chip device each have a programmable logic region, and when a portion of any of the programmable logic regions is defective or faulty, that portion of the programmable logic region of that chip can be disabled, while the programmable logic regions of the other chips and the remaining portions of the programmable logic regions of that chip can be operational.

3 is a schematic diagram of disabling programmable logic regions of chips in a multi-chip device according to some examples. The first chip 102 includes an interconnect 302. The second chip 104, the third chip 106, and the fourth chip 108 each include programmable logic regions 304-1, 304-2, 304-3 (individually or collectively, programmable logic regions 304). The interconnect 302 includes a controller 303 (e.g., of a processing system) and is communicatively coupled to each of the programmable logic regions 304 by a programming interconnect 306 (e.g., a configuration frame (CFRAME) interconnect). For example, the controller 303 can communicate configuration data to each of the programmable logic regions 304 via the programming interconnect 306. In some examples, each of the chips 102-108, or any subset thereof, can include a controller such that control of communicating configuration data can be distributed throughout the multi-chip device. Each of the chips 102-108 is communicatively connected to an adjacent chip via a connection 308.

In FIG. 3, the programmable logic region 304-2 of the third chip 106 is shown as defective or faulty. In other examples, any of the programmable logic regions 304 may be defective or faulty. After forming the multi-chip device (as in the fabrication in FIG. 2), the multi-chip device may be tested for functionality, for example, to identify whether any of the programmable logic regions 304 are defective or faulty. If a sufficient number of the programmable logic regions 304 are functional (e.g., not defective or faulty), the multi-chip device may be operated to include several functioning programmable logic regions 304. The controller 303 in the first chip 102 may include memory (such as electronic fuses (eFuses)) that may be programmed to indicate which programmable logic regions 304 are functional and/or faulty or faulty. In response, the controller 303 may distribute configuration data to the functioning programmable logic regions 304 via the programming interconnects 306 based on the programmed memory. Additionally, power gating may be implemented using controller 303 to reduce or eliminate power consumption by faulty or defective programmable logic regions 304 and/or corresponding chips. In this example, the entirety of a faulty chip, or the entirety of a chip's faulty programmable logic regions 304, is disabled while the entirety of the functioning programmable logic regions 304 remains operational.

In the context of a programmable logic device (e.g., an FPGA) implemented by a multi-chip device as described, a user design may be implemented in the programmable logic regions 304. Which programmable logic regions 304 are functional or faulty or defective is transparent to the user design. For example, in the situation of FIG. 3, the multi-chip device may implement a user design in two programmable logic regions 304 (e.g., programmable logic regions 304-1, 304-3) as if those two programmable logic regions 304 were adjacent in the chip stack of the multi-chip device (e.g., as if the programmable logic regions 304 were in the second chip 104 and the third chip 106, respectively). The controller 303 of the first chip 102 is configured to distribute configuration data for the programmable logic regions 304 to accommodate the middle faulty programmable logic region 304-2 without the user design being aware of the middle faulty programmable logic region 304-2.

Figure 4 is a representation 400 of some example multi-chip device specifications that may enable some example regeneration schemes. Figure 4 shows four device specifications 402, 404, 406, 408 of a multi-chip device. The device specifications 402-408 are shown in a single plane for ease of illustration, but may be configured in a multi-chip device (although the number of chips may vary) as generally shown in Figure 1.

As shown, the device specifications 402-408 include a base chip 410 that is the same across the different specifications. The base chip 410 can be, for example, the first chip 102 of FIG. 1 and can include, for example, the interconnect 302 and the controller 303 described with respect to FIG. 3. The device specification 402 includes a single fabric chip 412. The fabric chip 412 can be, for example, any of the second chip 104, the third chip 106, and the fourth chip 108 of FIG. 1 and can include, for example, the programmable logic region 304 described with respect to FIG. 3. The device specification 404 includes two fabric chips 414, 416. The fabric chips 414, 416 can be, for example, any of the second chip 104, the third chip 106, and the fourth chip 108 of FIG. 1 and can each include, for example, the programmable logic region 304 described with respect to FIG. 3. The device specification 406 includes three fabric chips 418, 420, 422. The fabric chips 418, 420, 422 can be any of the second chip 104, the third chip 106, and the fourth chip 108 of FIG. 1, and can each include, for example, the programmable logic region 304 described with respect to FIG. 3. The device specification 408 includes one fabric chip 424 and an accelerator chip 426 (e.g., different from the fabric chip 424). The fabric chip 424 can be any of the second chip 104 and the third chip 106 of FIG. 1, and can each include, for example, the programmable logic region 304 described with respect to FIG. 3. The accelerator chip 426 is physically above the fabric chip 424 in the multi-chip device, and can be the third chip 106 or the fourth chip 108 of FIG. 1. The fabric chips 412-424 each have the same integrated circuit.

A multi-chip device manufactured according to a given device specification includes chips of that specification stacked in sequence. For example, a multi-chip device manufactured according to device specification 402 has a first chip (e.g., base chip 410), a second chip (e.g., fabric chip 412) stacked on the first chip, and no other chips. For example, a multi-chip device manufactured according to device specification 404 has a first chip (e.g., base chip 410), a second chip (e.g., fabric chip 414) stacked on the first chip, and a third chip (e.g., fabric chip 416) stacked on the second chip, and no other chips. As a further example, a multi-chip device manufactured according to device specification 406 may have a first chip (e.g., base chip 410), a second chip (e.g., fabric chip 418) stacked on top of the first chip, a third chip (e.g., fabric chip 420) stacked on top of the second chip, a fourth chip (e.g., fabric chip 422) stacked on top of the third chip, and no other chips.

Assume that a multi-chip device is manufactured according to device specification 408 (e.g., in the context of FIG. 1, the first chip 102 is a base chip 410, the second chip 104 is a fabric chip 424, and the third chip 106 is an accelerator chip 426). If the accelerator chip 426 is bad or defective and inoperable, and the base chip 410 and fabric chip 424 are operable, the multi-chip device may implement device specification 402 with a base chip 410 and a single fabric chip 412 (e.g., a single layer of programmable logic region or fabric).

Assume that a multi-chip device is manufactured according to device specification 406 (e.g., in the situation of FIG. 1, the first chip 102 is a base chip 410, and the second chip 104, the third chip 106, and the fourth chip 108 are fabric chips 418, 420, 422, respectively). If one of the fabric chips 418, 420, 422 is bad or defective and not operational, and the base chip 410 and two of the fabric chips 418, 420, 422 are operational, the multi-chip device may implement device specification 404 with the base chip 410 and two fabric chips 414, 416 (e.g., two layers of programmable logic regions or fabric). If two of the fabric chips 418, 420, 422 are bad or failed and not operational, and the base chip 410 and one of the fabric chips 418, 420, 422 are operational, the multi-chip device may implement the device specification 402 with the base chip 410 and a single fabric chip 412 (e.g., a single layer of programmable logic region or fabric).

Assume that a multi-chip device is manufactured according to device specification 404 (e.g., in the situation of FIG. 1, the first chip 102 is a base chip 410, the second chip 104 and the third chip 106 are fabric chips 414, 416, respectively, and there is no fourth chip 108). If one of the fabric chips 414, 416 is bad or defective and not operational, and the other of the base chip 410 and the fabric chips 414, 416 is operational, the multi-chip device may implement device specification 402 with a base chip 410 and a single fabric chip 412 (e.g., a single layer of programmable logic region or fabric).

The above example shows how a multi-chip device manufactured according to one device specification can be realized or operable according to another device specification when a chip is faulty or defective. The multi-chip device can be configured to logically implement the device specifications that the multi-chip device can meet, and the logical configuration is transparent to the user and the user design. For example, if a user design is to be implemented on a multi-chip device that meets device specification 404, it is unknown and transparent to the user design whether the multi-chip device was manufactured according to device specification 404 or according to device specification 406 (one of fabric chips 418, 420, 422 is faulty or defective), and the user design is implemented functionally identically in either case. The logical implementation can be based on configuration data stored in memory in base chip 410, which can determine how a controller in base chip 410 distributes the configuration data to the corresponding fabric chips.

In some examples, the architectures of different multi-chip devices are similar enough that the metrics are substantially identical in terms of connectivity, delay, and power, which may allow multi-chip devices with different physical components (e.g., different numbers of chips) to meet the same device specifications. In some examples, the multi-chip device includes inter-chip connections that allow signals to optionally pass through a chip, e.g., through TSVs, with little delay overhead when the chip is inactive. In some examples, the multi-chip device includes a configuration scheme for optionally sending configuration data to different layers. In some examples, the multi-chip device includes a timing method for adapting to the worst-case delay through any of the possible inter-chip paths.

5 is a schematic diagram of disabling sub-regions of a programmable logic region of a multi-chip device according to some examples. The first chip 102 includes an interconnect 502. The second chip 104, the third chip 106, and the fourth chip 108 each include a programmable logic region 504-1, 504-2, 504-3 (individually or collectively, programmable logic regions 504). The interconnect 502 includes a controller 503 (e.g., of a processing system) communicatively coupled to each of the programmable logic regions 504 by a programming interconnect 506. For example, the controller 503 can communicate configuration data to each of the programmable logic regions 504 via the programming interconnect 506. In some examples, each of the chips 102-108, or any subset thereof, can include a controller such that control of communicating configuration data can be distributed throughout the multi-chip device. Each of chips 102-108 is communicatively connected to adjacent chips via connection 508.

Each of the programmable logic regions 504 includes subregions. Programmable logic region 504-1 includes subregions 504-11, 504-12, 504-13, 504-14. Programmable logic region 504-2 includes subregions 504-21, 504-22, 504-23, 504-24. Programmable logic region 504-3 includes subregions 504-31, 504-32, 504-33, 504-34. The subregions can be physically divided and/or logically divided. The division between the subregions can be based on any number of logical and/or physical boundaries, such as boundaries between different clock domains, boundaries between different voltage domains, boundaries between different types of circuit or logic blocks, etc. In this example, an individual subregion can be disabled when that subregion is faulty and when that subregion is selected not to be an active subregion in the multichip device.

Each sub-region may communicate with other adjacent sub-regions in adjacent chips via connections 508. The connections 508 may be passive connections including, for example, TSVs and metal lines and vias in the front and/or back dielectric layers. Thus, disabling an intervening sub-region may not affect other sub-regions in communicating with each other via connections 508. In some examples, the sub-regions may include separate receiving and driving circuitry for relaying signals via connections 508, which is not affected when a given sub-region is disabled. Thus, in some examples, not all of the circuitry in a disabled sub-region may go unused.

In FIG. 5, sub-areas 504-13, 504-14 of the second chip 104 and sub-area 504-34 of the fourth chip 108 are shown as defective or faulty. In other examples, any of the sub-areas may be defective or faulty. After forming the multi-chip device (as in the fabrication in FIG. 2), the multi-chip device may be tested for functionality, for example, to identify whether any of the sub-areas of the programmable logic region 504 are defective or faulty. If a sufficient number of the sub-areas of the programmable logic region 504 are functional (e.g., not defective or faulty), the multi-chip device may be operational to include some sub-areas of the programmable logic region 504 that are functional. The controller 503 in the first chip 102 may include memory (such as eFuses) that may be programmed to indicate which sub-areas of the programmable logic region 504 are functional and/or faulty or faulty. In response, controller 503 may distribute configuration data to functioning programmable logic region 304 via programming interconnect 506 based on the programmed memory. Additionally, power gating may be implemented using controller 503 to reduce or eliminate power consumption by sub-regions of programmable logic region 504 that are faulty or defective.

In the illustrated example of FIG. 5, the multi-chip device may operate to include, for example, two programmable logic regions 504 that may be distributed across chips 104-108. Any number of sub-regions may function on any of chips 104-108, allowing the multi-chip device to meet device specifications with a higher degree of granularity for sub-regions, as described above with respect to FIG. 4. Those skilled in the art will readily appreciate additional levels of granularity.

In the context of a programmable logic device (e.g., an FPGA) implemented by a multi-chip device as described, a user design may be implemented in the programmable logic region 504. Which sub-regions of the programmable logic region 504 are functional and/or faulty or defective is transparent to the user design. For example, in the situation of FIG. 5, the multi-chip device may implement a user design in eight sub-regions (e.g., using sub-regions 504-11, 504-12, 504-21, 504-22, 504-23, 504-24, 504-31, 504-32) (e.g., equivalent to two complete programmable logic regions 504) as if those sub-regions of the programmable logic region 504 were adjacent in the chip stack of the multi-chip device. In the illustrated example, each half of the programmable logic regions 504-1, 504-3 may be implemented to form a logical layer of the programmable logic region, regardless of the arrangement (logical or physical) of the functional sub-regions. As described, half of programmable logic region 504-1 may include sub-regions 504-11, 504-12, and half of programmable logic region 504-3 may include any two of sub-regions 504-31, 504-32, 504-33. Different numbers of sub-regions may be combined for any given programmable logic region 504 to form a layer of programmable logic region. Controller 503 of first chip 102 is configured to distribute configuration data for sub-regions of programmable logic region 504 to accommodate intermediate faulty sub-regions of programmable logic region 504 without the user design being aware of the intermediate faulty sub-regions of programmable logic region 504.

In the above description of FIG. 5, the sub-regions may be implemented to form an integer number of logical, complete programmable logic regions 504. In other examples, a multi-chip device may implement any combination of partial programmable logic regions 504, for example, without regard to implementing an integer number of logical, complete programmable logic regions 504. For example, in the illustrated example of FIG. 5, a first tier may be implemented as a half tier comprising sub-regions 504-11, 504-12, a second tier may be implemented as a complete tier of programmable logic region 504-2, and a third tier may be implemented as a three-quarter tier comprising sub-regions 504-31, 504-32, 504-33.

6 is a schematic diagram of disabling sub-regions of a programmable logic region of a multi-chip device according to some examples. The first chip 102 includes an interconnect 602. The second chip 104, the third chip 106, and the fourth chip 108 each include a programmable logic region 604-1, 604-2, 604-3 (individually or collectively, programmable logic regions 604). The interconnect 602 includes a controller 603 (e.g., of a processing system) communicatively coupled to each of the programmable logic regions 604 by a programming interconnect 606. For example, the controller 603 can communicate configuration data to each of the programmable logic regions 604 via the programming interconnect 606. In some examples, each of the chips 102-108, or any subset thereof, can include a controller such that control of communicating configuration data can be distributed throughout the multi-chip device. Each of chips 102-108 is communicatively connected to adjacent chips via connection 608.

Each of the programmable logic regions 604 includes subregions. Programmable logic region 604-1 includes subregions 604-11, 604-12, 604-13, 604-14. Programmable logic region 604-2 includes subregions 604-21, 604-22, 604-23, 604-24. Programmable logic region 604-3 includes subregions 604-31, 604-32, 604-33, 604-34. The subregions may be physically divided and/or logically divided. The division between the subregions may be based on any number of logical and/or physical boundaries, such as boundaries between different clock domains, boundaries between different voltage domains, boundaries between different types of circuit or logic blocks, etc.

In this example, an individual sub-region may be disabled when that sub-region is faulty and when that sub-region is selected to not be an active sub-region in the multi-chip device. Sub-regions that logically and/or physically align across chips 104-108 may form a sliver. Each sub-region in a sliver is the same as and/or functionally equivalent to other sub-regions in that sliver. Sub-regions in different slivers may have different circuitry and/or functionality. During operation, one or more sub-regions of a sliver may be disabled. For example, if one sub-region in a sliver is faulty, that sub-region is disabled while other sub-regions in the sliver are enabled and operational. Further, for example, if no sub-regions in a sliver are faulty, any sub-region in the sliver may be selected to be disabled while other sub-regions in the sliver are enabled and operational.

In the illustrated example situation, there are four slivers in the multi-chip device. The first sliver includes sub-areas 604-11, 604-21, 604-31. The second sliver includes sub-areas 604-12, 604-22, 604-32. The third sliver includes sub-areas 604-13, 604-23, 604-33. The fourth sliver includes sub-areas 604-14, 604-24, 604-34. In some examples, the multi-chip device may operate to logically include up to three programmable logic regions (e.g., fabric chips) as long as a sufficient number of sub-areas within each sliver are not faulty. For example, if sub-areas 604-31, 604-13, and 604-14 are faulty and/or disabled, sub-areas 604-11 and 604-21 can operate in a first sliver, sub-areas 604-12 and 604-22 can operate in a second sliver, sub-areas 604-23 and 604-33 can operate in a third sliver, and sub-areas 604-24 and 604-34 can operate in a fourth sliver.

Each sub-region in a sliver may communicate with other sub-regions in that sliver through connections 608. The connections 608 may be passive connections including, for example, TSVs and metal lines and vias in the front and/or back dielectric layers. Thus, disabling an intervening sub-region in a sliver may not affect other sub-regions in that sliver in terms of communicating with each other through connections 608. In some examples, sub-regions in a sliver may include separate receiving and driving circuitry for relaying signals through connections 608, which is not affected when a given sub-region in a sliver is disabled. For example, if sub-region 604-13 is disabled, the driver and receiver circuitry for connection 608 through sub-region 604-13 may still operate such that sub-regions 604-23, 604-33 may communicate through connections 608. Thus, in some examples, not all of the circuitry in a disabled sub-region may go unused.

Chip-to-chip bridges 610 are disposed at the boundaries between the sub-regions, allowing each sub-region to selectively communicate with sub-regions in adjacent slivers. Through the chip-to-chip bridges 610, each sub-region may communicate with another sub-region in the sliver adjacent to the respective sub-region, either in the same chip as the respective sub-region or in a chip adjacent to the chip in which the respective sub-region is disposed. For example, through the chip-to-chip bridge 610, the sub-region 604-22 in the second sliver may communicate with one or more of the sub-regions 604-11, 604-21, 604-31 in the first sliver, and through another chip-to-chip bridge 610, the sub-region 604-22 in the second sliver may communicate with one or more of the sub-regions 604-13, 604-23, 604-33 in the third sliver. In some examples where multiple redundant physical chips are included in a multi-chip device, the chip-to-chip bridges may enable selective communication between sub-regions on a chip where one or more other chips are interposed between the sub-regions.

As an example, assume that sub-areas 604-31, 604-13, and 604-14 are faulty and/or disabled. Sub-areas 604-11, 604-12, 604-23, and 604-24 can communicate through their respective chip-to-chip bridges 610 and can operate as a first logical die. Sub-areas 604-21, 604-22, 604-33, and 604-34 can communicate through their respective chip-to-chip bridges 610 and can operate as a second logical die. Under these circumstances, chips 104-108 operate as a multi-chip device of logical two fabric chips. These features can be extended to multi-chip devices having different numbers of physical chips and logical dies.

Chip-to-chip bridge 610 includes active devices (e.g., including transistors) on the semiconductor substrate of each of the chips, TSVs in the semiconductor substrate, and metallization in the chips. Those skilled in the art will readily appreciate such components that may be implemented in chip-to-chip bridge 610.

In some examples, chip-to-chip bridges, such as chip-to-chip bridge 610 of FIG. 6, may be implemented in the above example of FIG. 5 to provide additional connectivity and/or flexibility. Chip-to-chip bridges may be implemented between sub-regions of programmable logic region 504 in FIG. 5, as shown and described with respect to sub-regions of programmable logic region 604 in FIG. 6.

Figure 7 shows circuit diagrams of chip-to-chip bridges 610-2, 610-4, 610-6 on each of chips 104, 106, 108 and between the first and second slivers, according to some examples. The chip-to-chip bridge 610 shown in Figure 7 is shown as unidirectional (e.g., from the first sliver to the second sliver). Similar circuit diagrams can be additionally implemented to enable bidirectional communication between slivers (e.g., by adding another unidirectional circuit from the second sliver to the first sliver). Those skilled in the art will readily appreciate such additions, and that any number of circuits can be implemented as the chip-to-chip bridge 610 to enable communication.

Each of the chip-to-chip bridges 610-2, 610-4, 610-6 (individually or collectively, the chip-to-chip bridges 610) includes a driver 702, a three-state driver 704, 706, a multiplexer 708, and a driver 710. The input node of the driver 702 is connected to the output nodes of the respective sub-areas 604-11, 604-21, 604-31 on the same chip 104-108 as the chip-to-chip bridge 610 in the first sliver. The output node of the driver 702 is connected to the respective input nodes of the three-state drivers 704, 706 and the multiplexer 708. The respective output nodes of the three-state drivers 704, 706 are connected to a first node 712 and a second node 714, which are further connected to the respective input nodes of the multiplexer 708. The output node of the multiplexer 708 is connected to the input node of the driver 710, which is connected to the input nodes of the respective sub-regions 604-12, 604-22, 604-32 on the same chip 104-108 as the chip-to-chip bridge 610 in the second sliver. In addition, a first node 712 in the chip-to-chip bridge 610 of a chip is connected to a second node 714 in the chip-to-chip bridge 610 of an overlying adjacent chip, for example, via a TSV in one or both chips. For example, the first node 712 in the chip 104 is connected to the second node 714 in the chip 106, and the first node 712 in the chip 106 is connected to the second node 714 in the chip 108.

The three-state drivers 704, 706 are controlled by respective enable signals EN1, EN2. For example, when the enable signals EN1, EN2 are asserted, the signal on the output node of each of the three-state drivers 704, 706 follows or corresponds to the signal at the input node of the three-state driver 704, 706, and when the enable signals are not asserted, the impedance at the output node of each of the three-state drivers 704, 706 is in a high impedance output state. The multiplexer 708 is controlled by a select signal SEL and, in response thereto, outputs the signal input to the multiplexer 708 at one of the input nodes of the multiplexer 708.

To illustrate different configurations of the chip-to-chip bridge 610, different examples showing communication to sub-area 604-22 are described. Those skilled in the art will readily understand how these configurations can be applied to other chip-to-chip bridges 610 and/or to communication between other sub-areas.

In a first example, sub-area 604-11 communicates with sub-area 604-22. In such an example, sub-area 604-12 may be disabled. Sub-area 604-11 outputs a signal (e.g., data) to driver 702 in chip-to-chip bridge 610-2, which outputs the signal to tri-state drivers 704, 706 and multiplexer 708 of chip-to-chip bridge 610-2. An enable signal EN1 in chip-to-chip bridge 610-2 causes tri-state driver 704 in chip-to-chip bridge 610-2 to output a signal to a first node 712 of chip-to-chip bridge 610-2 and therefore to a second node 714 of chip-to-chip bridge 610-4. An enable signal EN2 in chip-to-chip bridge 610-2 causes tri-state driver 706 in chip-to-chip bridge 610-2 to a high impedance output state. The select signal SEL in chip-to-chip bridge 610-2 causes multiplexer 708 in chip-to-chip bridge 610-2 to output a signal to a second node 714 in chip-to-chip bridge 610-2. Because tri-state driver 706 in chip-to-chip bridge 610-2 has a high impedance output state, there can be no signal on second node 714 in chip-to-chip bridge 610-2 or there can be a signal from the underlying chip that can be propagated to subregion 604-12.

Enable signal EN2 in chip-to-chip bridge 610-4 causes tri-state driver 706 in chip-to-chip bridge 610-4 to go to a high impedance output state. Select signal SEL in chip-to-chip bridge 610-4 causes multiplexer 708 in chip-to-chip bridge 610-4 to output a signal to a second node 714 in chip-to-chip bridge 610-4, which is the signal output by sub-area 604-11 via driver 702 and tri-state driver 704 in chip-to-chip bridge 610-2. Thus, the signal output by sub-area 604-11 can propagate to sub-area 604-22.

In a second example, sub-area 604-21 communicates with sub-area 604-22. Sub-area 604-21 outputs a signal (e.g., data) to driver 702 in chip-to-chip bridge 610-4, which outputs the signal to tri-state drivers 704, 706 and multiplexer 708 of chip-to-chip bridge 610-4. A select signal SEL in chip-to-chip bridge 610-4 causes multiplexer 708 in chip-to-chip bridge 610-4 to output the signal from driver 702 in chip-to-chip bridge 610-4. Thus, the signal output by sub-area 604-21 can be propagated to sub-area 604-22. An enable signal EN1, EN2 in chip-to-chip bridge 610-4 can cause tri-state drivers 704, 706 in chip-to-chip bridge 610-4 to go to a high impedance output state. Enable signal EN1 in chip-to-chip bridge 610-2 can place tri-state driver 704 in chip-to-chip bridge 610-2 in a high impedance output state. Enable signal EN2 in chip-to-chip bridge 610-6 can place tri-state driver 706 in chip-to-chip bridge 610-6 in a high impedance output state.

In a third example, sub-area 604-31 communicates with sub-area 604-22. In such an example, sub-area 604-32 may be disabled. Sub-area 604-31 outputs a signal (e.g., data) to driver 702 in chip-to-chip bridge 610-6, which outputs the signal to tri-state drivers 704, 706 and multiplexer 708 of chip-to-chip bridge 610-6. Enable signal EN1 in chip-to-chip bridge 610-6 causes tri-state driver 704 in chip-to-chip bridge 610-6 to a high impedance output state. Enable signal EN2 in chip-to-chip bridge 610-6 causes tri-state driver 706 in chip-to-chip bridge 610-6 to output a signal to second node 714 of chip-to-chip bridge 610-6 and therefore to first node 712 of chip-to-chip bridge 610-4. A select signal SEL in chip-to-chip bridge 610-6 causes a multiplexer 708 in chip-to-chip bridge 610-6 to output a signal to a first node 712 in chip-to-chip bridge 610-6. Because the tri-state driver 704 in chip-to-chip bridge 610-6 has a high impedance output, there can be no signal on the first node 712 in chip-to-chip bridge 610-6 or there can be a signal from an overlying chip that can be propagated to subregion 604-32.

Enable signal EN1 in chip-to-chip bridge 610-4 causes tri-state driver 704 in chip-to-chip bridge 610-4 to go to a high impedance output state. Select signal SEL in chip-to-chip bridge 610-4 causes multiplexer 708 in chip-to-chip bridge 610-4 to output a signal to a first node 712 in chip-to-chip bridge 610-4, which is the signal output by sub-area 604-31 via driver 702 and tri-state driver 706 in chip-to-chip bridge 610-6. Thus, the signal output by sub-area 604-31 can be propagated to sub-area 604-22.

Data for the enable signals EN1, EN2 and the select signal SEL may be stored, for example, in one or more configuration registers, eFuses, and/or other storage on each chip 104-108. The data stored for these signals configures the inter-chip bridge 610 of each chip 104-108. The data may be stored after the multi-chip device is manufactured and tested. The testing may indicate any sub-regions that are faulty. Based on the test results, if a sufficient number of operable sub-regions remain in each sliver, the data may be stored, for example, in configuration registers, eFuses, and/or other storage to configure the inter-chip bridge 610 accordingly to enable communication between the operable sub-regions. For example, the data may be written to the eFuses by blowing the eFuses.

FIG. 8 is a flow chart of a method 800 for implementing a multi-chip device according to some examples. At block 802, the multi-chip device is manufactured according to a device specification. For example, the multi-chip device may be manufactured as described above with respect to FIG. 2.

At block 804, the chips in the multi-chip device are inspected to identify non-functional programmable logic regions or sub-regions. At block 806, the method 800 determines whether sufficient programmable logic regions or sub-regions are operable to meet the device specifications. In some examples, the determination of block 806 first attempts to determine whether the multi-chip device is operable to meet the most stringent device specification, followed by determining whether it is operable to meet successively less stringent device specifications. For example, with reference to FIG. 4, if the multi-chip device is manufactured according to device specification 406, the determination of block 806 first determines whether the multi-chip device is operable to meet device specification 406, and if not, the determination of block 806 determines whether the multi-chip device is operable to meet device specification 404, and if not, the determination of block 806 determines whether the multi-chip device is operable to meet device specification 402. The determination can be by using a programmable logic region level analysis or a sub-region level analysis, as described above.

If it is determined in block 606 that the multi-chip device is operable to meet the device specifications, then in block 808 the multi-chip device is configured to meet the corresponding device specifications. More generally, a multi-chip device (e.g., a chip stack) may be configured to operate a subset of the functionality of the ICs of a chip when any portion of the ICs of the chip is faulty. A multi-chip device may also be configured to operate the entire functionality of the ICs of a chip when no portion of the IC is faulty. A multi-chip device may be configured by programming memory (e.g., eFuses) on any of the chips. For example, the memory may be programmed in a controller of the processing system (e.g., of the first chip 102) to configure operable programmable logic regions and/or sub-regions by controlling the distribution of configuration data in the multi-chip device in response thereto. In some examples, the memory in the chips 104-108 may be programmed to configure chip-to-chip bridges to interconnect sub-regions of the programmable logic regions in the appropriate layers. The configuration of block 808 may disable any bad or failing chips (e.g., the entire chip and/or the entire programmable logic region of the chip) or portions thereof. The configuration of block 808 may enable a functioning chip in its entirety and/or enable a functioning portion of the chip.

If, at block 806, it is determined that the multi-chip device is not operable to meet the device specifications, at block 810, the multi-chip device is discarded or reworked.

Redundancy in the multi-chip device architectures described herein can enable refurbishment. Generally, the more chips in a chip stack of a multi-chip device manufactured according to a device specification, the lower the yield of the multi-chip device that is operable according to the device specification. The additional chips generally introduce additional instances of defects that can reduce yield. The refurbishment scheme is based on the premise that a multi-chip device manufactured with a certain number of chips in the stack can be defective as a result of manufacturing, but can be configured to be operable with fewer chips in the stack.

As an example, a lot of multi-chip devices may be manufactured according to device specification 406 (e.g., having three fabric chips 418, 420, 422). Some multi-chip devices in the lot may be defective and not operable according to device specification 406. However, those multi-chip devices may be able to be configured to be operable according to device specification 404 (e.g., having two fabric chips 414, 416). Furthermore, some defective multi-chip devices manufactured according to device specification 406 may be able to be configured to be operable according to device specification 402 (e.g., having one fabric chip 412). Thus, a multi-chip device manufactured according to device specification 406 that is defective and not operable according to that device specification 406 may be refurbished and configured to operate according to another device specification 402, 404. By considering the possibility of refurbishment of otherwise defective multi-chip devices when planning for manufacturing, fewer multi-chip devices may be manufactured and/or cost savings may be achieved.

Assume that 1000 multi-chip devices operable according to device specification 402 are to be realized, and 1000 multi-chip devices operable according to device specification 404 are to be realized. Assume further that the yield for manufacturing device specification 402 is 90% and the yield for manufacturing device specification 404 is 50%. Assume further that the cost of each chip is 1 arbitrary unit (AU), such that the cost of a multi-chip device manufactured according to device specification 402 is 2 AU, and the cost of a multi-chip device manufactured according to device specification 402 is 3 AU.

If the multi-chip devices operable according to device specification 402 are realized independently of the multi-chip devices operable according to device specification 404, the number of such devices to be manufactured based on the yield is a simple calculation. 1111 multi-chip devices manufactured according to device specification 402 are manufactured to realize 1000 multi-chip devices operable according to device specification 402 (e.g., 1111 x 0.9 = 1000), and 2000 multi-chip devices manufactured according to device specification 404 are manufactured to realize 1000 multi-chip devices operable according to device specification 404 (e.g., 2000 x 0.5 = 1000). This results in a cost of 8222 AU (e.g., 1111 x 2 + 2000 x 3).

If the specification with the greater number of chips, e.g., device specification 404, is considered independently and the specification with the lesser number of chips, e.g., device specification 402 in this example, is considered dependent on the specification with the greater number of chips, the cost can be reduced. As described above, 2000 multi-chip devices manufactured according to device specification 404 are manufactured to realize 1000 multi-chip devices operable according to device specification 404 (e.g., 2000 x 0.5 = 1000). As is evident, the multi-chip devices manufactured according to the specification with the lesser number of chips may not affect the number of multi-chip devices operable according to the specification with the greater number of chips. Assume that 40% of the defective multi-chip devices manufactured according to device specification 404 can be remanufactured to be operable according to device specification 402. 400 of the defective multi-chip devices manufactured according to device specification 404 are remanufactured to be operable according to device specification 402 (e.g., 1000 x 0.4 = 400). This results in an additional 600 multi-chip devices that need to be realized as operable in accordance with device specification 402. Based on yield, 667 multi-chip devices manufactured in accordance with device specification 402 are manufactured to achieve 600 multi-chip devices that are operable in accordance with device specification 402 (e.g., 667 x 0.9 = 600). Under these circumstances, this results in a cost of 7334 AU (e.g., 2000 x 3 + 667 x 2), which is a 10.8% reduction from the 8222 AU described above.

FIG. 9 is a flowchart of a method 900 for implementing a multi-chip device according to some examples. The example method 900 is described in conjunction with device specifications 402, 404, 406, and 408 to provide an illustration of various aspects of the method 900. Other example implementations of the method 900 may use different device specifications. Additionally, although the method 900 may be described below in conjunction with a defect that causes a chip to fail, other implementations may be applied to situations where a defect causes a portion or sub-region of the chip to fail while the remainder of the chip is operational.

Before beginning the description of method 900, various variables are defined to simplify the following description.

T _A is the target number of multi-chip devices that should be implemented and operable according to device specification A.

C _A is the cost of a multi-chip device manufactured according to device specification A.

Y _A is the expected yield of manufacturing according to device specification A.

D _A is the expected number of defective multi-chip devices manufactured according to device specification A (for example, D _A =M _A ×(1−Y _A )).

は、デバイス仕様Ａに従って製造される不良のマルチチップデバイスであって、デバイス仕様Ｂに従って再生され動作可能となるマルチチップデバイスの期待歩留まりである。

is the expected yield of defective multi-chip devices manufactured according to device specification A that are refurbished and made operable according to device specification B.

）。 R _{B |A} is the number of defective devices manufactured according to device specification A that are expected to be refurbished and made operable according to device specification B (e.g.,

).

U _B is the number of multi-chip devices that are expected to remain filled to reach T _B , where U _B =T _B -(M _B xY _B )-Σ _A R _B|A .

M _B is the number of multi-chip devices determined to be manufactured according to device specification B (eg, M _B =U _B /Y _B ).

Each M _A is initialized to 0.

At block 902, a target number of different multi-chip devices to be realized corresponding to the device specifications is identified. As an example, the target numbers are listed below, with the subscript identifying which of the device specifications 402, 404, 406, 408 corresponds to the target number. Initially, _{U_A} is set equal to _{T_A} .
T ₄₀₂ = U ₄₀₂ = 1000
T ₄₀₄ = U ₄₀₄ = 1000
T ₄₀₆ = U ₄₀₆ = 1000
T ₄₀₈ = U ₄₀₈ = 1000

As will become apparent, these targets can be achieved by manufacturing a multi-chip device according to the corresponding device specification, and by manufacturing a multi-chip device according to another device specification and regenerating it so that it is operable according to the corresponding device specification.

At block 904, an expected yield for manufacturing according to the device specifications is identified. For example, the expected yields are listed below:
_Y402 = 90%
_Y404 = 50%
_Y406 = 30%
_Y408 = 40%

At block 906, a number of multi-chip devices to be manufactured according to the highest cost remaining device specification based on the corresponding expected yield that meets the target number to be realized for that device specification is determined. For purposes of example, the costs of manufacturing a multi-chip device are listed below:
_C402 = 2AU
_C404 = 3AU
_C406 = 4AU
C ₄₀₈ = 3.2 AU

In the described method 900, it is assumed that increasing the number of chips generally results in increased cost and decreased yield. In other example implementations, other considerations may be taken into account instead of or in addition to cost to determine in what order to analyze device specifications to determine the number of multi-chip devices to be manufactured for the corresponding device specifications in block 906 and subsequent blocks and iterations.

Under these assumptions, the highest cost device specification remaining in the first instance of block 906 is device specification 406. The number of devices (e.g., identified as M ₄₀₆ ) to be manufactured in accordance with device specification 406 is 3333 (e.g., M ₄₀₆ ×Y ₄₀₆ =U ₄₀₆ ==3333×0.3=1000). Thus, the target number of multi-chip devices to be realized and operational in accordance with device specification 406 can be met by manufacturing 3333 multi-chip devices in accordance with device specification 406.

At block 908, a number of multi-chip devices that are expected to be defective and that can be refurbished to be operational according to another device specification to at least partially meet a target number of multi-chip devices to be realized for the other device specification is determined. Continuing with the example, the expected yield of defective multi-chip devices that should be refurbished and operational according to one device specification but are manufactured according to another specification is listed below:

Note that in this example, any of the defective multi-chip devices manufactured according to device specification 406 cannot be refurbished to be operable according to device specification 408 because such defective multi-chip devices were not manufactured to include accelerator chip 426.

Under the above assumptions and circumstances, through a first pass through blocks 906 and 908, the various determined quantities are summarized as shown below.

At block 910, a determination is made as to whether the target number of distinct multi-chip devices has been met. If not, the method 900 loops back to block 906, where blocks 906 and 908 are performed iteratively until the target number of distinct multi-chip devices has been met. In the illustrated example, the method 900 loops back to block 906 by the operation of block 910 until _U402 = _U404 = _U406 = _U408 = 0. If the determination at block 910 is that the target number of distinct multi-chip devices has been met, then at block 912, distinct multi-chip devices are fabricated based on the determined number of multi-chip devices to be fabricated. In the illustrated example, the determined _M402 , M404, _M406 , and M408 are fabricated according to the respective device specifications 402, ₄₀₄ , 406, _408. Fabrication according to device specifications may be, for example, according to the method 200 of FIG. 2. Any defective multi-chip devices that are to be refurbished to be operable according to another device specification are configured as described with respect to method 800 of FIG.

In the illustrated example, after the first pass of blocks 906 and 908, the target number remains unsatisfied (e.g., U ₄₀₂ , U ₄₀₄ , and U ₄₀₆ are not 0). Therefore, a second iteration of blocks 906 and 908 is performed, with the resulting decisions and assumptions illustrated below. The highest cost specification remaining is the device specification 408.

It should be noted that in this example, any of the faulty multi-chip devices manufactured according to device specification 408 cannot be refurbished to be operable according to device specification 404 because such faulty multi-chip devices were not manufactured to include two fabric chips 414, 416.

In the illustrated example, after the second pass of blocks 906 and 908, the target number remains unsatisfied (e.g., U ₄₀₂ and U ₄₀₄ are not 0). Therefore, a third iteration of blocks 906 and 908 is performed, with the resulting decisions and assumptions illustrated below. The highest cost specification remaining is device specification 404.

In the illustrated example, after the third pass of blocks 906 and 908, the target number remains unsatisfied (e.g., U ₄₀₂ is not 0). Therefore, a fourth iteration of blocks 906 and 908 is performed, with the resulting decisions and assumptions illustrated below. The highest cost specification remaining is the device specification 404.
M ₄₀₂ = U ₄₀₂ / Y ₄₀₂ = 308/0.9 = 342
U ₄₀₂ = T ₄₀₂ - (M ₄₀₂ × Y ₄₀₂ ) - Σ _A R _{402 | A} =
1000-(342×0.9)-(466+150+76)=0
U ₄₀₄ = T ₄₀₄ - (M ₄₀₄ × Y ₄₀₄ ) - Σ _A R _{404 | A} = 1000 - (1534 x 0.5) - (233 + 0) = 0
U ₄₀₆ = T ₄₀₆ - (M ₄₀₆ × Y ₄₀₆ ) - Σ _A R _{406 | A} = 1000 - (3333 × 0.3) - 0 = 0
U ₄₀₈ = T ₄₀₈ - (M ₄₀₈ × Y ₄₀₈ ) - Σ _A R _{408 | A} = 1000 - (2500 × 0.4) - 0 = 0

In the illustrated example, after the fourth pass of blocks 906 and 908, the target number is met and a corresponding number of multi-chip devices are produced that are to be manufactured according to the device specifications, which are listed below.
_M402 = 342
_M404 = 1534
_M406 = 3333
_M408 = 2500

Thus, in the illustrated example, for device specification 408, a target number of multi-chip devices (e.g., 1000) that should be realized and operable according to the specification may be achieved by manufacturing a number (e.g., 2500) of multi-chip devices determined to be manufactured for a given expected manufacturing yield (e.g., 40%). For device specification 406, a target number of multi-chip devices (e.g., 1000) that should be realized and operable according to the specification may be achieved by manufacturing a number (e.g., 3333) of multi-chip devices determined to be manufactured for a given expected manufacturing yield (e.g., 30%). For device specification 404, a target number of multi-chip devices (e.g., 1000) that should be realized and operable according to the specification may be achieved by manufacturing a number (e.g., 1534) of multi-chip devices determined to be manufactured for a given expected manufacturing yield (e.g., 50%) and refurbish a number (e.g., 233) of defective multi-chip devices manufactured according to device specification 406. For device specification 402, a target number of multi-chip devices (e.g., 1000) that should be realized and operational according to the specification can be achieved by manufacturing the number of multi-chip devices (e.g., 342) determined to be manufactured for a given expected manufacturing yield (e.g., 90%) and remanufacturing a number (e.g., 150) of defective multi-chip devices manufactured according to device specification 408, a number (e.g., 466) of defective multi-chip devices manufactured according to device specification 406, and a number (e.g., 76) of defective multi-chip devices manufactured according to device specification 404.

By using the disclosed reconditioning scheme, several manufactured multi-chip devices can be reconditioned. Other examples can have any number of device specifications, can use any reconditioning mechanism, and can have any number of devices to be realized. The above examples are provided to more clearly illustrate the described methods.

An example includes a multi-chip device including a chip stack including vertically stacked chips. Adjacent pairs of the chips are directly connected to each other. The chips include a first chip including a controller and a memory. The chips include two or more second chips above the first chip in the chip stack, each of the two or more second chips including a processing integrated circuit. The chip stack is configurable to operate a subset of the functionality of the processing integrated circuits of the two or more second chips when a portion of the processing integrated circuits is defective. The memory is operable to store configuration information related to operability of the processing integrated circuits. The controller is communicatively coupled to the processing integrated circuits and is operable to deliver configuration data to the processing integrated circuits based on the configuration information for implementing operation of at least the subset of the functionality.

In the above exemplary multi-chip device, each of the processing integrated circuits may include a programmable logic area, and the chip stack may be configurable to operate the entirety of each of the programmable logic areas of fewer than two or more second chips, and to disable the entirety of each of the programmable logic areas of at least one of the two or more second chips.

In the above exemplary multi-chip device, each of the processing integrated circuits may include a programmable logic region, and the chip stack may be configurable to activate any sub-region of the programmable logic region of the two or more second chips and disable any sub-region of the programmable logic region of the two or more second chips. Furthermore, in the above exemplary multi-chip device, the sub-regions of the programmable logic region of the two or more second chips may be arranged as slivers, each of which may include a sub-region of the programmable logic region of each of the two or more second chips. Each of the two or more second chips may include a chip-to-chip bridge, each of which may be connected between sub-regions of the programmable logic region (i) in adjacent slivers and (ii) in adjacent chips or in the same chip.

In the exemplary multi-chip device above, the controller can be operable to load configuration data, and the configuration data can be operable on one or more of the processing integrated circuits. The chip stack can be configurable to operate the configuration data independent of which portions of the processing integrated circuits of the chip stack are configured to operate.

In the exemplary multi-chip device described above, at least one of the processing integrated circuits of the two or more second chips can be different from at least another of the processing integrated circuits of the two or more second chips.

In the above exemplary multi-chip device, two or more of the processing integrated circuits of the two or more second chips are the same processing integrated circuit.

Another example includes a method for implementing a device, in which a chip stack is configured by a controller to operate a subset of the functionality of a plurality of processing integrated circuits when some of the processing integrated circuits are faulty. The chip stack comprises vertically stacked chips. Adjacent pairs of the chips are directly connected to each other. The chips include a first chip and two or more second chips above the first chip. The first chip includes a controller and a memory. Each of the two or more second chips includes a respective one of the processing integrated circuits. The controller configures which one or more portions of the plurality of processing integrated circuits operate the subset of functionality based on configuration information stored in the memory.

In the above exemplary method, configuring the chip stack may include configuring the chip stack to operate the entirety of each of the programmable logic regions of fewer than two or more second chips and to disable the entirety of each of the programmable logic regions of at least one of the two or more second chips, each of the processing integrated circuits including a programmable logic region.

In the above exemplary method, configuring the chip stack may include configuring the chip stack to activate any sub-region of the programmable logic region of the two or more second chips and disable any sub-region of the programmable logic region of the two or more second chips, each of the processing integrated circuits including a programmable logic region. Further, in the above exemplary method, the sub-regions of the programmable logic region of the two or more second chips may be arranged as slivers, each of the slivers including a sub-region of the programmable logic region of each of the two or more second chips. Each of the two or more second chips may include a chip-to-chip bridge, each of the chip-to-chip bridges may be connected between sub-regions of the programmable logic region (i) in adjacent slivers and (ii) in adjacent chips or in the same chip. Configuring the chip stack may include configuring the chip-to-chip bridge.

In the above exemplary method, at least one of the processing integrated circuits of the two or more second chips can be different from at least another of the processing integrated circuits of the two or more second chips.

In the above exemplary method, two or more of the processing integrated circuits of the two or more second chips can be the same processing integrated circuit.

A further example includes a multi-chip device including a chip stack including stacked chips with adjacent pairs of chips bonded together. The chips include a first chip and two or more second chips stacked on the first chip. The first chip includes a controller and a memory. Each of the two or more second chips includes a processing integrated circuit. The memory is operable to store configuration information indicative of a portion of the processing integrated circuit that is defective. The controller is communicatively coupled to the processing integrated circuit and is operable to deliver configuration data to non-defective portions of the processing integrated circuit based on the configuration information for implementing operation of at least a subset of the functionality of the processing integrated circuits of the two or more second chips. The chip stack is configurable to operate a subset of the functionality of the processing integrated circuits of the two or more second chips when a portion of the processing integrated circuit is defective.

In the exemplary multi-chip device above, each of the processing integrated circuits includes a programmable logic region.

Yet a further example is a method of implementing a device. A multi-chip device is tested, the multi-chip device comprising a chip stack of chips. Each of the chips includes a processing integrated circuit. The multi-chip device is manufactured according to a first device specification. It is determined, based on testing the multi-chip device, whether the multi-chip device is operable according to the first device specification or a second device specification different from the first device specification. The multi-chip device is programmed, based on the determination, to be operable according to one of the first device specification and the second device specification.

In the exemplary method described above, programming the multi-chip device includes disabling at least a portion of at least one of the chips.

In the above exemplary method, two or more of the chips may include the same processing integrated circuit with programmable logic regions, and programming the multi-chip device may include configuring the multi-chip device to be operational using the entirety of at least one logical programmable logic region and disabling at least a portion of at least one of the programmable logic regions.

In the above exemplary method, two or more of the chips may include the same processing integrated circuit with a programmable logic region, and programming the multi-chip device may include configuring the multi-chip device to be operational using the entire programmable logic region of at least one of the chips and disabling the entire programmable logic region of at least one of the chips.

In the above exemplary method, two or more of the chips may include the same integrated circuit with a programmable logic area, and programming the multi-chip device may include configuring the multi-chip device to be operational using at least a portion of the programmable logic areas of the two or more chips and disabling at least a portion of the programmable logic area of at least one of the chips that includes the same integrated circuit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various examples. In other implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, depending on the functionality involved, or the blocks may be executed in the reverse order. While the above is directed to certain examples, other and further examples may be devised without departing from the basic scope thereof, the scope of which is determined by the appended claims.

Claims (15)

1. A multi-chip device comprising a chip stack comprising vertically stacked chips,
adjacent pairs of the chips are directly connected to each other;
the chips include a first chip including a controller and a memory;
the chip includes two or more second chips above the first chip in the chip stack, each of the two or more second chips including a processing integrated circuit;
the chip stack is configurable to operate a subset of the functionality of the processing integrated circuits of the two or more second chips when a portion of the processing integrated circuits is faulty;
the memory is operable to store configuration information relating to operability of the processing integrated circuit;
A multi-chip device, wherein the controller is communicatively coupled to the processing integrated circuit and is operable to deliver configuration data to the processing integrated circuit based on the configuration information for implementing operations of at least a subset of the functions. each of said processing integrated circuits includes a programmable logic region;
2. The multi-chip device of claim 1, wherein the chip stack is configurable to operate the entirety of each of the programmable logic regions of fewer than the two or more second chips and to disable the entirety of each of the programmable logic regions of at least one of the two or more second chips. each of said processing integrated circuits includes a programmable logic region;
2. The multi-chip device of claim 1 , wherein the chip stack is configurable to activate any sub-region of the programmable logic region of the two or more second chips and to disable any sub-region of the programmable logic region of the two or more second chips. The multichip device of claim 3, wherein the sub-regions of the programmable logic regions of the two or more second chips are arranged as slivers, each of the slivers including a sub-region of the programmable logic region of each of the two or more second chips, and each of the two or more second chips includes a chip-to-chip bridge, each of the chip-to-chip bridges connecting between sub-regions of the programmable logic regions (i) in adjacent slivers and (ii) in adjacent chips or in the same chip. the controller is operable to load the configuration data, the configuration data being operable on one or more of the processing integrated circuits;
10. The multi-chip device of claim 1, wherein the chip stack is configurable to operate on the configuration data independent of which portions of the processing integrated circuits of the chip stack are configured to operate. The multichip device of claim 1, wherein at least one of the processing integrated circuits of the two or more second chips is different from at least one other of the processing integrated circuits of the two or more second chips. The multichip device of claim 1, wherein two or more of the processing integrated circuits of the two or more second chips are the same processing integrated circuit. 1. A method of realizing a device, the method comprising:
11. A method comprising: configuring a chip stack by a controller to operate a subset of functions of a plurality of processing integrated circuits when some of the processing integrated circuits are faulty, the chip stack comprising vertically stacked chips, adjacent pairs of the chips being directly connected to each other, the chips including a first chip and two or more second chips above the first chip in the chip stack , the first chip including the controller and memory, each of the two or more second chips including a respective one of the processing integrated circuits, the controller being communicatively connected to the plurality of processing integrated circuits and delivering configuration data for configuring which one or more portions of the plurality of processing integrated circuits operate the subset of functions based on configuration information stored in the memory, the configuration information relating to operability of the plurality of processing integrated circuits . The method of claim 8, wherein configuring the chip stack includes configuring the chip stack to operate the entirety of each of a programmable logic area that is fewer than the two or more second chips and to disable the entirety of each of at least one programmable logic area of the two or more second chips, each of the processing integrated circuits including a programmable logic area. The method of claim 8, wherein configuring the chip stack includes configuring the chip stack to operate any sub-regions of the programmable logic regions of the two or more second chips and to disable any sub-regions of the programmable logic regions of the two or more second chips, and each of the processing integrated circuits includes a programmable logic region. 11. The method of claim 10, wherein sub-regions of the programmable logic regions of the two or more second chips are arranged as slivers, each of the slivers including a sub-region of the programmable logic region of each of the two or more second chips, each of the two or more second chips including a chip-to-chip bridge, each of the chip-to-chip bridges being connected between sub-regions of the programmable logic regions (i) in adjacent slivers and (ii) in adjacent chips or within the same chip, and configuring the chip stack includes configuring the chip-to-chip bridge. The method of claim 8, wherein at least one of the processing integrated circuits of the two or more second chips is different from at least one other of the processing integrated circuits of the two or more second chips. The method of claim 8, wherein two or more of the processing integrated circuits of the two or more second chips are the same processing integrated circuit. 1. A multi-chip device comprising a chip stack comprising stacked chips, adjacent pairs of the chips being bonded together, comprising:
the chip includes a first chip and two or more second chips stacked on the first chip;
the first chip includes a controller and a memory;
each of the two or more second chips includes a processing integrated circuit;
the memory is operable to store configuration information indicative of portions of the processing integrated circuit that are faulty;
the controller is communicatively coupled to the processing integrated circuit and is operable to deliver configuration data to non-faulty portions of the processing integrated circuit based on the configuration information for implementing operation of at least a subset of functions of the processing integrated circuit of the two or more second chips;
A multi-chip device, wherein the chip stack is configurable to operate a subset of the functions of the processing integrated circuits of the two or more second chips when a portion of the processing integrated circuits is defective. The multichip device of claim 14, wherein each of the processing integrated circuits includes a programmable logic region.

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