JP7614136B2 - Power Controller - Google Patents

Description

This disclosure relates to a power controller installed on a satellite or the like.

The satellite is equipped with a bus voltage controller.
The bus voltage controller is called a Sequential Shunt Unit (SSU).

To reduce the weight of the bus voltage controller, it is necessary to resolve the issue of heat concentration in specific shunts. Therefore, technology to disperse heat is required.

Patent Document 1 discloses that by employing an interleaved PWM method, heat generation is dispersed and the maximum heat generation is suppressed.
PWM is an abbreviation for Pulse Width Modulation.

Specifically, Patent Document 1 discloses the following:
The switching period of each string and the phase difference provided between the strings satisfy the relationship shown in the following formula.
Tpe = Tph x N
"Tpe" is the switching period of each string.
"Tph" is the phase difference provided between the strings.
"N" is the number of stages of the string.

The switching period in the entire shunt operation is equal to the phase difference Tph.
This distributes the switching losses across each string.

To reduce switching losses during shunt operation, a switching period Tph is set that corresponds to a relatively low frequency.

In this method, the switching period Tph is fixed, and serves as a sampling period in voltage feedback control.
Therefore, the cutoff frequency must be sufficiently lower than the Nyquist frequency for this period.
As a result, a control delay occurs in response to a sudden load change, resulting in poor transient response characteristics.

Patent No. 5987609

In the technology disclosed in Patent Document 1, the control bandwidth decreases in a multi-stage configuration. In other words, the control response speed worsens as the number of stages increases.

The purpose of this disclosure is to provide a power controller that does not deteriorate the control response speed even with a large number of stages.

The power controller of the present disclosure comprises:
a plurality of switch elements connected in parallel to the plurality of power sources, respectively, for shorting the connected power sources among the plurality of power sources when the power sources are in an on state;
A calculation and driving unit that controls the plurality of switch elements;
Equipped with.
The arithmetic and driving unit sets one of the switch elements, the number of which is the same as the number of short-circuit stages, which is the number of power supplies to be short-circuited among the multiple power supplies, to a switching state in which switching between the off state and the on state is repeated, sets the remaining of the switch elements, the number of which is the same as the number of short-circuit stages, to the on state, and sets the remaining of the multiple switch elements to the off state, thereby sequentially changing the switch elements to be set to the switching state.

This disclosure makes it possible to provide a power controller in which the control response speed does not deteriorate even with a large number of stages.

FIG. 1 is a configuration diagram of an artificial satellite 100 according to a first embodiment. FIG. 2 is a configuration diagram of a power controller 11 according to the first embodiment. FIG. 4 is a configuration diagram of a first calculation and driving unit A in the first embodiment. FIG. 4 is a diagram showing a signal relationship according to the first embodiment. FIG. 4 is a diagram showing the waveform of an offset signal Of in the first embodiment. 4 is a diagram showing the relationship between a drive signal AO and a reference voltage Re in the first embodiment. 4 is a table showing the relationship between phase and switch state in the first embodiment.

In the embodiments and drawings, the same or corresponding elements are given the same reference numerals. Explanations of elements given the same reference numerals as previously described elements are omitted or simplified as appropriate. Arrows in the drawings primarily indicate the flow of signals.

Embodiment 1.
The power controller 11 will be described with reference to FIGS.
The power controller 11 is mounted on, for example, a satellite 100 .

＊＊＊Description of configuration and operation＊＊＊
The configuration of an artificial satellite 100 will be described with reference to FIG.
The satellite 100 includes a power controller 11 , a plurality of solar cell arrays SA, a load 15 , and a capacitor bank 16 .
Specifically, the satellite 100 is equipped with three or more solar arrays SA.

The solar cell array SA is an example of a power source.
The load 15 becomes the power source for user equipment such as an antenna and a heater via a power distributor.

The power controller 11 is connected to multiple solar cell arrays SA and shorts out the solar cell arrays SA that generate excess power. A short circuit is also called a shunt.

The configuration of the power controller 11 will be described with reference to Fig. 2. The number of solar cell arrays SA is n, where n is an integer of 3 or more.
The power controller 11 includes a power bus 12 .
The load 15 and the capacitor bank 16 are connected in parallel.
The n solar cell arrays SA are connected in parallel.
Each solar cell array SA is connected in parallel to a load 15 and a capacitor bank 16 via a power bus 12 .
Each solar cell array SA supplies power to a load 15 and a capacitor bank 16 .
Is represents the generated power. The generated power Is is the power generated by the solar cell array SA.
Il represents the load current. The load current Il is the current flowing through the load 15.

The power controller 11 includes n switch elements SW. Specifically, the switch elements SW are field effect transistors (FETs).
The switch element SW is connected in parallel with the solar cell array SA. Specifically, the solar cell array SA is connected to the drain terminal and source terminal of the switch element SW.

The power controller 11 includes n second calculation driving units B. Specifically, the second calculation driving units B are comparators.
The second calculation driver B is connected to the switch element SW. Specifically, the second calculation driver B is connected to the gate terminal of the switch element SW.
The second calculation and driving unit B controls the switch element SW. Specifically, the second calculation and driving unit B sets the switch element SW in an on state, an off state, or a switching state.
When the switch element SW is turned on, the solar cell array SA is short-circuited.
When the switch element SW is turned off, the power generated by the solar cell array SA is supplied.
In the switching state, the switch element SW repeats an operation of switching between an on state and an off state (switching operation) during a switching period.

The power controller 11 includes n backflow prevention elements D. Specifically, the backflow prevention elements D are diodes.
The backflow prevention element D is connected to the power bus 12, the switch element SW, and the solar cell array SA. Specifically, the cathode terminal of the backflow prevention element D is connected to the power bus 12. In addition, the anode terminal of the backflow prevention element D is connected to the solar cell array SA and the drain terminal of the switch element SW.

The power controller 11 includes a first calculation and driving unit A, an error amplifier 13, and an offset signal generating unit 14. The first calculation and driving unit A is a feature of the power controller 11.
The first calculation and driving unit A is connected to n second calculation and driving units B, an error amplifier 13 and an offset signal generating unit 14 .

The error amplifier 13 is connected to a load 15 , a capacitor bank 16 and a first calculation and driving unit A.
The error amplifier 13 generates and outputs an error amplified signal Dr, which will be described later, in response to the bus voltage Vb.

The offset signal generating unit 14 is connected to the first calculation and driving unit A.
The offset signal generating section 14 outputs an offset signal Of, which will be described later.

The first calculation drive unit A controls n switch elements SW via n second calculation drive units B based on the error amplification signal Dr, the offset signal Of, and a reference voltage group Vt described later.

The configuration of the first calculation and driving unit A will be described with reference to FIG.
The first calculation and driving unit A is a shunt circuit having n stages.

The reference voltage group Vt is made up of n reference voltage sets, which are also called hysteresis levels.
The reference voltage set consists of a reference voltage L_H and a reference voltage L_L.
The reference voltage L_H is a high-level reference voltage higher than the reference voltage L_L.
The reference voltage L_L is a low-level reference voltage lower than the reference voltage L_H.
The error amplified signal Dr, the reference voltage L_H, and the reference voltage L_L are used for bang-bang control. When the error amplified signal Dr exceeds the reference voltage L_H, the bus voltage Vb is controlled to decrease. When the error amplified signal Dr falls below the reference voltage L_L, the bus voltage Vb is controlled to increase.
The n reference voltage sets are different from each other.

The first calculation and driving unit A includes n control units A1.
The control unit A1 compares the voltage of the error amplified signal Dr with a reference voltage set, and outputs a voltage according to the comparison result.
The error amplified signal Dr has a voltage indicating the number of short-circuited solar cell arrays SA (the number of short-circuited stages).

The first calculation and driving unit A includes a stage number signal generating unit A2.
The stage number signal generating unit A2 is connected to the n control units A1.
The stage number signal generating section A2 generates a stage number signal M_S based on the output voltage of each control section A1, and outputs the stage number signal M_S.
The stage number signal M_S is a signal that indicates the number of short-circuited stages.

The stage number signal M_S will be described with reference to Fig. 4. Fig. 4 shows a waveform of the stage number signal M_S when the number of short-circuited stages is 4. When the number of short-circuited stages is 4, three switch elements SW are turned on and one switch element SW is turned on in a switching state.
The stage number signal M_S is a pulse signal having a voltage magnitude proportional to the number of short-circuited stages.
The pulse width (switching period) of the stage number signal M_S is sufficiently shorter than the pulse width t (stage period) of the offset signal Of described later.

Returning to FIG. 3, the explanation will be continued.
The offset signal generating section 14 outputs n offset signals Of.

The offset signal Of will be described with reference to Fig. 4. Fig. 4 shows the waveform of the offset signal Of(1) when n=6.
The offset signal Of changes stepwise from zero voltage to (n-1) voltage steps for each control period T.
The voltage of the offset signal Of changes at intervals of a pulse width t. The voltage that has risen to the (n-1)th stage returns to zero when the pulse width t has elapsed.
The voltage of one stage of the offset signal Of is equal to the voltage of one stage of the stage number signal M_S.
The relationship between the control period T, the pulse width t (stage period), and the number of stages n is as follows:
T = t × n

The n offset signals Of will be described with reference to Fig. 5. Fig. 5 shows the waveforms of the offset signals Of when n=6.
The n offset signals Of are out of phase with each other by 2π/n [Rad].

Returning to FIG. 3, the explanation will be continued.
The first calculation and driving unit A includes n driving signal generating units A3.
The drive signal generating unit A3 is connected to the stage number signal generating unit A2, the offset signal generating unit 14 and the second calculation drive unit B.
The drive signal generating section A3 generates a drive signal AO using the stage number signal M_S and the offset signal Of, and outputs the drive signal AO.
The drive signal AO is generated by adding the stage number signal M_S to the offset signal Of.

FIG. 6 shows the waveform of the drive signal AO(1) when n=6.
The drive signal AO(1) is generated by adding the stage number signal M_S (see FIG. 4) to the offset signal Of(1) (see FIG. 4).

Returning to FIG. 3, the explanation will be continued.
Each drive signal AO is input to a second calculation and drive unit B.
The second calculation drive unit B compares the voltage of the drive signal AO with a reference voltage Re, and controls the switch element SW according to the comparison result.

The reference voltage Re will be described with reference to Fig. 4. Fig. 4 shows the reference voltage Re when n=6.
The reference voltage Re is greater than the voltage of (n-1) stages of the stage number signal M_S and the offset signal Of and less than the voltage of n stages. Specifically, the reference voltage Re is an intermediate value between the voltage of (n-1) stages and the voltage of n stages.

The operation of the second calculation and driving unit B will be described with reference to FIG.
The second calculation drive unit B keeps the switch element SW in the OFF state while the voltage of the drive signal AO is smaller than the reference voltage Re.
The second calculation drive unit B keeps the switch element SW in the on state while the voltage of the drive signal AO is higher than the reference voltage Re.
The second calculation drive unit B keeps the switch element SW in a switching state while the magnitude of the voltage of the drive signal AO relative to the reference voltage Re changes every switching period.

The pulse width of the stage number signal M_S corresponds to the switching period.
The pulse width t is sufficiently longer than the switching period.

In FIG. 6, the switch element SW(1) is controlled as follows.
When the phase is between zero and 2π/3, the voltage of the drive signal AO(1) is smaller than the reference voltage Re, so the switch element SW(1) is in the OFF state.
When the phase is between 2π/3 and π, the magnitude of the voltage of the drive signal AO(1) relative to the reference voltage Re changes every switching period, so the switch element SW(1) is in a switching state.
When the phase is from π to 2π, the voltage of the drive signal AO(1) is greater than the reference voltage Re, so the switch element SW(1) is in the on state.

The operation of the n switch elements SW will be described with reference to Fig. 7. Fig. 7 shows the relationship between the phase of the drive signal AO and the state of the switch elements SW when the number of stages n is 6 and the number of short-circuited stages is 4.
"ON" means that the switch element SW is in the on state.
"OFF" means that the switch element SW is in the off state.
"SW" means that the switch element SW is in a switching state.
Each switch element SW switches between an on state and an off state while the phase changes by 2π, that is, during a control period T.
Every time the phase changes by 2π/n, that is, every time the pulse width t elapses, the set of switch elements SW in the ON state changes. The set of switch elements SW in the OFF state also changes. Furthermore, the switch elements SW in the switching state change.
In FIG. 7, the switching elements SW are switched on in the order of SW3, SW2, SW1, SW6, SW5, and SW4.

***Advantages of First Embodiment***
According to the first embodiment, high-speed response operation is possible for shunt switching control by voltage hysteresis control. Voltage hysteresis control is control based on the result of comparison between a hysteresis level and a control signal.
The distributed switching control switches at a period longer than the shunt switching period.
This makes it possible to achieve both heat dispersion and control bandwidth.

According to the first embodiment, even when the number of short-circuited stages is fixed, the short-circuited stage performing switching is switched every time the pulse width t elapses. That is, the switching operation is distributed among a plurality of switch elements.
For shunt switching control, high-speed response operation is possible using an analog circuit configuration.
The distributed switching control switches at a period (e.g., 10 milliseconds or more) longer than the shunt switching period (e.g., 1 millisecond or less), enabling high-speed control response of the shunt operation.

***Features of the First Embodiment***
The power controller (11) includes a plurality of switch elements (SW) connected in parallel with each of a plurality of power sources, and short-circuiting the connected power sources among the plurality of power sources when the power sources are in an on state;
A calculation and driving unit (A, B) for controlling the plurality of switch elements;
Equipped with.
The arithmetic and driving unit sets one of the switch elements, the number of which is the same as the number of short-circuit stages, which is the number of power supplies to be short-circuited among the multiple power supplies, to a switching state in which switching between the off state and the on state is repeated, sets the remaining of the switch elements, the number of which is the same as the number of short-circuit stages, to the on state, and sets the remaining of the multiple switch elements to the off state, thereby sequentially changing the switch elements to be set to the switching state.

The number of power sources (n) is the number of the plurality of power sources.
The control period (T) is a predetermined period.
The step period (t) is a period obtained by dividing the control period by the number of power supplies.
The switching period is shorter than the stage period.
The arithmetic and driving unit includes:
The switch element to be switched is changed every step period;
The switching of the switching state is performed every switching period.

The number of stages (n) corresponds to the number of power sources,
The power controller includes:
The offset signal generating section outputs a plurality of offset signals, which change for each step period and change stepwise having the number of constituent steps for each control period, with mutually different phases.
The arithmetic and driving unit includes:
a first calculation and driving unit (A) that generates a stage number signal, which is a pulse signal that changes by a voltage magnitude of one stage of the offset signal for each switching period based on a voltage having a magnitude proportional to the short-circuit stage number, and outputs a driving signal that is generated by adding the stage number signal to the offset signal for each offset signal;
and a plurality of second calculation drive units (B) connected to the plurality of switch elements, each of which receives a plurality of drive signals corresponding to the plurality of offset signals, compares a voltage of an input drive signal among the plurality of drive signals with a reference voltage (Re), and controls a connected switch element among the plurality of switch elements in accordance with a comparison result.

The reference voltage is greater than the maximum voltage of the offset signal and less than a voltage obtained by adding the maximum voltage to the voltage of one stage of the offset signal.
The second calculation and driving unit is
keeping the switch element in the off state while the voltage of the drive signal is smaller than the reference voltage;
keeping the switch element in the on state while the voltage of the drive signal is greater than the reference voltage;
The switch element is placed in the switching state while the magnitude of the voltage of the drive signal relative to the reference voltage changes for each switching period.

***Additional Notes to the First Embodiment***
The power controller 11 may be mounted on a device other than the satellite 100 .

Embodiment 1 is an example of a preferred embodiment and is not intended to limit the technical scope of this disclosure.

11 Power controller, 12 Power bus, 13 Error amplifier, 14 Offset signal generator, 15 Load, 16 Capacitor bank, 100 Satellite, A First calculation driver, A1 Control unit, A2 Stage signal generator, A3 Drive signal generator, AO Drive signal, B Second calculation driver, D Backflow prevention element, Dr Error amplification signal, Il Load current, Is Generated power, L Reference voltage, M_S Stage signal, Of Offset signal, Re Reference voltage, SA Solar cell array, SW Switch element, T Control period, Vb Bus voltage, Vt Reference voltage group, t Pulse width.

Claims (4)

a plurality of switch elements connected in parallel to the plurality of power sources, respectively, for shorting the connected power sources among the plurality of power sources when the power sources are in an on state;
A calculation and driving unit that controls the plurality of switch elements;
Equipped with
The arithmetic and driving unit is a power controller that sets one of the switch elements, the number of which is the same as the number of short-circuit stages, which is the number of power supplies to be short-circuited among the multiple power supplies, to a switching state in which switching between an off state and the on state is repeated, sets the remaining of the switch elements, the number of which is the same as the number of short-circuit stages, to the on state, and sets the remaining of the multiple switch elements to the off state, thereby sequentially changing the switch elements that are set to the switching state. the number of power sources is the number of the plurality of power sources;
The control period is a predetermined period.
a step period is a period obtained by dividing the control period by the number of power sources,
The switching period is shorter than the stage period,
The arithmetic and driving unit includes:
The switch element to be switched is changed every step period;
The power controller of claim 1 , wherein the switching in the switching state is performed every switching period. The number of configuration stages corresponds to the number of power sources,
The power controller includes:
an offset signal generating unit that outputs a plurality of offset signals that change in each step period and change in a stepwise manner having the number of constituent steps in each control period, with mutually different phases;
The arithmetic and driving unit includes:
a first calculation and driving unit that generates a stage number signal, which is a pulse signal that changes by a voltage magnitude of one stage of the offset signal for each switching period based on a voltage having a magnitude proportional to the short-circuit stage number, and outputs a driving signal generated by adding the stage number signal to the offset signal for each offset signal;
a plurality of second calculation drive units each connected to the plurality of switch elements, each receiving a plurality of drive signals corresponding to the plurality of offset signals, comparing a voltage of an input drive signal among the plurality of drive signals with a reference voltage, and controlling a connected switch element among the plurality of switch elements in accordance with a comparison result;
The power controller of claim 2 . the reference voltage is greater than a maximum voltage of the offset signal and less than a voltage obtained by adding the maximum voltage to the voltage of one stage of the offset signal,
The second calculation and driving unit is
keeping the switch element in the off state while the voltage of the drive signal is smaller than the reference voltage;
keeping the switch element in the on state while the voltage of the drive signal is greater than the reference voltage;
4. The power controller according to claim 3, wherein the switch element is in the switching state while the magnitude of the voltage of the drive signal relative to the reference voltage changes for each switching period.

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