JP7614840B2 - Image processing device, control method and program thereof - Google Patents

Description

The present invention relates to an image processing device and a control method and program thereof.

Generally, many reading devices such as scanners, printing devices such as printers, and display devices such as displays are capable of handling color images/color originals (for example, images having multiple colors such as RGB color images and CMYK color images). For this reason, the image processing devices installed in many of these devices are configured based on color processing. The image processing device has an image processing circuit that processes, for example, three colors for RGB color images and four colors for CMYK color images. General image processing circuits are often designed so that the threshold table referenced in dither processing can be arbitrarily changed by register settings, so that the circuit can be used for not only one process but also other processes. Therefore, the dither circuits corresponding to each color can be the same circuit. The image processing device can have as many dither circuits in parallel as the number of corresponding colors, for example, three for RGB color images and four for CMYK color images. In such an image processing device based on color processing, when a color image is input, dither processing can be performed in parallel on pixel data of each color using multiple dither circuits. Also, when a monochrome (single-color) image is input, multiple dither circuits can be used to perform dither processing on multiple pixel data of the monochrome image in parallel, improving processing performance. This dither processing may use a threshold table with blue noise characteristics to obtain favorable dot dispersion. This blue noise characteristic is a visual characteristic in which the low-frequency region with high sensitivity has almost no power, and the high-frequency region with low sensitivity has power. For this reason, when a human visually views an image that has been quantized using a threshold table with blue noise characteristics, the bias or periodicity of the dots is difficult to detect, and the image is recognized as being of good quality. When dither processing is performed using a threshold table with such blue noise characteristics, the dot arrangement of the output image also has blue noise characteristics.

In such an image processing device based on color processing, multiple partial images are input and dithering is performed in parallel by referencing a threshold table having blue noise characteristics corresponding to each partial image, thereby improving processing performance while imparting blue noise characteristics to the entire output image.

For example, the technology described in Patent Document 1 describes that in an image processing device that processes a color image composed of multiple color components, when a monochrome image is to be processed, multiple partial images of the monochrome image are stored in multiple fields that can store multiple color components, and an image processing circuit performs image processing on the multiple partial images simultaneously. Also, the technology described in Patent Document 2 describes that when the input image is a monochrome image, the monochrome image is divided into rectangular sizes, and pixel data of multiple different coordinates is input to a rectangular image processing unit in a pseudo manner to perform image processing simultaneously.

JP 2015-115837 A JP 2007-221343 A

According to the technology disclosed in Patent Document 1, when image processing of monochrome image data is performed, multiple partial images are extracted from the monochrome image data, and monochrome pixel values are obtained from each of the multiple partial images. The multiple monochrome pixel values are then stored in multiple fields of an image processing command, and image processing is performed, thereby distributing and parallelizing the performance of image processing to increase speed.

However, Patent Document 1 does not disclose any means for performing dither processing on multiple partial images of monochrome image data in parallel. If dither processing is performed on multiple partial images based on the method of Patent Document 1, it would be necessary to place threshold tables having blue noise characteristics corresponding to the size of the partial images in the memory area of the dither circuit as many times as the number of partial images to be processed in parallel. This would result in an increase in the circuit scale for dithering monochrome images in parallel.

The present invention has been made in consideration of such problems. The present invention aims to provide a technology that can process image data using multiple processing circuits, each of which has a limited memory area, and yet can execute image processing based on a number of setting values that exceeds the size of each memory area.

In order to solve this problem, for example, an image processing device according to the present invention has the following arrangement.
An image processing device that processes image data based on matrix data composed of a plurality of setting values arranged in a matrix,
a plurality of processing circuits, each of which has a memory area for storing the setting values therein and performs image processing based on the setting values set in the memory area and input image data;
a determining means for determining a size of a partial area when the matrix data is divided based on a size of the matrix data to be used and a size of the storage area;
a setting means for setting the partial region setting values determined by the determining means to the plurality of processing circuits;
A dividing means for dividing the image data into a plurality of partial image data based on the size of the partial region;
The image processing device further comprises a control means for controlling the plurality of processing circuits and causing each of the processing circuits to execute processing on the partial image data divided by the dividing means.

The present invention provides a technology that can process image data using multiple processing circuits, each of which has a limited memory area, and yet can perform image processing based on a number of setting values that exceeds the size of each memory area.

1 is a block diagram showing the overall configuration of an image processing apparatus according to an embodiment; FIG. 4 is a diagram showing an image area in the embodiment. FIG. 4 is a diagram showing a threshold table according to the embodiment. 5 is a flowchart showing a process of setting a control register and an operation register in the first embodiment. 4A and 4B are diagrams illustrating input and output image areas divided into rectangular areas according to the first embodiment. 5A and 5B are diagrams showing the relationship between rectangular areas and divided threshold tables according to the first embodiment. FIG. 2 is a block diagram showing a configuration of an image processing circuit unit. 5A and 5B are diagrams showing the structure of commands exchanged between an input/output control circuit unit and an image processing execution circuit unit in the embodiment. 6A and 6B are diagrams showing the structures of a color image data command and a monochrome odd data command in the embodiment. FIG. 4 is a block diagram showing a configuration of a dither circuit unit. 10 is a flowchart showing a process of setting a control register and an operation register according to the second embodiment. 13A and 13B are diagrams illustrating input and output image areas divided into rectangular areas according to the second embodiment. 13A and 13B are diagrams showing the relationship between rectangular areas and threshold tables according to the second embodiment.

The following embodiments are described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe multiple features, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicate explanations are omitted.

[First embodiment]
1 is a block diagram showing the overall configuration of an image processing apparatus according to the first embodiment. This apparatus includes a CPU 100, a RAM 101, a ROM 102, an image processing circuit section 103, an I/F section 104, and a system bus 105 that connects these components to each other so that they can communicate with each other. The I/F section 104 can transmit and receive data to and from an external device via a network. The CPU 100 is a central processing unit that controls the entire image processing apparatus, and executes a control program loaded into the RAM 101 or the ROM 102. The CPU 100 stores input image data received from the I/F 104 in the RAM 101 according to the control program, and executes image processing using the image processing circuit section 103. The image processing circuit section 103 performs image processing on the input image data stored in the RAM 101, and stores output image data, which is the result of the image processing, in the RAM 101. The CPU 100 also performs processing to transmit the output image data stored in the RAM 101 to an external device through the I/F 104 according to the control program.

In the above configuration, the device of the embodiment processes image data input via the I/F unit 104, for example, in units of image areas 200 (described below). There is no particular limit to the source of the image data input by the I/F unit 104, but it is assumed that, for example, an image scanner or a storage device that stores the image data to be processed is connected to the I/F unit 104.

Figure 2 is a diagram showing an image area according to this embodiment. The size of the image area 200 is represented by the width Pl of the image area and the height Ph of the image area (in units of the number of pixels). In this embodiment, the image area 200 for storing the input image to be processed and the image area 200 for storing the processed output image are each reserved in advance in the RAM 101. Here, the image area for storing the input image and the image area for storing the output image may be configured to have different sizes in order to perform enlargement or reduction processing on the input image.

Figure 3 is a diagram showing a threshold table according to this embodiment. The size of this threshold table is the width W of the threshold table and the height Dh of the threshold table, and is defined as the number of elements W x Dh. The width W, height Dh, and the arrangement of the stored thresholds depend on the type of processing and settings made by the user. In addition, multiple threshold tables corresponding to the size and arrangement of the thresholds are stored in ROM 102, and Figure 3 shows one of them.

The entire threshold table is also defined as a two-dimensional matrix-like dither matrix data. Here, the width Pl of the image area 200 is equal to or greater than the width W of the threshold table in FIG. 3. In this embodiment, since the input image has 256 levels of gradation, 8-bit threshold data of 0 to 255 is stored in each element of the threshold table. This threshold data does not necessarily have to be 256 levels, and may be another level according to the number of gradations of the input image. Here, the closer the height Dh of the threshold table is to the height Ph of the image area, the more blue noise characteristics can be maintained, and the more likely it is that the image quality after dither processing will be improved. In addition, by defining the width W of the threshold table as a predetermined length, even if it is smaller than the width Pl of the image area, the blue noise characteristics can be maintained by repeatedly referring to the threshold table 300 in the main scanning direction for the image area 200. In this embodiment, the threshold table 300 is placed in the RAM 101, and before the image processing circuit unit 103 starts dither processing, the CPU 100 transfers a part of the reference range of the threshold table 300 to the storage area of the dither circuit. Here, the height Dh of the threshold table is equal to the height Ph of the image area, and the width W of the threshold table is smaller than the width Pl of the image area.

Figure 4 is a flow chart showing how the CPU 100 divides the monochrome image area 200 into multiple rectangular areas along the sub-scanning direction and sets the registers for the image processing circuit unit 103 to perform parallel image processing on the multiple rectangular areas. The device of the embodiment can process color images of four color components such as YMCK. For monochrome images, an example is described in which four dither circuits 1000a to 1000d are used for each of the four color components to perform four parallel dither processing. The dither processing circuits 1000a to 1000d have the same circuit configuration, and unless otherwise specified, the dither processing circuits 1000a to 1000d are simply referred to as the dither circuit 1000 when referring to one of them. Each of the dither circuits 1000a to 1000d has its own internal storage area, the size of which is sufficiently small compared to the size of the dither matrix to be used. Conversely, the dither circuits 1000a to 1000d of the embodiment improve processing performance even if they have a memory area smaller than the dither matrix size to be used.

At S400, the CPU 100 acquires the size S of the threshold table to be stored in the memory area of the dither circuit 1000, i.e., the area size S of the threshold table block 600 of the dither circuit 1000. Here, it is assumed that the area size of the threshold table block 600 of the dither circuit 1000 is smaller than the area size of the threshold table 300 to be used, which is stored in the RAM 101.

At S401, the CPU 100 acquires the width W of the threshold table to be stored in the memory area of the dither circuit unit 1000. The width W of this threshold table is a predetermined length that can maintain the blue noise characteristics when the threshold tables 601, 602, 603, and 604 are repeatedly applied to the image area 200 in the main scanning direction. Here, the width W of this threshold table may be a value that is stored in advance in the ROM 102, or may be a value acquired from an external device via the I/F unit 104.

At S402, the CPU 100 divides the area size S of the threshold table block 600 obtained at S400 by the width W of the threshold table obtained at S401 to obtain the height Th of the threshold table to be stored in the memory area of the dither circuit unit 1000. This formula makes it possible to determine the size of the threshold table that can maintain the blue noise characteristics.

In S403, the CPU 100 acquires the maximum color component Dmax of the input/output image that the image processing circuit unit 103 can process. Here, the maximum color component Dmax may be any number of colors greater than or equal to two colors for processing a color image. The device of the embodiment is capable of handling color images with a maximum of four color components, such as CMYK, so Dmax is "4". This is also the reason why the dither circuits 1000 described above have four. Note that the value of Dmax is a value according to the device settings, so it does not necessarily have to be 4. In addition, the number of colors Dmax of the input image and the output image may differ, for example, when performing image processing on an input image with three colors, RGB (Dmax = 3), and outputting an output image with four colors, CMYK (Dmax = 4).

In S404, the CPU 100 calculates the height Bh of the rectangular region in order to divide the image region 200 having the height Th of the threshold table determined in S402 into rectangular regions for parallel processing. Specifically, the CPU 100 divides the height Th of the threshold table calculated in S402 by the number of colors that can be simultaneously processed by the image processing circuit 103, that is, by the maximum number of color components Dmax of the input/output images acquired in S403, to calculate the height Bh of the rectangular region.

At S405, the CPU 100 divides the image area 200 into rectangular areas with the image area length Pl and the rectangular area height Bh calculated at S404, as shown in FIG. 5. Specifically, as shown in FIG. 5, the image area for storing the input image is divided into 12 rectangular areas (also called partial images or partial image data) A0-0, A0-1, A0-2, A0-3, A1-0, A1-1, A1-2, A1-3, A2-0, A2-1, A2-2, and A2-3. Furthermore, the image area for storing the output image (image after dithering) is divided into 12 rectangular areas B0-0, B0-1, B0-2, B0-3, B1-0, B1-1, B1-2, B1-3, B2-0, B2-1, B2-2, and B2-3.

In S406, the CPU 100 acquires the maximum number of color components Dmax ("4" in the embodiment) of the input/output images and sets the number of parallel processes Vn to 4. Here, the maximum number of color components Dmax of the input/output images does not necessarily have to be four colors, and may be a specific value of two or more colors.

At S407, the CPU 100 groups the rectangular areas divided at S405 into input areas 500, 501, and 502 as input rectangular areas, and into output rectangular areas 503, 504, and 505 as output rectangular areas, based on the number of parallel processes Vn (=4) obtained at S406.

In S408, the CPU 100 sets the start address of each rectangular area divided in S405 in the control registers in the dither circuits 1000a to 1000d so that parallel image processing is performed in the order from top to bottom in the units grouped in S407. Specifically, the start address and area size of each rectangular area for the input area 500 and the output area 503 are set in the control registers of the dither circuits 1000a to 1000d so that the input area 500 is input and the output area 503 is output. Here, the start address of each rectangular area in the input area 500 may be set in the control register, and an offset value from the start address of each rectangular area in the input area 500 may be set in the control register as start address information for each rectangular area in the input area 501 and the input area 502.

In S409, the CPU 100 sets a control register for transferring the divided threshold tables in the threshold table 300 shown in FIG. 6A to the image processing circuit unit 103. Specifically, the CPU 100 sets the addresses and sizes of the threshold tables 601, 602, 603, and 604, which are the transfer source, in the control register. Furthermore, the CPU 100 sets the addresses of the threshold table divided blocks 613, 614, 615, and 616 of the dither circuit unit 1000, which are the transfer destination, in the control register.

At S410, the CPU 100 sets the reference start position of the threshold table in the threshold table block 600, which the dither circuit units 1000a to 1000d refer to when dithering each rectangular area, in the operation register. Hereinafter, the divided tables 601 to 612 in the threshold table 300 stored in the RAM 101 are also referred to as threshold tables. Specifically, the CPU 100 sets the reference start position of each area of the threshold table division blocks 613, 614, 615, and 616 in the operation register of each of the dither circuits 1000a to 1000d. In other words, the operation register is set so that the dither circuit 1000a, which performs dithering on the pixel data in the K1 area of the monochrome image data command 901, refers to the threshold table in the threshold table division block 613. Also, the operation register is set so that the dither circuit 1000b, which performs dithering on the pixel data in the K2 area of the monochrome image data command 901, refers to the threshold table in the threshold table division block 614. In addition, the dither circuit 1000c, which performs dither processing on pixel data in the K3 region of the monochrome image data command 901, is set in the operation register to refer to the threshold table in the threshold table division block 615. The dither circuit 1000d, which performs dither processing on pixel data in the K4 region of the monochrome image data command 901, is set in the operation register to refer to the threshold table in the threshold table division block 616.

In S411, the CPU 100 sets the operation register so that the dither circuit units 1000a to 1000d repeatedly refer to the threshold table in the main scanning direction within each rectangular region based on the reference start position of the threshold table set in S410 for each rectangular region. Specifically, as shown in FIG. 6B, the rectangular region A0-0 is assigned to the dither circuit 1000a, and the operation register of the circuit is set so that the threshold table 601 stored in the threshold table division block 613 is repeatedly referred to in the main scanning direction. The rectangular region A0-1 is assigned to the dither circuit 1000b, and the operation register of the circuit is set so that the threshold table 602 stored in the threshold table division block 614 is repeatedly referred to in the main scanning direction. The rectangular region A0-2 is assigned to the dither circuit 1000c, and the operation register of the circuit is set so that the threshold table 603 stored in the threshold table division block 615 is repeatedly referred to in the main scanning direction. The rectangular area A0-3 is handled by the dither circuit 1000d, and the operation register of that circuit is set so that the threshold table 604 stored in the threshold table division block 616 is repeatedly referenced in the main scanning direction.

Next, the flow of the image processing circuit unit 103 receiving the threshold table setting values, operation register setting values, control register setting values, image processing execution command, and input image data shown in FIG. 7, which are set by the CPU 100 based on the flowchart in FIG. 4, and performing parallel image processing will be described with reference to FIGS. 7 to 10.

First, the configuration of the image processing circuit unit 103 will be described. FIG. 7 is a block diagram showing the configuration of the image processing circuit unit 103. The image processing circuit unit 103 is composed of an input/output control circuit unit 700 that inputs register setting values, a threshold table, and input image data and outputs output image data, and an image processing execution circuit unit 701 that performs image processing on a command basis input from the input/output control circuit unit 700. The input/output control circuit unit 700 is composed of a data input unit 702, an intermediate buffer 703, a register block 719, a command generation unit 704, a command transmission unit 705, a command reception unit 716, a command analysis unit 717, and a data output unit 718. Next, the configuration of the image processing execution circuit unit 701 will be described. The image processing execution circuit unit 701 is composed of P image processing circuits, namely, an image processing circuit (1) 709, an image processing circuit (2) 712, ..., an image processing circuit (P) 715, and an interconnect 706. The P image processing circuits and the interconnect 706 are connected to each other via input ports 707, 710, 713, etc., and output ports 708, 711, 714, etc.

In this embodiment, the image processing circuit (P) 715 includes dither circuits 1000a to 1000d that perform dither processing. The image processing circuits other than the image processing circuit (P) 715 perform processing including one or more of, for example, input color correction processing, color space conversion, density correction processing, spatial filter processing, resolution conversion, trimming processing, edge expansion processing, IP conversion, and chroma upsampling. The P image processing circuits may be realized by hardware such as a pipeline circuit, or may be realized by a processor and a program (software), etc. In this embodiment, the image processing execution circuit unit 701 sets the interconnect 706 so that image processing is performed in the order of the image processing circuit (1) 709, the image processing circuit (2) 712, and the image processing circuit (P) 715, which is the dither circuit unit 1000.

Here, the format of commands sent and received between the input/output control circuit unit 700 and the image processing execution circuit unit 701 will be explained using Figures 8 and 9.

The operation register command 800 shown in FIG. 8(a) is a command for setting the operation register setting value of one of the image processing circuits, the image processing circuit (1) 709, the image processing circuit (2) 712, and the image processing circuit (P) 715. The format of the operation register command 800 is composed of a header area, an address area, and a data area. Here, the header area of the operation register command 800 contains at least an identifier indicating that it is an operation register command, an identifier indicating one of the image processing circuits (1) 709, the image processing circuit (2) 712, and the image processing circuit (P) 715, and an identifier indicating one of the subcircuits therein (in the embodiment, the dither processing circuits 1000a to 1000d of the image processing circuit (P) 715 correspond to this). The address area of the operation register command 800 contains an address indicating a specific register in the image processing circuit indicated by the identifier in the header area. The data area of the operation register command 800 contains a value to be set in the operation register indicated by the address in the address area. The threshold data command 801 shown in FIG. 8(b) is a command for setting threshold data for dithering one pixel data for the image processing circuit (P) 715 that performs dithering. The format of the threshold data command 801 is composed of a header area, an address area, and a data area. Here, the header area of the threshold data command 801 contains at least an identifier indicating that it is a threshold data command and an identifier indicating the dither circuit of the image processing circuit (P) 715. The address area of the threshold data command 801 contains a specific address in the threshold table block 600 of the dither circuit section 1000 of the image processing circuit (P) 715. The data area of the threshold data command 801 contains threshold data to be stored at an address indicated by the address in the address area.

The color image data command 900 shown in FIG. 9(a) and the monochrome image data command 901 shown in FIG. 9(b) are commands for the image processing circuits (1) 709, (2) 712, and (P) 715 to perform image processing. In this embodiment, the monochrome image data command 901 is used. The color image data command 900 is composed of a header area and four color pixel data areas C (Cyan), M (Magenta), Y (Yellow), and K (Black). Here, the header area of the color image data command 900 contains at least an identifier indicating that it is a command that stores pixel data and a flag indicating the pixel position in each rectangular area into which the image area 200 is divided. The monochrome image data command 901 is composed of a header area and four monochrome pixel data areas K1, K2, K3, and K4. Here, in the header area of the monochrome image data command 901, as in the color image data command 900, at least an identifier indicating that it is a command that stores pixel data and a flag indicating the pixel position within each rectangular area divided from the image area 200 are set. With regard to the flag indicating the pixel position, for example, if the upper left pixel of rectangular areas A0-0 to A0-3 in Figure 5 is set in the monochrome image data command 901, an identifier indicating that it is the first pixel of the rectangular area is set. Furthermore, if one of the pixels at the bottom of rectangular areas A0-0 to A0-3 in Figure 5 is set in the monochrome image data command 901, an identifier indicating that it is the bottom pixel of the rectangular area is set.

Next, we will explain the flow in which the image processing circuit unit 103 reads the threshold table setting values.

The data input unit 702 of the input/output control circuit unit 700 reads the threshold table setting value to be stored in the memory area of the image processing circuit (P) 715 including the dither circuit unit 1000 set by the CPU 100. The data input unit 702 reads the partial areas 601, 602, 603, and 604 of the threshold table stored in the RAM 101 in a predetermined unit and stores them in the intermediate buffer 703. Next, the data input unit 702 reads the threshold data stored in the intermediate buffer 703 in units of one element and inputs it to the command generation unit 704. The command generation unit 704 generates a threshold data command 801 including the threshold data in units of one element and inputs it to the command transmission unit 705. The command transmission unit 705 inputs the threshold data command 801 to the image processing execution circuit unit 701. Next, the image processing execution circuit unit 701 transmits the threshold data command 801 to the input port 707 via the interconnect 706. When the image processing circuit (1) 709 receives the threshold data command 801 from the input port 707, it refers to the identifier in the header area of the threshold data command 801 and determines that it is a threshold data command 801 for another image processing circuit. It then transmits the received threshold data command 801 to the output port 708. The interconnect 706 then transmits the threshold data command 801 received from the output port 708 to the input port 710. When the image processing circuit (2) 712 receives the threshold data command 801 from the input port 710, it refers to the identifier in the header area of the threshold data command 801 and determines that it is a threshold data command 801 for another image processing circuit. It then transmits the received threshold data command 801 to the output port 711. The interconnect 706 then transmits the threshold data command 801 received from the output port 711 to the input port 713.

Here, the flow when the image processing circuit (P) 715, which is the dither circuit 1000, receives the threshold data command 801 will be described using the dither circuit unit 1000 in FIG. 10. The command receiving unit 1001 receives the threshold data command 801. The command analyzing unit 1002 analyzes the identifier stored in the header area of the threshold data command 801 and interprets that the received command is the threshold data command 801. Then, it obtains an address in the threshold table block 600 for storing the threshold table of the dither circuit unit 1000 from the address area of the threshold data command 801, and obtains one element of threshold data from the data area. The threshold data writing unit 1005 stores one element of threshold data in the address in the threshold table block 600 obtained by the command analyzing unit 1002, that is, the address of the threshold table block 600. Next, the command transmitting unit 1010 transmits the threshold data command 801 received by the command receiving unit 1001 to the output port 714.

Next, the flow of reading the operation register setting value by the image processing circuit (P) 715, which is the dither circuit unit 1000 of the image processing circuit unit 103, will be described. The data input unit 702 of the input/output control circuit unit 700 sequentially reads the operation register setting values of the image processing circuits of the image processing circuit (1) 709, the image processing circuit (2) 712, and the image processing circuit (P) 715 set by the CPU 100. The command generation unit 704 generates an operation register command 800 for the image processing circuit (P) 715, which is the dither circuit unit 1000, and inputs it to the command transmission unit 705. The command transmission unit 705 inputs the operation register command 800 to the image processing execution circuit unit 701. Next, the image processing execution circuit unit 701 transmits the operation register command 800 to the input port 707 via the interconnect 706. When the image processing circuit (1) 709 receives the operation register command 800 from the input port 707, it refers to the identifier in the header area of the operation register command 800 and determines that it is an operation register command 800 for another image processing circuit. Then, it transmits the received operation register command 800 to the output port 708. Then, the interconnect 706 transmits the operation register command 800 received from the output port 708 to the input port 710. When the image processing circuit (2) 712 receives the operation register command 800 from the input port 710, it refers to the identifier in the header area of the operation register command 800 and determines that it is an operation register command 800 for another image processing circuit. Then, it transmits the received operation register command 800 to the output port 711. Then, the interconnect 706 transmits the operation register command 800 received from the output port 711 to the input port 713.

Here, the flow when the image processing circuit (P) 715, which is the dither circuit unit 1000, receives the operation register command 800 will be described using the dither circuit unit 1000 in FIG. 10. The command receiving unit 1001 receives the operation register command 800. The command analyzing unit 1002 analyzes the identifier stored in the header area of the operation register command 800 and interprets that the received command is the operation register command 800. Then, it obtains an address indicating a specific register of the dither circuit unit 1000 from the address area of the operation register command 800, that is, a specific address of the register block 1004, and obtains a register setting value from the data area. The register value writing unit 1003 writes the register setting value to the specific address of the register block 1004 obtained by the command analyzing unit 1002. Next, the command transmitting unit 1010 transmits the operation register command 800 received by the command receiving unit 1001 to the output port 714. Here, an operation register command 800 is set for the image processing circuit (P) 715, which is the dither circuit unit 1000, indicating the reference start positions of at least the threshold table division blocks 613, 614, 615, and 616 set in step S410 of FIG. 4. Furthermore, an operation register command 800 is set for repeatedly referencing the threshold table set in step S411 in the main scanning direction within each rectangular area.

Next, the operation register command 800 for the image processing circuit (1) 709 and the image processing circuit (2) 712 is also used in a similar flow to set the operation register setting value in the register block within each image processing circuit.

Next, a flow of setting the control register setting value by the input/output control circuit section 700 will be described. The data input section 702 of the input/output control circuit section 700 reads the control register setting value set by the CPU 100 and writes it to the register block 719. At least the following control registers are written here.
4 ; a control register indicating the start addresses of rectangular areas A0-0, A0-1, A0-2, and A0-3 in the input area 500 set in S408 in Fig. 4; a control register indicating the start addresses of rectangular areas B0-0, B0-1, B0-2, and B0-3 in the output area 503 set in S408; a control register indicating the area size Pl*Bh of the rectangular area based on the size of the rectangular area determined in S405 Next, a flow in which the input/output control circuit unit 700 reads an image processing execution command will be described. When the data input unit 702 of the input/output control circuit unit 700 reads an image processing execution command, it reads the following control registers from the register block 719.
A control register indicating the start addresses of rectangular areas A0-0, A0-1, A0-2, and A0-3 in the input area 500 set in S408 A control register indicating the start addresses of rectangular areas B0-0, B0-1, B0-2, and B0-3 in the output area 503 set in S408 A control register indicating the area size Pl*Bh of the rectangular area based on the size of the rectangular area determined in S405 Then, the data input unit 702 reads out the input image data in predetermined block units from the input area 500 based on the control register setting values, and stores it in the intermediate buffer 703. Next, the data input unit 702 reads out the block data A0-0 to A0-3 stored in the intermediate buffer 703 in units of one pixel, and inputs it to the command generation unit 704. The command generation unit 704 sets the four image data corresponding to A0-0 to A0-3 in the K1 area, K2 area, K3 area, and K4 area of the monochrome image data command 901 to generate the monochrome image data command 901, and inputs it to the command transmission unit 705. As a result, the image data is transmitted to each of the dither circuits 1000a to 1000d of the image processing circuit (P) 715.

Next, the flow of the image processing execution circuit unit 701 receiving the monochrome image data command 901 from the input/output control circuit unit 700 and performing parallel image processing will be described. The image processing circuit (1) 709 receives the monochrome image data command 901 from the input port 707 via the interconnect 706. The image processing circuit (1) 709 extracts four pixel data from the K1 to K4 areas of the monochrome image data command 901 and performs parallel image processing, stores the image data after parallel image processing in the K1 to K4 areas of the monochrome image data command 901, and outputs it to the output port 709. Next, the image processing circuit (2) 712 receives the monochrome image data command 901 from the input port 710 via the interconnect 706. The image processing circuit (2) 712 extracts four pixel data from the K1 to K4 areas of the monochrome image data command 901 and performs parallel image processing, stores the image data after parallel image processing in the K1 to K4 areas of the monochrome image data command 901, and outputs it to the output port 711.

Then, the image processing circuit (P) 715 having the dither circuits 1000a to 1000d receives the monochrome image data command 901 from the input port 713 via the interconnect 706. The image processing circuit (P) 715 uses the internal dither circuits 1000a to 1000d to extract four pixel data from the K1 to K4 areas of the monochrome image data command 901 and perform dither processing in parallel. The image data after the dither processing is then stored in the K1 to K4 areas of the monochrome image data command 901 and output to the output port 714.

Here, the flow of the dither circuit 1000a (one of four) when the image processing circuit (P) 715, which is the dither circuit unit 1000, receives the monochrome image data command 901 will be explained using FIG. 10. The other dither circuits 1000b to 1000c are similar.

First, the flow of dither processing of the first monochrome image data command 901 by the dither circuit unit 1000a will be described. The command receiving unit 1001 receives the monochrome image data command 901. The command analyzing unit 1002 analyzes the identifier stored in the header area of the monochrome image data command 901 and interprets that the received command is the monochrome image data command 901. Furthermore, the command analyzing unit 1002 analyzes another identifier stored in the header area and interprets that the pixel position of the pixel data set in the monochrome image data command 901 is the first pixel of the rectangular area A0-0. Then, one pixel data is obtained from the K1 area of the monochrome image data command 901. The dither processing unit 1006 requests the threshold data obtaining unit 1008 to obtain threshold data corresponding to each pixel data obtained by the command analyzing unit 1002. The threshold data obtaining unit 1008 manages the pixel positions of the pixel data specified in the monochrome image data command 901 in a coordinate format. Specifically, as shown in Figure 5, the upper left corner of rectangular area A0-0 is the origin, and the main scanning direction from left to right is the direction in which the x coordinate value increases. Additionally, the sub-scanning direction from top to bottom is the direction in which the y coordinate value increases. Here, the pixel position of the pixel data of rectangular area A0-0 stored in the K1 area of the monochrome image data command 901 is expressed as the coordinate value K1 (x1, y1).

Since the pixel data of the monochrome image data command 901 is the first pixel of the rectangular area A0-0, the threshold data acquisition unit 1008 initializes the coordinate value K1 (x1, y1) to (0, 0). Next, the threshold data acquisition unit 1008 acquires the reference start position K1 (b) for the threshold table division block 613 written in S410 from the register block 1004. Here, the reference start position is expressed as an element-by-element logical address of the threshold table with the upper left corner of the threshold table division block 613 as the origin. The threshold data acquisition unit 1008 calculates the logical address K1 (p0) of the threshold table corresponding to the coordinate value K1 (x1, y1) of the rectangular area A0-0 stored in the K1 area of the monochrome image data command 901. Specifically, the calculation is performed as K1 (p0) = K1 (b) + y1 * W + x1 using the coordinate value K1 (x1, y1) and the width W of the threshold table acquired in S401. Then, the threshold data acquisition unit 1008 acquires the threshold data K1(q0) stored at logical address K1(p0) of the threshold table block 600.

Next, the dither processing unit 1006 acquires threshold data K1 (q0) from the threshold data acquisition unit 1008. The dither processing unit 1006 compares the pixel data stored in the K1 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K1 (q0) and performs binarization. Specifically, when the pixel data in the K1 area is equal to or greater than the threshold data K1 (q0), it is determined that a dot is to be printed, and when the pixel data in the K1 area is less than the threshold data K1 (q0), it is determined that a dot is not to be printed, and performs binarization to generate output pixel data K1 (r0). Note that the output pixel data is binary, so 1 bit is sufficient.

Next, the coordinate update unit 1007 updates the coordinate value K1 (x1, y1) indicating the pixel position of the pixel data managed by the threshold data acquisition unit 1008. The coordinate update unit 1007 shifts the pixel position downward by one position with respect to the y coordinate in the coordinate value K1 (x1, y1) indicating the pixel data of the first monochrome image data command. Specifically, the coordinate update unit 1007 adds 1 to the value of the y coordinate, and updates the pixel position of the pixel data specified in the next monochrome image data command to K1 (x1, y1 + 1).
Next, the command generation unit 1009 sets the pixel data K1 (r0) output by the dither processing unit 1006 in the K1 area of the monochrome image data command 901. The command transmission unit 1010 outputs the monochrome image data command 901 generated by the command generation unit 1009 to the output port 714.
Next, a flow of dither processing performed by the dither circuit 1000a on the second monochrome image data command 901 will be described.

The command receiving unit 1001 receives the monochrome image data command 901. The command analyzing unit 1002 analyzes the identifier stored in the header area of the monochrome image data command 901 and interprets that the received command is the monochrome image data command 901. Then, it acquires the pixel data of the K1 area of the monochrome image data command 901. The dither processing unit 1006 requests the threshold data acquisition unit 1008 to acquire threshold data corresponding to the pixel data acquired by the command analyzing unit 1002. The pixel position of the pixel data of the rectangular area A0-0 stored in the K1 area of the monochrome image data command 901 is the coordinate value K1 (x1, y1+1).

The threshold data acquisition unit 1008 acquires the coordinate value K1 (x1, y1+1). Next, the threshold data acquisition unit 1008 acquires the reference start position K1 (b) for the threshold table division block 613 written in S410 from the register block 1004. The threshold data acquisition unit 1008 calculates the logical address K1 (p1) of the threshold table corresponding to the coordinate value K1 (x1, y1+1) of the rectangular area A0-0 stored in the K1 area of the monochrome image data command 901. Specifically, using the coordinate value K1 (x1, y1+1) and the width W of the threshold table acquired in S401, the calculation is made as K1 (p1) = K1 (b) + (y1 + 1) * W + x1. Then, the threshold data acquisition unit 1008 acquires the threshold data K1 (q1) stored in the logical address K1 (p1) of the threshold table block 600.

The dither processing unit 1006 then acquires threshold data K1 (q1) from the threshold data acquisition unit 1008. The dither processing unit 1006 compares the pixel data stored in the K1 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K1 (q1) and performs binarization. Specifically, when the pixel data in the K1 area is equal to or greater than the threshold data K1 (q1), it is determined that a dot is to be printed, and when the pixel data in the K1 area is less than the threshold data K1 (q1), it is determined that a dot is not to be printed, and performs binarization to generate output pixel data K1 (r1).

Next, the coordinate update unit 1007 updates the coordinate value K1 (x1, y1+1) indicating the pixel position of the pixel data managed by the threshold data acquisition unit 1008. The coordinate update unit 1007 shifts the pixel position downward by one position relative to the y coordinate in the coordinate value K1 (x1, y1+1) indicating the pixel data of the second monochrome image data command. Specifically, it adds 1 to the value of the y coordinate and updates the pixel position of the pixel data specified in the next monochrome image data command to K1 (x1, y1+2).

Next, the command generation unit 1009 sets the pixel data K1 (r1) output by the dither processing unit 1006 to the K1 area of the monochrome image data command 901. The command transmission unit 1010 outputs the monochrome image data command 901 generated by the command generation unit 1009 to the output port 714.

Based on the above flow, the dither circuit 1000a performs dither processing on the third and subsequent monochrome image data commands 901, and repeats dither processing for the number of pixels in the rectangular area.

The above is the processing of the dither circuit 1000a, but the other dither circuits 1000b to 1000d are similar. However, the dither circuit 1000b processes the pixel data stored in the K2 area of the rectangular area A0-01, and the command generation unit 1009 sets the pixel data K2(ri) (i = 0, 1, 2, ...) output by the dither processing unit 1006 in the K2 area of the monochrome image data command 901 and outputs it to the output port 714. The dither circuit 1000c processes the pixel data stored in the K2 area of the rectangular area A0-02, and the command generation unit 1009 sets the pixel data K3(ri) (i = 0, 1, 2, ...) output by the dither processing unit 1006 in the K3 area of the monochrome image data command 901 and outputs it to the output port 714. The dither circuit 1000d then processes the pixel data stored in the K4 area of the rectangular area A0-03, and the command generation unit 1009 sets the pixel data K4(ri) (i = 0, 1, 2, ...) output by the dither processing unit 1006 in the K4 area of the monochrome image data command 901, and outputs it to the output port 714.

When the value of each y coordinate indicates a pixel at the bottom of the rectangular area A0-0, the coordinate update unit 1007 shifts the pixel position to be processed next by one pixel to the right column of the rectangular area and returns the y coordinate to the top of the rectangular area. Specifically, when y=Bh-1, the coordinate value is set to (x+1,0), the value in the x coordinate direction is added by 1, and the value in the y coordinate direction is set to 0. Furthermore, based on the pixel position analyzed by the command analysis unit 1002, when the value of each y coordinate indicates a pixel at the bottom of the rectangular area A0-0 and the value of each x coordinate is the length W-1 of the threshold table shown in FIG. 6, the coordinate update unit 1007 sets the coordinate value to (0,0). This also applies to the coordinate update units 1007 of the dither circuits 1000b to 1000c.

When the input/output control circuit section 700 has completed outputting rectangular areas B0-0 to B0-3, it issues an interrupt to the CPU 100 to notify it that parallel image processing of the input area 500 has been completed. When the software running on the CPU 100 receives the interrupt from the input/output control circuit section 700, it controls the parallel image processing of the input area 501, and then controls the parallel image processing of the input area 502.

As described above, matrix data such as dither matrices are divided into a plurality of partial matrix data each having a height according to the size of the storage area of the processing circuit (dither circuit), and the plurality of partial matrix data divided are stored in the processing circuit for the number of processing circuits. Then, image data can also be divided into rectangular areas of the height of the partial matrix data, and parallel processing can be performed in each processing circuit. For example, in the embodiment, the dither threshold table has a number of thresholds indicated by width W x height Dh as shown in FIG. 6, but the number of thresholds for dither processing set in one dither circuit 1000 (any of 1000a to 1000d) can be 1/12 the size in the case of FIG. 6. In addition, since processing equivalent to dither processing using a threshold table indicated by width W x height Dh can be realized, processing performance can be improved without degrading blue noise characteristics.

Second Embodiment
In the following, an example will be described in which an image area is divided in the main scanning direction according to the width of the threshold table in order to perform dither processing in parallel by referring to the same threshold table, and further, in order to make maximum use of the memory area of the dither circuit section, the divided image area is divided in the sub-scanning direction by the height of the threshold table, and parallel processing is performed. Here, in the second embodiment, as in the first embodiment, the description will be made using Figures 7, 10, 11, 12, and 13 based on the configurations in Figures 1, 2, 3, 8, and 9.

Figure 11 is a flowchart showing how a monochrome image area 200 is divided along the main scanning direction, and each divided area is then divided into rectangular areas along the sub-scanning direction, after which register settings are made in the image processing circuit unit 103 to perform parallel image processing on the multiple rectangular areas.

At S1100, the CPU 100 acquires the size S of the threshold table to be stored in the memory area of the dither circuit 1000, i.e., the area size S of the threshold table block 1300 of the dither circuit unit 1000. Here, the area size of the threshold table block 1300 of the dither circuit 1000 is smaller than the area size of the threshold table 300 stored in the RAM 101.

At S1101, the CPU 100 acquires the width W of the threshold table to be stored in the memory area of the dither circuit 1000. The width W of this threshold table is a predetermined length that can maintain the blue noise characteristics when the threshold tables 1301, 1302, and 1303 are repeatedly applied to the image area 200 in the main scanning direction. The width W of this threshold table may be a value that is stored in advance in the ROM 102, or may be a value acquired from an external device via the I/F unit 104.

At S1102, the CPU 100 divides the area size S of the threshold table block 1300 obtained at S1100 by the width W of the threshold table obtained at S1101 to obtain the height Th of the threshold table to be stored in the memory area of the dither circuit unit 1000. This formula makes it possible to determine the size of the threshold table that can maintain the blue noise characteristics.

In S1103, the CPU 100 sets the height Bh of the rectangular region for dividing the image area 200 along the sub-scanning direction to the height Th in the threshold table calculated in S1102.

At S1104, the CPU 100 obtains the image area width Pl and image area height Ph of the image area 200.

In S1105, the CPU 100 obtains the maximum number of color components Dmax of the input/output images, and sets the number of parallel processes Vn to 4. Here, the maximum number of color components Dmax of the input/output images does not necessarily have to be 4, and may be a specific value of two or more colors.

In S1106, the CPU 100 calculates the width Dl of a dummy area to be added to the right side of each area for parallel image processing for the divided area along the main scanning direction with the height Bh of the rectangular area determined in S1103, using the following calculation formula and conditional formula.
・Ple = W * Vn * n (Ple≧Pl, n≧1)
・Dl = Ple - Pl
Here, as shown in FIG. 12, Pl is the width of the input image area, Dl is the length of the dummy area, and Ple is the length of the image area including the dummy area. Here, the dummy area is added by the image processing circuit (1) 709 in FIG. 7. That is, the length Ple of the image area including the dummy area shown in FIG. 12 is the length of the image area after image processing by the image processing circuit (1) 709. Furthermore, W is the width W of the threshold table acquired in S1101, Vn is the number of parallel processes set in S1105, and n is an integer of 1 or more that represents the number of repetitions of the number of parallel processes. Here, as shown in FIG. 12 and the conditional expression in S1106, the length Ple of the image area including the dummy area is equal to or greater than the length Pl of the image area not including the dummy area, and the CPU 100 finds the smallest integer n of 1 or more that satisfies this conditional expression. The reason for minimizing the number of repetitions n is to minimize the length of the dummy area. Also, the length Ple of the image area including the dummy area is a multiple of the value obtained by multiplying the width W of the threshold table by the number of parallel processes Vn, which means that the number of rectangular areas in each parallel process is always Vn, and the dummy area is corrected so that the width of each rectangular area is W. Specifically, the maximum number of color components Dmax of the input/output image acquired in S1107 is 4, and Pl is (W*3)<Pl<(W*4) as shown in FIG. 12. Specifically, when n is (1), Ple becomes W*4, which satisfies Ple≧Pl, and the length Dl of the dummy area becomes (W*4)-Pl as shown in FIG. 12. Here, in this embodiment, the case where the number of repetitions n is 1 is shown, but when n is 2 or more, it is necessary to set the start address of each rectangular area referred to in the second parallel process or an offset value for calculating the start address in the control register.

At S1107, the CPU 100 sets the width of the rectangular area to the width W of the threshold table obtained at S1101, and the height of the rectangular area to Bh determined at S1103.

In S1108, the CPU 100 first divides the image area along the main scanning direction according to the width W of the threshold table that can be stored in the threshold table block 1300 in order to perform dither processing in parallel by referencing the same threshold table as shown in FIG. 12(a). Specifically, as shown in FIG. 12(a), the input area 1200 is divided into four areas C0, C1, C2, and C3, and the output area 1204 is also divided into four areas D0, D1, D2, and D3. Here, each of the areas C0 to C4 and D0 to D4 is an integer multiple of the width of the dither matrix. Therefore, the input area 1200 and the output area 1204 have the width Ple and height Ph of the image area including the dummy area corrected in S1106.

Here, in this second embodiment, as shown in FIG. 12, the height Ph of the image area is three times the height Th of the threshold table that can be stored in the threshold table block 1300. Therefore, next, each area divided in FIG. 12(a) is divided according to the size of the threshold table that can be stored in the threshold table block 1300. Specifically, first, as shown in FIG. 12(b), in the input area 1200, area C0 is divided into rectangular areas C0-0, C0-1, C0-2, area C1 into C1-0, C1-1, C1-2, area C2 into C2-0, C2-1, C2-2, and area C3 into C3-0, C3-1, C3-2.

Next, as shown in FIG. 12(b), in the output area 1204, area D0 is divided into rectangular areas D0-0, D0-1, and D0-2, area D1 is divided into rectangular areas D1-0, D1-1, and D1-2, area D2 is divided into rectangular areas D2-0, D2-1, and D2-2, and area D3 is divided into rectangular areas D3-0, D3-1, and D3-2.

In S1109, the CPU 100 sets the length Dl of the dummy area to be added to the right side of the image processor, calculated in S1106, in the control register.

In S1110, the start address of each rectangular area divided in S1108 is set in a control register so that parallel image processing is performed. Specifically, the start address of each rectangular area and the area size of the rectangular area are set in the control register for the input area 1201 and the output area 1205 so that the input area 1201 is input and the output area 1205 is output.

At S1111, the CPU 100 sets a control register for dividing and transferring the threshold table 300 to the image processing circuit unit 103 based on the width W of the threshold table obtained at S1101 and the height Th of the threshold table calculated at S1102. Specifically, the address and size of each threshold table and the address of each threshold table division block for transferring the threshold table 1301 in the threshold table 300 in FIG. 13(a) to the threshold table block 1300 of the dither circuit unit 1000 are set in the control register.

In S1112, the start address of the threshold table block 1300 is set in the operation register as the reference start position of the common threshold table block 1300 that the dither circuit unit 1000 refers to when dithering each rectangular area. Specifically, in order to transfer the threshold table 1301 to the threshold table block 1300 of the dither circuit unit 1000 for the rectangular area in the input area 1201 of FIG. 12, each rectangular area refers to the common threshold table 1301 as shown in the input area 1201 of FIG. 13(b). Here, when dithering pixel data in the K1 area of the monochrome image data command 901, the operation register is set to refer to the threshold table 1301. Also, when dithering pixel data in the K2 area of the monochrome image data command 901, the operation register is set to refer to the threshold table 1301. Also, when dithering pixel data in the K3 area of the monochrome image data command 901, the operation register is set to refer to the threshold table 1301. When performing dithering on pixel data in the K4 region of the monochrome image data command 901, the operation register is set to refer to the threshold table 1301.

The flow in which the image processing circuit unit 103 reads the threshold table setting values is the same as in the first embodiment.

The flow in which the image processing circuit (P) 715 having the dither circuits 1000a to 1000d in the image processing circuit unit 103 reads the operation register setting value is the same as in the first embodiment. Here, an operation register command 800 is set for the dither circuit units 1000a to 1000d, which indicates the start position of reference to the common threshold table for at least the threshold table block 1300 set in S1112 of FIG. 11.

Next, a flow in which the input/output control circuit unit 700 sets the control register setting value will be described. The data input unit 702 of the input/output control circuit unit 700 reads the control register setting value set by the CPU 100 and writes it to the register block 719. Here, at least the following control registers are written: A control register indicating the start addresses of the rectangular areas C0-0, C1-0, C2-0, and C3-0 in the input area 1201 set in S1110 of FIG. 11; A control register indicating the start addresses of the rectangular areas D0-0, D1-0, D2-0, and D3-0 in the output area 1205 set in S1110; A control register indicating the area size W*Bh of the rectangular area based on the size of the rectangular area determined in S1107. Next, a flow in which the input/output control circuit unit 700 reads the image processing execution command will be described. When the data input unit 702 of the input/output control circuit unit 700 reads the image processing execution command, it reads the control register set by the CPU 100 in S1110 of FIG. 11 from the register block 719. Then, the data input unit 702 reads out the input image data in units of a predetermined block from the input area 1201 based on these control register setting values, and stores the input image data in the intermediate buffer 703. Next, the data input unit 702 reads out the block data of the rectangular areas C0-0 to C3-0 stored in the intermediate buffer 703 in units of one pixel each, and inputs the data to the command generation unit 704. The command generation unit 704 sets the four pieces of image data corresponding to the rectangular areas C0-0 to C3-0 in the K1 area, K2 area, K3 area, and K4 area of the monochrome image data command 901, generates the monochrome image data command 901, and inputs the generated command to the command transmission unit 705.

Next, the flow of the image processing execution circuit unit 701 receiving the monochrome image data command 901 from the input/output control circuit unit 700 and performing parallel image processing will be described. The image processing circuit (1) 709 receives the monochrome image data command 901 from the input port 707 via the interconnect 706. The image processing circuit (1) 709 extracts four pixel data from the K1 to K4 areas of the monochrome image data command 901 and performs parallel image processing, stores the image data after parallel image processing in the K1 to K4 areas of the monochrome image data command 901, and outputs it to the output port 709. Next, the image processing circuit (2) 712 receives the monochrome image data command 901 from the input port 710 via the interconnect 706. The image processing circuit (2) 712 extracts four pixel data from the K1 to K4 areas of the monochrome image data command 901 and performs parallel image processing, stores the image data after parallel image processing in the K1 to K4 areas of the monochrome image data command 901, and outputs it to the output port 711. Next, the image processing circuit (P) 715, which is the dither circuit unit 1000, receives the monochrome image data command 901 from the input port 713 via the interconnect 706.

The image processing circuit (P) 715 extracts four pixel data from the K1 to K4 areas of the monochrome image data command 901 and performs dither processing in parallel using the dither circuits 1000a to 1000d. The image data after dither processing is then stored in the K1 to K4 areas of the monochrome image data command 901 and output to the output port 714.

Here, the flow when the dither circuit 1000a of the image processing circuit (P) 715 receives the monochrome image data command 901 will be described with reference to FIG. 10. Note that the dither circuits 100b to 1000c differ in that they perform processing on areas K2 to K4 (division areas C1 to C3).

The flow of dither processing of the first monochrome image data command 901 by the dither circuit unit 1000a will be described. The command receiving unit 1001 receives the monochrome image data command 901. The command analyzing unit 1002 analyzes the identifier stored in the header area of the monochrome image data command 901 and interprets that the received command is the monochrome image data command 901. Furthermore, the command analyzing unit 1002 analyzes another identifier stored in the header area and interprets that the pixel position of the pixel data set in the monochrome image data command 901 is the first pixel of the rectangular area C0-0. Then, the pixel data of the K1 area of the monochrome image data command 901 is acquired. The dither processing unit 1006 requests the threshold data acquisition unit 1008 to acquire threshold data corresponding to the pixel data acquired by the command analyzing unit 1002. The threshold data acquisition unit 1008 manages the pixel positions of the pixel data specified in the monochrome image data command 901 in coordinate format. Specifically, as shown in Figure 12, the upper left corner of rectangular area C0-0 is the origin, the main scanning direction from left to right is the x coordinate, and the sub-scanning direction from top to bottom is the y coordinate. Here, the pixel position of each pixel data of rectangular area C0-0 stored in the K1 area of the monochrome image data command 901 is expressed as a common coordinate value K(x, y).

Since the pixel data of the monochrome image data command 901 is the first pixel of the rectangular area C0-0, the threshold data acquisition unit 1008 initializes the common coordinate value K(x,y) to (0,0). Next, the threshold data acquisition unit 1008 acquires the common reference start position K(b) indicating the beginning of the threshold table block 1300 written in S1112 from the register block 1004. Here, the reference start position is expressed as an element-by-element logical address of the threshold table with the upper left corner of the threshold table block 1300 as the origin. The threshold data acquisition unit 1008 calculates the logical address K(p0) of the threshold table corresponding to the coordinate value K(x,y) (shared with other dither circuits) of the rectangular area C0-0 stored in the K1 area of the monochrome image data command 901. Specifically, the calculation is performed as K(p0)=K(b)+y*W+x using the coordinate value K(x,y) and the width W of the threshold table acquired in S1101. Then, the threshold data acquisition unit 1008 acquires the threshold data K(q0) stored at logical address K(p0) of the threshold table block 1300.

The dither processing unit 1006 then acquires threshold data K(q0) from the threshold data acquisition unit 1008. The dither processing unit 1006 compares the pixel data stored in the K1 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K(q0) and performs binarization. Specifically, when the pixel data in the K1 area is equal to or greater than the threshold data K(q0), it is determined that a dot is to be printed, and when the pixel data in the K1 area is less than the threshold data K(q0), it is determined that a dot is not to be printed, and performs binarization to generate output pixel data K1(r0).

The dither processing unit 1006 of the dither circuit 1000b compares the pixel data stored in the K2 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K(q0) and performs binarization. Specifically, when the pixel data in the K2 area is equal to or greater than the threshold data K(q0), it is determined that a dot is to be printed, and when the pixel data in the K2 area is less than the threshold data K(q0), it is determined that a dot is not to be printed, and binarizes the data to generate the output pixel data K2(r0).

The dither processing unit 1006 of the dither circuit 1000c compares the pixel data stored in the K3 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K(q0) and performs binarization. Specifically, when the pixel data in the K3 area is equal to or greater than the threshold data K(q0), it is determined that a dot is to be printed, and when the pixel data in the K3 area is less than the threshold data K(q0), it is determined that a dot is not to be printed, and binarizes the data to generate the output pixel data K3(r0).

Furthermore, the dither processing unit 1006 of the dither circuit 1000d compares the pixel data stored in the K4 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K(q0) and performs binarization. Specifically, when the pixel data in the K4 area is equal to or greater than the threshold data K(q0), it is determined that a dot is to be printed, and when the pixel data in the K4 area is less than the threshold data K(q0), it is determined that a dot is not to be printed, and binarizes the data, outputting the output pixel data K4(r0).

Returning to the explanation of the dither circuit 1000a, the coordinate update unit 1007 then updates the common coordinate value K(x,y) that indicates the pixel position of the pixel data managed by the threshold data acquisition unit 1008. In this embodiment, the pixels in the rectangular area C0-0 are processed sequentially from top to bottom in the sub-scanning direction. However, the pixel scanning direction may be configured to process image data sequentially in parallel from left to right in the main scanning direction.

The coordinate update unit 1007 shifts the pixel position downward by one with respect to the y coordinate at the initialized common coordinate K(x,y). Specifically, it adds 1 to the value of the y coordinate and updates the pixel position of the pixel data specified in the next monochrome image data command to K1(x,y+1). Next, the command generation unit 1009 sets the pixel data K1(r0) resulting from the dither processing by the dither processing unit 1006 in the K1 area of the monochrome image data command 901. The command transmission unit 1010 outputs the monochrome image data command 901 generated by the command generation unit 1009 to the output port 714.

Next, the flow of dither processing by the dither circuit unit 1000a on the second monochrome image data command 901 will be described. The command receiving unit 1001 receives the monochrome image data command 901. The command analyzing unit 1002 analyzes the identifier stored in the header area of the monochrome image data command 901 and interprets that the received command is the monochrome image data command 901. Then, pixel data is obtained from the K1 area of the monochrome image data command 901. The dither processing unit 1006 requests the threshold data obtaining unit 1008 to obtain threshold data corresponding to the pixel data obtained by the command analyzing unit 1002. The pixel position of the pixel data of the rectangular area C0-0 stored in the K1 area of the monochrome image data command 901 is the coordinate value K(x, y+1) common to each dither circuit. The threshold data obtaining unit 1008 obtains this common coordinate value K(x, y+1). Next, the threshold data acquisition unit 1008 acquires from the register block 1004 the common reference start position K(b) that indicates the beginning of the threshold table block 1300 written in S1112. The threshold data acquisition unit 1008 calculates the logical address K(p1) of the threshold table corresponding to the common coordinate value K(x, y+1) of the rectangular area C0-0 stored in the K1 area of the monochrome image data command 901. Specifically, the calculation is performed as K(p1) = K(b) + (y+1) * W + x using the coordinate value K(x, y+1) and the width W of the threshold table acquired in S1101. Then, the threshold data acquisition unit 1008 acquires the threshold data K(q1) stored at the logical address K(p1) of the threshold table block 1300.

Next, the dither processing unit 1006 acquires threshold data K(q1) from the threshold data acquisition unit 1008. The dither processing unit 1006 compares the pixel data stored in the K1 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K(q1) and performs binarization. Specifically, when the pixel data in the K1 area is equal to or greater than the threshold data K(q1), it is determined that a dot is to be printed, and when the pixel data in the K1 area is less than the threshold data K(q1), it is determined that a dot is not to be printed, thereby performing binarization and generating output pixel data K1(r1).

The dither processing unit 1006 of the dither circuit 1000b compares the pixel data stored in the K2 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K(q1) and performs binarization. Specifically, when the pixel data in the K2 area is equal to or greater than the threshold data K(q1), it determines that a dot is to be printed, and when the pixel data in the K2 area is less than the threshold data K(q1), it determines that a dot is not to be printed, performs binarization, and generates the output pixel data K2(r1).

The dither processing unit 1006 of the dither circuit 1000c compares the pixel data stored in the K3 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K(q1) and performs binarization. Specifically, when the pixel data in the K3 area is equal to or greater than the threshold data K(q1), it determines that a dot is to be printed, and when the pixel data in the K3 area is less than the threshold data K(q1), it determines that a dot is not to be printed, performs binarization, and generates the output pixel data K3(r1).

The dither processing unit 1006 of the dither circuit 1000d then compares the pixel data stored in the K4 area of the monochrome image data command 901 acquired by the command analysis unit 1002 with the threshold data K(q1) and performs binarization. Specifically, when the pixel data in the K4 area is equal to or greater than the threshold data K(q1), it determines that a dot is to be printed, and when the pixel data in the K4 area is less than the threshold data K(q1), it determines that a dot is not to be printed, performs binarization, and outputs the output pixel data K4(r1).

Returning to the explanation of the dither circuit 1000a, the coordinate update unit 1007 then updates the common coordinate value K(x, y+1) that indicates the pixel position of the pixel data managed by the threshold data acquisition unit 1008. The coordinate update unit 1007 shifts the pixel position down by one in the sub-scanning direction, i.e., in the y coordinate, with respect to the common coordinate K(x, y+1) that indicates the pixel data of the second monochrome image data command. Specifically, it adds 1 to the y coordinate value, and updates the pixel position of the pixel data specified in the next monochrome image data command to K(x, y+2). This is the same as updating the pixel positions in the other dither circuits 1000a.

The command sending unit 1010 outputs the monochrome image data command 901 generated by the command generating unit 1009 to the output port 714.

Based on the above flow, the dither circuit unit 1000 performs dither processing on the third and subsequent monochrome image data commands 901, and repeats dither processing for the number of pixels in the rectangular area. Here, when the value of each y coordinate indicates a pixel at the bottom of the rectangular area, the coordinate update unit 1007 of each dither circuit shifts the x coordinate by one pixel to the right column of the rectangular area as the pixel position to be processed next, and controls the y coordinate to return to the top of the rectangular area. Specifically, when y=Bh-1, the coordinate update unit 1007 sets the coordinate value to (x+1,0), adds 1 to the value in the x coordinate direction, and sets the value in the y coordinate direction to 0. Furthermore, based on the pixel position analyzed by the command analysis unit 1002, when the value of each y coordinate indicates a pixel at the bottom of the rectangular area C0-0 to C3-0 and the value of each x coordinate is the length W-1 of the threshold table shown in FIG. 13, the coordinate update unit 1007 sets the coordinate value to (0,0).

When the input/output control circuit unit 700 of each dither circuit completes output of rectangular areas D0-0 to D3-0, it issues an interrupt to the CPU 100 to notify it that parallel image processing of input area 1201 is complete. When the software running on the CPU 100 receives the interrupt from the input/output control circuit unit 700, it controls the parallel image processing of input area 1202, and then controls the parallel image processing of input area 1203.

As described above, by dividing the image area into the maximum threshold table size that the threshold table block of the dither circuit section can represent and performing parallel image processing, the threshold table corresponding to the pixel position in the sub-scanning direction of the image area can be referenced in the dither processing of each rectangular area. This makes it possible to improve processing performance without degrading the blue noise characteristics of the threshold table corresponding to the image area. Furthermore, it is possible to reference a single threshold table in the dither processing of each rectangular area, and a single access circuit can be configured for the threshold table block of the dither circuit.

In the above embodiment, parallel image processing for four rectangular regions has been described. However, parallel image processing for two or more input rectangular regions may also be implemented.

In the above embodiment, an example was described in which a monochrome image area is divided into rectangular areas and parallel image processing is performed. However, the input image area does not necessarily have to be monochrome, and the input image area may be colored. Specifically, the method of the first embodiment may be used to realize parallel image processing of one or more C rectangular areas, one or more M rectangular areas, one or more Y rectangular areas, and one or more K rectangular areas for a frame-sequential image area of four colors CMYK.

In the above embodiment, the size of the input image area and the size of the output image area are the same, and the number of parallel processes Vn for the input image area and the number of parallel processes Vn for the output image area are equal. However, parallel image processing may be realized in which the size of the input image area and the size of the output image area are different, and the number of parallel processes Vn for the input image area and the number of parallel processes Vn for the output image area are different.

In the above embodiment, an example was described in which the number of color components in the input image is the same as the number of color components in the output image. However, the number of colors in the input image and the output image may differ, such as when image processing is performed on an input image with three RGB color components and an output image with four CMYK color components is output.

In the above embodiment, a single threshold table is referenced to dither a monochrome image. However, a configuration in which multiple different threshold tables corresponding to different colors are referenced to dither a color image may also be used.

As described above, according to the first and second embodiments, the image area is divided into rectangular areas according to the capacity of the memory area that stores the threshold table of the image processing circuit, and parallel image processing is performed, thereby improving processing performance without degrading the blue noise characteristics of the threshold table corresponding to the image area.

In the above embodiment, dither processing is used as an example of processing that uses matrix data, but the processing is not limited to dither processing, and can be applied as long as the processing refers to matrix data.

Other Examples
The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

The invention is not limited to the above-described embodiment, and various modifications and variations are possible without departing from the spirit and scope of the invention. Therefore, the following claims are appended to disclose the scope of the invention.

100...CPU, 101...RAM, 102...102 ROM, 103...image processing circuit section, 104...I/F section, 105...bus

Claims (7)

An image processing device that processes image data based on matrix data composed of a plurality of setting values arranged in a matrix,
a plurality of processing circuits, each of which has a memory area for storing the setting values therein and performs image processing based on the setting values set in the memory area and input image data;
a determining means for determining a size of a partial area when the matrix data is divided based on a size of the matrix data to be used and a size of the storage area;
a setting means for setting the partial region setting values determined by the determining means to the plurality of processing circuits;
A dividing means for dividing the image data into a plurality of partial image data based on the size of the partial region;
a control means for controlling the plurality of processing circuits to cause each of the processing circuits to execute processing on the partial image data divided by the dividing means;
13. An image processing device comprising: The determining means is
Dividing the image data along a sub-scanning direction into a plurality of rectangular regions each having a height determined based on the size of the matrix data and the matrix that can be stored in the storage area;
The setting means is
2. The image processing device according to claim 1, further comprising: dividing the matrix data into partial matrix data having the height of the rectangular area along the sub-scanning direction; and setting, of the partial matrix data obtained by the division, partial matrix data corresponding to the number of the processing circuits in the memory area of the corresponding processing circuit. The determining means is
Dividing the image data into rectangular regions along a main scanning direction, the rectangular regions having widths determined based on the size of the matrix data and the matrix that can be stored in the storage area, and the number of the rectangular regions being equal to the number of the processing circuits;
The setting means is
3. The image processing apparatus according to claim 2, wherein common partial matrix data having the height of the rectangular area of the matrix data is set in a storage area of each of the processing circuits. The image processing device according to claim 3, characterized in that the determining means adds a dummy area to the image data to be processed so that the width of the rectangular area is an integer multiple of the width of the matrix data. The image processing device according to any one of claims 1 to 4, characterized in that each of the plurality of processing circuits is a circuit that performs dither processing of image data using a setting value stored in the storage area as a threshold value. A control method for an image processing device having a plurality of processing circuits, each having a memory area for storing a setting value therein, and performing image processing based on the setting value set in the memory area and input image data, the method utilizing the plurality of processing circuits to process image data based on matrix data composed of a plurality of setting values arranged in a matrix, comprising:
a determining step of determining a size of a partial area when the matrix data is divided based on a size of the matrix data to be used and a size of the storage area;
a setting step of setting the partial region setting values determined in the determining step in the plurality of processing circuits;
A dividing step of dividing the image data into a plurality of partial image data based on the sizes of the partial regions;
a control step of controlling the plurality of processing circuits to cause each of the processing circuits to execute processing on the partial image data divided in the dividing step;
13. A method for controlling an image processing apparatus comprising the steps of: A program that, when read and executed by a computer, causes the computer to execute each step of the method according to claim 6.

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