JP7615142B2 - FAN-OUT STRUCTURE FOR LIGHT EMITTING DIODE DEVICES AND LIGHTING SYSTEMS - Patent application - Google Patents

Description

(Reference to Related Applications)
This application claims the benefit of U.S. Non-provisional Application No. 16/750,824, filed January 23, 2020, European Patent Application No. 20158288.9, filed February 19, 2020, U.S. Provisional Application No. 62/951,601, filed December 20, 2019, and U.S. Provisional Application No. 62/937,629, filed November 19, 2019, the contents of which are incorporated herein by reference.

Precisely controlled lighting applications may require the creation and manufacture of small addressable light emitting diode (LED) lighting systems. The smaller size of such systems may require non-traditional components and manufacturing processes.

An LED lighting system, vehicle headlamp system, and manufacturing method are described. The LED lighting system includes a silicon backplane having a top surface, a bottom surface, and a side surface, and a substrate surrounding the sides of the silicon backplane, the substrate having a top surface, a bottom surface, and a side surface. A first redistribution layer is provided on the top surface of the silicon backplane and the top surface of the substrate. A second redistribution layer is provided on the bottom surface of the silicon backplane and the bottom surface of the substrate. At least one via extends through the substrate between the first redistribution layer and the second redistribution layer and is filled with a metal material.

A more detailed understanding can be had from the following description, given by way of example in conjunction with the accompanying drawings, in which:

FIG. 2 is a top view of an exemplary LED array.

1 is a cross-sectional view of an exemplary LED lighting system.

FIG. 1C is a top view of the exemplary LED lighting system of FIG.

FIG. 1C is a bottom view of the exemplary LED lighting system of FIG.

FIG. 1C is a cross-sectional view of an exemplary application system incorporating the LED lighting system of FIG.

FIG. 1C is a diagram of an exemplary vehicle headlamp system incorporating the LED lighting system of FIG.

FIG. 2 is a diagram of another exemplary vehicle headlamp system.

1C is a flow diagram of an exemplary method for manufacturing an LED lighting system such as the LED lighting system of FIG. 1B.

1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process. 1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process. 1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process. 1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process. 1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process. 1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process. 1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process. 1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process. 1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process. 1A-1D are cross-sectional views of an LED lighting system at various stages in a manufacturing process.

FIG. 6F is a bottom view illustrating the bottom of the LED lighting system of FIG. 6E.

Examples of different light illumination systems and/or light emitting diodes ("LEDs") are described more fully below with reference to the accompanying drawings. These examples are not mutually exclusive, and configurations found in one example may be combined with configurations found in one or more other examples to achieve additional implementations. Accordingly, it will be understood that the examples shown in the accompanying drawings are provided for illustrative purposes only, and that they are not intended to limit the present disclosure in any manner. Like numbers refer to like elements throughout.

Although terms such as first, second, third, etc. may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms may be used to distinguish one element from another element. For example, a first element may be referred to as a second element and a second element may be referred to as a first element without departing from the scope of the present invention. As used herein, the term "and/or" may include any and all combinations of one or more items of the associated listed items.

When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that it may be directly on or extending directly onto the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there may be no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that it may be directly connected or coupled to the other element and/or connected or coupled to the other element via one or more intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements between the element and the other element. It will be understood that these terms are intended to encompass different orientations of the elements in addition to any orientations shown in the figures.

Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

Furthermore, whether the LEDs, LED arrays, electrical components and/or electronic components are contained on one, two or more electronic boards may also depend on design constraints and/or application.

Optical power emitting devices, such as semiconductor light emitting devices (LEDs) or devices that emit ultraviolet (UV) or infrared (IR) optical power, are among the most efficient light sources currently available. These devices (hereafter "LEDs") may include light emitting diodes, resonant cavity light emitting diodes, vertical cavity laser diodes, edge emitting lasers, or the like. For example, due to their compact size and lower power requirements, LEDs may be attractive candidates for many different applications. For example, they may be used as light sources (e.g., flashlights and camera flashes) for handheld battery-powered devices such as cameras and mobile phones. They may also be used, for example, for automotive lighting, head-up display (HUD) lighting, horticultural lighting, street lighting, video torches, general lighting (e.g., home, store, office, studio lighting, theater/stage lighting, and architectural lighting), augmented reality (AR) lighting, virtual reality (VR) lighting, backlighting for displays, and IR spectroscopy. A single LED may provide less bright light than an incandescent light source, therefore, for applications where more brightness is desired or required, multi-junction devices or arrays of LEDs (such as monolithic LED arrays, micro LED arrays, etc.) may be used.

FIG. 1A is a top view of an exemplary LED array 102. In the example shown in FIG. 1A, the LED array 102 is an array of emitters 120. LED arrays may be used for any application, such as those requiring precise control of the LED array emitters. The emitters 120 in the LED array 102 may be individually addressable or may be addressable in groups/subsets.

1A. As shown in the exploded view of the 3×3 portion, the LED array 102 may include emitters 120 each having a width w1. In an embodiment, the width w1 may be about 100 μm or less (e.g., 40 μm). The lanes 122 between the emitters 120 may be a width w2. In an embodiment, the width w2 may be about 20 μm or less (e.g., 5 μm). The lanes 122 may provide an air gap between adjacent emitters or may include other materials. The distance d1 from the center of one emitter 120 to the center of an adjacent emitter 120 may be about 120 μm or less (e.g., 45 μm). It will be understood that the widths and distances provided herein are merely exemplary and that actual widths and/or dimensions may vary.

Although rectangular emitters arranged in a symmetric matrix are shown in FIG. 1A, it will be understood that emitters of any shape and arrangement may be applied to the embodiments described herein. For example, the LED array 102 of FIG. 1A may include over 20,000 emitters in any applicable configuration, such as a 200×100 matrix, a symmetric matrix, an asymmetric matrix, or the like. It will also be understood that multiple sets of emitters, matrices, and/or substrates may be arranged in any applicable format to implement the embodiments described herein.

As mentioned above, LED arrays such as LED array 102 may contain up to 20,000 emitters or more. Such arrays may have a surface area of 90 mm2 or more and may require significant power to power them, such as 60 watts or more. Such LED arrays are sometimes referred to as micro-LED arrays or simply micro-LEDs. Micro-LEDs may include an array of individual emitters provided on a substrate, or may be a single silicon wafer or die that is divided into segments that form the emitters. The latter type of micro-LEDs are sometimes referred to as monolithic LEDs.

To individually drive or control each LED in the array, a silicon backplane may be provided in close proximity to the LED array, which may become very hot during operation. Thus, heat dissipation may be difficult for such devices. Although several solutions are known for heat dissipation for semiconductor devices, such solutions often include structures that dissipate heat through the top of the device. However, due to light emission, LED arrays such as LED array 102 of FIG. 1A may not be able to dissipate heat through the top of the device.

In addition, LED arrays such as LED array 102 may be used in applications such as vehicle headlamp systems that may include passive elements, such as resistors and capacitors, that may form drivers, controllers, and other circuitry. It may be desirable to package at least some of the passive elements in the LED array.

The embodiments described herein may provide a low profile LED array package that may house one or more passive elements and may allow for dissipation of heat generated by the silicon backplane and the LED array.

FIG. 1B is a cross-sectional view of an exemplary LED lighting system 100. In the example shown in FIG. 1B, the LED lighting system 100 includes a silicon backplane 104. The silicon backplane 104 has a top surface 101, a bottom surface 103, and a side surface 105. The side surface 105 of the silicon backplane 104 is surrounded by a substrate 106 formed from a molding material. The substrate 106 has a top surface 107, a bottom surface 109, and a side surface 190. One or more metal layers 110 or redistribution layers (shown in an alternative embodiment in FIG. 6E) are provided on the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106. The RDL 117 may be formed on at least a portion of the top surface 101 of the silicon backplane 104 and the top surface 107 of the substrate 106. In the example shown in FIG. 1B, the RDL 117 includes two layers 116a and 116b of dielectric material 116 and a single metal layer 112. One or more vias 108 may extend through the substrate 106 and may be filled with a metal material. Thus, the vias may form a continuous electrical connection between the silicon backplane 104, the RDL 117, and the metallization/RDL 110. An LED array, such as the LED array 102 of FIG. 1A, may be provided on the top surface 101 of the silicon backplane 104 and electrically coupled thereto via an array of metal connectors (not shown in FIG. 1B). In an embodiment, an electronic component 114 may be provided on the RDL 117 and electrically coupled to the LED lighting system 100 via the metal layer 112.

The LED array 102 may be a micro LED as described above with respect to FIG. 1A. The LED array 102 may have a depth d1. In an embodiment, the depth d1 may be, for example, between 5 and 250 μm.

The silicon backplane 104 may include circuitry and connectors that provide individually addressable connections to the emitters in the LED array 102. In an embodiment, the silicon backplane may be a complementary metal-oxide semiconductor (CMOS) integrated circuit, which may be an application specific integrated circuit (ASIC) in an embodiment. The silicon backplane 104 may have a depth d3. In an embodiment, the depth d3 may be, for example, 100 μm to 1 mm.

The structure consisting of silicon backplane 104, substrate 106, metallization/RDL 110, RDL 117 and vias 108 may have a depth d2. In an embodiment, depth d2 may be, for example, 100 μm to 1 mm. Because silicon backplane 104 is integrated into the substrate and LED array 102 is provided on top of silicon backplane 104, LED lighting system 100 may have a lower profile than a system that stacks one or more of these elements vertically.

In the example shown in FIG. 1B, the RDL 117 includes two layers 116a and 116b of dielectric material 116 and a single metal layer 112. The first layer 116a of the two layers of dielectric material 116 may be on at least a portion of the top surface 107 of the substrate 106 and the top surface 101 of the silicon backplane 104. The metal layer 112 may be patterned on the first layer 116a of dielectric material 116, for example, by copper plating and copper etching. The second layer 116b of dielectric material 116 may be on top of the patterned metal layer 112 and on the exposed portion of the first layer 116a of dielectric material 116. Although an RDL consisting of two layers of dielectric material and a single metal layer is shown in FIG. 1B, one skilled in the art will recognize that the RDL 117 may include more or fewer layers of dielectric material and/or multiple metal layers depending on design constraints. The dielectric material 116 may be any suitable dielectric material. In an embodiment, the dielectric material may be a polymer dielectric material, such as polyimide.

The RDL 117 may extend from the peripheral region of the silicon backplane 104 toward the side 190 of the substrate 106. It may house the LED array 102 attached to the top surface 101 of the silicon backplane 104 in a central region and may aid in heat dissipation by housing a dielectric material that may further insulate the LED lighting system 100 to areas away from the highest heat region in the center of the LED lighting system 100. The metal layer 112 may have portions exposed from the dielectric material 116 to form bond pads. The metal layer 112 may include portions that extend between the peripheral region of the silicon backplane 104 and the bond pads to create a continuous electrical connection therebetween. The bond pads may be electrically coupled to the vias 108 to form a continuous electrical connection between the top and bottom surfaces of the LED lighting system 100. The bond pads may be located in a peripheral region of the substrate, or may be spaced apart from, but closer to, the LED array (e.g., as shown in FIG. 1C).

The metallization/RDL 110 may be formed in a number of different ways. In the example shown in FIG. 1B, the metallization/RDL 110 is a metal layer that includes a first portion that is electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in a central region and a second portion that fans out from a peripheral region of the silicon backplane 104 toward the side 190 of the substrate 106. In an embodiment, the first and second portions may be electrically isolated from each other. Although not visible in FIG. 1B, the second portion may extend from the silicon backplane 104 and join with the individual vias 108 at bond pads to electrically couple the silicon backplane 104 to the metal layer 112 at the top surface. Both the first and second portions of the metal layer 110 may be coupled to an external circuit board (not shown), for example, by soldering. This may allow for direct connection between the LED lighting system 100 and an external circuit board, which provides improved heat sinking through the bottom of the LED lighting system. In addition, this structure may allow communication between the silicon backplane 104, the LED array 102, the passive components 114 on the substrate 106, and any electronic components on the external circuit board.

In another example, described in more detail below with respect to Figures 6E and 7, the metallization/RDL 110 may be a combination of a metal layer and an RDL. Similar to the embodiment shown in Figure 1B, the metal layer may be electrically and thermally coupled to the bottom surface 103 of the silicon backplane 104 in the central region. However, the fan-out may be achieved using an RDL instead of a metal layer. In such an embodiment, the LED lighting device 100 may have an RDL on both the top and bottom surfaces.

In both cases, the metallization/RDL 110 may be a thin structure compared to conventional silicon device packages and may contain significantly less dielectric material than conventional silicon device packages. For example, the metal layer 100 in the embodiment shown in FIG. 1B may be a single metal layer and the RDL may contain as few dielectric layers as possible. This increases the efficiency of heat dissipation in such packages and enables packaging for micro-LEDs and CMOS backplanes that can radiate substantial heat.

In the LED lighting system 100 shown in FIG. 1B, the top surface 101 of the silicon backplane 104 and the top surface 107 of the substrate 106 are in the same plane. Similarly, the bottom surface 103 of the silicon backplane 104 and the bottom surface 109 of the substrate 106 are in the same plane. This configuration may allow for the smallest possible packaging and ease of manufacturing. However, one skilled in the art will appreciate that since the substrate 106 is molded, it may take any shape, such as, for example, the substrate 106 having a top surface 107 that is higher than the top surface 101 of the silicon backplane 104 to further separate the electronic components 114 from the high heat areas of the LED lighting system 100. Thus, in embodiments, these surfaces may not be in the same plane.

1C is a top view of the top surface 130 of the exemplary LED lighting system 100 of FIG. 1B. In the example shown in FIG. 1C, the top surface 130 of the LED lighting system includes a top layer 116b of the dielectric material 116 in the RDL 117. The electronic component 114 is electrically coupled to the metal 112 in the RDL and is exposed from the dielectric material 116. In an embodiment, the electronic component 114 may not be electrically coupled to all areas of the metal 112, and thus the top surface 130 may also include some areas of the metal 112 exposed from the dielectric material 116 in an embodiment. The top surface of at least a portion of the silicon backplane 104 is shown in FIG. 1C, including the portion of the top surface of the silicon backplane 104 that is not covered by the LED array 102 or the dielectric material 116. The top surface of the LED array 102 is also shown attached to the top surface of the silicon backplane 104.

1C, the LED lighting system 100 has a length _l1 and a width _w1 . In an embodiment, the length _l1 may be about 20 mm, and the width _w1 may be about 15 mm. The silicon backplane 104 may have a length _l2 and a width _w2 . In an embodiment, the length _l2 may be about 15.5 mm, and the width _w2 may be about 6.5 mm. The LED array 102 may have a length _l3 and a width _w3 . In an embodiment, the length _l3 may be about 11 mm, and the width _w3 may be about 4.4 mm.

Given these exemplary dimensions, an LED array package may be provided having a relatively large surface area (300 ^mm2 in the above example) with a relatively large amount of surface area not occupied by the LED array (which in the above example has a surface area of approximately 100 ^mm2 ). This design therefore provides ample space for mounting electronic components on the LED array package.

1D is a bottom view of the bottom surface 140 of the exemplary LED lighting system 100 of FIG. 1B. In the example shown in FIG. 1D, the bottom surface 140 includes an area of the substrate 106 and an area of metal 110 exposed from the molding compound 106 or solder pads coupled thereto. In embodiments, some areas of the substrate may be covered by portions of the RDL and/or metallization that interconnect the silicon backplane and the bond pads, which are not shown in FIG. 1D. In some embodiments, the interconnecting metal areas and/or the RDL may be covered by a dielectric material or other encapsulating or protective material (not shown in FIG. 1D).

FIG. 2 is a cross-sectional view of an application system 200 incorporating the LED lighting system 100 of FIG. 1B. The application system 200 may include a circuit board 150 having a number of bond pads 152. In the example shown in FIG. 2, the exposed metal areas/bond pads of the RDL/metallization 110 of the LED lighting system 100 are directly bonded to the bond pads 152 of the circuit board 150. As mentioned above, the direct bond between the metal layer 110 on the bottom side of the silicon backplane 104 and the circuit board 150 allows for efficient heat transfer from the LED lighting system 100 to the circuit board 150 for heat sinking purposes, for example, without the need for additional heat dissipation structures on the top of the LED lighting system 100 (or elsewhere) that may otherwise block light emission from the LED array 102. The circuit board 150 may be part of a larger system used in a particular application, such as a vehicle lighting or flash application (an exemplary vehicle lighting system is described below with respect to FIGS. 3 and 4). In such a system, some of the passive components used in the application may be components 114 and may be provided directly on the LED lighting system 100 prior to attachment to the circuit board 150. The circuit board 150 may include other circuit elements required for the larger system in addition to a heat sink. The RDL 117, RDL/metallization 110 and vias 108 may provide a continuous electrical connection between the components 114, the silicon backplane 104 and the circuit board 150.

3 is a diagram of an exemplary vehicle headlamp system 300 that may incorporate the LED lighting system 100 of FIG. 1B. The exemplary vehicle headlamp system 300 shown in FIG. 3 includes a power line 302, a data bus 304, an input filter and protection module 306, a bus transceiver 308, a sensor module 310, an LED direct current to direct current (DC/DC) module 312, a logic low dropout (LDO) module 314, a microcontroller 316, and an active headlamp 318. In an embodiment, the active headlamp 318 may include an LED lighting system, such as the LED lighting system 100 of FIG. 1B. As mentioned above, the LED lighting system 100 provides sufficient space and bond pads on the top surface of the substrate such that one, multiple, or all of the modules shown in FIG. 3 may be accommodated on the top surface of the LED lighting system 100. Modules that are not provided on the top surface of the LED lighting system 100 may be provided on the circuit board 150 (as shown in FIG. 2). In some embodiments, some electronic components of some or all of the modules in the vehicle lighting system 300 may be housed on the top surface of the LED lighting system 100 and some may be provided on the circuit board 150 (as shown in FIG. 2).

The power line 302 may have an input to receive power from the vehicle, and the data bus 304 may have inputs/outputs that may exchange data between the vehicle and the vehicle headlamp system 300. For example, the vehicle headlamp system 300 may receive commands from elsewhere in the vehicle, such as commands to turn on turn signaling or commands to turn on headlamps, and may send feedback to elsewhere in the vehicle, if desired. The sensor module 310 may be communicatively coupled to the data bus 304 and may provide additional data to the vehicle headlamp system 300 or elsewhere in the vehicle, for example, related to environmental conditions (e.g., time of day, rain, fog, or ambient light levels), vehicle status (e.g., parked, in motion, speed of motion, or direction of motion), and the presence/location of other objects (e.g., vehicles or pedestrians). A headlamp controller, separate from any vehicle controller communicatively coupled to the vehicle data bus, may also be included in the vehicle headlamp system 300. In FIG. 3, the headlamp controller may be a microcontroller, such as a microcontroller (μc) 316. The microcontroller 316 may be communicatively coupled to the data bus 304.

The input filter and protection module 306 may be electrically coupled to the power line 302 and may support various filters to, for example, reduce conducted emissions and provide power immunity. Additionally, the input filter and protection module 306 may provide electrostatic discharge (ESD) protection, load-dump protection, alternator field decay protection, and/or reverse polarity protection.

An LED DC/DC module 312 may be coupled between the filter and protection module 306 and the active headlamp 318 to receive the filtered power and provide a drive current to power the LEDs in the LED array in the active headlamp 318. The LED DC/DC module 312 may have an input voltage between 7-18 volts with a nominal voltage of about 13.2 volts (e.g., as determined by factors or local calibration and operating condition adjustments due to load, temperature or other factors) and an output voltage that may be slightly higher (e.g., 0.3 volts) than the maximum voltage of the LED array.

The logic LDO module 314 may be coupled to the input filter and protection module 306 to receive filtered power. The logic LDO module 314 may also be coupled to the microcontroller 314 and the active headlamp 318 to provide power to a silicon backplane (e.g., CMOS logic) within the microcontroller 314 and/or the active headlamp 318.

The bus transceiver 308 may have, for example, a universal asynchronous receiver transmitter (UART) or serial peripheral interface (SPI) interface and may be coupled to a microcontroller 316. The microcontroller 316 may convert vehicle input based on or including data from the sensor module 310. The converted vehicle input may include a video signal that can be transferred to an image buffer in the active headlamp module 318. In addition, the microcontroller 316 may load a default image frame and test for open/short pixels during startup. In an embodiment, the SPI interface may load an image buffer in the CMOS. The image frame may be a full frame, a differential frame, or a partial frame. Other configurations of the microcontroller 316 may include a control interface monitoring of CMOS status including die temperature as well as a logic LDO output. In an embodiment, the LED DC/DC output may be dynamically controlled to minimize headroom. In addition to providing image frame data, other headlamp functions may also be controlled, such as complementary use in conjunction with side marker or turn signal lights, and/or activation of daytime running lights.

FIG. 4 is a diagram of another exemplary vehicle headlamp system 400. The exemplary vehicle headlamp system 400 shown in FIG. 4 includes an application platform 402, two LED lighting systems 406 and 408, and optical systems 410 and 412. The two LED lighting systems 406 and 408 may be LED lighting systems such as the LED lighting system 100 of FIG. 1B, or may include the LED lighting system 100 in addition to some or all of the other modules in the vehicle headlamp system 300 of FIG. 3. In the latter embodiment, the LED lighting systems 406 and 408 may be vehicle headlamp subsystems.

The LED lighting system 408 may emit a light beam 414 (shown between arrows 414a and 414b in FIG. 4). The LED lighting system 406 may emit a light beam 416 (shown between arrows 416a and 416b in FIG. 4). In the embodiment shown in FIG. 4, a secondary optic 410 is adjacent to the LED lighting system 408, and light emitted from the LED lighting system 408 passes through the secondary optic 410. Similarly, a secondary optic 412 is adjacent to the LED lighting system 412, and light emitted from the LED lighting system 412 passes through the secondary optic 412. In an alternative embodiment, the secondary optic 410/412 is not provided in the vehicle headlamp system.

If a secondary optic 410/412 is included, the secondary optic 410/412 may be or may include one or more light guides. The one or more light guides may be edge lit or may have an internal opening that defines an internal edge of the light guide. The LED lighting systems 408 and 406 (or active headlamps of a vehicle headlamp subsystem) may be inserted into the internal openings of the one or more light guides such that they inject light into the internal edge (internal opening light guide) or external edge (edge lit light guide) of the one or more light guides. In an embodiment, the one or more light guides may be shaped in a desired manner, such as with a gradient, chamfer distribution, narrow distribution, wide distribution, or angular distribution, to direct the light emitted by the LED lighting systems 408 and 406.

The application platform 402 may provide power and/or data to the LED lighting systems 406 and/or 408 via lines 404, which may include one or more or portions of the power lines 302 and data bus 304 of FIG. 3. One or more sensors (which may be sensors within the system 300 or other additional sensors) may be internal or external to the housing of the application platform 402. Alternatively or additionally, as shown in the example LED lighting system 300 of FIG. 3, each LED lighting system 408 and 406 may include its own sensor module, connectivity and control module, power module, and/or LED array.

In an embodiment, vehicle headlamp system 400 may represent an automobile having a steerable light beam, where LEDs may be selectively activated to provide steerable light. For example, an array of LEDs (e.g., LED array 102) may be used to define or project a shape or pattern, or to illuminate only selective sections of a road. In an exemplary embodiment, infrared camera or detector pixels in LED systems 406 and 408 may be sensors (e.g., similar to sensors in sensor module 310 of FIG. 3) that identify portions of a scene (e.g., a road or pedestrian crossing) that require illumination.

5 is a flow diagram of an exemplary method 500 of manufacturing an LED lighting system, such as the LED lighting system 100 of FIG. 1B. FIGS. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I, and 6J are cross-sectional views of an LED lighting system at various stages of the manufacturing method. In an embodiment, the method 500 may produce a panel-level packaged high density LED lighting system.

In the exemplary method 500 of FIG. 5, a silicon backplane may be attached to a first carrier (502) to form a first structure. In an embodiment, the silicon backplane may be attached to a temporary (e.g., plastic) carrier via an adhesive material such as tape or a temporary adhesive. An example first structure 600A is shown in FIG. 6A and includes a silicon backplane 104, a first carrier 602, and an optional adhesive material 604.

The silicon backplane attached to the first carrier may be molded (504) to form a second structure. An example of a second structure 600B is shown in FIG. 6B and includes the first structure 600A of FIG. 6A with a molding material surrounding the sides of the silicon backplane 104. The molding material forms a substrate 106 with an embedded silicon backplane 104. In an embodiment, a mold may be placed over the structure 600A, filled with molding material, and cured. If necessary, excess molding material may be removed from the top surface of the silicon backplane. In an embodiment, the molding may be panel level molding, the molding material may be a polymer material, and the second structure 600B may be a plastic substrate with an embedded silicon backplane on a temporary substrate.

One or more vias may be formed (506) through the substrate to form a third structure. In an embodiment, the one or more vias may be formed using a laser or a drill. An example of a third structure 600C is shown in FIG. 6C and includes a silicon backplane 104 embedded within a substrate 106 with two vias 108 formed therethrough. At this stage, the silicon backplane 104 and substrate 106 with the vias 108 may remain attached to the first temporary carrier 602. The vias 108 may be filled with a metal material.

At least one metal layer may be formed on the silicon backplane and one surface of the substrate (508). This may be done in a number of different ways.

In some embodiments, a metal layer may be patterned or plated onto the silicon backplane and one surface of the substrate to form a fourth structure. FIG. 6D shows an example of a fourth structure 600D, which includes a third structure having a metal layer 110. As shown in FIG. 6D, the metal layer 110 forms bond pads over areas and vias that extend from the peripheral areas of the silicon backplane 104. A metal layer is also provided in a central region of one surface of the silicon backplane 104. The bottom view of the LED lighting system 100 shown in FIG. 1D shows an example of this.

In other embodiments, a metal layer may be formed on one surface of the silicon backplane in a central region, and a redistribution layer may be formed on one surface of the substrate and silicon backplane adjacent to the single metal layer to form a fifth structure. FIG. 6E shows an example 600E of the fifth structure, including a third structure having a single metal layer 618 and a redistribution layer 616. In the example shown in FIG. 6E, the redistribution layer 616 includes a layer of dielectric material 614 and a metal layer 612. Although three metal layers are shown in FIG. 6E, one, two, or more than three metal layers may be used as needed due to design constraints. The redistribution layer may be formed, for example, by alternating deposition of layers of dielectric material, selective removal of portions of the dielectric material (if needed), and patterning of the top metal layer. As can be seen in FIG. 6E, the metal layer 612 begins at a peripheral region of one surface of the silicon backplane and extends toward the side of the substrate. The metal layer 612 is electrically coupled between the silicon backplane 104 and the vias. A portion of the metal layer 612 may be exposed from the dielectric material 614 to form a solder pad, or a separate solder pad may be formed on the outermost surface of the outermost dielectric layer.

7 is a bottom view of the bottom surface 700 of the LED lighting system of FIG. 6E. Line 702 represents the outermost perimeter of the substrate. Line 104 represents the outermost perimeter of the area occupied by the silicon backplane 104 relative to the outermost perimeter of the substrate. Dashed line 704 indicates the boundary of the area between line 704 and the outermost perimeter of the silicon backplane 104, which may be referred to herein as the peripheral area of the silicon backplane 104. The metal layer 612 of the redistribution layer 616 may begin in the peripheral area and extend toward the side of the substrate (bounded by line 702). There is a gap between the boundary 704 of the peripheral area of the silicon backplane and the single metal layer 618 formed on one surface of the silicon backplane. This gap may be filled with a dielectric material, for example, as reflected in FIG. 6E.

The resulting structure of 508 (e.g., the fourth or fifth structure) may be inverted and attached (510) to a second carrier to form a sixth structure. In an embodiment, the structure (e.g., the fourth or fifth structure) may be attached to a temporary (e.g., plastic) carrier via an adhesive material such as tape or a temporary adhesive. The structure may be disposed with at least one metal layer adjacent to the second carrier. An example sixth structure 600G is shown in FIG. 6G and includes a second carrier 608 and an optional adhesive material 606. Once the structure is attached to the second carrier, the first carrier may be removed (512) to form a seventh structure. An example seventh structure 600G is shown in FIG. 6G.

A redistribution layer and an array of metal connectors may be formed (514) on the surface exposed by the removal of the second carrier to form an eighth structure. In an embodiment, the array of metal connectors may be formed by plating or otherwise patterning or forming an array of copper pillar bumps on the surface. An example eighth structure 600H is shown in FIG. 6H and includes metal connectors 640 and a redistribution layer 117, which includes at least one metal layer 112 and a dielectric material 116. As described above with respect to FIG. 6E, the redistribution layer may be formed by alternately depositing layers of dielectric material, selectively removing portions of the dielectric material (if necessary), and patterning a metal layer on top. In an embodiment, more than 20,000 (e.g., about 28,000) metal connectors may be formed on the surface.

The LED array may be attached (516) to the silicon backplane via the electrical connector to form a ninth structure. In an embodiment, this may be done by aligning the silicon backplane with the electrical connector and applying heat to reflow the solder copper material in the copper pillar bumps. The reflow may create an underfill under the LED array. In an embodiment, the LED array may be a monolithic LED array. An example ninth structure 600I is shown in FIG. 6I and includes the LED array 102 and the underfill.

The LED array may undergo a laser liftoff (LLO) process and phosphor integration (518). Optional passive components may be attached onto the exposed metal areas in the redistribution layer 117 to form a tenth structure. An example tenth structure 600J is shown in FIG. 600J and includes an LED array 102 with phosphor material 610 and passive components 114.

Optionally, the tenth structure, which may be an LED lighting system such as the LED lighting system 100 of FIG. 1B, may be attached (520) to an external circuit board, for example to incorporate the LED lighting system 100 into a vehicle headlamp or other application system.

Although the embodiments have been described in detail, those skilled in the art will appreciate, given the present disclosure, that modifications may be made to the embodiments described herein without departing from the spirit of the inventive concept. Accordingly, it is not intended that the scope of the invention be limited to the specific embodiments shown and described.

Claims (16)

1. A method of manufacturing a system, comprising:
Attaching the silicon backplane to a carrier;
molding the molding material over the carrier such that the molding material surrounds sides of the silicon backplane to form a structure including a substrate with an embedded silicon backplane, the structure having a first surface opposite the carrier, a second surface adjacent the carrier, and a side;
forming at least one via through the molding material;
filling the at least one via with a metallic material;
forming a metal layer over a central region of the first surface of the structure such that the metal layer is thermally coupled to the silicon backplane;
forming a redistribution layer on the first surface of the structure adjacent to the metal layer such that the redistribution layer is electrically insulated from the metal layer;
removing the carrier; and
forming an array of copper pillar bumps on a surface of the silicon backplane exposed by removing the carrier.
method. forming the redistribution layer
forming a first layer of dielectric material over the first surface of the structure;
patterning another metal layer over the first layer of dielectric material such that at least a portion of the another metal layer remains in contact with the at least one via and at least another portion of the another metal layer remains in contact with the silicon backplane;
forming a second layer of dielectric material over the metal layer and the first layer of dielectric material;
and removing portions of the second layer of dielectric material overlying areas of the further metal layer corresponding to bond pad locations.
The method of claim 1. The method of claim 2, further comprising attaching another carrier to the redistribution layer before removing the carrier. The method of claim 3, further comprising forming another redistribution layer on the second layer of the structure. aligning an array of LEDs with the array of copper pillar bumps;
and applying heat to reflow the copper pillar bump.
The method of claim 1. performing a laser lift-off on the LED array;
and providing phosphor integration over the LED array.
The method according to claim 5. The method of claim 5, wherein aligning the LED array with the array of copper pillar bumps includes aligning an LED array including up to 20,000 emitters with an array of copper pillar bumps including at least one copper pillar bump per emitter. 1. A method of manufacturing a system, comprising:
Attaching the silicon backplane to a carrier;
molding the molding material over the carrier such that the molding material surrounds sides of the silicon backplane to form a structure including a substrate with an embedded silicon backplane, the structure including a first surface opposite the carrier, a second surface adjacent the carrier, and a side;
forming at least one via through the molding material;
filling the at least one via with a metallic material;
patterning a metal layer on the first surface of the structure, the metal layer having a first portion thermally coupled to a bottom surface of the silicon backplane in a central region and a second portion extending from a peripheral region of the silicon backplane toward a side of the substrate and forming at least one bond pad over the at least one via , the second portion being electrically isolated from the first portion;
removing the carrier; and
forming an array of copper pillar bumps on a surface of the silicon backplane exposed by removing the carrier.
method. The method of claim 8, further comprising attaching another carrier to the metal layer before removing the carrier. The method of claim 9, further comprising forming another redistribution layer on the second surface of the structure. aligning an array of LEDs with the array of copper pillar bumps;
and applying heat to reflow the copper pillar bump.
The method according to claim 8. performing a laser lift-off on the LED array;
and performing phosphor integration on the LED array.
The method of claim 11. The method of claim 11, wherein aligning the LED array with the array of copper pillar bumps includes aligning an LED array including up to 20,000 emitters with an array of copper pillar bumps including at least one copper pillar bump per emitter. The method of claim 12 , further comprising attaching at least one electronic component to at least one redistribution layer over the molding material and the surface of the silicon backplane exposed by removing the carrier. The method of claim 1, wherein the silicon backplane and the metal layer have approximately the same length and width. The method of claim 8, wherein the silicon backplane and the metal layer have approximately the same length and width.

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