JP7615569B2 - Test method and test device - Google Patents

Description

The present invention relates to a method and device for testing semiconductor chips.

Conventionally, defect inspection has been performed based on images of semiconductor chips (see, for example, Japanese Patent Application Laid-Open No. 2003-233633). In the image test of semiconductor chips, there are cases where even chips that have no problem with electrical characteristics are judged to be defective.
Patent Document 1: JP 2009-044083 A

In image testing of semiconductor chips, it is desirable to reduce the number of cases in which products that have no electrical problems are judged to be defective.

In order to solve the above problem, a first aspect of the present invention provides a test method for testing semiconductor chips. The test method may include a reference distribution acquisition step. In the reference distribution acquisition step, a reference distribution for each defect mode generated from images of defects in a plurality of semiconductor chips may be acquired. The test method may include a judgment step. In the judgment step, the quality of the semiconductor chip may be judged based on the reference distribution.

The test method may include an image acquisition step. In the image acquisition step, an image of a defect in the semiconductor chip may be acquired. In the reference distribution acquisition step, a reference distribution may be generated from the image of the defect.

During the reference distribution creation stage, the reference distribution may be created on a wafer-by-wafer basis.

The test method may include an electrical characteristic acquisition step of acquiring electrical characteristics of a plurality of semiconductor chips. In a judgment step, the quality of the semiconductor chips may be judged based on the electrical characteristics and the reference distribution.

The test method may include a correlation acquisition step in which, for each semiconductor chip, defect images and electrical characteristics are associated with each other to acquire a correlation between the defect mode and the electrical characteristics.

During the correlation acquisition stage, the correlation between the defect mode and the electrical characteristics may be displayed for each defect mode.

In the judgment stage, the quality of the semiconductor chip may be judged based on a reference distribution of defect modes that have a high correlation with electrical characteristics.

In the assessment stage, the quality of the semiconductor chip may be determined by calculating the degree of impact of the defect on the semiconductor chip.

In the determination stage, the impact may be calculated based on whether the defect is within the active area of the semiconductor chip. In the determination stage, the impact may be calculated based on the distance between the defect and the gate of the semiconductor chip.

In the judgment stage, the quality of the semiconductor chip may be judged based on the difference from a reference distribution. In the judgment stage, the quality of the semiconductor chip may be judged based on the difference from an input reference distribution input by a user.

In a second aspect of the present invention, a test apparatus for testing semiconductor chips is provided. The test apparatus may include a reference distribution creation unit. The reference distribution creation unit may acquire a reference distribution for each defect mode generated from images of defects in a plurality of semiconductor chips. The test apparatus may include a judgment unit. The judgment unit may judge the quality of the semiconductor chip based on the reference distribution.

Note that the above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions.

FIG. 1 illustrates an example of a test apparatus 100 according to an embodiment of the present invention. FIG. 13 is a diagram illustrating an example of a reference distribution. FIG. 13 is a diagram showing another example of the reference distribution. 1 is a flow chart according to one embodiment of the present invention. The brightness distribution of an optical photograph of a defect image is taken and the image is binarized into black and white. 4 shows an example of the distribution of luminance values of each pixel included in a defect image before binarization. FIG. 11 is a diagram illustrating an example of a method for calculating an influence degree. 13 is a diagram in which the relationship between the influence degree and leakage current of a plurality of semiconductor chips 40 is plotted. FIG. 13 is a diagram illustrating the relationship between the judgment value of the influence degree and the matching rate. FIG. 13 is a flowchart showing how to obtain a correlation between a defect mode and an electrical characteristic. 1 is an example of an image acquired by the image acquisition unit 2 in the data measurement step S201. 13 is an example of an electrical characteristic acquired by the electrical characteristic acquiring unit 12 in the data measuring step S201. 13 is an example of an electrical characteristic acquired by the electrical characteristic acquiring unit 12 in the data measuring step S201. 13 is an example of an electrical characteristic acquired by the electrical characteristic acquiring unit 12 in the data measuring step S201. 13 is an example of an electrical characteristic acquired by the electrical characteristic acquiring unit 12 in the data measuring step S201. 13 is an example of an electrical characteristic acquired by the electrical characteristic acquiring unit 12 in the data measuring step S201. 13 is an example of an electrical characteristic acquired by the electrical characteristic acquiring unit 12 in the data measuring step S201. 13 is an example of an electrical characteristic acquired by the electrical characteristic acquiring unit 12 in the data measuring step S201. FIG. 11 is a flowchart showing the principal component analysis in the principal component analysis step S202. FIG. 13 is a diagram showing the results of the principal component analysis step S202. FIG. 13 is a flowchart showing a method for classifying electrical characteristics of a semiconductor chip 40 in the level division step S203. 11 is a diagram showing the classification results of electrical characteristics of a semiconductor chip 40 in the level division step S203. FIG. FIG. 2 is a diagram showing a method of feature extraction in the feature extraction step S205. FIG. 11 is a diagram showing the results of group division in the group division step S206. This is an example of the correlation acquired by the correlation acquiring unit 26 in correlation acquisition step S208. 13 is another example of the correlation acquired by the correlation acquiring section 26 in the correlation acquiring step S208.

The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

FIG. 1 is a diagram showing an example of a test device 100 according to an embodiment of the present invention. The test device 100 of this example includes an image acquisition unit 2, a camera control unit 4, a light source 6, a stage unit 8, a stage control unit 10, an electrical characteristic acquisition unit 12, a stand 14, a display unit 16, an operation unit 18, and a data processing unit 20. The test device 100 tests a semiconductor wafer 30. Similarly, the test device 100 tests semiconductor chips 40 that are separated by dicing the semiconductor wafer 30. As an example, a PIN diode is formed on the semiconductor chip 40.

The image acquisition unit 2 acquires images of defects in the multiple semiconductor chips 40 included in the semiconductor wafer 30. That is, the image acquisition unit 2 may acquire images of defects in the semiconductor wafer 30. In this example, the defects in the semiconductor chip 40 are crystal defects such as dislocations. The image of the defect may be an image obtained by irradiating the semiconductor wafer 30 with light and capturing scattered light and reflected light from the substrate surface in a predetermined area of the semiconductor chip 40 (for example, the entire semiconductor chip 40, or an area in which an element is formed in the semiconductor chip 40). In the image of the area, an area where a defect exists is displayed darker (or brighter) than an area where a defect does not exist. The image acquisition unit 2 is, for example, an optical system such as an image sensor provided in a camera. The image acquisition unit 2 is controlled by the camera control unit 4. The camera control unit 4 is, for example, a control system such as a signal processing device provided in the camera.

The light source 6 irradiates light onto the semiconductor wafer 30. The light irradiated by the light source 6 may include a visible light component, or may include a non-visible light component. The light source 6 may be capable of adjusting the intensity of each wavelength component of the irradiated light. In addition, the contrast of the image of the defect, etc., is adjusted by the light source 6.

A semiconductor wafer 30 including a plurality of semiconductor chips 40 is placed on the stage unit 8. The stage unit 8 is controlled by a stage control unit 10. The stage control unit 10 drives the stage unit 8 by controlling an actuator provided on the stage unit 8, and adjusts the relative position between the image acquisition unit 2 and the semiconductor wafer 30.

The electrical characteristic acquisition unit 12 acquires the electrical characteristics of the semiconductor chip 40 placed on the base 14. The electrical characteristic acquisition unit 12 may acquire the electrical characteristics of the semiconductor chip 40 cut out from the semiconductor wafer 30, or may acquire the electrical characteristics of the semiconductor chip 40 before it is cut out from the semiconductor wafer 30. The electrical characteristics of the semiconductor chip 40 include, but are not limited to, a leakage current that flows in a specified area of the semiconductor chip 40 when a specified voltage is applied to a specified terminal of the semiconductor chip 40. The electrical characteristic acquisition unit 12 may measure at least one of the magnitude, frequency, and rate of change of the voltage or current in the specified area of the semiconductor chip 40.

The data processing unit 20 controls the camera control unit 4, the stage control unit 10, and the electrical characteristic acquisition unit 12 to acquire images or electrical characteristics. In other words, the image acquisition unit 2, the stage unit 8, and the electrical characteristic acquisition unit 12 may be controlled by the data processing unit 20. The data processing unit 20 in this example is a computer including an arithmetic unit, a memory, a signal input/output device, etc. The operation unit 18 inputs a signal corresponding to the result of an operation by the user to the data processing unit 20. The operation unit 18 is, for example, a keyboard or a pointing device. The user can operate the test device 100 by operating the operation unit 18. The display unit 16 displays information corresponding to the display data input from the data processing unit 20.

The data processing unit 20 has a reference distribution creation unit 22, a judgment unit 24, and a correlation acquisition unit 26. The reference distribution creation unit 22 creates a reference distribution for each defect mode from an image of the defect. The defect mode is an index for evaluating the defect. The defect mode may be information indicating the attributes of the defect. The defect mode is, for example, the sum of the area of the defects in the semiconductor chip 40. The defect mode may also be the size of the defect or the number of defects. The defect mode may also be the sum of the area of a specific defect, the size of a specific defect, or the number of specific defects. The specific defect is, for example, a threading screw dislocation. Threading screw dislocations are known to be a cause of leakage current.

The reference distribution for each defect mode is a distribution obtained by plotting the number of semiconductor chips 40 or the number of defects when images of defects are evaluated for the defect mode. For example, the reference distribution is a histogram with the sum of the defect areas on the horizontal axis and the number of corresponding semiconductor chips 40 on the vertical axis. The reference distribution may also be a histogram with the size of the defects on the horizontal axis and the number of corresponding defects on the vertical axis. The reference distribution is a distribution that a good semiconductor chip 40 should have. The reference distribution may be generated from one or more semiconductor chips 40 that have been determined to be good in tests such as electrical tests. If it is known in advance that the defect rate is low, the average of the distributions of a large number of semiconductor chips 40 may be used as the reference distribution.

The judgment unit 24 judges the quality of the semiconductor chip 40 from the reference distribution created by the reference distribution creation unit 22. The semiconductor chip 40 to be judged may or may not be included in the semiconductor chip 40 used to create the reference distribution. When the reference distribution is a distribution of defects included in one semiconductor chip 40, the judgment unit 24 may compare the distribution of defects included in the semiconductor chip 40 to be judged with the reference distribution to judge the quality of the semiconductor chip 40. When the reference distribution is a distribution of the number of semiconductor chips 40, the judgment unit 24 may judge the quality of the semiconductor chip 40 based on where the semiconductor chip 40 to be judged is located in the reference distribution. In other words, the judgment unit 24 may judge the quality of the semiconductor chip 40 from information obtained from an image of defects in the semiconductor chip 40 to be judged.

The correlation acquisition unit 26 acquires the correlation between the reference distribution created by the reference distribution creation unit 22 and the electrical characteristics of the semiconductor chip 40 acquired by the electrical characteristic acquisition unit 12. Because a reference distribution is created for each defect mode, it is possible to acquire a correlation with the electrical characteristics for each defect mode. Therefore, it is possible to determine the defect mode that is highly correlated with the electrical characteristics. The test device 100 may perform an image test for the defect mode that is most highly correlated with the electrical characteristics among the multiple defect modes.

Figure 2 is a diagram showing an example of a reference distribution. In Figure 2, the horizontal axis shows defect size, and the vertical axis shows the number of defects. Figure 2 shows the distribution of defects contained in a 3 mm square area on a semiconductor chip 40. Note that Figure 2 shows the average distribution of 1,500 semiconductor chips 40.

In FIG. 2, the number of defects peaks at the position where the defect size is "8". In this example, the semiconductor chip 40 has many minute threading screw dislocations. For this reason, the peak in the reference distribution is considered to correspond to threading screw dislocations. The number of defects increases as the defect size approaches 0, but this is considered to be because minute noise on the image is counted as a defect. From FIG. 2, it can be seen that the average semiconductor chip 40 contains threading screw dislocations of similar defect sizes. Although threading screw dislocations cause leakage current, threading screw dislocations of minute size do not pose much of a problem. The reference distribution shown in FIG. 2 is the defect distribution contained in a good semiconductor chip 40. Therefore, even if a defect exists in the semiconductor chip 40, if the defect distribution is similar to the reference distribution shown in FIG. 2, the semiconductor chip 40 can be determined to be good. On the other hand, if the defect distribution of the semiconductor chip 40 to be tested is different from the reference distribution, the semiconductor chip 40 can be determined to be defective.

Therefore, it is possible to determine whether the semiconductor chip 40 is good or bad based on the reference distribution. In other words, the quality of the semiconductor chip 40 can be determined by obtaining a distribution of semiconductor chip defect sizes that is determined in the same manner as the reference distribution and comparing it with the reference distribution. For example, if the defect distribution of the semiconductor chip 40 has only a peak that corresponds to the peak of the reference distribution, it is determined to be a good product, and if the defect distribution of the semiconductor chip 40 has a peak other than the peak that corresponds to the peak of the reference distribution, it is determined to be a defective product.

In the past, if threading screw dislocations were found in image testing, the product was deemed defective, and even products with no problem with electrical properties were sometimes deemed defective. By comparing with a reference distribution to determine the quality of the semiconductor chip 40, it is now possible to determine that a product is good even if threading screw dislocations are found, and the difference between image testing and electrical property testing can be reduced.

Figure 3 is a diagram showing another example of the reference distribution. In Figure 3, the horizontal axis shows the number of defects in a semiconductor chip 40, and the vertical axis shows the number of semiconductor chips 40 having each number of defects. Note that in Figure 3, the total number of semiconductor chips is 1,500. The multiple semiconductor chips may be chips that have been proven to be good products by a specified test, or they may be chips before testing. However, it is preferable that it is a collection of semiconductor chips that can be estimated to have a sufficiently low defect rate.

In Figure 3, a peak in the number of defects occurs when the number of defects reaches a maximum near 50. As in Figure 2, most of the semiconductor chips are good, so the semiconductor chips included in this peak are likely to be good.

Therefore, it is possible to judge whether the semiconductor chip 40 is good or bad based on the reference distribution as in FIG. 2. In other words, as in the reference distribution, the number of defects in the semiconductor chip 40 to be tested can be obtained, and the quality of the semiconductor chip 40 can be judged based on where the defects are in the reference distribution. For example, if the number of defects in the semiconductor chip 40 is in the peak part of the reference distribution, it is judged to be a good product, and if the number of defects in the semiconductor chip 40 is in a part other than the peak part of the reference distribution (if it is to the right of the peak in FIG. 3), it is judged to be a defective product. The peak part may be, for example, a range of 3σ of the peak part, a range of 2σ, or other range. σ is the standard deviation of the peak part. Even in the case of FIG. 3, by comparing the quality of the semiconductor chip 40 with the reference distribution and judging whether it is good or bad, it is possible to judge it to be a good product even if it has defects such as threading screw dislocations, and the difference between the image test and the test of electrical properties can be reduced. Next, the combination with the test of electrical properties will be described.

Figure 4 is a flowchart according to one embodiment of the present invention. The flowchart in Figure 4 includes an image acquisition step S101, a reference distribution acquisition step S102, a dicing step S103, an electrical characteristic acquisition step S104, and a judgment step S105.

In the image acquisition step S101, the image acquisition unit 2 acquires defect images of the semiconductor chip 40 to be tested. Also, in the image acquisition step S101, the image acquisition unit 2 may acquire images of defects of multiple semiconductor chips 40. In the subsequent reference distribution acquisition step S102, the data processing unit 20 acquires a reference distribution corresponding to the semiconductor chip 40 to be tested. The reference distribution is a distribution generated from the defect distributions of multiple semiconductor chips 40 having the same structure as the semiconductor chip 40 to be tested. The data processing unit 20 may generate the reference distribution from the images of defects of the multiple semiconductor chips 40 acquired in the image acquisition step S101. The data processing unit 20 may acquire information on the reference distribution from an external device. The data processing unit 20 may acquire a reference distribution for each defect mode generated from images of defects of the semiconductor chip 40.

In the reference distribution acquisition step S102, the degree of influence of the semiconductor chip 40 may be further calculated from the reference distribution and the defect image of the semiconductor chip 40 being tested. The degree of influence is an index calculated taking into consideration the effect that each defect has on the electrical characteristics of the semiconductor chip 40. The greater the degree of influence, the higher the probability that the semiconductor chip 40 is defective.

For example, the influence value of each defect is calculated based on how much the value of the size of each defect in the semiconductor chip 40 deviates from the peak in the reference distribution. The cumulative influence value of each defect is the influence degree of the semiconductor chip 40. For example, as shown in FIG. 2, when the defect size (defect area on the image or the number of pixels on the image) is set as the defect mode, the influence value of the defect included in the peak portion corresponding to the reference distribution is set to 0. In addition, for defects not included in the peak portion, the defect size is set as the influence value of the defect. The peak portion may be in the range of 3σ of the peak, may be in the range of 2σ, or may be in another range. In other words, the influence degree of the semiconductor chip 40 can be calculated as the sum of the areas of the defects in the semiconductor chip 40 that are not included in the peak portion of the reference distribution. Note that the calculation of the influence degree may be performed before the determination step S105, or may be performed after the electrical characteristic acquisition step S104.

In the reference distribution acquisition step S102, the reference distribution may be created on a wafer-by-wafer basis. By creating a reference distribution on a wafer-by-wafer basis, the semiconductor chip 40 can be evaluated on a wafer-by-wafer basis.

In the dicing step S103, the semiconductor wafer 30 is diced into individual semiconductor chips 40. Then, in the electrical characteristic acquisition step S104, the electrical characteristics of the semiconductor chips 40 are acquired. In this example, the electrical characteristic is leakage current.

In the judgment step S105, the quality of the semiconductor chip 40 is judged based on the reference distribution. In the judgment step S105, the quality of the semiconductor chip 40 may be judged based on the electrical characteristics and the reference distribution. In the judgment step S105, the semiconductor chip 40 may be determined as a good product if it is judged as a good product in both the electrical test using the electrical characteristics and the image test using the defect image. In the image test, the quality of the semiconductor chip 40 may be judged based on the above-mentioned influence. If the influence is equal to or less than a predetermined threshold, the semiconductor chip 40 may be judged as a good product. By judging the quality of the semiconductor chip 40 based on the influence calculated from the electrical characteristics and the reference distribution, it is possible to judge long-term reliability, which cannot be judged by the test of electrical characteristics alone.

In addition, even without calculating the degree of influence, in the judgment step S105, the quality of the semiconductor chip 40 may be judged based on the difference between the defect distribution of the semiconductor chip 40 being tested and the reference distribution. In the judgment step S105, the quality of the semiconductor chip 40 may be judged based on the difference from the input reference distribution input by the user. The quality of the semiconductor chip 40 can also be judged based on the difference between the reference distribution and the input reference distribution.

Figures 5A and 5B are diagrams showing a method for calculating defect size. Figure 5A is a binarized black and white image of the brightness distribution of an optical photograph of a defect image. In Figure 5A, the areas where dislocations have occurred in the crystal are white. Note that Figure 5A is an enlarged image of the vicinity of a defect contained in a defect image of semiconductor chip 40. The defect size can be calculated by calculating the area of the white region in Figure 5A.

Figure 5B shows an example of the distribution of the luminance values of each pixel in the defect image before binarization. In Figure 5B, the luminance values of each pixel in the defect image are shown in 256 gradations. In the example of Figure 5B, the larger the luminance value, the darker (black), and the smaller the luminance value, the brighter (white). In the defect image, pixels without dislocation are black, and pixels with dislocation are white. For this reason, the distribution shown in Figure 5B has a peak of black pixels without dislocation and a peak of white pixels with dislocation. By setting a threshold value that separates the two peaks, the defect image can be binarized as shown in Figure 5A. In addition, the size of the defect can be calculated by counting the number of pixels included in the white peak.

FIG. 6 is a diagram showing an example of a method for calculating the degree of influence. In this example, the influence value of the defect is corrected according to the position where the defect exists. For example, depending on the position where the defect exists, the defect may not affect the electrical characteristics or may have a very small effect. Defects 52 and 54 exist on the semiconductor chip 40 in FIG. 6. In addition, the semiconductor chip 40 is divided into an active region 62 and an outer peripheral region 64 when calculating the degree of influence. The active region 62 is a region in which semiconductor elements such as transistors or diodes are formed inside the semiconductor substrate. The outer peripheral region 64 is provided outside the active region 62 and surrounding the active region 62. A voltage-resistant structure such as a guard ring or a field plate may be formed in the outer peripheral region 64. The guard ring is a P-type region that surrounds the active region 62 in a top view of the semiconductor substrate. The field plate is a conductive member such as polysilicon that surrounds the active region 62 in a top view of the semiconductor substrate. In this example, the surface on which the active region 62 is provided is the xy plane, and the plane perpendicular to the xy plane is the z axis. In FIG. 6, a gate wiring 66 is provided across the active region 62 in the x-axis direction. The gate wiring 66 is connected to a gate pad (not shown) and supplies a gate potential to each transistor. The gate wiring 66 is made of a conductive material such as polysilicon.

The degree of influence can be calculated by adding up the influence values of defects present within the chip. In this example, the degree of influence is the sum of the influence values of defect 52 and defect 54. In this example, the influence value of defect 54 present only in outer peripheral region 64 is set to 0 and is not included in the calculation of the degree of influence. This is because outer peripheral region 64 of semiconductor chip 40 is outside the active region of semiconductor chip 40, and therefore even if a defect exists, the influence on leakage current is small. Furthermore, defects that exist across active region 62 and outer peripheral region 64 may be included in the calculation of the degree of influence. In the determination step S105, the degree of influence may be calculated based on whether or not the defect is within the active region (active region 62) of semiconductor chip 40.

In addition, in the judgment step S105, the degree of influence may be calculated based on the distance between the defect and the gate wiring 66 of the semiconductor chip 40. For defects where the distance is equal to or greater than a predetermined threshold, the influence value may be set to 0. This is because if the defect and the gate wiring 66 of the semiconductor chip 40 are sufficiently far apart, the effect of the defect on the gate wiring 66 is small.

7 is a plot of the relationship between the influence and leakage current of multiple semiconductor chips 40. The horizontal axis indicates the influence, and the vertical axis indicates the leakage current. In the electrical test, for example, a semiconductor chip 40 with a leakage current of 2 μA (1×10 ⁻⁶ A) or more is determined to be defective. In the conventional image test, if a defect is present, that is, if the influence is greater than 0, the semiconductor chip 40 is determined to be defective.

As shown in FIG. 7, even if the semiconductor chip 40 has an influence level greater than 0, the leakage current may be equal to or less than the threshold. According to this example, by using a value greater than 0 as the judgment value to be compared with the influence level, a semiconductor chip 40 that is not actually defective can be judged as a good product. The judgment value may be determined based on the relationship shown in FIG. 7. For example, the judgment value may be set so that the agreement rate between the pass/fail judgment based on the influence level and the pass/fail judgment based on the electrical test is as high as possible.

Figure 8 shows the relationship between the impact judgment value and the match rate. The match rate is the sum of the percentage of electrical test: good and impact (image test): good, and the percentage of electrical test: bad and impact (image test): bad. Furthermore, a semiconductor chip 40 whose impact is equal to or less than the judgment value is judged to be a good product. For example, when the impact judgment value is 0, a semiconductor chip 40 whose impact is equal to or less than 0 is judged to be a good product.

In Figure 8, as the judgment value of the degree of influence for determining a product as a pass increases, the matching rate increases. As the matching rate increases, the difference between the image test and the electrical characteristics test can be reduced. Therefore, it is possible to make a judgment using only the image test.

Figure 9 is a diagram showing a flowchart for acquiring the correlation between defect modes and electrical characteristics. The flowchart in Figure 9 includes a data measurement stage S201, a principal component analysis stage S202, a level division stage S203, an image aggregation stage S204, a feature extraction stage S205, a group division stage S206, a digitization and pattern extraction stage S207, and a correlation acquisition stage S208.

In the data measurement step S201, the test device 100 measures data. That is, the image acquisition unit 2 may acquire images of defects in the semiconductor wafer 30. The electrical characteristic acquisition unit 12 may acquire electrical characteristics of the semiconductor chips 40 obtained by singulating the semiconductor wafer 30. In the data measurement step S201, the image acquisition step S101, the reference distribution acquisition step S102, the dicing step S103, and the electrical characteristic acquisition step S104 in the flowchart of FIG. 4 may be performed.

Figure 10 is an example of an image acquired by the image acquisition unit 2 in the data measurement stage S201. In Figure 10, defects in the semiconductor chip 40 are represented by dots. In Figure 10, one semiconductor chip 40 has defects 72, 74, and 76. The wafers from which the images are acquired are each made into chips, and the electrical characteristics are acquired by the electrical characteristic acquisition unit 12.

Figures 11, 12, 13, 14, 15, 16, and 17 are examples of electrical characteristics acquired by the electrical characteristic acquisition unit 12 in the data measurement stage S201. The electrical characteristics of each semiconductor chip 40 may be similar to any of the electrical characteristics shown in Figures 11 to 17. In the figures, the horizontal axis indicates the applied voltage, and the vertical axis indicates the leakage current. The applied voltages are divided into Case 1, Case 2, Case 3, and Case 4, respectively. Of Cases 1 to 4, Case 1 indicates the minimum applied voltage, and Case 4 indicates the maximum applied voltage. As shown in Figures 11 to 17, the electrical characteristics of the semiconductor chip 40 show multiple distribution trends depending on the defect distribution, etc.

In Figures 12, 14, and 17, leakage current flows from voltage case 1 onwards. In other examples, almost no leakage current flows in voltage case 1. Also, the applied voltage at which leakage current starts to rise is different in each example. As such, various trends appear in the electrical characteristics, so it is preferable to classify and analyze the electrical characteristics acquired by the electrical characteristics acquisition unit 12.

Figure 18 is a diagram showing a flowchart of the principal component analysis in the principal component analysis step S202. Each electrical characteristic in Figures 11 to 17 can be expressed by four variables, Case 1 to Case 4. Case 1 to Case 4 correspond to the dotted lines when the applied voltage shown in Figures 11 to 17 is divided into four. The value at the point where the dotted line intersects with the leakage current curve becomes the variable. Therefore, the principal axis of the current variable can be extracted by the principal component analysis. The flowchart of the principal component analysis may include an average calculation step S301, a covariance matrix generation step S302, an eigenvalue calculation step S303, and an eigenvector calculation step S304.

Figure 19 shows the results of the principal component analysis step S202. In Figure 19, the analysis results of the electrical characteristics of the semiconductor chip 40 are plotted two-dimensionally using the first and second principal axes. One plot in Figure 19 corresponds to the electrical characteristics of one semiconductor chip 40.

Figure 20 is a diagram showing a flowchart of a method for classifying electrical characteristics of a semiconductor chip 40 in the level division step S203. In this example, each plot shown in Figure 19 is classified into multiple classes. That is, the electrical characteristics of each semiconductor chip 40 are classified into multiple classes. One example of classification of electrical characteristics by level division is k-means. k-means is a method for clustering by specifying the number of divisions in advance. Classes are randomly assigned to target points (S402). The number of classes starts from 1. The center of gravity of the classes is calculated and the class of the point is changed to the class of the closest center of gravity (S403). This method repeats the calculation until there is no change. Clustering is possible using this method. Since the number of classes of electrical characteristics is not known in advance, it is preferable to perform clustering sequentially while changing the number of classes (S401). The total value of the distance from the center of gravity between the clustered points for each number of classes is calculated using this method (S404). The number of classification classes that has the greatest change in the distance value before and after changing the number of classification classes is determined as the number of electrical characteristic classification classes (S405).

Figure 21 is a diagram showing the classification results of the electrical characteristics of the semiconductor chip 40 in the level division stage S203. In Figure 21, the results of the electrical characteristics of the semiconductor chip 40 are classified into class 1, class 2, class 3, class 4, and class 5. In Figure 21, each class is indicated by a mark of a different shape.

After that, feature amounts are extracted from the defect images according to the clustering results. Feature amounts are extracted from the defect images for each electrical property class. The feature amount from the defect image may be the value of the defect mode described above. In other words, by extracting the value of each defect mode from the defect images of multiple semiconductor chips 40 classified as having the same electrical property class, the strength of correlation between the electrical property class and each defect mode can be calculated. In the image aggregation stage S204, the images of the semiconductor chips 40 clustered into the same class are aggregated.

Figure 22 is a diagram showing a method of extracting features in the feature extraction step S205. In Figure 22, change points between a visual image and an X-ray topography image are derived. A visual image is an image obtained by capturing visible light from a semiconductor chip 40. An X-ray topography image is a two-dimensional mapping image of a semiconductor chip 40 obtained by a beam emitted from an X-ray source. A change point is a pixel whose difference in luminance value between adjacent pixels on an image is equal to or greater than a predetermined reference value. The change point is extracted even when there is a change in either one of the images. In Figure 22, the profile of the change in the visual image is shown by a dotted line, and the profile of the change in the X-ray topography image is shown by a solid line. In Figure 22, change points of multiple images 90 are extracted. In Figure 22, the order in which changes are searched for in multiple images 90 after the profile is calculated is shown by an arrow. In addition, in image 90, defects 78, 80, and 82 exist. In FIG. 22, defects 78 and 80 exist in one image 90, and defect 82 exists in another image 90. Since there is a difference between defect candidate areas in the chip and areas where no defects occur, this method searches for areas that are effective as image features. The x and y coordinates of the locations where change points occur are stored, and this is carried out over the entire surface. A collection of the x and y coordinates of the changes is output. Using k-means, a collection of the respective x and y coordinates is output.

Figure 23 is a diagram showing the results of group division in group division step S206. In group division step S206, each dot of the defect detected in the image of the semiconductor chip 40 is clustered, and the dots are collected into an aggregate image 92 to form a single defect. By performing group division, defects 78, 80, and 82 can be identified as shown in Figure 23, and by obtaining the area of each chip, etc., the feature amount can be calculated in the quantification/pattern extraction step S207. The feature amount can be obtained for each defect mode.

In the digitization and pattern extraction stage S207, feature values are calculated. The feature values are, for example, the area, center of gravity coordinates, and length of the image feature. The feature values are stored in the data processing unit 20 and can be used for comparison when inspecting a new wafer to help estimate the classification class of the device characteristics.

Figure 24 is an example of a correlation acquired by the correlation acquisition unit 26 in the correlation acquisition step S208. In Figure 24, the correlation between the class of electrical characteristics and defect mode a for approximately 100 semiconductor chips 40 is graphed. Defect mode a indicates a specific defect mode. In Figure 24, the horizontal axis indicates the value of defect mode a, and the vertical axis indicates the class of electrical characteristics.

Figure 25 is another example of the correlation acquired by the correlation acquisition unit 26 in the correlation acquisition step S208. In Figure 25, the correlation between the electrical characteristic class and defect mode d is graphed for approximately 100 semiconductor chips 40. Defect mode d indicates a specific defect mode different from defect mode a. Comparing Figures 24 and 25, it can be seen that defect mode d has a higher correlation with electrical characteristics than defect mode a. Therefore, it can be seen that by inspecting the image features of defect mode d, results similar to those of electrical characteristic testing can be obtained.

In the correlation acquisition step S208, the defect image and the electrical characteristics may be associated with each other for each semiconductor chip 40, and the correlation between the defect mode and the electrical characteristics may be acquired. In the correlation acquisition step S208, the display unit 16 may display the correlation between the defect mode and the electrical characteristics for each defect mode. By providing the correlation acquisition step S208, it becomes easier to find a defect mode that produces results similar to those of the electrical characteristics test.

In addition, in the judgment step S105, the quality of the semiconductor chip 40 may be judged based on a reference distribution of defect modes that have a high correlation with electrical characteristics. By judging the quality of the semiconductor chip 40 based on a reference distribution of defect modes that have a high correlation with electrical characteristics, the accuracy of the quality judgment can be improved.

The present invention has been described above using an embodiment, but the technical scope of the present invention is not limited to the scope described in the above embodiment. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiment. It is clear from the claims that forms with such modifications or improvements can also be included in the technical scope of the present invention.

2: Image acquisition unit, 4: Camera control unit, 6: Light source, 8: Stage unit, 10: Stage control unit, 12: Electrical characteristic acquisition unit, 14: Stand, 16: Display unit, 18: Operation unit, 20: Data processing unit, 22: Reference distribution creation unit, 24: Judgment unit, 26: Correlation acquisition unit, 30: Semiconductor wafer, 40: Semiconductor chip, 52: Defect, 54: Defect, 62: Active region, 64: Outer peripheral region, 66: Gate wiring, 72: Defect, 74: Defect, 76: Defect, 78: Defect, 80: Defect, 82: Defect, 90: Image, 92: Collective image, 100: Testing device

Claims (30)

A test method for testing a semiconductor chip under test, comprising the steps of:
a reference distribution acquisition step of acquiring a reference distribution, which is an image of a plurality of defects included in one semiconductor chip, generated from the image of one or more of the semiconductor chips, and which is a distribution of evaluation results of the plurality of the defects;
a judgment step of comparing the reference distribution with information obtained from an image of defects in the semiconductor chip under test to judge whether the semiconductor chip under test is good or bad. A test method for testing a semiconductor chip under test, comprising the steps of:
A reference distribution acquisition step of acquiring a reference distribution for each defect mode generated from images of defects of a plurality of semiconductor chips;
a judgment step of comparing the reference distribution with information obtained from an image of defects in the semiconductor chip to be tested to judge whether the semiconductor chip to be tested is good or bad;
an electrical characteristic acquisition step of acquiring electrical characteristics of the plurality of semiconductor chips;
a correlation acquisition step of associating the defect image with the electrical characteristic for each of the plurality of semiconductor chips and acquiring a correlation between the defect mode and the electrical characteristic,
in the judging step, the quality of the semiconductor chip being tested is judged based on the electrical characteristics and the reference distribution. A test method for testing a semiconductor chip under test, comprising the steps of:
A reference distribution acquisition step of acquiring a reference distribution for each defect mode generated from images of defects of a plurality of semiconductor chips;
a judgment step of comparing the reference distribution with information obtained from an image of defects in the semiconductor chip to be tested to judge whether the semiconductor chip to be tested is good or bad;
the determining step determines whether the semiconductor chip under test is defective or not by calculating a degree of influence of the defect on the semiconductor chip under test. A test method for testing a semiconductor chip under test, comprising the steps of:
A reference distribution acquisition step of acquiring a reference distribution for each defect mode generated from images of defects of a plurality of semiconductor chips;
a determining step of determining whether the semiconductor chip to be tested is good or bad based on the reference distribution;
Equipped with
In the determination step, a degree of influence of the defect on the semiconductor chip to be tested is calculated to determine whether the semiconductor chip to be tested is good or bad;
The degree of influence is calculated based on whether the defect is in an active region, which is a region in which a semiconductor element of the semiconductor chip under test is formed.
Test method. A test method for testing a semiconductor chip under test, comprising the steps of:
A reference distribution acquisition step of acquiring a reference distribution for each defect mode generated from images of defects of a plurality of semiconductor chips;
a determining step of determining whether the semiconductor chip to be tested is good or bad based on the reference distribution;
Equipped with
In the determination step, a degree of influence of the defect on the semiconductor chip to be tested is calculated to determine whether the semiconductor chip to be tested is good or bad;
The degree of influence is calculated based on the distance between the defect and the gate wiring of the semiconductor chip under test.
Test method . A test method for testing a semiconductor chip under test, comprising the steps of:
a reference distribution acquisition step of acquiring a reference distribution, which is an image of a plurality of defects included in one semiconductor chip, generated from the image of one or more of the semiconductor chips, and which is a distribution of evaluation results of the plurality of the defects;
a determining step of determining whether the semiconductor chip to be tested is good or bad based on the reference distribution;
Equipped with
The horizontal axis of the reference distribution is the number of the defects in the semiconductor chip, and the vertical axis is the number of the semiconductor chips having each number of the defects.
Test method. A test method for testing a semiconductor chip under test, comprising the steps of:
A reference distribution acquisition step of acquiring a reference distribution for each defect mode generated from images of defects of a plurality of semiconductor chips;
a determining step of determining whether the semiconductor chip being tested is good or bad based on the reference distribution;
an electrical characteristic acquisition step of acquiring electrical characteristics of the plurality of semiconductor chips;
a correlation acquisition step of associating the defect image with the electrical characteristic for each of the plurality of semiconductor chips and acquiring a correlation between the defect mode and the electrical characteristic;
Equipped with
the horizontal axis of the reference distribution is the number of the defects in the semiconductor chip, and the vertical axis is the number of the semiconductor chips having each number of the defects;
In the judgment step, the quality of the semiconductor chip to be tested is judged based on the electrical characteristics and the reference distribution.
Test method. A test method for testing a semiconductor chip under test, comprising the steps of:
A reference distribution acquisition step of acquiring a reference distribution for each defect mode generated from images of defects of a plurality of semiconductor chips;
a determining step of determining whether the semiconductor chip to be tested is good or bad based on the reference distribution;
Equipped with
the horizontal axis of the reference distribution is the number of the defects in the semiconductor chip, and the vertical axis is the number of the semiconductor chips having each number of the defects;
In the judging step, the quality of the semiconductor chip under test is judged by calculating the degree of influence of the defect on the semiconductor chip under test.
Test method. 8. The test method according to claim 2, wherein in the correlation acquisition step, the correlation between the defect mode and the electrical characteristic is displayed for each of the defect modes. 10. The test method according to claim 2, wherein in the judgment step, the quality of the semiconductor chip being tested is judged based on the reference distribution of the defect modes that have a high correlation with the electrical characteristics among the defect modes. further comprising an image acquisition step of acquiring an image of the defect;
The test method according to claim 1 , wherein the reference distribution acquisition step generates the reference distribution from an image of the defect. The test method according to claim 1 , wherein the reference distribution is generated on a wafer-by -wafer basis in the reference distribution acquisition step. The testing method according to claim 1 , wherein in the judging step, the quality of the semiconductor chip being tested is judged based on a difference between information obtained from an image of defects in the semiconductor chip being tested and the reference distribution. The test method according to claim 1 , wherein in the judging step, the quality of the semiconductor chips being tested is judged based on a difference from an input reference distribution input by a user. The test method according to claim 1 , wherein the defect is a crystal defect. The test method according to claim 1 , wherein the horizontal axis of the reference distribution represents the size of the defects and the vertical axis represents the number of the defects. The test method according to claim 1 , wherein the semiconductor chip to be tested is included in one or more of the semiconductor chips used to obtain the reference distribution. The test method according to claim 1 , wherein the semiconductor chip to be tested is not included in the one or more semiconductor chips used to obtain the reference distribution. The reference distribution is a distribution that a good semiconductor chip should have.
19. The test method according to any one of claims 1 to 18. A test apparatus for testing a semiconductor chip to be tested, comprising:
a reference distribution creation unit that acquires a reference distribution, which is an image of a plurality of defects included in one semiconductor chip, generated from the image of one or more of the semiconductor chips, and is a distribution of evaluation results of the plurality of the defects;
a judgment unit that compares the reference distribution with information obtained from an image of defects in the semiconductor chip under test to judge whether the semiconductor chip under test is good or bad. A test apparatus for testing a semiconductor chip to be tested, comprising:
a reference distribution creation unit that acquires a reference distribution for each defect mode generated from images of defects in a plurality of semiconductor chips;
a determination unit that compares the reference distribution with information obtained from an image of defects in the semiconductor chip to be tested and determines whether the semiconductor chip to be tested is good or bad;
an electrical characteristic acquisition unit that acquires electrical characteristics of the semiconductor chips;
a correlation acquisition unit that associates the defect image with the electrical characteristic for each of the plurality of semiconductor chips and acquires a correlation between the defect mode and the electrical characteristic,
The judgment unit judges pass/fail of the semiconductor chip to be tested based on the electrical characteristics and the reference distribution. A test apparatus for testing a semiconductor chip to be tested, comprising:
a reference distribution creation unit that acquires a reference distribution for each defect mode generated from images of defects in a plurality of semiconductor chips;
a judgment unit that compares the reference distribution with information obtained from an image of defects in the semiconductor chip to be tested and judges whether the semiconductor chip to be tested is good or bad;
The determination unit determines pass/fail of the semiconductor chip under test by calculating a degree of influence of the defect on the semiconductor chip under test. A test apparatus for testing a semiconductor chip to be tested, comprising:
a reference distribution creation unit that acquires a reference distribution, which is an image of a plurality of defects included in one semiconductor chip, generated from the image of one or more of the semiconductor chips, and is a distribution of evaluation results of the plurality of the defects;
a determination unit for determining whether the semiconductor chip being tested is good or bad based on the reference distribution;
Equipped with
The horizontal axis of the reference distribution is the number of the defects in the semiconductor chip, and the vertical axis is the number of the semiconductor chips having each number of the defects.
Test equipment. A test apparatus for testing a semiconductor chip to be tested, comprising:
a reference distribution creation unit that acquires a reference distribution for each defect mode generated from images of defects in a plurality of semiconductor chips;
a determination unit that determines whether the semiconductor chip being tested is good or bad based on the reference distribution;
an electrical characteristic acquisition unit that acquires electrical characteristics of the semiconductor chips;
a correlation acquisition unit that associates the defect image with the electrical characteristic for each of the plurality of semiconductor chips and acquires a correlation between the defect mode and the electrical characteristic;
Equipped with
the horizontal axis of the reference distribution is the number of the defects in the semiconductor chip, and the vertical axis is the number of the semiconductor chips having each number of the defects;
The judgment unit judges whether the semiconductor chip under test is good or bad based on the electrical characteristics and the reference distribution.
Test equipment. A test apparatus for testing a semiconductor chip to be tested, comprising:
a reference distribution creation unit that acquires a reference distribution for each defect mode generated from images of defects in a plurality of semiconductor chips;
a determination unit for determining whether the semiconductor chip being tested is good or bad based on the reference distribution;
Equipped with
the horizontal axis of the reference distribution is the number of the defects in the semiconductor chip, and the vertical axis is the number of the semiconductor chips having each number of the defects;
The determination unit determines whether the semiconductor chip under test is good or bad by calculating the degree of influence of the defect on the semiconductor chip under test.
Test equipment. 26. The test apparatus of claim 20 , wherein the defect is a crystal defect. 23. The test apparatus according to claim 20 , wherein the horizontal axis of the reference distribution represents the size of the defects and the vertical axis represents the number of the defects. 28. The test apparatus according to claim 20 , wherein the semiconductor chip to be tested is included in one or more of the semiconductor chips used to obtain the reference distribution. The test apparatus according to claim 20 , wherein the semiconductor chip to be tested is not included in the one or more semiconductor chips used to obtain the reference distribution. The reference distribution is a distribution that a good semiconductor chip should have.
30. A test device according to any one of claims 20 to 29.

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