JP7616381B2 - Semiconductor device and power conversion device - Google Patents

Description

The present invention relates to the configuration of a semiconductor device, and in particular to technology that is effective when applied to a cascode-type high-voltage element configured by connecting multiple low-voltage elements in series.

In the development of power semiconductor devices such as power transistors and power diodes, an important challenge is to manufacture devices that have high voltage resistance, low on-resistance, and minimal switching losses.

A power transistor typically has a drift region that is located between the body region and the drain region and is lightly doped relative to the drain region. The on-resistance of a conventional power transistor depends on the length of the drift region in the direction of current flow and the doping concentration of the drift region, and shortening the length of the drift region or increasing the doping concentration of the drift region reduces the on-resistance.

However, shortening the length of the drift region or increasing the doping concentration of the drift region reduces the device's breakdown voltage.

Well-known methods for reducing the on-resistance of a power transistor with a given breakdown voltage include providing a complementarily doped compensation region in the drift region, and providing a field plate in the drift region that is dielectrically insulated from the drift region and connected, for example, to the gate or source terminal of the transistor.

In these types of power transistors, the compensation zone or field plate partially compensates for the doping charge in the drift region when the device is in the off state, allowing for a higher doping concentration in the drift region, lowering the on-resistance without reducing the breakdown voltage. However, the output capacitance of these devices tends to be higher.

As background technology in this technical field, for example, there is technology such as that in Patent Document 1. Patent Document 1 discloses "a semiconductor element that can improve the withstand voltage and reduce the output capacity by autonomously controlling multiple power transistors in a cascode connection."

The technology of Patent Document 1 not only provides benefits in terms of power transistor performance, such as improved breakdown voltage, reduced on-resistance, and reduced switching losses, but also simplifies design by allowing the breakdown voltage to be changed by the number of cascode connection stages.

US Patent Application Publication No. 2012/0175635

However, the technology disclosed in the above-mentioned Patent Document 1 has the following problems because it uses a cascode connection that connects the gate electrode to the source electrode of the previous stage:

[Problem 1]
The power transistors in the second and subsequent stages must be normally-on type power transistors that conduct when the gate voltage is 0 V, which reduces the freedom in design and manufacturing process of the power transistors. In addition, when the power transistor is turned on (conducting), the gate-source voltage cannot be made higher than 0 V, which causes a problem in that the channel resistance cannot be made sufficiently small.

[Problem 2]
In Patent Document 1, the withstand voltage of power transistors in the second and subsequent stages is limited by the withstand voltage of the gate oxide film, and the withstand voltage of each individual power transistor is usually limited to about 20 V. In addition, to obtain a high withstand voltage, it is necessary to increase the number of stages of the cascode connection, but as the number of stages increases, the number of channels of the power transistors and the number of contacts connecting the power transistors increase, which causes a problem of increasing parasitic resistance.

[Problem 3]
Since it is configured by connecting multiple power transistors in series, reliability becomes an issue.

For example, in Patent Document 1, if the source-drain region of even one of the power transistors connected in series is destroyed, all power transistors in the stage following the destroyed power transistor cannot be turned off, resulting in a problem that the probability of failure increases as the number of stages in series increases.

Therefore, in order to address the above-mentioned problem 1, it is desirable to realize a semiconductor device having a circuit configuration in which the second-stage or later power transistors among multiple power transistors connected in series can be controlled autonomously in conjunction with the first-stage power transistor even if they are normally-off type, in other words, a circuit configuration in which a raw gate-source voltage can be applied to the second-stage or later power transistors when the first-stage power transistor is on.

In addition, to address the above-mentioned problem 2, it is desirable to realize a semiconductor device in which, even if some of the multiple power transistors connected in series have a source-drain breakdown voltage failure (short circuit), the other power transistors can be turned off, and the breakdown voltage of the entire series of power transistors connected in series does not decrease significantly.

Furthermore, in order to address issue 3 above, it is important to be able to appropriately design the ratio of parasitic resistances, such as channel resistance and contact resistance, among the resistance components of a power transistor, and to be able to freely design the number of series-connected power transistors from the second stage onwards for a certain target breakdown voltage. In other words, it is desirable to realize a semiconductor device in which the breakdown voltage of power transistors from the second stage onwards is not limited by the breakdown voltage of the gate oxide film.

Therefore, the object of the present invention is to provide a semiconductor device having a high degree of freedom in design and manufacturing and high reliability, in which a normally-off type power transistor can be used for each power transistor in a cascode-type semiconductor device configured by connecting a plurality of power transistors in series, and in which the source-drain breakdown voltage and gate-source breakdown voltage of each power transistor can be designed independently, and in which the breakdown voltage of the semiconductor device as a whole does not decrease significantly even if the source-drain of some power transistors becomes defective in breakdown voltage, and a power conversion device using the same.

In order to solve the above problem, the present invention provides a semiconductor device having a plurality of semiconductor elements connected in multiple stages in which a drive signal from a gate drive circuit is input to the gate of a first stage and the drain of a previous stage and the source of a next stage are connected in series, and when one of the N-type and P-type conductivity types is a first conductivity type and the other conductivity type is a second conductivity type, the plurality of semiconductor elements are first conductivity type MOSFETs, and when an on drive signal is input from the gate drive circuit to the gate of the first stage semiconductor element, one or more first second conductivity type MOSFETs supply the on drive signal to the second stage or later semiconductor elements to turn on the second stage or later semiconductor elements, and one or more second second conductivity type MOSFETs turn off when an off drive signal is input from the gate drive circuit to the gate of the first stage semiconductor element and supply the source or drain voltage of the previous stage semiconductor element to the gate of the second stage or later semiconductor element to turn off the second stage or later semiconductor elements.

According to the present invention, in a cascode-type semiconductor device configured by connecting multiple power transistors in series, normally-off type power transistors can be used for each of the power transistors, and the source-drain breakdown voltage and gate-source breakdown voltage of each power transistor can be designed independently. Even if the source-drain of some power transistors becomes defective in breakdown voltage, the breakdown voltage of the semiconductor device as a whole does not decrease significantly. This makes it possible to realize a semiconductor device with high design and manufacturing freedom and reliability, and a power conversion device using the same.

Issues, configurations and effects other than those described above will become clear from the description of the embodiments below.

1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention; Fig. 2 is a diagram showing a modification of Fig. 1 (Modification 1). FIG. 11 is a circuit diagram showing a configuration of a semiconductor device according to a second embodiment of the present invention. Fig. 4 is a diagram showing a modification of Fig. 3 (Modification 2).

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the same components in each drawing are given the same reference numerals, and detailed descriptions of overlapping parts will be omitted.

A semiconductor device according to a first embodiment of the present invention will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing the configuration of the semiconductor device according to the first embodiment.

In addition, while Figure 1 shows an example in which a lateral MOSFET is used as the power transistor that constitutes the semiconductor device, it is also possible to use a power transistor in which an IGBT and a diode are connected in reverse to be connected in series, or a HEMT (High Electron Mobility Transistor) made of a material such as gallium nitride (GaN).

1, the semiconductor device 11 of this embodiment is configured to include a gate drive circuit 0, an N-type MOSFET 1, an N-type MOSFET 2a, an N-type MOSFET 2b, a P-type MOSFET 3a, a P-type MOSFET 3b, a P-type MOSFET 4a, and a P-type MOSFET 4b. Note that the gate drive circuit 0 may not be built into the semiconductor device 11, and a drive signal may be input from a gate drive circuit 0 provided outside the semiconductor device 11.

The first stage circuit is formed by an N-type MOSFET 1, the second stage circuit 10a is formed by an N-type MOSFET 2a, a P-type MOSFET 3a, and a P-type MOSFET 4a, and the third stage circuit 10b is formed by an N-type MOSFET 2b, a P-type MOSFET 3b, and a P-type MOSFET 4b.

The drain of N-type MOSFET 1 is connected to the source of N-type MOSFET 2a in the next stage, and the drain of N-type MOSFET 2a is connected to the source of N-type MOSFET 2b in the next stage. As shown in Figure 1, a high-voltage semiconductor device 11 is configured by connecting multiple N-type MOSFETs 1 to 2b in series.

The N-type MOSFET 1 in the first stage may be either a normally-off type or a normally-on type, and the N-type MOSFETs 2a and 2b in the second stage and thereafter are normally-off type.

Here, in this embodiment, as an example, it is assumed that the drain-source breakdown voltage of N-type MOSFETs 1, 2a, 2b and P-type MOSFETs 3a, 3b, 4a, 4b is 20V.

The gate drive circuit 0 is connected to the gate of the first stage N-type MOSFET 1.

The P-type MOSFET 3a in the second stage circuit 10a has a source connected to the gate of the N-type MOSFET 2a of that stage, a drain connected to the source of the N-type MOSFET 2a of that stage, and a gate connected to the gate of the N-type MOSFET 1 of the previous stage.

The P-type MOSFET 4a in the second stage circuit 10a has a source connected to the gate of the N-type MOSFET 2a of that stage and the source of the P-type MOSFET 3a of that stage, a drain connected to the gate of the N-type MOSFET 1 of the previous stage and the gate of the P-type MOSFET 3a of that stage, and a gate connected to the source of the N-type MOSFET 2a of that stage, the drain of the P-type MOSFET 3a of that stage, and the drain of the N-type MOSFET 1 of the previous stage.

The connection relationship of the N-type MOSFET 2b and the P-type MOSFETs 3b and 4b constituting the circuit 10b is the same as that of the N-type MOSFET 2a and the P-type MOSFETs 3a and 4a constituting the circuit 10a. In other words, in FIG. 1, two circuits identical to the circuit 10a are connected in series as the second and subsequent stages in the stage following the first stage circuit. In this embodiment, an example of two series is shown, but the number of series may be changed arbitrarily depending on the target withstand voltage, and the number of series may be one.

In this embodiment, the N-type MOSFETs 1, 2a, 2b and the P-type MOSFETs 3a, 3b, 4a, 4b connected as described above are operated as a single semiconductor device 11.

Therefore, in semiconductor device 11, the gate is the gate of N-type MOSFET 1, the source is the source of N-type MOSFET 1, and the drain is the drain of N-type MOSFET 2b.

Next, we will explain how it works.

[Operation example 1]
First, a state in which a voltage is applied to the drain of the N-type MOSFET 2b and the gate drive circuit 0 outputs an off signal (≦0V) will be described.

The signal from gate drive circuit 0 turns off N-type MOSFET 1, and the potential at the drain of N-type MOSFET 1 rises.

As a result, the gate voltage of the P-type MOSFET 4a (i.e. the drain voltage of the N-type MOSFET 1) rises, the gate-source voltage of the P-type MOSFET 4a exceeds the gate threshold voltage of the P-type MOSFET 4a, and the P-type MOSFET 4a enters the off state.

In addition, when the drain voltage of P-type MOSFET 3a (i.e., the drain voltage of N-type MOSFET 1) rises, the built-in diode of P-type MOSFET 3a becomes conductive, and the source voltage of P-type MOSFET 3a also rises in tandem.

The gate-source voltage of P-type MOSFET 3a falls below the gate threshold voltage of P-type MOSFET 3a, and P-type MOSFET 3a turns on.

As a result of the above-mentioned P-type MOSFET 4a being turned off and P-type MOSFET 3a being turned on, the gate of N-type MOSFET 2a becomes at the same potential as the source of N-type MOSFET 2a, and since N-type MOSFET 2a is a normally-off type, it is turned off.

The above series of operations also occurs in P-type MOSFET 3b, P-type MOSFET 4b, and N-type MOSFET 2b, turning N-type MOSFET 2b off, and the entire semiconductor device 11 turns off, demonstrating high voltage resistance performance.

[Operation example 2]
Next, a state will be described in which a voltage is applied to the drain of the N-type MOSFET 2b via a load (not shown) and the gate drive circuit 0 outputs an ON signal (for example, 15V).

The signal from gate drive circuit 0 turns on N-type MOSFET 1, causing the potential at the drain of N-type MOSFET 1 to decrease.

As a result, the gate voltage of the P-type MOSFET 4a (i.e. the drain of the N-type MOSFET 1) drops, the gate-source voltage of the P-type MOSFET 4a falls below the gate threshold voltage of the P-type MOSFET 4a, and the P-type MOSFET 4a turns on.

In addition, when the P-type MOSFET 4a is turned on, the gate-source voltage of the P-type MOSFET 3a exceeds the gate threshold voltage of the P-type MOSFET 3a, and the P-type MOSFET 3a is turned off.

As a result of the above-mentioned P-type MOSFET 4a being turned on and P-type MOSFET 3a being turned off, an on signal (e.g. 15V) is supplied to the gate of N-type MOSFET 2a from gate drive circuit 0, and N-type MOSFET 2a is turned on.

At this time, a sufficiently large voltage is applied between the gate and source of the N-type MOSFET 2a, making the channel resistance of the N-type MOSFET 2a sufficiently small.

The above series of operations also occurs in P-type MOSFET 3b, P-type MOSFET 4b, and N-type MOSFET 2b, causing N-type MOSFET 2b to turn on, and the entire semiconductor device 11 to turn on and conduct current.

[Operation example 3]
Next, a state will be described in which a voltage higher than that during normal operation is applied to the drain of the N-type MOSFET 2b due to a short circuit in the main circuit or the like while the gate drive circuit 0 is outputting an ON signal (e.g., 15V).

Basically, a voltage is applied to the drain of N-type MOSFET 2b via a load (not shown), and the circuit operates in the same manner as when the gate drive circuit 0 is outputting an on signal (e.g., 15 V), and a current flows. However, because a large voltage is applied to the drain of N-type MOSFET 2b, the source potential of N-type MOSFET 2b also rises.

On the other hand, since a voltage (e.g. 15 V) is applied to the gate of N-type MOSFET 2b relative to ground, the gate-source voltage of N-type MOSFET 2b decreases as the source potential of N-type MOSFET 2b increases.

As a result, the channel resistance of N-type MOSFET 2b increases, preventing excessive current conduction.

Therefore, the semiconductor device 11 of this embodiment can suppress the conduction of an excessive current due to a short circuit or the like.

[Operation Example 4]
Next, the operation when a defect occurs in which the drain and source of the N-type MOSFET 2a are short-circuited will be described.

First, we will explain the state in which a voltage is applied to the drain of N-type MOSFET 2b and gate drive circuit 0 outputs an off signal (≦0V).

As described above, the signal from gate drive circuit 0 turns N-type MOSFET 1 and P-type MOSFET 4a off and P-type MOSFET 3a on, but because the drain and source of N-type MOSFET 2a are shorted, almost no potential difference is generated between the drain and source of N-type MOSFET 2a.

Although the gate voltage of the P-type MOSFET 4b (i.e. the drain voltage of the N-type MOSFET 2a) does not rise sufficiently, if the charge accumulated between the gate and source of the N-type MOSFET 2b is discharged until the gate-source voltage of the P-type MOSFET 4b falls to the gate threshold voltage of the P-type MOSFET 4b, the P-type MOSFET 4b will be turned off.

In this embodiment, when the sum of the gate threshold voltage of N-type MOSFET 2b and the gate threshold voltage of P-type MOSFET 4b is a positive value (for example, the gate threshold voltage of N-type MOSFET 2b is 3 V and the gate threshold voltage of P-type MOSFET 4b is -2 V), the gate-source voltage of N-type MOSFET 2b at this time becomes lower than the gate threshold voltage, and therefore N-type MOSFET 2b is also turned off.

In addition, in this embodiment, when the gate threshold voltage of P-type MOSFET 3b is greater than or equal to the gate threshold voltage of P-type MOSFET 4b (for example, the gate threshold voltage of P-type MOSFET 4b is -2 V and the gate threshold voltage of P-type MOSFET 3b is -1 V), P-type MOSFET 3b is in the ON state, and the gate and source of N-type MOSFET 2b are at the same potential, so N-type MOSFET 2b is in the OFF state.

[Operation Example 5]
Next, a state will be described in which a voltage is applied to the drain of the N-type MOSFET 2b via a load (not shown) and the gate drive circuit 0 outputs an ON signal (for example, 15V).

Even if the drain and source of N-type MOSFET 2a are shorted, when the transistors are conductive, the voltage applied to each terminal of each power transistor (N-type MOSFETs 1 to 2b) is the same as during normal operation, and the transistors can operate in the same manner as normal.

As a result, even if the drain-source of N-type MOSFET 2a is shorted, N-type MOSFET 2b (or all N-type MOSFETs from the next stage onwards, if the number of series connections is large) can be turned off, so that the deterioration of voltage resistance performance compared to normal conditions is limited to only the part originally covered by N-type MOSFET 2a. Also, conduction operation is possible in the same way as normal conditions.

Therefore, even if a short occurs between the drain and source of some of the power transistors (e.g., N-type MOSFET 2a) in the entire semiconductor device 11, the operation of the entire semiconductor device 11 can continue.

<Modification 1>
A modification of the semiconductor device of the present embodiment described above will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing the configuration of the modification of Fig. 1.

The difference from the configuration in Figure 1 is that the drain of P-type MOSFET 3a is connected to the source rather than the drain of the preceding N-type MOSFET 1, and the drain of P-type MOSFET 3b is connected to the source (and the gate of the preceding P-type MOSFET 4a) rather than the drain of the preceding N-type MOSFET 2a.

A feature of this modified example is that the N-type MOSFETs 2a and 2b in the second and subsequent stages can be either normally-off type or normally-on type.

Next, we will explain how it works.

[Operation Example 6]
First, a state in which a voltage is applied to the drain of the N-type MOSFET 2b and the gate drive circuit 0 outputs an off signal (≦0V) will be described.

The signal from gate drive circuit 0 turns off N-type MOSFET 1, and the potential at the drain of N-type MOSFET 1 rises.

As a result, the gate voltage of the P-type MOSFET 4a (i.e. the drain voltage of the N-type MOSFET 1) rises, the gate-source voltage of the P-type MOSFET 4a exceeds the gate threshold voltage of the P-type MOSFET 4a, and the P-type MOSFET 4a enters the off state.

In addition, the gate-source voltage of P-type MOSFET 3a falls below the gate threshold voltage of P-type MOSFET 3a, and P-type MOSFET 3a turns on.

As a result of the above-mentioned P-type MOSFET 4a being turned off and P-type MOSFET 3a being turned on, the gate of N-type MOSFET 2a has the same potential as the source of N-type MOSFET 1, i.e., a negative voltage is applied between the gate and source of N-type MOSFET 2a, so that N-type MOSFET 2a is turned off even though it is a normally-on type.

The above series of operations also occurs in P-type MOSFET 3b, P-type MOSFET 4b, and N-type MOSFET 2b, turning N-type MOSFET 2b off, and the entire semiconductor device 11 turns off, demonstrating high voltage resistance performance.

[Operation Example 7]
Next, a state will be described in which a voltage is applied to the drain of the N-type MOSFET 2b via a load (not shown) and the gate drive circuit 0 outputs an ON signal (for example, 15V).

The signal from gate drive circuit 0 turns on N-type MOSFET 1, causing the potential at the drain of N-type MOSFET 1 to decrease.

As a result, the gate voltage of the P-type MOSFET 4a (i.e. the drain voltage of the N-type MOSFET 1) drops, the gate-source voltage of the P-type MOSFET 4a falls below the gate threshold voltage of the P-type MOSFET 4a, and the P-type MOSFET 4a turns on.

In addition, the gate voltage of the P-type MOSFET 3a increases due to the signal from the gate drive circuit 0, causing the gate-source voltage of the P-type MOSFET 3a to exceed the gate threshold voltage of the P-type MOSFET 3a, turning off the P-type MOSFET 3a.

As a result of the above-mentioned P-type MOSFET 4a being turned on and P-type MOSFET 3a being turned off, an on signal (e.g. 15V) is supplied to the gate of N-type MOSFET 2a from gate drive circuit 0, and N-type MOSFET 2a is turned on.

At this time, a sufficiently large voltage is applied between the gate and source of the N-type MOSFET 2a, making the channel resistance of the N-type MOSFET 2a sufficiently small.

The above series of operations also occurs in P-type MOSFET 3b, P-type MOSFET 4b, and N-type MOSFET 2b, causing N-type MOSFET 2b to turn on, and the entire semiconductor device 11 to turn on and conduct current.

A semiconductor device according to a second embodiment of the present invention will be described with reference to Fig. 3. Fig. 3 is a circuit diagram showing the configuration of the semiconductor device according to this embodiment. The basic configuration is the same as that of the first embodiment, and the difference is that P-type MOSFETs 5a and 5b are added. Descriptions of parts common to the first embodiment will be omitted or simplified as appropriate.

In Example 1 (Figure 1), the voltage applied between the gate of N-type MOSFET 1 and the gate of N-type MOSFET 2a (equivalent to the source-drain voltage of N-type MOSFET 1) is equal to the voltage applied between the gate and source of P-type MOSFET 3a, so the voltage that can be applied between the drain and source of each N-type MOSFET (1, 2a, 2b) is limited to the drain-source withstand voltage of the N-type MOSFET (1, 2a, 2b) as well as the gate-source withstand voltage of P-type MOSFET 3a (generally around 20V).

Therefore, in this embodiment, a circuit configuration is described in which the voltage that can be applied between the drain and source of the N-type MOSFETs (1, 2a, 2b) is not limited by the gate-source withstand voltage of the P-type MOSFET 3a.

In this embodiment, as an example, the drain-source withstand voltage of N-type MOSFETs 1, 2a, and 2b is 100 V, and the drain-source withstand voltage of P-type MOSFETs 3a, 3b, 4a, and 4b is 20 V. In addition, the withstand voltage of P-type MOSFETs 5a and 5b is 80 V.

The source of the P-type MOSFET 3a is connected to the gate of the N-type MOSFET 2a, the drain is connected to the source of the N-type MOSFET 2a, and the gate is connected to the drain of the P-type MOSFET 4a and the source of the P-type MOSFET 5a.

The source of the P-type MOSFET 4a is connected to the gate of the N-type MOSFET 2a and the source of the P-type MOSFET 3a, the drain is connected to the source of the P-type MOSFET 5a and the gate of the P-type MOSFET 3a, and the gate is connected to the source of the N-type MOSFET 2a, the drain of the P-type MOSFET 3a, and the gate of the P-type MOSFET 5a.

The source of P-type MOSFET 5a is connected to the drain of P-type MOSFET 4a and the gate of P-type MOSFET 3a, the drain is connected to the gate of N-type MOSFET 1, and the gate is connected to the source of N-type MOSFET 2a, the drain of P-type MOSFET 3a, and the gate of P-type MOSFET 4a.

The connection relationship between the N-type MOSFET 2b and the P-type MOSFETs 3b, 4b, and 5b that constitute the circuit 20b is the same as the connection relationship between the N-type MOSFET 2a and the P-type MOSFETs 3a, 4a, and 5a that constitute the circuit 20a. In other words, the second stage and onwards in Figure 3 are two circuits 20a connected in series. In this embodiment, an example of two in series is shown, but the number of series connections may be changed as desired depending on the target withstand voltage.

In this embodiment, the N-type MOSFETs 1, 2a, 2b and the P-type MOSFETs 3a, 3b, 4a, 4b, 5a, 5b connected as described above are operated as a single semiconductor device 21.

Next, we will explain how it works.

[Operation example 8]
First, a state in which a voltage is applied to the drain of the N-type MOSFET 2b and the gate drive circuit 0 outputs an off signal (≦0V) will be described.

The signal from gate drive circuit 0 turns off N-type MOSFET 1, and the potential at the drain of N-type MOSFET 1 rises.

As a result, the gate voltage of the P-type MOSFET 4a (i.e. the drain voltage of the N-type MOSFET 1) rises, the gate-source voltage of the P-type MOSFET 4a exceeds the gate threshold voltage of the P-type MOSFET 4a, and the P-type MOSFET 4a enters the off state.

In addition, the gate voltage of P-type MOSFET 5a (i.e., the drain voltage of N-type MOSFET 1) rises, the gate-source voltage of P-type MOSFET 5a exceeds the gate threshold voltage of P-type MOSFET 5a, and P-type MOSFET 5a enters the off state.

In addition, when the drain voltage of P-type MOSFET 3a (i.e., the drain voltage of N-type MOSFET 1) rises, the built-in diode of P-type MOSFET 3a becomes conductive, and the source voltage of P-type MOSFET 3a (i.e., the source voltage of P-type MOSFET 4a) also rises in tandem.

Because the P-type MOSFETs 4a and 5a in the off state share the voltage applied to the source of P-type MOSFET 4a, the gate voltage of P-type MOSFET 3a becomes lower than the source voltage of P-type MOSFET 3a (i.e. the source voltage of P-type MOSFET 4a), so P-type MOSFET 3a enters the on state, the gate of N-type MOSFET 2a has the same potential as its source, and N-type MOSFET 2a enters the off state because it is a normally-off type.

The above series of operations also occurs in P-type MOSFETs 3b, 4b, 5b and N-type MOSFET 2b, turning N-type MOSFET 2b off, and the entire semiconductor device 21 turns off, demonstrating high voltage resistance performance.

In this embodiment, the voltage applied between the gate of N-type MOSFET 1 and the gate of N-type MOSFET 2a in the switch-off state (equivalent to the source-drain voltage of N-type MOSFET 1) is shared between the source-drain of P-type MOSFETs 4a and 5a, so that the voltage applied between the gate and source of P-type MOSFET 3a (i.e. the source-drain voltage of P-type MOSFET 4a) can be made smaller than the source-drain voltage of N-type MOSFET 1.

As a result, a semiconductor device can be realized having a circuit configuration in which the source-drain breakdown voltage of the N-type MOSFET 1 is not limited by the gate-source breakdown voltage of the P-type MOSFET 3a.

[Operation Example 9]
Next, a state will be described in which a voltage is applied to the drain of the N-type MOSFET 2b via a load (not shown) and the gate drive circuit 0 outputs an ON signal (for example, 15V).

The signal from gate drive circuit 0 turns on N-type MOSFET 1, causing the potential at the drain of N-type MOSFET 1 to decrease.

As a result, the gate voltage of the P-type MOSFET 4a (i.e. the drain of the N-type MOSFET 1) drops, the gate-source voltage of the P-type MOSFET 4a falls below the gate threshold voltage of the P-type MOSFET 4a, and the P-type MOSFET 4a turns on.

In addition, the gate voltage of the P-type MOSFET 5a (i.e., the drain voltage of the N-type MOSFET 1) decreases, the gate-source voltage of the P-type MOSFET 5a falls below the gate threshold voltage of the P-type MOSFET 5a, and the P-type MOSFET 5a enters the on state.

In addition, when the P-type MOSFET 4a is turned on, the gate-source voltage of the P-type MOSFET 3a exceeds the gate threshold voltage of the P-type MOSFET 3a, and the P-type MOSFET 3a is turned off.

As a result of the above-mentioned P-type MOSFETs 4a and 5a being turned on and P-type MOSFET 3a being turned off, an on signal (e.g., 15 V) is supplied to the gate of N-type MOSFET 2a from gate drive circuit 0, and N-type MOSFET 2a is turned on.

At this time, a sufficiently large voltage is applied between the gate and source of the N-type MOSFET 2a, making the channel resistance of the N-type MOSFET 2a sufficiently small.

The above series of operations also occurs in P-type MOSFET 3b, P-type MOSFET 4b, P-type MOSFET 5b, and N-type MOSFET 2b, causing N-type MOSFET 2b to turn on, and the entire semiconductor device 21 to turn on and conduct current.

[Operation Example 10]
Next, the operation when a defect occurs in which the drain and source of the N-type MOSFET 2a are short-circuited will be described.

First, we will explain the state in which a voltage is applied to the drain of N-type MOSFET 2b and gate drive circuit 0 outputs an off signal (≦0V).

As described above, the signal from gate drive circuit 0 turns N-type MOSFET 1, P-type MOSFETs 4a and 5a off and P-type MOSFET 3a on, but because the drain and source of N-type MOSFET 2a are shorted, almost no potential difference is generated between the drain and source of N-type MOSFET 2a.

Although the gate voltage of P-type MOSFETs 4b and 5b (i.e. the drain voltage of N-type MOSFET 2a) does not rise sufficiently, if the charge accumulated between the gate and source of N-type MOSFET 2b is discharged until the gate-source voltage of P-type MOSFET 4b or 5b falls to the gate threshold voltage of P-type MOSFET 4b or 5b, P-type MOSFET 4b or 5b will be turned off.

In this embodiment, when the sum of the gate threshold voltage of N-type MOSFET 2b and the gate threshold voltage of P-type MOSFET 4b is a positive value (for example, the gate threshold voltage of N-type MOSFET 2b is 3 V and the gate threshold voltage of P-type MOSFET 4b is -2 V), or when the sum of the gate threshold voltage of N-type MOSFET 2b and the gate threshold voltage of P-type MOSFET 5b is a positive value (for example, the gate threshold voltage of N-type MOSFET 2b is 3 V and the gate threshold voltage of P-type MOSFET 5b is -2 V), the gate-source voltage of N-type MOSFET 2b will then be lower than the gate threshold voltage, and N-type MOSFET 2b will also be in the off state.

<<Modification 2>>
A modification of the semiconductor device of the present embodiment described above will be described with reference to Fig. 4. Fig. 4 is a circuit diagram showing the configuration of the modification of Fig. 3.

The difference from the configuration in Figure 3 is that the gate of P-type MOSFET 5a is connected to the gate of P-type MOSFET 4a indirectly via a constant voltage diode 7a rather than directly, and is also connected to the source of the preceding N-type MOSFET 1 indirectly via a constant voltage diode 6a rather than directly.

Similarly, the gate of P-type MOSFET 5b is connected to the gate of P-type MOSFET 4b via a constant voltage diode 7b, and is also connected to the source of N-type MOSFET 2a via a constant voltage diode 6b.

According to this modification, in the switch-off state, the gate voltage of the P-type MOSFET 5a can be made arbitrarily smaller than the gate voltage of the P-type MOSFET 4a by voltage sharing by the constant voltage diodes 6a and 7a.

Therefore, when a circuit configuration is adopted in which the number of series connections in circuit 22, which is composed of a combination of P-type MOSFETs 5a and constant voltage diodes 6a, is increased, a gate voltage appropriate to the source voltage of the P-type MOSFETs 5a connected in series in the switch-off state can be applied to each of the P-type MOSFETs 5a, 5b, thereby preventing an excessive voltage from being applied between the gate and source of the P-type MOSFET 5a.

According to each of the embodiments of the present invention described above, in a high-voltage power transistor configured by connecting a plurality of power transistors in series and capable of controlling the plurality of power transistors by a single gate drive circuit,
(1) It is possible to realize a semiconductor device having a circuit configuration in which, even if the second-stage or later power transistors among a plurality of power transistors connected in series are of normally-off type, they can be autonomously controlled in conjunction with the first-stage power transistor.

(2) In addition, a semiconductor device can be realized in which the withstand voltage of power transistors in the second stage and beyond is not limited by the withstand voltage of the gate oxide film.

(3) Furthermore, even if some of the multiple power transistors connected in series have a source-drain voltage failure (short circuit), the other power transistors can be turned off, thereby realizing a semiconductor device in which the voltage resistance of the entire series of power transistors connected in series does not decrease significantly.

By forming the N-type MOSFETs 1 to 2b on a chip having a substrate of GaN (gallium nitride) or SiC (silicon carbide), and forming the P-type MOSFETs 3a, 3b, 4a, and 4b on a chip having a substrate of Si (silicon), it is possible to prevent malfunction of the P-type MOSFETs 3a, 3b, 4a, and 4b while improving the operating characteristics of the power transistors N-type MOSFETs 1 to 2b.

Alternatively, it goes without saying that the N-type MOSFETs 1 to 2b and the P-type MOSFETs 3a, 3b, 4a, and 4b may be formed on the same chip having a GaN or SiC substrate.

The present invention is not limited to the above-mentioned embodiment, and various modifications are included. For example, the above-mentioned embodiment has been described in detail to easily explain the present invention, and is not necessarily limited to those having all the configurations described. In addition, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with another configuration.
In addition, in the present invention, the N-type and P-type conductivity types may be reversed.

0...gate drive circuit, 1...N-type MOSFET, 2a...N-type MOSFET, 2b...N-type MOSFET, 3a...P-type MOSFET, 3b...P-type MOSFET, 4a...P-type MOSFET, 4b...P-type MOSFET, 5a...P-type MOSFET, 5b...P-type MOSFET, 6a...voltage regulating diode, 6b...voltage regulating diode, 7a...voltage regulating diode, 7b...voltage regulating diode, 10a...circuit consisting of P-type MOSFET and N-type MOSFET, 10b...circuit consisting of P-type MOSFET and N-type MOSFET, 11...semiconductor device, 20a...circuit consisting of P-type MOSFET and N-type MOSFET, 20b...circuit consisting of P-type MOSFET and N-type MOSFET, 21...semiconductor device, 22...circuit consisting of P-type MOSFET and voltage regulating diode

Claims (13)

A semiconductor device including a plurality of semiconductor elements connected in multiple stages, in which a drive signal is input from a gate drive circuit to a gate of a first stage and a drain of a previous stage and a source of a next stage are connected in series,
When one of the N-type and P-type conductivity types is defined as a first conductivity type and the other conductivity type is defined as a second conductivity type,
the plurality of semiconductor elements are first conductivity type MOSFETs;
one or more first second-conductivity-type MOSFETs that, when an on-drive signal is input from the gate drive circuit to a gate of a first-stage semiconductor element, supply the on-drive signal to a second-stage or subsequent semiconductor element to turn on the second-stage or subsequent semiconductor element;
one or more second second-conductivity-type MOSFETs that turn off the first second-conductivity-type MOSFET and supply a source or drain voltage of a previous-stage semiconductor element to a gate of the second-stage or later semiconductor element when an off drive signal is input from the gate drive circuit to the gate of the first-stage semiconductor element, thereby turning off the second-stage or later semiconductor element;
A semiconductor device comprising: 2. The semiconductor device according to claim 1,
a first second-conductivity-type MOSFET that supplies an on-drive signal to an n-th stage semiconductor element among the first second-conductivity-type MOSFETs has a gate connected to a drain of an n-1-th stage semiconductor element, a source connected to a gate of the n-th stage semiconductor element, and a drain connected directly or indirectly to a gate of the n-1-th stage semiconductor element. 3. The semiconductor device according to claim 2,
the first MOSFET having a gate connected directly or indirectly to the gate of the first MOSFET of a second conductivity type, the first MOSFET having a source connected directly or indirectly to the drain of the first MOSFET of a second conductivity type, and the n-1th stage semiconductor element having a drain connected directly or indirectly to the gate of the n-1th stage semiconductor element. 4. The semiconductor device according to claim 3,
a gate of the third second-conductivity-type MOSFET is connected to a gate of the first second-conductivity-type MOSFET via a first constant-voltage diode, and is connected to a source of a preceding-stage semiconductor element via a second constant-voltage diode. 2. The semiconductor device according to claim 1,
Among the plurality of semiconductor elements, the semiconductor elements in the second and subsequent stages are normally-off type,
a second second-conductivity-type MOSFET provided corresponding to a first second-conductivity-type MOSFET that supplies an on-drive signal to an n-th stage semiconductor element, the second second-conductivity-type MOSFET having a gate connected to a drain of the first second-conductivity-type MOSFET, a source connected to a gate of the n-th stage semiconductor element, and a drain connected to the gate of the first second-conductivity-type MOSFET and the drain of the n-1-th stage semiconductor element. 2. The semiconductor device according to claim 1,
a second second-conductivity-type MOSFET provided corresponding to a first second-conductivity-type MOSFET that supplies an on-drive signal to an n-th stage semiconductor element, the second second-conductivity-type MOSFET having a gate connected to a drain of the first second-conductivity-type MOSFET, a source connected to a gate of the n-th stage semiconductor element, and a drain connected to a source of the n-1-th stage semiconductor element. 2. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the semiconductor elements in the second and subsequent stages among the plurality of semiconductor elements are of a normally-off type. 2. The semiconductor device according to claim 1,
a second or subsequent stage semiconductor element among the plurality of semiconductor elements is a normally-on type, and the second second-conductivity-type MOSFET supplies a source voltage of a previous stage semiconductor element to a gate of the second or subsequent stage semiconductor element to turn off the second or subsequent stage semiconductor element. 2. The semiconductor device according to claim 1,
The semiconductor element is formed on a chip having a substrate of GaN or SiC,
The first second-conductivity-type MOSFET and the second second-conductivity-type MOSFET are formed on a chip having a Si substrate. 2. The semiconductor device according to claim 1,
a first MOSFET of a second conductivity type and a second MOSFET of a second conductivity type formed on a single chip having a substrate made of GaN or SiC; 11. The semiconductor device according to claim 1,
13. A semiconductor device, comprising: a first conductivity type being an N-type; and a second conductivity type being a P-type. 11. The semiconductor device according to claim 1,
13. A semiconductor device, comprising: a first conductivity type being P-type; and a second conductivity type being N-type. A power conversion device using a semiconductor device according to any one of claims 1 to 10.

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