JP7617171B2 - Resistive random access memory having a post-patterned memory film to provide improved endurance characteristics and method of forming same - Google Patents

Description

This disclosure relates to semiconductor structures and methods for forming the same.

Some types of resistive memory devices use a dielectric metal oxide material in which conductive paths containing oxygen vacancies are formed. The conductive paths can be formed or erased by applying an electrical bias to two electrodes provided on the dielectric metal oxide material, and information can be stored by providing different resistance values between the two electrodes depending on the presence or absence of the conductive paths.

According to various embodiments of the present disclosure, a semiconductor structure is provided that includes a first electrode comprising a first metallic material, a memory film comprising at least one dielectric metal oxide material and contacting the first electrode, the memory film comprising a central region having a first average atomic ratio of a passivating element to oxygen less than 0.01 and a peripheral region having a second average atomic ratio of a passivating element to oxygen greater than 0.05, and a second electrode comprising a second metallic material and contacting the memory film. In one embodiment, the passivating element is selected from fluorine and nitrogen.

According to another aspect of the present disclosure, there is provided a semiconductor structure including a two-dimensional array of memory cells, the memory cells including a respective first electrode overlaid with a substrate 8, a respective memory film, and a respective second electrode, each memory film in the two-dimensional array stack including a respective central region having an average atomic ratio of a passivation element to oxygen less than 0.01 and a respective peripheral region having an average atomic ratio of the passivation element to oxygen greater than 0.05. In one embodiment, the passivation element is selected from fluorine and nitrogen.

According to various embodiments of the present disclosure, a method for forming a semiconductor structure is provided, comprising forming a stack above a substrate, the stack including a first electrode, at least one memory film including a non-stoichiometric oxygen-deficient dielectric metal oxide material, and a second electrode, and performing a passivation plasma treatment on the stack such that an average atomic ratio of the passivation element to oxygen in a peripheral region of the memory film increases from a first number less than 0.01 to a second number greater than 0.05, the passivation element being selected from fluorine and nitrogen.

Aspects of the present disclosure are best understood from the following detailed description when considered in conjunction with the accompanying drawings, in which: It should be noted that, as is standard practice in the industry, various features are not drawn to scale, and in fact, sizes of various features may be arbitrarily increased or decreased for clarity.
FIG. 2 is a vertical cross-sectional view of a first exemplary structure after formation of a complementary metal-oxide-semiconductor (CMOS) transistor and a lower level metal interconnect structure formed in a lower level dielectric material layer and a lower level via hole dielectric layer in accordance with an embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view of the first exemplary structure after a bottom connection via hole structure is formed according to an embodiment of the present disclosure. FIG. 2B is a plan view of the first exemplary structure of FIG. 2A. FIG. 2B is an enlarged view of region C in FIG. 2A. FIG. 2 is a vertical cross-sectional view of an enlarged view of region C of the first exemplary structure after an etch-stop dielectric material layer and a patterned photoresist layer are formed in accordance with an embodiment of the present disclosure. FIG. 13 is a vertical cross-sectional view of an enlarged view of region C of the first exemplary structure after patterning an etch-stop dielectric material layer according to an embodiment of the present disclosure to deposit a layer stack including at least one bottom metal barrier layer, a bottom electrode layer, at least one dielectric metal oxide layer, a top electrode layer, at least one top metal barrier layer, and a hard shield layer. FIG. 2 is a vertical cross-sectional view of an enlarged view of region C of the first exemplary structure after a patterned photoresist layer is formed in accordance with an embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view of an expanded view of region C including memory cells of the first exemplary structure after a memory cell array has been formed according to an embodiment of the present disclosure. 6B is a plan view of a first exemplary structure at the processing stage of FIG. 6A. FIG. 2 is a vertical cross-sectional view of an expanded view of region C including memory cells of the first exemplary structure after a passivation plasma treatment process has been performed according to an embodiment of the present disclosure. 1 shows exemplary x-ray photoelectron spectroscopy data from an untreated hafnium oxide surface and from a hafnium oxide surface treated with a plasma containing a passivating element. FIG. 2 is a vertical cross-sectional view of a first exemplary structure after an upper via level dielectric material layer and a connecting via structure are formed in accordance with an embodiment of the present disclosure. 9B is an enlarged view of a region of the first exemplary structure at the processing stage of FIG. 9A. FIG. 2 is a vertical cross-sectional view of a first exemplary structure after bitlines are formed in accordance with an embodiment of the present disclosure. FIG. 10B is a plan view of the first exemplary structure of FIG. 10A. 2 is a vertical cross-sectional view of a region of a memory cell including an alternative configuration of a first exemplary structure according to an embodiment of the present disclosure. FIG. 13 is a vertical cross-sectional view of a region of a second exemplary structure after an etch-stop dielectric material layer, a bottom metal barrier via-hole structure, a bottom electrode layer, at least one dielectric metal oxide layer, a top electrode layer, at least one top metal barrier layer, and a hard shield layer are formed in accordance with an embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view of an area of a second exemplary structure after a patterned photoresist layer is formed thereon according to an embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view of a region of the second exemplary structure after a hard shield structure and a top electrode are formed in accordance with an embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view of an area of the second exemplary structure after dielectric spacers have been formed in accordance with an embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view of an area of a second exemplary structure after a memory film and a bottom electrode are formed in accordance with an embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view of a second exemplary structure after a dielectric material layer for an upper via hole and a connecting via hole structure are formed according to an embodiment of the present disclosure. 17B is an enlarged view of a region of the second exemplary structure at the processing stage of FIG. 17A. FIG. 13 is a vertical cross-sectional view of a second exemplary structure after bitlines are formed in accordance with embodiments of the present disclosure. FIG. 18B is a plan view of the second exemplary structure of FIG. 18A. 4 is a vertical cross-sectional view of a region of a memory cell including a first alternative configuration of a second exemplary structure according to an embodiment of the present disclosure. 11 is a vertical cross-sectional view of a region of a memory cell including a second alternative configuration of a second exemplary structure according to an embodiment of the present disclosure. 11 is a vertical cross-sectional view of a region of a memory cell including a third alternative configuration of the second exemplary structure according to an embodiment of the present disclosure. FIG. 1 is a flow diagram illustrating general process steps for manufacturing a semiconductor device of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing different features of the provided objects. In the following, specific examples of assembly parts and arrangements are described to simplify the disclosure. Of course, these are merely examples and are not limiting. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first feature is formed so as to directly contact the second feature, and may include an embodiment in which an additional feature may be formed between the first feature and the second feature such that the first feature does not directly contact the second feature. It should be noted that the disclosure may refer to repeated numbers and/or letters in various examples. This repetition is for the purposes of simplicity and clarity and does not indicate a relationship between the various embodiments and/or configurations described.

It should be noted that, for ease of explanation, spatially relative terms such as "below," "under," "lower," "over," "top," and the like may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures. The spatially relative terms are intended to cover different orientations in which the device is used or operated other than that shown in the figures. The device may be oriented in another way (rotated 90 degrees or at another orientation) and the spatially relative descriptors used herein may be interpreted similarly. Elements having the same reference numbers refer to the same elements and are assumed to have the same material composition and thickness ranges unless otherwise specified.

A resistive memory cell includes a resistive memory material whose resistivity changes in response to programming conditions. One type of memory cell uses a high dielectric constant (high-k) metal oxide material in which conductive threads can be formed. The conductive threads may include continuous oxygen-deficient regions formed by oxygen atomic migration. Such oxygen-deficient conductive threads are considered to be crystal defects, and can be programmed by applying an appropriate electrical bias voltage. Also, such oxygen-deficient conductive threads can be erased by applying a reverse electrical bias voltage. Thus, the presence or absence of oxygen-deficient conductive threads can be used to encode binary data bits in a resistive memory cell.

During the fabrication process, the exposed surface segments of the metal oxide material may be incidentally damaged by etchant ions, making them more susceptible to the formation of oxygen-deficient conductive filaments and providing unfavorable conditions for the removal of the oxygen-deficient conductive filaments. Such surface segments may reduce the endurance of the resistive memory cell, e.g., below 200,000 program and erase cycles, and may cause an increase in the leakage current of the resistive memory cell.

Oxygen vacancy filaments may be more likely to form at locations with the strongest electric field. Simulations show that oxygen vacancy filaments may be more likely to form on the surface regions under the sidewalls of the dielectric metal oxide thin film. Oxygen vacancies in the central region of the dielectric metal oxide material provide stable electrical properties for the resistive memory device, but oxygen vacancies formed on the etched surface of the dielectric metal oxide material tend to change electrical properties due to damage caused during the etching process, increasing the variability of the electrical properties of the resistive memory device.

According to aspects of the present disclosure, plasma treatment with a fluorine-containing or nitrogen-containing plasma can suppress oxygen deficiency filaments formed by crystal defects introduced during an anisotropic etching process in surface regions of the dielectric metal oxide memory film outside the programming voltage range. A surface passivation layer is formed having an oxygen content less than a central region of the dielectric metal oxide memory film. The surface passivation layer can be oxygen-free or oxygen-containing. The formation of oxygen deficiency filaments in the surface passivation layer is suppressed. The endurance of the memory cell can be enhanced, such as over 100,000 programming and erasing cycles, and the lack of oxygen deficiency filaments in the surface region of the memory film can reduce leakage current through the memory cell. Although described using a resistive memory cell, the structures and methods of the present disclosure are also applicable to conductive bridge random access memory devices, and such applications are expressly contemplated herein. Each aspect of the present disclosure will now be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, a first exemplary structure according to a first embodiment of the present disclosure is shown. The first exemplary structure includes a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at at least a top portion thereof. The semiconductor material layer 9 may be a surface segment of a bulk semiconductor substrate or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single crystal semiconductor material, such as single crystal silicon. In one embodiment, the substrate 8 may include a single crystal silicon substrate, which includes a single crystal silicon material.

A shallow trench isolation structure 720 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer 9. Appropriately doped semiconductor wells, such as p-type wells and n-type wells, may be formed in each region laterally bounded by a portion of the shallow trench isolation structure 720. Field effect transistors (70A, 701) may be formed above an upper surface of the semiconductor material layer 9. The field effect transistors (70A, 701) may include an array of access transistors 70A, which are used to individually access each memory cell in a two-dimensional array of memory cells to be subsequently formed. The field effect transistors (70A, 701) may also include peripheral field effect transistors 701 in peripheral circuitry. For example, the peripheral field effect transistors 701 may include bit line drivers for applying bit line bias voltages to subsequently formed bit lines, and sense amplifiers for detecting current flowing through the bit lines during a read operation.

For example, each field effect transistor (70A, 701) may include a source electrode 732, a drain electrode 738, a semiconductor channel 735 including a surface segment of the substrate 8 extending between the source electrode 732 and the drain electrode 738, and a gate structure 750. The semiconductor channel 735 may include a single crystal semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source side metal semiconductor alloy region 742 may be formed on each source electrode 732, and a drain side metal semiconductor alloy region 748 may be formed on each drain electrode 738.

The first exemplary structure may include a memory array region 100 in which a memory cell array may later be formed. The first exemplary structure may further include a peripheral region 200 in which metal wiring for the memory device array is provided. In general, the access transistors 70A in the CMOS circuit system 700 may be electrically connected to electrodes of individual memory cells that are later formed with individual metal interconnect structures.

The devices in the peripheral region 200 (e.g., peripheral field effect transistors 701) can provide functionality for operating a memory cell array that is subsequently formed. In particular, the devices in the peripheral region can be used to control programming, erasing, and sensing (read) operations of the memory cell array. For example, the devices in the peripheral region may include sensing circuitry and/or programming circuitry. The devices formed on the top surface of the semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.), collectively referred to as the CMOS circuitry system 700.

One or more of the field effect transistors (70A, 701) in the CMOS circuit system 700 may include a semiconductor channel 735 that includes a portion of the semiconductor material layer 9 in the substrate 8. If the semiconductor material layer 9 includes a single crystal semiconductor material, such as single crystal silicon, the semiconductor channel 735 of each field effect transistor (70A, 701) in the CMOS circuit system 700 may include a single crystal semiconductor channel, such as a single crystal silicon channel. In one embodiment, the multiple access transistors 70A in the CMOS circuit system 700 may include individual nodes that are subsequently electrically connected to nodes of individual memory cells that are subsequently formed.

In one embodiment, the substrate 8 may include a single crystal silicon substrate, and the field effect transistor 701 may include a discrete portion of the single crystal silicon substrate as a semiconductor channel. As used herein, a "semiconductor" device refers to a device having a conductivity in the range of 1.0×10 ^-6 S/cm to 1.0×10 ⁵ S/cm. As used herein, a "semiconductor material" refers to a material that has a conductivity in the range of 1.0×10 ^-6 S/cm to 1.0×10 ⁵ S/cm in the absence of dopants, and that can produce a conductivity in the range of 1.0 S/cm to 1.0×10 ⁵ S/cm when appropriately doped with dopants.

Various metal interconnect structures formed within the dielectric material layers may later be formed above the substrate 8 and semiconductor devices thereon (e.g., field effect transistors (70A, 701)). In an illustrative example, the dielectric material layers may include a first dielectric material layer 601, which may be, for example, a layer surrounding contact structures connected to the source and drain (sometimes referred to as contact level dielectric material layer 601), a first interconnect level dielectric material layer 610, and a second interconnect level dielectric material layer 620. The metal interconnect structure may include a device contact via structure 612 formed in the first dielectric material layer 601 and contacting individual elements of the CMOS circuit system 700, a first metal wiring structure 618 formed in the first interconnect level dielectric material layer 610, a first metal via structure 622 formed in a lower portion of the second interconnect level dielectric material layer 620, a second metal wiring structure 628 formed in an upper portion of the second interconnect level dielectric material layer 620, a second metal via structure 632 formed in a lower portion of the third interconnect level dielectric material layer 630, and a third metal wiring structure 638 formed in an upper portion of the third interconnect level dielectric material layer 630.

Each of the dielectric material layers (601, 610, 620, 630) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638) may include at least one conductive material that may be a combination of a metal lining (e.g., a metal nitride or a metal carbide) and a metal fill material. Each metal lining may include TiN, TaN, WN, TiC, TaC, and WC, and each metal fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable linings and metal fill materials may be used within the contemplation of the disclosure. In one embodiment, the first metal via structure 622 and the second metal wiring structure 628 may be formed into an integrated wiring and via structure by a dual damascene process. Similarly, the second metal via structure 632 and the third metal wiring structure 638 may be formed into an integrated wiring and via structure by a dual damascene process. In this specification, the dielectric material layers (601, 610, 620, 630) are referred to as lower-lower level dielectric material layers. The metal interconnect structures (612, 618, 622, 628, 632, 638) formed in the lower-lower level dielectric material layers are referred to as lower level metal interconnect structures.

Although this disclosure describes embodiments in which the memory cell array may be formed above the third wiring-via level dielectric material layer 630, embodiments in which the memory cell array may be formed at a different metal interconnect level are expressly contemplated herein.

In one embodiment, a planar dielectric material layer having a uniform thickness may be formed above the lower level dielectric material layer (601, 610, 620, 630). The planar dielectric material layer is referred to herein as the lower via hole level dielectric layer 645. The lower via hole level dielectric layer 645 comprises a dielectric material. In one embodiment, the lower via hole level dielectric layer 645 may comprise an extremely low-k (ELK) dielectric material. In one embodiment, the lower via hole level dielectric layer 645 comprises and/or consists essentially of at least one dielectric material selected from undoped silicate glass, doped silicate glass, organo-silicon glass, porous dielectric material, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon carbonitride. The lower via hole level dielectric layer 645 may be deposited, for example, by chemical vapor deposition. The thickness of the lower via hole level dielectric layer 645 may be in the range of 20 nm to 300 nm, although smaller or larger thicknesses may be used.

In general, metal interconnect structures (referred to herein as lower level metal interconnect structures (612, 618, 622, 628, 632, 638)) embedded within an interconnect level dielectric layer (e.g., lower level dielectric material layer (601, 610, 620, 630)) may be formed above the semiconductor device. A lower via level dielectric layer 645 may be formed above the interconnect level dielectric layer.

2A-2C, a photoresist layer (not shown) can be applied over the lower via hole level dielectric layer 645 and lithographically patterned to form a two-dimensional array of openings. The two-dimensional array of openings can have a first pitch along a first horizontal direction hd1 and a second pitch along a second horizontal direction hd2. Each of the openings in the photoresist layer can have a circular, oval, elliptical, rectangular, rounded rectangular, or any other two-dimensional curvilinear horizontal cross-sectional shape with a closed perimeter. An anisotropic etching process can be performed to transfer the pattern of openings in the photoresist layer through the lower via hole level dielectric layer 645. The top surfaces of the individual lower level metal interconnect structures (e.g., the top surfaces of the individual third metal wiring structures 638 in the illustrated example) can be substantially exposed at the bottom of each opening through the lower via hole level dielectric layer 645. The photoresist layer can then be removed, for example, by ashing.

The two-dimensional array of openings may be filled with at least one metal fill material. In one embodiment, the at least one metal fill material may include a combination of a metal lining layer including a metal barrier material and a metal fill material layer including a metal fill material. The metal lining layer may include a metal barrier material such as TiN, TaN, WN, TiC, TaC, WC, or stacks thereof, and may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the metal lining layer may be in the range of 1 nm to 30 nm, although smaller or larger thicknesses may be used. The metal fill material layer may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to remove the metal lining layer and portions of the metal fill material layer that are covered by horizontal surfaces, including the top surface of the lower via hole level dielectric layer 645.

Each remaining portion of the at least one metal material includes a bottom connection via hole structure 15 that is in electrical contact with a respective lower level metal interconnect structure (e.g., the top surface of the respective third metal wiring structure 638 in the illustrated example). A two-dimensional array of bottom connection via hole structures 15 may be formed in the lower via hole level dielectric layer 645. In general, the horizontal cross-sectional shape of each bottom connection via hole structure 15 may be any two-dimensional shape having a closed perimeter. For example, the horizontal cross-sectional shape of the bottom connection via hole structure 15 may be a circle, an oval, an ellipse, a rectangle, a round-cornered rectangle, or any two-dimensional curved shape having a closed perimeter. Other shapes are contemplated within the scope of the disclosure. The top surface of the bottom connection via hole structure 15 may be flush with the top surface of the lower via hole level dielectric layer 645. The periodicity of the bottom connection via hole structures 15 along a first horizontal direction hd1 may be a first pitch p1. The periodicity of the bottom connection via hole structures 15 along the second horizontal direction hd2 is referred to herein as the second pitch p2.

3, an etch stop dielectric material layer 18 may be formed above the lower via hole level dielectric layer 645. The etch stop dielectric material layer 18 includes a dielectric material that can be used as an etch stop structure for an anisotropic etching process to subsequently pattern the memory cells. In one embodiment, the etch stop dielectric material layer 18 includes and/or consists essentially of a material such as silicon carbide, silicon nitride, or silicon carbonitride. In one embodiment, the etch stop dielectric material layer 18 includes and/or consists essentially of silicon carbide. The thickness of the etch stop dielectric material layer 18 may be in the range of 3 nm to 60 nm, such as 6 nm to 30 nm, although lesser or greater thicknesses may be used. The etch stop dielectric material layer 18 may be formed, for example, by chemical vapor deposition. Typically, the etch stop dielectric material layer 18 is above the metal interconnect structures (612, 618, 622, 628, 632, 638, 15).

Above the etch-stop dielectric material layer 18, a photoresist layer 19 may be applied and lithographically patterned to form a periodic two-dimensional array of openings therein. Each opening in the photoresist layer 19 may be formed in a distinct area below the top surface of the bottom connection via hole structure 15. The periodic two-dimensional array of openings may have the same periodicity as the two-dimensional array of bottom connection via hole structures 15.

Referring to FIG. 4, an anisotropic etching process can be performed to transfer the pattern of openings in the photoresist layer 19 through the etch-stop dielectric material layer 18. A two-dimensional array of openings can be formed through the etch-stop dielectric material layer 18. The photoresist layer 19 can then be removed, for example, by ashing. The top surface of the bottom connection via hole structure 15 can be substantially exposed at the bottom of each opening by the etch-stop dielectric material layer 18.

A layer stack of material layers can then be deposited above the etch stop dielectric material layer 18 and the exposed surface of the bottom connection via hole structure 15. According to aspects of the present disclosure, the layer stack can include, from bottom to top, at least one optional bottom metal barrier layer 22L, a first electrode layer 24L, a memory material layer 26L, a second electrode layer 28L, at least one optional top metal barrier layer 29L, and a hard shield layer 30L. In total, the layer stack including at least one optional bottom metal barrier layer 22L, a first electrode layer 24L, a memory material layer 26L, a second electrode layer 28L, and at least one optional top metal barrier layer 29L can represent a memory cell stack 20L.

The at least one selective bottom metal barrier layer 22L includes at least one metal barrier material, such as titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium, tantalum, and/or tungsten. In an illustrative example, the at least one selective bottom metal barrier layer 22L may include a layer stack including, from bottom to top, a first bottom metal barrier layer 221L, a second bottom metal barrier layer 222L, and a third bottom metal barrier layer 223L. In an illustrative example, the first bottom metal barrier layer 221L may include titanium nitride, the second bottom metal barrier layer 222L may include tantalum, and the third bottom metal barrier layer 223L may include tantalum nitride. The total thickness of the at least one bottom metal barrier layer 22L may be in the range of 3 nm to 60 nm, such as 6 nm to 30 nm, although smaller or larger thicknesses may be used. Each of the at least one bottom metal barrier layer 22L can be deposited by physical vapor deposition or chemical vapor deposition.

The first electrode layer 24L (also referred to as the bottom electrode layer) comprises a metallic material such as titanium nitride, tantalum, tungsten, platinum, ruthenium, iridium, molybdenum, niobium, rhenium, osmium, or other elemental metals having a melting temperature greater than 1500 degrees Celsius. The thickness of the first electrode layer 24L may be in the range of 3 nm to 60 nm, such as 6 nm to 30 nm, although lesser or greater thicknesses may be used. The first electrode layer 24L may be deposited by physical vapor deposition or chemical vapor deposition.

The memory material layer 26L includes at least one dielectric metal oxide layer (261L, 262L). According to aspects of the present disclosure, each of the at least one dielectric metal oxide layer (261L, 262L) includes and/or consists essentially of at least one filamentary dielectric metal oxide material. As used herein, a filamentary dielectric metal oxide material refers to a dielectric metal oxide material capable of forming an oxygen-deficient filament (i.e., an oxygen-deficient filament) upon application of an electrical bias, where the electric field produced by the electrical bias has a value greater than the strength of the respective critical electric field. In one embodiment, each of the at least one filamentary dielectric metal oxide material in the at least one dielectric metal oxide layer (261L, 262L) is a non-stoichiometric oxygen-deficient dielectric metal oxide material.

In an illustrative example, the at least one dielectric metal oxide layer (261L, 262L) may include a layer stack of a first dielectric metal oxide layer 261L and a second dielectric metal oxide layer 262L. The first dielectric metal oxide layer 261L includes and/or consists essentially of a first dielectric metal oxide material including a dielectric metal oxide of at least one first metal. The second dielectric metal oxide layer 262L includes and/or consists essentially of a second dielectric metal oxide material including a dielectric metal oxide of at least one second metal. The second dielectric metal oxide material may differ in material composition from the first dielectric metal oxide material. In one embodiment, the at least one second metal differs from the at least one first metal by the presence of a metal element not present in the at least one first metal or the absence of a metal element present in the at least one first metal.

In one embodiment, one, more, and/or each of the dielectric metal oxide materials in the at least one dielectric metal oxide layer (261L, 262L) may include and/or consist of individual threadlike metal oxide materials, which are binary oxide materials, i.e., compounds of a single metal element and oxygen. For example, one, more, and/or each of the at least one dielectric metal oxide layer (261L, 262L) may include and/or consist of a material selected from _HfO2(1-α) , _{Ta2O5 (1-β)} , and _{Y2O3 (1-γ)} . In this embodiment, α, β, and γ may each independently be in the range of 1.0× ^10-6 to 1.0× ^10-1 .

In one embodiment, one, more than one, and/or each of the dielectric metal oxide materials in at least one dielectric metal oxide layer (261L, 262L) may include and/or consist of individual thread-like metal oxide materials, which are ternary oxide materials, i.e., compounds of two metal elements and an acid. Non-limiting examples of such ternary filamentous metal oxide materials include hafnium silicate (HfSiO _x ), hafnium zirconate (HfZrO _x ), barium titanate (BaTiO ₃ ), lead titanate (PbTiO ₃ ), strontium titanate (SrTiO ₃ ), potassium manganate (CaMnO ₃ ), bismuth ferrate (BiFeO ₃ ), doped HfO ₂ (containing dopants selected from Si, Zr, Y, Al, Gd, Sr, La, Sc, Ge, etc.), and alloys of HfO _{2 (1-α)} , Ta ₂ O _{5 (1-β)} , and Y ₂ O _{3 (1-γ)} .

In one embodiment, multiple and/or each of the dielectric metal oxide materials in at least one dielectric metal oxide layer (261L, 262L) may include and/or consist of individual threadlike metal oxide materials, which are quaternary oxide materials, i.e., compounds of three metal elements and _oxygen . Non-limiting examples of such threadlike metal _{quaternary oxide materials include lead zirconium titanate (PZT: PbZrxTiyOz), barium strontium titanate (BaSrTiOx), strontium bismuth tantalate (SBT: SrBi2Ta2O9 ) , and alloys of} the binary and/or ternary threadlike metal oxide materials listed above.

In general, the at least one dielectric metal oxide layer (261L, 262L) formed in this process step may be free of fluorine and nitrogen atoms and/or may contain only trace amounts of fluorine or nitrogen atoms (e.g., atomic concentrations less than 0.1 parts per million). The at least one dielectric metal oxide layer (261L, 262L) may be formed by any suitable deposition process known in the art, such as physical vapor deposition or chemical vapor deposition. The thickness of the memory material layer 26L may be in the range of 4 nm to 60 nm, such as 6 nm to 30 nm, although smaller or larger thicknesses may be used. In embodiments where the memory material layer includes a layer stack of multiple dielectric metal oxide layers, such as a layer stack of a first dielectric metal oxide layer 261L and a second dielectric metal oxide layer 262L, the thickness of each dielectric oxide layer (261L or 262L) may be in the range of 1 nm to 50 nm, although smaller or larger thicknesses may be used.

The second electrode layer 28L (also referred to as the top electrode layer) comprises a metallic material such as titanium nitride, tantalum, tungsten, platinum, ruthenium, iridium, molybdenum, niobium, rhenium, osmium, or other elemental metals having a melting temperature greater than 1500 degrees Celsius. The thickness of the second electrode layer 28L may be in the range of 3 nm to 60 nm, such as 6 nm to 30 nm, although lesser or greater thicknesses may be used. The second electrode layer 28L may be deposited by physical vapor deposition or chemical vapor deposition.

The at least one selective top metal barrier layer 29L includes at least one metal barrier material, such as titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium, tantalum, and/or tungsten. In an illustrative example, the at least one selective top metal barrier layer 29L may include a layer stack, including, from bottom to top, a first top metal barrier layer 291L and a second top metal barrier layer 292L. In an illustrative example, the first top metal barrier layer 291L may include titanium nitride and the second top metal barrier layer 292L may include tantalum nitride. The total thickness of the at least one top metal barrier layer 29L may be in the range of 3 nm to 60 nm, such as 6 nm to 30 nm, although lesser or greater thicknesses may be used. Each of the at least one top metal barrier layer 29L may be deposited by physical vapor deposition or chemical vapor deposition.

A hard shield layer 30L may be deposited above the at least one selective top metal barrier layer 29L. The hard shield layer 30L includes a material capable of protecting the underlying material during a subsequent anisotropic etching process. The hard shield layer 30L may include a metallic material such as titanium nitride, or may include a dielectric material such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and/or a dielectric metal oxide (e.g., but not limited to, titanium oxide and aluminum oxide). The thickness of the hard shield layer 30L may be in the range of 20 nm to 200 nm, such as 30 nm to 100 nm, although smaller or larger thicknesses may be used. The hard shield layer 30L may be deposited by chemical vapor deposition or physical vapor deposition.

One, more than one, and/or each of the layers in the layer stack (i.e., 22L, 24L, 26L, 28L, 29L, 30L) may form a conformal profile that provides a convex segment around each opening in the etch-stop dielectric material layer 18.

Referring to FIG. 5, above the hard shield layer 30L, a photoresist layer can be applied and lithographically patterned to form a patterned photoresist layer 37. The patterned photoresist layer 37 can include a two-dimensional periodic array of discrete photoresist material portions that are covered by individual ones of the bottom connection via hole structures 15. Thus, the two-dimensional periodic array of discrete photoresist material portions can have the same two-dimensional periodicity as the two-dimensional array of bottom connection via hole structures 15. Each of the discrete photoresist material portions can overlap in area with a respective underlying opening in the etch stop dielectric material layer 18. In one embodiment, each of the discrete photoresist material portions can have a perimeter that is laterally offset outwardly relative to the perimeter of the underlying opening in the etch stop dielectric material layer 18 in a plan view (i.e., a top-down view).

6A and 6B, the pattern of the two-dimensional array of discrete photoresist material portions of the patterned photoresist layer 37 can be transferred through the hard shield layer 30L by performing a first anisotropic etching process. The hard shield layer 30L can be patterned as a two-dimensional array of hard shield caps 30 by the first anisotropic etching process. The patterned photoresist layer 37 can then be removed, for example, by ashing. Alternatively, the patterned photoresist layer 37 can be consumed in parallel during the first anisotropic etching process. Alternatively, the first portion of the patterned photoresist layer 37 can be consumed in parallel during the first anisotropic etching process, and the remaining portion of the patterned photoresist layer 37 can be subsequently removed during a second anisotropic etching process.

A second anisotropic etching process can be performed to transfer the pattern in the two-dimensional array of hard shield caps 30 through at least one selective top metal barrier layer 29L, second electrode layer 28L, memory material layer 26L, first electrode layer 24L, and at least one selective bottom metal barrier layer 22L. Each patterned portion of the at least one selective top metal barrier layer 29L (if used) includes at least one selective top metal barrier plate 29. Each patterned portion of the second electrode layer 28L includes a second electrode 28. Each patterned portion in the memory material layer 26L includes a memory film 26. Each patterned portion of the first electrode layer 24L includes a first electrode 24. Each patterned portion of the at least one selective top metal barrier layer 29L (if used) includes at least one selective bottom metal barrier plate 22.

In one embodiment, the optional bottom metal barrier plate 22 may include a stack of a first bottom metal barrier plate 221 (patterned portion of the first bottom metal barrier layer 221L), a second bottom metal barrier plate 222 (patterned portion of the second bottom metal barrier layer 222L), and a third bottom metal barrier plate 223 (patterned portion of the third bottom metal barrier layer 223L). The memory film 26 includes at least one dielectric metal oxide layer and includes an oxygen-deficient filamentous dielectric metal oxide material. For example, the memory film 26 may include a layer stack including a first dielectric metal oxide layer 261 (patterned portion of the first dielectric metal oxide layer 261L formed in the process of FIG. 4) and a second dielectric metal oxide layer 262 (patterned portion of the second dielectric metal oxide layer 262L formed in the process of FIG. 4). In one embodiment, the optional top metal barrier plate 29 may include a stack of a first top metal barrier plate 291 (a patterned portion of a first top metal barrier layer 291L) and a second top metal barrier plate 292 (a patterned portion of a second top metal barrier layer 292L).

In general, the portions of the second electrode layer 28L, the memory material layer 26L, and the first electrode layer 24L that are located outside the area of the patterned etch shield layer 37 may be anisotropically etched during the second anisotropic etching process. The remaining portions of the second electrode layer 28L, the memory material layer 26L, and the first electrode layer 24L include the second electrode 28, the memory film 26, and the first electrode 24.

Each connected set of at least one optional bottom metal barrier plate 22, first electrode 24, memory film 26, top electrode 28, and at least one optional top metal barrier plate 29 constitutes a memory cell 20. A two-dimensional periodic array of memory cells 20 may be formed. The two-dimensional periodic array of memory cells 20 may have a first pitch p1 along a first horizontal direction hd1 and a second pitch p2 along a second horizontal direction hd2. In one embodiment, each first interface between the memory film 26 and the first electrode 24 may include a horizontal central segment, an annular contour segment (where the convex surface of the first electrode 24 contacts the concave surface of the memory film 26), and a horizontal annular segment adjacent to the outer periphery of the annular contour segment. Each second interface between the memory film 26 and the second electrode 28 may include a horizontal central segment, an annular contour segment (where the concave surface of the second electrode 28 contacts the convex surface of the memory film 26), and a horizontal annular segment adjacent to the outer periphery of the annular contour segment.

In one embodiment, all sidewalls of the elements in the memory cell 20 may be vertically overlapping, i.e., may lie in the same vertical plane. Thus, in each memory cell 20, one or more sidewalls of at least one optional bottom metal barrier plate 22, one or more sidewalls of the first electrode 24, one or more sidewalls of the memory film 26, one or more sidewalls of the top electrode 28, and one or more sidewalls of at least one optional top metal barrier plate 29 may be vertically overlapping. In an illustrative embodiment, the memory cell 20 has a circular horizontal cross-sectional shape, and the vertical plane may be a cylindrical vertical plane.

In one embodiment, the second anisotropic etching process may utilize an etching chemistry that is selective to the material of the etch-stop dielectric material layer 18. However, parallel etching of the top portion of the etch-stop dielectric material layer 18 may occur at the end portions of the second anisotropic etching process. In one embodiment, the etch-stop dielectric material layer 18 includes a horizontally extending portion that underlies each of the first electrodes 24 and a two-dimensional array of vertical protrusions. Each of the vertical protrusions includes a sidewall that vertically overlaps the sidewall of the first electrode 24 and has a bottom perimeter P adjacent the perimeter of the horizontally extending portion. The etch-stop dielectric material layer 18 includes an opening that extends through the area of each of the first electrodes 24 in plan view.

Typically, each memory film 26 includes at least one non-stoichiometric oxygen-deficient dielectric metal oxide material disposed in the memory material layer 26L. However, the exposed surface of the memory film 26 may have structural and/or compositional defects introduced during the second anisotropic etching process. Some of these defects may provide conditions favorable for the early formation of oxygen-deficient filaments and may be unfavorable for the removal of the oxygen-deficient filaments, for example, under an electric field having a value less than the critical field amount (so that the application of an electric field that should be sufficient to erase the defect-free oxygen-deficient filaments of the dielectric metal oxide may not completely remove the oxygen-deficient filaments). Also, such defects may act as leakage paths for the memory cells 20 under normal operating conditions.

7, according to an aspect of the present disclosure, a passivation plasma treatment process may be performed to passivate the surface region of the memory film 26. The defects induced during the second anisotropic etching process are passivated by replacing oxygen atoms with a passivating element provided during the passivation plasma treatment process. In one embodiment, the passivation plasma treatment process uses a fluorine gas plasma or a nitrogen gas plasma. The temperature of the gas plasma treatment may be, for example, in the range of 40° C. to 75° C., although lower or higher plasma treatment temperatures may be used. The power of the gas plasma depends on the size of the semiconductor wafer being processed in the process chamber and may generally be in the range of 200 watts to 1500 watts, although lower or higher gas plasma powers may be used. During the passivation plasma treatment process, fluorine gas or nitrogen gas may be flowed into the process chamber. The gate flow rate during the passivation plasma treatment process may be in the range of 10 standard cubic centimeters per minute (sccm) to 200 sccm, although lower or higher gate flow rates may be used.

In general, the material of the memory film 26 and the species of the gas in the gas plasma can be selected such that the atomic bond strength between the metal element(s) in the memory film 26 and the fluorine or nitrogen atoms provided from the gas plasma is greater than the atomic bond strength between the metal element and the oxygen atom. Therefore, after the oxygen atoms in the surface segments of the memory film 26 are replaced with fluorine or nitrogen atoms in the passivation plasma treatment process, even if the memory film 26 is exposed to an atmosphere containing oxygen after the passivation plasma treatment process, the fluorine or nitrogen atoms in the surface segments of the memory film 26 are not replaced with oxygen atoms.

Each memory film 26 includes a central region (261C, 262C) whose material composition is essentially unaffected by the passivation plasma treatment, and a peripheral region (261P, 262P) in which the passivation plasma treatment process replaces a significant fraction of oxygen atoms with fluorine atoms or nitrogen atoms, and the average atomic ratio of the passivation element (which may be fluorine or nitrogen) to oxygen in the peripheral region (261P, 262P) increases from a first number less than 0.01 (and/or less than 0.001, and/or less than 0.0001, and/or less than 1.0×10 ⁻⁵ , and/or less than 1.0×10 ⁻⁶ , and/or less than 1.0×10 ⁻⁷ ) to a second number greater than 0.05 (and/or greater than 0.10, and/or greater than 0.10, and/or greater than 0.5, and/or greater than 1.0, and/or greater than 2, and/or greater than 5, and/or greater than 10). In one embodiment, the average atomic ratio of passivating elements (i.e., fluorine atoms or nitrogen atoms) to oxygen in each peripheral region (261P, 262P) of each memory film 26 may be greater than 0.05, and/or greater than 0.10, and/or greater than 0.5, and/or greater than 1.0, and/or greater than 2, and/or greater than 5, and/or greater than 10. In one embodiment, the central region (261C, 262C) of each memory film 26 may have an average atomic ratio of passivating elements to oxygen that is less than 0.01 (and/or less than 0.001, and/or less than 0.0001, and/or less than 1.0×10 ⁻⁵ , and/or less than 1.0×10 ⁻⁶ , and/or less than 1.0×10 ⁻⁷ ). In one embodiment, the central region (261C, 262C) of the memory film 26 may include each volume of the memory film 26 having an atomic ratio of the passivation element to oxygen that is less than 0.05, and the peripheral region (261P, 262P) of the memory film 26 may include each volume of the memory film 26 having an atomic ratio of the passivation element to oxygen that is greater than 0.05 or is infinity (i.e., a condition in which no oxygen atoms are present).

In an alternative embodiment, a non-plasma process may be used to introduce a passivation element into the peripheral regions (261P, 262P) to form either the peripheral region of the structure of FIG. 7 or the structures described below. For example, a low energy angled ion implantation process may be used to implant fluorine or nitrogen atoms into the peripheral regions (261P, 262P) of the memory film 26.

In an embodiment in which the memory film 26 includes a stack of a first dielectric metal oxide layer 261 and a second dielectric metal oxide layer 262, the first dielectric metal oxide layer 261 may include a first central region 261C having an atomic ratio of the passivation element to oxygen that is less than 0.05 and a first peripheral region 261P having an atomic ratio of the passivation element to oxygen that is greater than 0.05, and the second dielectric metal oxide layer 262 may include a second central region 262C having an atomic ratio of the passivation element to oxygen that is less than 0.05 and a second peripheral region 262P having an atomic ratio of the passivation element to oxygen that is greater than 0.05.

The lateral thickness of the peripheral regions (261P, 262P) in each memory film 26 may be in the range of 1 nm to 5 nm, such as 2 nm to 4 nm, although smaller or larger lateral thicknesses may be used. In one embodiment, each peripheral region (261P, 262P) of the memory film 26 may have a concentration gradient of the passivation element, where the atomic concentration of the passivation element (which may be fluorine or nitrogen atoms) decreases with distance from the surface (i.e., sidewall) of the memory film 26.

According to aspects of the present disclosure, the presence of peripheral regions (261P, 262P) that are free of oxygen atoms or have some of them substituted with fluorine or nitrogen atoms may inhibit the formation of conductive threads in the peripheral regions (261P, 262P) of each memory cell 20. In some embodiments, the outer segments of each peripheral region (261P, 262P) may be free of oxygen atoms. As used herein, a material volume is "free of an element" if the atomic percentage of that element is less than 1.0×10 ⁻⁶ % (i.e., the atomic fraction is less than 1.0×10 ⁻⁸ ) or is below the detection limit of analytical equipment available in the art for determining the material composition within the material volume. The lateral thickness of such oxygen-free surface segments may be in the range of 1 nm to 4 nm, although smaller or larger thicknesses may be used. In the peripheral regions (261P, 262P), the lack or reduction of oxygen atoms increases the endurance of the memory cell 20, and the absence of oxygen-deficient threads reduces cell leakage current.

8, which is exemplary x-ray photoemission spectroscopy (XPS) data from an untreated hafnium oxide surface and from a hafnium oxide surface treated with a fluorine plasma. A first curve 810 shows the XPS data from an untreated hafnium oxide surface. A second curve 820 shows the XPS data from a hafnium oxide surface treated with a fluorine plasma. In this example, the normalized metal-fluorine bond (e.g., Hf-F) intensity may be in the range of about 1 to about 10. The XPS data shows a significant fraction, and/or a major fraction, of the surrounding regions (261P, 262P) may be passivated by the fluorine plasma, replacing metal-oxygen bonds with metal-fluorine bonds. The XPS data illustrates an example of fluorine plasma treatment on a hafnium oxide surface, but it is believed that a similar phenomenon also occurs with nitrogen plasma and/or other oxygen-deficient filamentous dielectric metal oxide materials as discussed above.

9A and 9B, an upper via hole level dielectric material layer 646 can be formed above the two-dimensional array of memory cells 20 and the hard shield cap 30. The upper via hole level dielectric material layer 646 can include any dielectric material that can be used for the lower via hole level dielectric material layer 645. In one embodiment, the upper via hole level dielectric material layer 646 can include a planarizable dielectric material such as silicon oxide or a planarizable dielectric material such as a spin-on dielectric material. In this embodiment, the upper surface of the upper via hole level dielectric material layer 646 can be formed as a planar or semi-planar surface. The thickness of the upper via hole level dielectric material layer 646 can be selected such that the upper surface of the upper via hole level dielectric material layer 646 is formed in a horizontal plane that includes the upper surface of the hard shield cap 30.

Via hole cavities may be formed above the two-dimensional array of memory cells 20 and above the metal interconnect structures (e.g., the third metal wiring structure 638) in the peripheral region 200. The upper surface of the top metal barrier plate 29 (or top electrode 28) may be substantially exposed to the bottom of the via hole cavities formed in the memory array region 100, and the upper surface of the underlying metal interconnect structures (e.g., the third metal wiring structure 638) may be substantially exposed to the bottom of the via hole cavities formed in the peripheral region 200. At least one metal material (e.g., a combination of a metal barrier lining and a metal fill material) may be deposited within each of the via hole cavities, and excess portions of the at least one metal material may be removed from the upper surface of the upper via hole level dielectric material layer 646 by a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process or a recess etching process. Each remaining portion of the at least one metal material filling a via hole cavity covered by a memory cell 20 constitutes a top connection via hole structure 35. Each remaining portion of the at least one metal material filling a via hole cavity in the peripheral region 200 constitutes a third metal via hole structure 642. Each top connection via hole structure 35 contacts the top metal barrier plate 29 and/or the top electrode 28.

10A and 10B, an interconnect level dielectric material layer 647 can be deposited above the upper via level dielectric material layer 646. The combination of the lower via level dielectric material layer 645, the etch stop dielectric material layer 18, the upper via level dielectric material layer 646, and the interconnect level dielectric material layer 647 constitutes an interconnect level dielectric material layer such as the fourth interconnect level dielectric material layer 640.

The wiring cavities may be formed in the wiring level dielectric material layer 647 and filled with at least one metal material (e.g., a combination of a metal barrier lining and a metal fill material) to form metal wiring structures, referred to herein as fourth metal wiring structures 648. In one embodiment, a subset of the fourth metal wiring structures 648 may include bit lines 648B extending laterally along the first horizontal direction hd1. Each of the bit lines 648B may contact a respective column of top connection via hole structures 35 disposed along the first horizontal direction hd1. In one embodiment, the bit lines 648B may have a periodicity of a second pitch p2 along the second horizontal direction hd2.

The first exemplary structure includes a semiconductor structure that includes a two-dimensional array of memory cells 20, each of which includes a respective first electrode 24, a respective memory film 26, and a respective second electrode 28 overlying a substrate 8. Each memory film 26 in the two-dimensional array stack includes a distinct central region (261C, 262C) having a first average atomic ratio of passivating element to oxygen less than 0.01 (and/or less than 0.001, and/or less than 0.0001, and/or less than 1.0×10 ⁻⁵ , and/or less than 1.0×10 ⁻⁶ , and/or less than 1.0×10 ⁻⁷ ), and a distinct peripheral region (261P, 262P) having a second average atomic ratio of passivating element to oxygen greater than 0.05 (and/or greater than 0.10, and/or greater than 0.10, and/or greater than 0.5, and/or greater than 1.0, and/or greater than 2, and/or greater than 5, and/or greater than 10).

The semiconductor structure further includes a two-dimensional array of access transistors 70A located in the substrate 8, each of the access transistors 70A being electrically connected to each of the memory cells 20 in the two-dimensional array of memory cells 20, and a metal interconnect structure (612, 618, 622, 628, 632, 638, 15) located in the dielectric material layer (601, 610, 620, 630, 645, 18) and providing electrical connection between the two-dimensional array of access transistors 70A and the two-dimensional array of memory cells 20.

In one embodiment, the metal interconnect structure (612, 618, 622, 628, 632, 638, 15) includes a two-dimensional array of via hole structures (e.g., bottom-connected via hole structures 15), and the dielectric material layer (601, 610, 620, 630, 645, 18) includes an etch-stop dielectric material layer 18 contacting the top surfaces of the via hole structures in the two-dimensional array of via hole structures 15 and including a two-dimensional array of horizontal extensions and vertical protrusions.

In one embodiment, each of the vertical protrusions includes a respective sidewall that vertically overlaps a respective one of the first electrodes 24 and has a respective bottom perimeter P adjacent a respective perimeter of the horizontally extending portion, the etch-stop dielectric material layer 18 includes a two-dimensional array of openings therethrough, and each opening through the etch-stop dielectric material layer 18 is located entirely within the area of a respective one of the first electrodes 24 in plan view.

11, an alternative configuration of the first exemplary structure can be obtained from the first exemplary structure by using a single dielectric metal oxide layer as the memory material layer 26L in the process step of FIG. 4. In this example, each memory film 26 can be composed of a single dielectric metal oxide layer. Each memory film 26 includes a central region 260C and a peripheral region 260P. The central region 260C and the peripheral region 260P can have the composition of the first central region 261C and the first peripheral region 261P described above, respectively, or can have the composition of the second central region 262C and the second peripheral region 262P described above, respectively. In this example, the central region of each memory film 26 can have the same material composition along the vertical direction (i.e., along the vertical direction) between the first interface of the first electrode 24 and the second interface of the second electrode 28.

Referring to FIG. 12, a second exemplary structure according to an embodiment of the present disclosure can be obtained from the first exemplary structure of FIG. 3 by forming a two-dimensional array of openings through the etch-stop dielectric material layer 18, removing the photoresist layer 19, forming a two-dimensional array of bottom metal barrier plates 22, and forming a layer stack including, from bottom to top, a first electrode layer 24L, a memory material layer 26L, a second electrode layer 28L, at least one optional top metal barrier layer 29L, and a hard shield layer 30L.

In one embodiment, a two-dimensional array of bottom metal barrier plates 22 may be formed by depositing at least one metal barrier material into the openings through the etch-stop dielectric material layer 18 and removing at least one metal barrier material portion from horizontal surfaces including the top surface of the etch-stop dielectric material layer 18 by a planarization process such as a chemical mechanical polishing process. The at least one metal barrier material of the bottom metal barrier plate 22 may include any of the metal barrier materials usable for the first bottom metal barrier layer 221L, the second bottom metal barrier layer 222L, and the third bottom metal barrier layer 223L described with reference to FIG. 5. Each of the first electrode layer 24L, the memory material layer 26L, the second electrode layer 28L, the at least one optional top metal barrier layer 29L, and the hard shield layer 30L may have the same material composition and thickness range as the first exemplary structure.

13, a photoresist layer can be applied over the hard shield layer 30L and lithographically patterned to form a patterned photoresist layer 37. The patterned photoresist layer 37 can include a two-dimensional periodic array of discrete photoresist material portions that are coated with individual ones of the bottom connection via hole structures 15. Thus, the two-dimensional periodic array of discrete photoresist material portions can have the same two-dimensional periodicity as the two-dimensional array of bottom connection via hole structures 15. Each of the discrete photoresist material portions can overlap in area with a respective underlying opening in the etch stop dielectric material layer 18. In one embodiment, each of the discrete photoresist material portions can have a perimeter that is laterally offset outwardly relative to the perimeter of the underlying opening in the etch stop dielectric material layer 18 in a plan view (i.e., a top-down view).

14, the pattern of the two-dimensional array of discrete photoresist material portions of the patterned photoresist layer 37 can be transferred through the hard shield layer 30L, the at least one optional top metal barrier layer 29L, and the second electrode layer 28L by performing a first anisotropic etching process. The hard shield layer 30L can be patterned as a two-dimensional array of hard shield caps 30. The at least one optional top metal barrier layer 29L (if used) can be patterned as a two-dimensional array of top metal barrier plates 29. In one embodiment, each top metal barrier plate 29 may include a stack of a first top metal barrier plate 291 (patterned portion of the first top metal barrier layer 291L) and a second top metal barrier plate 292 (patterned portion of the second top metal barrier layer 292L). The second electrode layer 28L can be patterned as a two-dimensional array of second electrodes 28. The memory material layer 26L may be used as an etch stop layer for the first anisotropic etching process. The patterned photoresist layer 37 may then be removed, for example, by ashing.

With reference to FIG. 15, an insulating material such as silicon nitride, silicon carbonitride, or silicon oxide can be conformally deposited over the two-dimensional array of second electrodes 28 by a conformal deposition process (e.g., a chemical vapor deposition process) to form an insulating material layer. An anisotropic etching process can be performed to remove horizontally extending portions of the insulating material layer. The individual remaining cylindrical portions of the insulating material layer that laterally surround the individual stacks of second electrodes 28, top metal barrier plate 29, and hard shield caps 30 constitute insulating spacers 32. The lateral thickness of each insulating spacer 32 measured between the inner and outer walls may be in the range of 4 nm to 80 nm, such as 8 nm to 40 nm, although smaller or larger lateral thicknesses may be used. Each insulating spacer 32 laterally surrounds an individual second electrode 28.

Referring to FIG. 16, the pattern of the combination of the two-dimensional array of hard shield caps 30 and the two-dimensional array of insulating spacers 32 can be transferred through the memory material layer 26L and the first electrode layer 24L by performing a second anisotropic etching process. Each patterned portion of the memory material layer 26L includes a memory film 26. Each patterned portion of the first electrode layer 24L includes a first electrode 24.

Each memory film 26 includes at least one dielectric metal oxide layer that includes an oxygen-deficient thread-like dielectric metal oxide material. For example, the memory film 26 can include a layer stack that includes a first dielectric metal oxide layer 261 and a second dielectric metal oxide layer 262.

In general, the portions of the second electrode layer 28L, the memory material layer 26L, and the first electrode layer 24L that are not shielded by the two-dimensional array of the second electrodes and the two-dimensional array of insulating spacers 32 may be anisotropically etched during the second anisotropic etching process. The remaining portions of the memory material layer 26L and the first electrode layer 24L include the memory film 26 and the first electrode 24.

Each successive set of bottom metal barrier plate 22, first electrode 24, memory film 26, top electrode 28, and top metal barrier plate 29 constitutes a memory cell 20. A two-dimensional periodic array of memory cells 20 can be formed. The two-dimensional periodic array of memory cells 20 can have a first pitch p1 along a first horizontal direction hd1 and a second pitch p2 along a second horizontal direction hd2. In one embodiment, each first interface between memory film 26 and first electrode 24 can include a horizontal segment. Each second interface between memory film 26 and second electrode 28 can include a horizontal segment.

In one embodiment, one or more sidewalls of the first electrode 24, one or more sidewalls of the memory film 26, and the outer wall covered by the insulating spacer 32 may vertically overlap one another. In an illustrative embodiment in which the memory cell 20 has a circular horizontal cross-sectional shape, the vertical plane may be a cylindrical vertical plane.

In one embodiment, the second anisotropic etching process may utilize an etching chemistry that is selective to the material of the etch-stop dielectric material layer 18. However, parallel etching of the top portion of the etch-stop dielectric material layer 18 may occur at the end portions of the second anisotropic etching process. In one embodiment, the etch-stop dielectric material layer 18 underlies each of the first electrodes 24 and includes a two-dimensional array of horizontally extending portions and vertical protrusions. Each of the vertical protrusions includes a sidewall that vertically overlaps the sidewall of the first electrode 24 and has a bottom perimeter P adjacent the perimeter of the horizontally extending portion. The etch-stop dielectric material layer 18 has an opening extending therethrough in a plan view within the area of each of the first electrodes 24.

As mentioned above, the exposed surface of the memory film 26 may have structural and/or compositional defects introduced during the second anisotropic etching process. Some of these defects provide conditions favorable for the early formation of oxygen-deficient filaments, e.g., under electric fields having values less than the critical field magnitude, and are unfavorable for the removal of the oxygen-deficient filaments (so that the application of an electric field that would be sufficient to erase the defect-free dielectric metal oxide oxygen-deficient filaments does not completely remove the oxygen-deficient filaments). Also, such defects act as leakage paths for the memory cell 20 under normal operating conditions.

A passivation plasma treatment process may be performed to passivate the surface region of the memory film 26. The defects induced during the second anisotropic etching process are passivated by replacing oxygen atoms with passivating elements provided during the passivation plasma treatment process. The passivation plasma treatment process uses a fluorine gas plasma or a nitrogen gas plasma. The process conditions of the gas plasma treatment process may be the same as the process conditions of the gas plasma treatment process described with reference to FIG. 7.

In general, the material of the memory film 26 and the species of the gas in the gas plasma can be selected such that the atomic bond strength between the metal element(s) in the memory film 26 and the fluorine or oxygen atoms provided from the gas plasma is greater than the atomic bond strength between the metal element and the oxygen atom. Therefore, after the oxygen atoms in the surface portion of the memory film 26 are replaced with fluorine atoms or nitrogen atoms during the passivation plasma treatment process, even if the memory film 26 is exposed to an atmosphere containing oxygen after the passivation plasma treatment process, the fluorine atoms or nitrogen atoms in the surface portion of the memory film 26 are not replaced with oxygen atoms.

Each memory film 26 includes a central region (261C, 262C) whose material composition is essentially unaffected by the passivation plasma treatment, and a peripheral region (261P, 262P) in which the passivation plasma treatment process replaces a significant fraction of oxygen atoms with fluorine atoms or nitrogen atoms, and the average atomic ratio of the passivation element (which may be fluorine or nitrogen) to oxygen in the peripheral region (261P, 262P) increases from a first number less than 0.01 (and/or less than 0.001, and/or less than 0.0001, and/or less than 1.0×10 ⁻⁵ , and/or less than 1.0×10 ⁻⁶ , and/or less than 1.0×10 ⁻⁷ ) to a second number greater than 0.05 (and/or greater than 0.10, and/or greater than 0.10, and/or greater than 0.5, and/or greater than 1.0, and/or greater than 2, and/or greater than 5, and/or greater than 10). In one embodiment, the average atomic ratio of passivating elements (i.e., fluorine atoms or nitrogen atoms) to oxygen in each peripheral region (261P, 262P) of each memory film 26 may be greater than 0.05, and/or greater than 0.10, and/or greater than 0.5, and/or greater than 1.0, and/or greater than 2, and/or greater than 5, and/or greater than 10. In one embodiment, the central region (261C, 262C) of each memory film 26 may have an average atomic ratio of passivating elements to oxygen that is less than 0.01 (and/or less than 0.001, and/or less than 0.0001, and/or less than 1.0×10 ⁻⁵ , and/or less than 1.0×10 ⁻⁶ , and/or less than 1.0×10 ⁻⁷ ). In one embodiment, the central region (261C, 262C) of the memory film 26 may include each volume of the memory film 26 having an atomic ratio of the passivation element to oxygen that is less than 0.05, and the peripheral region (261P, 262P) of the memory film 26 may include each volume of the memory film 26 having an atomic ratio of the passivation element to oxygen that is greater than 0.05 or is infinity (i.e., a condition in which no oxygen atoms are present).

In an embodiment in which the memory film 26 includes a stack of a first dielectric metal oxide layer 261 and a second dielectric metal oxide layer 262, the first dielectric metal oxide layer 261 may include a first central region 261C having an atomic ratio of the passivation element to oxygen that is less than 0.05 and a first peripheral region 261P having an atomic ratio of the passivation element to oxygen that is greater than 0.05, and the second dielectric metal oxide layer 262 may include a second central region 262C having an atomic ratio of the passivation element to oxygen that is less than 0.05 and a second peripheral region 262P having an atomic ratio of the passivation element to oxygen that is greater than 0.05.

The lateral thickness of the peripheral regions (261P, 262P) in each memory film 26 may be in the range of 1 nm to 5 nm, such as 2 nm to 4 nm, although smaller or larger lateral thicknesses may be used. In one embodiment, each peripheral region (261P, 262P) of the memory film 26 may have a concentration gradient of the passivation element, where the atomic concentration of the passivation element (which may be fluorine or nitrogen atoms) decreases with distance from the surface (i.e., sidewall) of the memory film 26.

According to aspects of the present disclosure, the presence of peripheral regions (261P, 262P) that are free of oxygen atoms or have some of them substituted with fluorine or nitrogen atoms may inhibit the formation of conductive threads in the peripheral regions (261P, 262P) of each memory cell 20. In some embodiments, the outer segments of each peripheral region (261P, 262P) may be free of oxygen atoms. The lateral thickness of such oxygen-free surface segments may be in the range of 1 nm to 4 nm, although smaller or larger thicknesses may be used. The lack or reduction of oxygen atoms in the peripheral regions (261P, 262P) improves the durability of the memory cell 20 and reduces cell leakage current due to the absence of oxygen-deficient threads.

17A and 17B, the process steps described with reference to FIGS. 9A and 9B can be performed to form an upper via level dielectric material layer 646, a top connection via hole structure 35, and a third metal via hole structure 642. Each top connection via hole structure 35 contacts a top metal barrier plate 29 and/or a top electrode 28.

18A and 18B, the process steps described with reference to FIGS. 10A and 10B may be performed to form an interconnect level dielectric material layer 647 and a fourth metal wiring structure 648. The combination of the lower via hole level dielectric material layer 645, the etch stop dielectric material layer 18, the upper via hole level dielectric material layer 646, and the wiring level dielectric material layer 647 constitutes an interconnect level dielectric material layer such as the fourth interconnect level dielectric material layer 640. In one embodiment, a subset of the fourth metal wiring structure 648 may include bit lines 648B extending laterally along the first horizontal direction hd1. Each of the bit lines 648B may contact a respective column of the top connection via hole structures 35 arranged along the first horizontal direction hd1. In one embodiment, the bit lines 648B may have a periodicity of the second pitch p2 along the second horizontal direction hd2.

A second exemplary structure includes a semiconductor structure. The semiconductor structure includes a two-dimensional array of memory cells 20, each of which includes an individual first electrode 24, an individual memory film 26, and an individual second electrode 28, overlaid by a substrate 8. Each memory film 26 in the two-dimensional array stack includes an individual central region (261C, 262C) having a first average atomic ratio of passivation element to oxygen less than 0.01, and an individual peripheral region (261P, 262P) having a second average atomic ratio of passivation element to oxygen greater than 0.05.

The semiconductor structure further includes a two-dimensional array of access transistors 70A located in the substrate 8, each of the access transistors 70A therein being electrically connected to each of the memory cells 20 in the two-dimensional array of memory cells 20, and a metal interconnect structure (612, 618, 622, 628, 632, 638, 15) located within the dielectric material layer (601, 610, 620, 630, 645, 18) and providing electrical connection between the two-dimensional array of access transistors 70A and the two-dimensional array of memory cells 20.

In one embodiment, the metal interconnect structure (612, 618, 622, 628, 632, 638, 15) includes a two-dimensional array of via hole structures (e.g., bottom-connected via hole structures 15), and the dielectric material layer (601, 610, 620, 630, 645, 18) includes an etch-stop dielectric material layer 18 contacting the top surfaces of the via hole structures in the two-dimensional array of via hole structures 15 and including a two-dimensional array of horizontal extensions and vertical protrusions.

In one embodiment, each of the vertical protrusions includes a respective sidewall that vertically overlaps a respective one of the first electrodes 24 and has a respective bottom perimeter P adjacent a respective perimeter of the horizontally extending portion, the etch-stop dielectric material layer 18 includes a two-dimensional array of openings therethrough, and each opening through the etch-stop dielectric material layer 18 is located entirely within the area of a respective one of the first electrodes 24 in plan view.

19, an alternative configuration of the second exemplary structure can be obtained from the second exemplary structure by using a single dielectric metal oxide layer as the memory material layer 26L in the process step of FIG. 12. In this example, each memory film 26 can be composed of a single dielectric metal oxide layer. Each memory film 26 includes a central region 260C and a peripheral region 260P. The central region 260C and the peripheral region 260P can have the composition of the first central region 261C and the first peripheral region 261P described above, respectively, or can have the composition of the second central region 262C and the second peripheral region 262P described above, respectively. In this example, the central region of each memory film 26 can have the same material composition along the vertical direction (i.e., along the vertical direction) between the first interface of the first electrode 24 and the second interface of the second electrode 28.

20, a second alternative configuration of the second exemplary structure can be obtained from the first exemplary structure shown in FIG. 4 by carrying out the process steps described with reference to FIGS. 13, 14, 15, 16, 17A and 17B, and 18A and 18B. In the second alternative configuration of the second exemplary structure, the optional bottom metal barrier plate 22 may include a stack of a first bottom metal barrier plate 221 (patterned portion of the first bottom metal barrier layer 221L), a second bottom metal barrier plate 222 (patterned portion of the second bottom metal barrier layer 222L), and a third bottom metal barrier plate 223 (patterned portion of the third bottom metal barrier layer 223L). In one embodiment, each first interface between the memory film 26 and the first electrode 24 may include a horizontal central segment, an annular contour segment where the convex surface of the first electrode 24 contacts the concave surface of the memory film 26, and a horizontal annular segment adjacent to the outer periphery of the annular contour segment. Each second interface between the memory film 26 and the second electrode 28 may include a horizontal central segment, an annular contour segment where the concave surface of the second electrode 28 contacts the convex surface of the memory film 26, and a horizontal annular segment adjacent to the outer periphery of the annular contour segment. In one embodiment, one or more sidewalls of the first electrode 24, one or more sidewalls of the memory film 26, and the outer wall coated with the insulating spacer 32 may vertically overlap one another. In an illustrative embodiment in which the memory cell 20 has a circular horizontal cross-sectional shape, the vertical plane may be a cylindrical vertical plane.

21, a third alternative configuration of the second exemplary structure can be obtained from the second alternative configuration of the second exemplary structure by using a single dielectric metal oxide layer as the memory material layer 26L. In this example, each memory film 26 can be composed of a single dielectric metal oxide layer. Each memory film 26 includes a central region 260C and a peripheral region 260P. The central region 260C and the peripheral region 260P can have the composition of the first central region 261C and the first peripheral region 261P described above, respectively, or can have the composition of the second central region 262C and the second peripheral region 262P described above, respectively. In this example, the central region of each memory film 26 can have the same material composition along the vertical direction (i.e., along the vertical direction) between the first interface of the first electrode 24 and the second interface of the second electrode 28.

Referring to FIG. 22, a flow diagram illustrates the general process steps of a method for forming the disclosed semiconductor device.

Referring to Figures 1-6B, 11, 12-16, 19, 20, and 21, in step 2210, a stack including a first electrode 24, a memory film 26, and a second electrode 28 can be formed above a substrate 8. In one embodiment, the memory film 26 includes at least one non-stoichiometric oxygen-deficient dielectric metal oxide material.

7-10B, 16-18B, 19, 20, and 21, in step 2220, the stack can be subjected to a passivation plasma treatment. The average atomic ratio of the passivation element to oxygen in the peripheral region {(261P, 262P), 260P} of the memory film 26 increases from a first number less than 0.01 to a second number greater than 0.05.

With reference to all the drawings, according to various embodiments of the present disclosure, a semiconductor structure is provided that includes a first electrode 24 comprising a first metallic material, a memory film 26 comprising at least one dielectric metal oxide material and contacting the first electrode 24, the memory film 26 including a central region {(261C, 262C), 260C} having a first average atomic ratio of the passivating element to oxygen less than 0.01 and a peripheral region {(261P, 262P), 260P} having a second average atomic ratio of the passivating element to oxygen greater than 0.05, and a second electrode 28 comprising a second metallic material and contacting the memory film 26. In one embodiment, the passivating element is selected from fluorine and nitrogen.

In one embodiment, the at least one dielectric metal oxide material includes at least one thread-like dielectric metal oxide material. In one embodiment, each of the at least one thread-like dielectric metal oxide material is a non-stoichiometric oxygen-deficient dielectric metal oxide material. In one embodiment, the central region {(261C, 262C), 260C} of the memory film 26 is free of passivating elements or has a ratio of passivating elements to oxygen that is less than 0.01.

In one embodiment, the central region {(261C, 262C), 260C} of the memory film 26 has the same material composition along a direction perpendicular to the first interface of the first electrode 24 and the second interface of the second electrode 28.

In one embodiment, the memory film 26 includes a layer stack including a first dielectric metal oxide material including a dielectric metal oxide of at least one first metal and a second dielectric metal oxide material including a dielectric metal oxide of at least one second metal, where the at least one second metal differs from the at least one first metal by the presence of a metal element that is not present in the at least one first metal or the absence of a metal element that is present in the at least one first metal.

In one embodiment, the first interface between the first electrode 24 and the memory film 26 includes a horizontal segment, and the sidewalls of the memory film 26 vertically overlap the sidewalls of the first electrode 24. In one embodiment, the sidewalls of the memory film 26 vertically overlap the sidewalls of the second electrode 28. In one embodiment, the semiconductor structure includes an insulating spacer 32 that laterally surrounds the second electrode 28, and the outer sidewalls of the insulating spacer 32 vertically overlap the sidewalls of the memory film 26.

In one embodiment, the peripheral regions of the memory film 26 {(261P, 262P), 260P} have a concentration gradient of the passivation element, such that the atomic concentration of the passivation element decreases with distance from the surface of the memory film 26.

In one embodiment, the semiconductor structure includes an etch-stop dielectric material layer 18 that underlies the first electrode 24 and includes a horizontally extending portion and a vertical protrusion that includes sidewalls that vertically overlap the sidewalls of the first electrode 24 and has a bottom periphery adjacent to the periphery of the horizontally extending portion, the etch-stop dielectric material layer 18 having an opening that penetrates within the region of the first electrode 24 in a plan view.

According to another aspect of the present disclosure, a semiconductor structure is provided that includes a two-dimensional array of memory cells 20, each of which includes a first electrode 24, a memory film 26, and a second electrode 28, each of which includes a substrate 8 overlying the first electrode 24, a memory film 26, and a second electrode 28, each of which includes a central region {(261C, 262C), 260C} having an average atomic ratio of the passivation element to oxygen less than 0.01, and a peripheral region {(261P, 262P), 260P} having an average atomic ratio of the passivation element to oxygen greater than 0.05. In one embodiment, the passivation element is selected from fluorine and nitrogen.

In one embodiment, the semiconductor structure includes a two-dimensional array of access transistors 70A located in a substrate 8, with each of the access transistors 70A electrically connected to a respective one of the memory cells 20 in the two-dimensional array of memory cells 20, and a metal interconnect structure (612, 618, 622, 628, 632, 638, 15) located in a dielectric material layer (601, 610, 620, 630, 645, 18) providing electrical connection between the two-dimensional array of access transistors 70A and the two-dimensional array of memory cells 20.

In one embodiment, the metal interconnect structure (612, 618, 622, 628, 632, 638, 15) includes a two-dimensional array of via hole structures 15, and the dielectric material layer (601, 610, 620, 630, 645, 18) includes an etch-stop dielectric material layer 18 contacting the top surfaces of the via hole structures in the two-dimensional array of via hole structures 15 and including a two-dimensional array of horizontal extensions and vertical protrusions.

In one embodiment, each of the vertical protrusions includes a respective sidewall that vertically overlaps a respective one of the first electrodes 24 and has a respective bottom perimeter adjacent a respective perimeter of the horizontally extending portion, the etch-stop dielectric material layer 18 includes a two-dimensional array of openings therethrough, and each opening through the etch-stop dielectric material layer 18 is located entirely within the area of a respective one of the first electrodes 24 in plan view.

According to various embodiments of the present disclosure, a method for forming a semiconductor structure includes forming a stack above a substrate, the stack including a first electrode, at least one memory film including a non-stoichiometric oxygen-deficient dielectric metal oxide material, and a second electrode, and performing a passivation plasma treatment on the stack such that an average atomic ratio of a passivation element to oxygen in a peripheral region of the memory film increases from a first number less than 0.01 to a second number greater than 0.05, the passivation element being selected from fluorine and nitrogen. In one embodiment, the method for forming a semiconductor structure further includes forming a first electrode layer, a memory material layer, and a second electrode layer on a substrate, and patterning the second electrode layer, the memory material layer, and the first electrode layer, the first electrode including a patterned portion of the first electrode layer, the memory film including a patterned portion of the memory material layer, and the second electrode including a patterned portion of the second electrode layer. In one embodiment, the method of forming a semiconductor structure further includes forming a patterned photoresist layer over the second electrode layer, and anisotropically etching a plurality of portions of the second electrode layer, the memory material layer, and the first electrode layer that are located outside the plurality of regions of the patterned photoresist layer, where the plurality of remaining portions of the second electrode layer, the memory material layer, and the first electrode layer include the second electrode, the memory film, and the first electrode. In one embodiment, the method of forming a semiconductor structure further includes forming a patterned photoresist layer over the second electrode layer, anisotropically etching the second electrode layer using the patterned photoresist layer as an etch shield, where the patterned portion of the second electrode layer includes the second electrode, removing the patterned photoresist layer, forming a dielectric spacer around the second electrode, and anisotropically etching a plurality of portions of the memory material layer and the first electrode layer that are not covered by the dielectric spacer or the second electrode, where the plurality of patterned portions of the memory material layer and the first electrode layer include the memory film and the first electrode. In one embodiment, the method for forming a semiconductor structure further includes forming an access transistor and a plurality of metal interconnect structures electrically connected to the access transistor above the substrate; forming an etch-stop dielectric material layer above the metal interconnect structures; forming an opening through the etch-stop dielectric material layer, where a top surface of one of the metal interconnect structures is exposed below the opening, and forming a first electrode layer, a memory material layer, and a second electrode layer above the opening; and patterning the second electrode layer, the memory material layer, and the first electrode layer, where the anisotropic etching process includes performing an etching chemistry selective to the material of the etch-stop dielectric material layer.

Various embodiments of the present disclosure may be used to increase the endurance of memory cells 20 including oxygen-deficient thread-like dielectric metal oxide materials to greater than 100,000 cycles, and/or greater than 1,000,000 cycles, and/or greater than 10,000,000 cycles. Various embodiments of the present disclosure may also reduce leakage current through memory cells 20 by removing oxygen defects from peripheral regions of memory film 26.

The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure can be readily used as a basis for designing or modifying other processes and structures for achieving the same purposes and/or advantages for implementing the embodiments introduced herein. Those skilled in the art should recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

8 Substrate 9 Semiconductor material layer 15 Bottom connection via hole structure 18 Etch stop dielectric material layer 19 Photoresist layer 20 Memory cell 20L Stack 22 Barrier plate 22L Barrier layer 24 First electrode 24L First electrode layer 26 Memory film 26L Memory material layer 28 Second electrode 28L Second electrode layer 29 Barrier plate 29L Barrier layer 30 Hard shield cap 30L Hard shield layer 32 Insulating spacer 35 Top connection via hole structure 37 Patterned photoresist layer/shield layer 70A Transistor 100 Memory array region 200 Peripheral region 221 Barrier plate 221L Barrier layer 222 Barrier plate 222L Barrier layer 223 Barrier plate 223L Barrier layer 260C Central region 260P Peripheral region 261 Oxide layer 261C Central region 261L Oxide layer 261P Peripheral region 262 Oxidation layer 262C Central region 262L Oxidation layer 262P Peripheral region 291 Barrier plate 291L Barrier layer 292 Barrier plate 292L Barrier layer 601 Dielectric material layer 610 Dielectric material layer 612 Via hole structure 618 Wiring structure 620 Dielectric material layer 622 Via hole structure 628 Wiring structure 630 Dielectric material layer 632 Via hole structure 638 Wiring structure 640 Dielectric material layer 642 Via hole structure 645 Dielectric layer/dielectric material layer 646 Dielectric material layer 647 Dielectric material layer 648 Wiring structure 648B Bit line 700 CMOS circuit system 701 Transistor 720 Shallow trench isolation structure 732 Source electrode 735 Semiconductor channel 738 Drain electrode 742 Alloy region 748 Alloy region 750 Gate structure 752 Dielectric layer 754 Gate electrode 756 Spacer 758 Dielectric 810 Curve 820 Curves 2210-2220 Step hd1 Horizontal direction hd2 Horizontal direction P Bottom periphery p1 Pitch p2 Pitch

Claims (9)

a first electrode including a first metallic material;
a memory film comprising at least one dielectric metal oxide material, in contact with the first electrode, the memory film comprising a central region having a first average atomic ratio of a passivating element to oxygen less than 0.01, and a peripheral region having a second average atomic ratio of the passivating element to oxygen greater than 0.05, the passivating element being selected from fluorine and nitrogen;
a second electrode including a second metallic material and in contact with the memory film;
an etch-stop dielectric material layer underlying the first electrode and including a horizontally extending portion and a vertical protrusion including sidewalls vertically overlapping sidewalls of the first electrode and having a bottom perimeter adjacent a perimeter of the horizontally extending portion;
The semiconductor structure , wherein the etch-stop dielectric material layer includes an opening extending therethrough in a plan view within the region of the first electrode . 2. The semiconductor structure of claim 1, wherein a first interface between the first electrode and the memory film includes a horizontal segment; and a sidewall of the memory film vertically overlaps a sidewall of the first electrode. The semiconductor structure of claim 2, wherein the sidewall of the memory film vertically overlaps the sidewall of the second electrode. The semiconductor structure of claim 2, further comprising an insulating spacer laterally surrounding the second electrode, the outer sidewall of the insulating spacer vertically overlapping the sidewall of the memory film. The semiconductor structure according to any one of claims 1 to 4, wherein the peripheral region of the memory film has a concentration gradient of a passivating element such that the atomic concentration of the passivating element decreases with distance from the surface of the memory film. 1. A semiconductor structure including a two-dimensional array of memory cells disposed on a substrate including respective first electrodes, respective memory films , and respective second electrodes,
Each individual memory film in the two-dimensional array of memory cells comprises:
a distinct central region having an atomic ratio of passivating element to oxygen of less than 0.01;
a discrete peripheral region in which the atomic ratio of the passivating element to oxygen is greater than 0.05, the passivating element being selected from fluorine and nitrogen;
an etch-stop dielectric material layer underlying the respective first electrodes and including a horizontally extending portion and a vertical protrusion having a bottom periphery adjacent a periphery of the horizontally extending portion and including sidewalls vertically overlapping the sidewalls of the respective first electrodes;
The semiconductor structure , wherein the etch-stop dielectric material layer includes openings therethrough that, in a plan view, are in the areas of the respective first electrodes . a two-dimensional array of access transistors located in the substrate, each access transistor therein being electrically connected to a respective memory cell in the two-dimensional array of memory cells;
a metal interconnect structure located within the plurality of layers of dielectric material and providing electrical connection between the two-dimensional array of access transistors and the two-dimensional array of memory cells;
7. The semiconductor structure of claim 6, further comprising: forming an etch-stop dielectric material layer over a substrate;
forming a stack above said substrate comprising a first electrode, at least one memory film comprising a non-stoichiometric oxygen deficient dielectric metal oxide material, and a second electrode;
the etch-stop dielectric material layer underlies the first electrode and includes a horizontally extending portion and a vertically protruding portion having a bottom periphery adjacent a periphery of the horizontally extending portion and including sidewalls vertically overlapping sidewalls of the first electrode;
the etch-stop dielectric material layer includes an opening extending through the first electrode region in a plan view;
performing a passivation plasma treatment on the stack such that an average atomic ratio of passivation element to oxygen in a peripheral region of the memory film increases from a first number less than 0.01 to a second number greater than 0.05;
Including,
A method for forming a semiconductor structure wherein said passivating element is selected from fluorine and nitrogen. forming a first electrode layer, a memory material layer, and a second electrode layer on the substrate;
patterning the second electrode layer, the memory material layer, and the first electrode layer;
Further comprising:
the first electrode includes a patterned portion of the first electrode layer;
the memory film includes a patterned portion of the layer of memory material;
The method of claim 8 , wherein the second electrode comprises a patterned portion of the second electrode layer.

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