JP7617698B2 - Ceramic Electronic Components - Google Patents

Description

The present invention relates to ceramic electronic components.

In ceramic electronic components such as multilayer ceramic capacitors, the insulation deterioration mechanism occurs when oxygen defects in the dielectric layer are deposited on the cathode by an electric field, lowering the electrical resistance at the interface between the cathode and the dielectric layer, and it has been reported that the time until this deposition determines the lifespan (see, for example, Non-Patent Document 1).

It is known that by following this model and reducing the amount of oxygen defects, reliability such as life span and voltage resistance can be improved (see, for example, Patent Documents 1 and 2). In Patent Documents 1 and 2, thermally stimulated depolarization current (TSDC) is used to quantify the oxygen defect concentration.

JP 2004-356305 A JP 2014-165447 A

"dc-Electrical Degradation of the BT-Based Material for Multilayer Ceramic Capacitor with Ni internal Electrode: Impedance Analysis and Microstructure", Jpn J Appl Phys, 40(2001) pp.5624-5629

In Patent Documents 1 and 2, the amount of oxygen defects is estimated from the integral value of the current in the TSDC data. However, the portion of the TSDC data that has a large effect on the lifespan of ceramic electronic components is the portion that corresponds to oxygen defects that cross the grain boundaries of the dielectric layer and migrate to the cathode. Patent Documents 1 and 2 make no disclosure of this.

The present invention has been made in consideration of the above problems, and aims to provide a ceramic electronic component that can improve reliability.

The ceramic electronic component according to the present invention has a laminated structure in which dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, and is characterized in that, in a TSDC in which the polarization temperature for the dielectric layers is 150°C, the polarization electric field is 15 V/μm to 20 V/μm, the polarization time is 60 min, and the temperature rise rate is 10°C/min, when a low-temperature peak current value of 160°C or higher and lower than 230°C is I _A and a high-temperature peak current value of 230°C or higher and 350°C or lower is I _B , a relationship of I _A /I _B > 0.30 is established and I _B is 100 pA/mm2 ^or less.

In the ceramic electronic component, I _A /I _B ≧0.50 may be satisfied.

In the ceramic electronic component, I _A /I _B ≧0.70 may be satisfied.

In the ceramic electronic component, I _A /I _B ≧2.00 may be satisfied.

In the ceramic electronic component, the I _B may be 95 pA/mm ² or less.

In the ceramic electronic component, the I _B may be 90 pA/mm ² or less.

In the ceramic electronic component, the I _B may be 80 pA/mm ² or less.

Another ceramic electronic component according to the present invention has a laminated structure in which dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, and the dielectric layers are polarized for a polarization time of 60 min, a polarization electric field of 10 V/μm, and a polarization temperature ranging from 150°C to 210°C. The dielectric layers are then polarized at a heating rate of 10°C/min after cooling to 130°C. In this TSDC, the peak current value of the peak occurring at the lowest temperature side when the temperature is raised to 350°C is J150 when the peak current value when polarized at 150°C is J150, and the peak current value when polarized at 170°C is J170, and the relationship (J170-J150)/J150≧0 is established.

In the above ceramic electronic component, the average thickness of the dielectric layer may be 1 μm or more.

In the above ceramic electronic component, the average thickness of the dielectric layer may be 3.5 μm or more.

In the ceramic electronic component, the average number of crystal grains in the thickness direction of the dielectric layer may be 3 or more.

In the above ceramic electronic component, the number of laminated dielectric layers may be 1000 or more.

In the ceramic electronic component, the main component of the dielectric layer may be _BaTiO3 .

In the above ceramic electronic component, there may be two or more TSDC peaks occurring in the temperature range of 130°C or higher and 350°C or lower.

In the above ceramic electronic component, there may be three or more TSDC peaks occurring in the temperature range of 130°C or higher and 350°C or lower.

The present invention provides ceramic electronic components that can improve reliability.

FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. 1A to 1E are diagrams illustrating a procedure for estimating the amount of oxygen defect movement using TSDC. 1A is a diagram illustrating the movement of oxygen defects, and FIG. 1B is a diagram illustrating the relationship between temperature and thermally stimulated current value. 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. FIG. 13 is a diagram illustrating a relationship between temperature and a thermal stimulation current value. FIG. 1 is a graph showing the results of Examples 6 to 10 and Comparative Examples 4 and 5.

The following describes the embodiment with reference to the drawings.

First Embodiment
First, an overview of the multilayer ceramic capacitor will be described. FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to the first embodiment. As illustrated in FIG. 1, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a rectangular parallelepiped shape, and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the upper and lower faces in the lamination direction are referred to as side faces. The external electrodes 20a, 20b extend on the upper, lower and two side faces in the lamination direction of the laminated chip 10. However, the external electrodes 20a, 20b are spaced apart from each other.

The laminated chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately laminated. The edges of each internal electrode layer 12 are alternately exposed to the end face of the laminated chip 10 on which the external electrode 20a is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the laminated ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are laminated via the internal electrode layers 12. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged on the outermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered by the cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layer 11 and the ceramic material.

The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high, or 0.4 mm long, 0.2 mm wide, and 0.2 mm high, or 0.6 mm long, 0.3 mm wide, and 0.3 mm high, or 1.0 mm long, 0.5 mm wide, and 0.5 mm high, or 1.6 mm long, 0.8 mm wide, and 0.8 mm high, or 3.2 mm long, 1.6 mm wide, and 1.6 mm high, or 4.5 mm long, 3.2 mm wide, and 2.5 mm high, but is not limited to these sizes.

The internal electrode layer 12 is mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layer 12.

The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO ₃ as a main phase. The perovskite structure includes ABO _3-α , which is not a stoichiometric composition. For example, the ceramic material may be BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), or Ba _1-x-y Ca _x Sr _y Ti _1-z Zr _z O ₃ (0≦x≦1, 0≦y≦1, 0≦z≦1) that forms a perovskite structure. The dielectric layer 11 is obtained by firing a ceramic raw material powder having a perovskite structure as a main component, for example.

In such a multilayer ceramic capacitor 100, the insulation deterioration mechanism occurs when oxygen defects in the dielectric layer 11 are deposited on the internal electrode layer 12, which acts as a cathode, at the interface between the internal electrode layer 12 and the dielectric layer 11 by the electric field, lowering the electrical resistance at the interface, and it has been reported and widely accepted that the time until this deposition determines the lifespan. It is known that reliability such as lifespan and withstand voltage can be improved by reducing the amount of oxygen defects according to this model. For example, the amount of oxygen defect migration can be estimated by thermally stimulated depolarization current (TSDC).

For example, Figures 2(a) to 2(e) are diagrams illustrating a procedure for estimating the amount of oxygen defect migration using TSDC. Figure 2(a) is a cross-sectional view illustrating a dielectric layer 11 sandwiched between an internal electrode layer 12 connected to one external electrode and an internal electrode layer 12 connected to the other external electrode. As illustrated in Figure 2(a), oxygen defects 14 exist in the dielectric layer 11, and are distributed, for example, approximately evenly in the dielectric layer 11.

Figure 2(b) partially shows the state in which the multilayer ceramic capacitor 100 is placed at a heated predetermined temperature and a DC voltage is applied between two adjacent internal electrode layers 12. When the unloaded multilayer ceramic capacitor 100 is heated and a DC voltage is applied between two adjacent internal electrode layers 12, the oxygen defects 14 distributed in the dielectric layer 11 become unevenly distributed on one electrode side (here, the negative electrode side). In this case, the temperature is, for example, 200°C. The electric field strength applied to the dielectric layer 11 is, for example, 10 V/μm.

Figure 2 (c) shows the state of the multilayer ceramic capacitor 100 when it is returned to an unloaded state at room temperature (25°C) after being subjected to a high-temperature load. Even after the temperature is returned to room temperature (25°C) and the voltage is released, the oxygen defects 14 remain concentrated in one of the internal electrode layers 12 (negative electrode side).

As shown in FIG. 2(d), when an ammeter is attached to the multilayer ceramic capacitor 100 and the multilayer ceramic capacitor 100 is heated again, the oxygen defects 14 that were unevenly distributed on one of the internal electrode layers 12 (here, the negative electrode side) in the dielectric layer 11 gradually move to the opposing internal electrode layer 12 side. These oxygen defects 14 become carriers and a current flows. This current is called a thermally stimulated current. The heating temperature is about 300°C. The thermally stimulated current occurs until the polarization caused by the oxygen defects 14 is released, as shown in FIG. 2(e), so the time integral value of the current value until the polarization is released is the total amount of charge Q of the carriers in the dielectric layer 11.

The charge Q obtained by the above measurement is divided by the charge per oxygen defect 14 (2×1.6×10 ⁻¹⁹ coulombs: expressed as a negative fixed charge of V ₀ ⁺² , and therefore the absolute value is twice the elementary charge) and the volume of the dielectric layer 11 to obtain the concentration of oxygen defects present in the multilayer ceramic capacitor 100. In this manner, the amount of oxygen defects can be estimated from the integral value of the current value.

Here, the movement of oxygen defects when a thermally stimulated current occurs will be described. FIG. 3(a) is a diagram illustrating the movement of oxygen defects. As illustrated in FIG. 3(a), the dielectric layer 11 includes a plurality of crystal grains 15. A crystal grain boundary 16 is formed between two crystal grains 15. As illustrated in the upper part of FIG. 3(a), the oxygen defects 14 move within the crystal grains 15. Also, as illustrated in the middle part of FIG. 3(a), the oxygen defects 14 move across the crystal grain boundaries 16. It is the oxygen defects 14 that move across the crystal grain boundaries 16 in the dielectric layer 11 that have a large effect on the life of the multilayer ceramic capacitor 100.

In this regard, in the TSDC with the polarization temperature of 150°C, the polarization electric field of 15V/μm to 20V/μm, the polarization time of 60 min, and the heating rate of 10°C/min, the relationship between the temperature and the thermally stimulated current value when the temperature is raised to about 350°C is illustrated in FIG. 3(b). As illustrated in FIG. 3(b), multiple peaks appear in the TSDC data. Broadly speaking, two main peaks typically appear at 160°C or higher. These peaks are a low-temperature peak (peak A) between 160°C and less than 230°C, and a high-temperature peak (peak B) between 230°C and 350°C. In the procedure of FIG. 2(a) to FIG. 2(e), the amount of oxygen defects is estimated from the integral value of these current peaks. Here, the polarization temperature refers to the temperature at which the dielectric layer 11 is polarized. The polarization electric field refers to the strength of the electric field that polarizes the dielectric layer 11. The polarization time refers to the time it takes to polarize the dielectric layer 11. Also, the peak refers to the maximum value (the upwardly convex inflection point) when the current value is represented on a graph.

In FIG. 3(b), the difference between the solid line and the dotted line is due to oxygen defects in the dielectric layer 11. In both the solid line and the dotted line, a low-temperature peak (peak A) between 160°C and 230°C and a high-temperature peak (peak B) between 230°C and 350°C appears. In addition, in the temperature range between 130°C and 350°C, two or more TSDC peaks appear, and sometimes three or more TSDC peaks appear.

This integral value alone is not sufficient to link the actual reliability of the multilayer ceramic capacitor 100 with the TSDC data. As described above, it is the oxygen defects 14 that move across the grain boundaries 16 in the dielectric layer 11 that have a large effect on the reliability of the multilayer ceramic capacitor 100. The movement of these oxygen defects 14 is the current represented by peak B. In contrast, the current represented by peak A is the movement of oxygen defects within the crystal grains 15 without crossing the grain boundaries 16. The effect of peak A on the life of the multilayer ceramic capacitor is smaller than the effect of peak B. Therefore, in order to improve reliability, it is necessary to reduce peak B.

The inventors have found through extensive research that the ratio (I _A /I _B ) of the peak current value I _A of peak A to the peak current value I _B of peak B is important for controlling reliability. Specifically, the inventors have found that in TSDC with a polarization temperature of 150° C., a polarization electric field of 15 V/μm to 20 V/μm, a polarization time of 60 min, and a temperature rise rate of 10° C./min, when the relationship I _A /I _B >0.30 holds and the peak current I _B is 100 pA/mm ² or less, a long life can be obtained even when a relatively high electric field is applied. Furthermore, by using this method, the reliability of the multilayer ceramic capacitor 100 can be estimated in a short time.

In the multilayer ceramic capacitor 100 according to this embodiment, at least one of the plurality of dielectric layers 11 has a configuration in which I _A / _IB exceeds 0.30 and I _B ≦100 pA/mm ^2. It is preferable that all of the dielectric layers 11 included in the multilayer ceramic capacitor 100 have a configuration in which I _A / _IB exceeds 0.30 and I _B ≦100 pA/mm ² .

For example, by adjusting parameters such as the composition, crystal grain size, and firing conditions of the dielectric layer 11, a configuration in which I _A /I _B exceeds 0.30 and I _B ≦100 pA/mm ² can be obtained. From the viewpoint of improving reliability, I _A /I _B is preferably 0.50 or more, more preferably exceeds 0.5, more preferably 0.70 or more, more preferably exceeds 1.0, and more preferably 2.00 or more. _{I B} is preferably 95 pA/mm ² or less, preferably 90 pA/mm ² or less, preferably 85 pA/mm ² or less, preferably 80 pA/mm ² or less, and preferably 50 pA/mm ² or less. The unit of the current value is A/mm ² , which indicates the current value per unit area. This value can be obtained by dividing the current value measured in the multilayer ceramic capacitor 100 by the total area of the region in which the internal electrodes included in the multilayer ceramic capacitor 100 face each other with the dielectric layer sandwiched therebetween.

For example, I _A /I _B can be increased by increasing the number of grain boundaries that cross the electric field or by thickening the grain boundaries. Also, the smaller I _B is, the more reliable the product is, which is preferable. When the value of I _B approaches 0, the value of I _A /I _B can become very large.

When the dielectric layer 11 contains multiple crystal grains in the thickness direction, peaks A and B are prominent. Therefore, it is preferable that the dielectric layer 11 contains multiple crystal grains in the thickness direction. For example, it is preferable that the average number of crystal grains per layer of the dielectric layer 11 is 3 to 8. The average value of the crystal grains per layer of such a dielectric layer 11 can be obtained by observing a cut surface parallel to the stacking direction with an electron microscope, determining the number of crystal grains that an arbitrary straight line drawn parallel to the stacking direction crosses in one dielectric layer, and performing this for 20 arbitrarily selected locations in the dielectric layer, and calculating the average value of the obtained 20 pieces of data.

The average thickness of the dielectric layer 11 is, for example, 1 μm or more and 3.5 μm or more. This is because it is preferable that the dielectric layer 11 contains multiple crystal grains in the thickness direction. The average thickness of the dielectric layer 11 can be obtained by observing a cut surface parallel to the stacking direction with an electron microscope, and taking the average thickness of, for example, 20 arbitrarily selected points.

In addition, since the values of _I , _I , and ( _I + _I ) themselves vary depending on the size of the multilayer ceramic capacitor 100, the electrode configuration, the dielectric layer thickness, the polarization conditions, and other conditions, it is difficult to control the lifespan using only these individual values. Based on this viewpoint, in this embodiment, attention is paid to the ratio of _I to _I.

Next, we will explain the manufacturing method of the multilayer ceramic capacitor 100. Figure 4 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.

(Raw material powder preparation process)
First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of _ABO3 particles. For example, _BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This _BaTiO3 can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. Various methods have been known so far as a method for synthesizing the main component ceramic of the dielectric layer 11, such as a solid-phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these methods can be adopted.

The resulting ceramic powder is added with a specific additive compound according to the purpose. Examples of additive compounds include oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium)), as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium) and Si (silicon).

For example, a compound containing an additive compound is wet mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.

(Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. Using the obtained slurry, a belt-shaped dielectric green sheet having a thickness of, for example, 1 μm or more is applied to a substrate by, for example, a die coater method or a doctor blade method, and then dried.

Next, a metal conductive paste for forming an internal electrode containing an organic binder is printed on the surface of the dielectric green sheet by screen printing, gravure printing, or the like to arrange an internal electrode layer pattern that is alternately drawn to a pair of external electrodes with different polarities. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11. For example, _BaTiO3 with an average particle size of 50 nm or less may be uniformly dispersed.

Then, the dielectric green sheet on which the internal electrode layer pattern is printed is punched out to a specified size, and the punched dielectric green sheet is laminated in a specified number of layers (e.g., 100 to 1000 layers) with the base material peeled off, so that the internal electrode layers 12 and the dielectric layers 11 are alternated, and the internal electrode layers 12 are alternately exposed at both longitudinal end faces of the dielectric layers 11 and alternately drawn out to a pair of external electrodes 20a, 20b of opposite polarity. Cover sheets for forming the cover layers 13 are pressed onto the top and bottom of the laminated dielectric green sheets, and the laminated dielectric green sheets are cut to the specified chip dimensions (e.g., 1.0 mm x 0.5 mm).

The obtained ceramic laminate is subjected to debinding in a _N2 atmosphere, and then a metal paste that contains a metal filler including the main component metal of the external electrodes 20a, 20b, a co-material, a binder, a solvent, etc. and that will serve as a base layer for the external electrodes 20a, 20b is applied to both end faces and each side face of the ceramic laminate, and then dried.

(Firing process)
The molded body thus obtained is subjected to a binder removal process in a _N2 atmosphere at 250 to 500°C, and then fired at 1100 to 1300°C for 10 minutes to 2 hours in a reducing atmosphere with an oxygen partial pressure of ^10-8 to ^10-13 atm, thereby sintering each particle of the molded body. In this way, a ceramic laminate is obtained.

(Reoxidation treatment process)
Then, reoxidation is performed at 600°C to 1000°C in an _N2 gas atmosphere. For example, reoxidation is performed at 950°C for 1 hour. Then, the _N2 gas atmosphere is cooled to 500°C, the atmosphere is switched to air, and the temperature is held at 500°C for 24 hours, and then the temperature is cooled to room temperature. By performing such a process, the oxygen concentration of the grain boundaries 16 of the dielectric layer 11 can be increased. This can greatly reduce the peak current value of TSDC, and can suppress the movement of oxygen defects 14 beyond or along the grain boundaries 16. As a result, _IB can be relatively reduced with respect to _IA . In addition, by holding the capacitor at 500°C for a long time, reoxidation of a large multi-layer ceramic capacitor with 1000 or more layers, such as a 4532 size (length 4.5 mm, width 3.2 mm, height 2.5 mm), is also possible.

(Plating process)
Thereafter, the underlayers of the external electrodes 20a, 20b are coated with a metal such as Cu, Ni, Sn, etc. by plating. Through the above steps, the multilayer ceramic capacitor 100 is completed.

According to the manufacturing method of this embodiment, at least one of the plurality of dielectric layers 11 has a configuration in which I _A /I _B exceeds 0.30 and I _B ≦100 pA/mm ^2. This provides a long life and improves reliability even when a relatively high electric field is applied.

Second Embodiment
Next, a second embodiment will be described. In the second embodiment, the TSDC conditions are changed in the multilayer ceramic capacitor 100 described with reference to FIG.

The inventors have conducted extensive research and found that in a TSDC in which the dielectric layer 11 is polarized for a polarization time of 60 minutes, the polarization field is 10 V/μm, and the polarization temperature is changed in the range of 150°C to 210°C, and then cooled to 130°C and then heated at a rate of 10°C/min, the peak current value at the lowest temperature side (near 150°C) among the peak currents generated when the temperature is raised to about 350°C does not show a decreasing trend with increasing polarization temperature, and therefore a long life can be obtained.

The peak that occurs on the lowest temperature side (near 150°C) is thought to be a peak derived from defect dipoles (clusters of oxygen defects and cation defects, metal defects, etc.). The fact that this peak does not tend to decrease as the polarization temperature increases can be interpreted as meaning that this cluster does not dissociate and oxygen defects are less likely to migrate. This is thought to suppress the increase in the peak that occurs on the high temperature side, which is thought to have a significant impact on the reliability of multilayer ceramic capacitors.

Specifically, if the peak current value of the TSDC peak occurring near 150°C when polarized at a polarization temperature of 150°C is J150, and the peak current value of the TSDC peak occurring near 150°C when polarized at a polarization temperature of 170°C is J170, then a long lifespan can be obtained by satisfying the relationship ΔJ = (J170 - J150) / J150 ≧ 0. Note that while normal TSDC requires heating to 350°C or higher, in this embodiment it is sufficient to heat the capacitor to about 350°C, so the reliability of the multilayer ceramic capacitor 100 can be evaluated easily.

Figure 5 is a diagram illustrating J170 and J150. In Figure 5, the solid line represents the TSDC when polarized at 170°C, and the dotted line represents the TSDC when polarized at 150°C. As illustrated in Figure 5, both J170 and J150 have peaks near 150°C. Furthermore, J170 is greater than J150. The temperatures at which the J170 and J150 peaks are observed are, for example, within the range of 130°C to 160°C.

In the multilayer ceramic capacitor 100 according to this embodiment, at least one of the multiple dielectric layers 11 has a configuration in which the relationship ΔJ=(J170-J150)/J150≧0 holds. It is preferable that all of the dielectric layers 11 included in the multilayer ceramic capacitor 100 have a configuration in which the relationship ΔJ=(J170-J150)/J150≧0 holds.

For example, by adjusting parameters such as the composition of the dielectric layer 11, the crystal grain size, and the firing conditions, the relationship ΔJ = (J170 - J150)/J150 ≧ 0 is established. From the viewpoint of improving reliability, it is preferable that the relationship ΔJ = (J170 - J150)/J150 ≧ 0.5 is established, and it is even more preferable that the relationship ΔJ = (J170 - J150)/J150 ≧ 1.0 is established.

For example, ΔJ=(J170-J150)/J150 can be increased by increasing the number of grain boundaries that cross the electric field or by thickening the grain boundaries. However, if ΔJ=(J170-J150)/J150 is made too large, the capacitance of the product may decrease. Therefore, from the standpoint of ensuring capacitance and high reliability, it is preferable to set an upper limit on ΔJ=(J170-J150)/J150. For example, ΔJ=(J170-J150)/J150 is preferably 2.0 or less, more preferably 1.5 or less, and even more preferably 1.25 or less.

In the above TSDC, regardless of whether the polarization temperature is 150°C to 210°C, it is preferable that, in a TSDC in which the temperature is increased at a rate of 10°C/min after cooling to 130°C, the peak current value of the peak at the lowest temperature (near 150°C) generated when the temperature is increased to about 350°C does not show a decreasing tendency with increasing polarization temperature.

The multilayer ceramic capacitor 100 according to this embodiment can be manufactured by the same manufacturing method as the first embodiment. According to this manufacturing method, at least one of the multiple dielectric layers 11 satisfies the relationship ΔJ=(J170-J150)/J150≧0. As a result, a long life is obtained and reliability is improved even when used in a relatively high temperature environment.

In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may be used.

The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were investigated.

Example 1
Barium titanate powder was prepared as the dielectric material. Necessary additives were added to the barium titanate powder, and the powder was thoroughly wet mixed and pulverized in a ball mill to obtain the dielectric material. An organic binder and a solvent were added to the dielectric material, and a dielectric green sheet was produced by the doctor blade method. Polyvinyl butyral (PVB) or the like was used as the organic binder, and ethanol, toluene, or the like was added as the solvent. Plasticizers and other additives were also added.

Next, a metal conductive paste for forming the internal electrodes, which contains the main component metal of the internal electrode layer 12, a co-material, a binder (ethyl cellulose), a solvent, and other auxiliary agents as necessary, was prepared using a planetary ball mill.

A metal conductive paste for forming internal electrodes was screen-printed on the dielectric green sheets. 301 sheets of the sheet members with the metal conductive paste printed on them were stacked on top of each other on the dielectric green sheets, and cover sheets were laminated on the top and bottom of each. A laminate was then obtained by thermocompression bonding and cut into the specified shape.

The obtained laminate was debindered in a _N2 atmosphere, and then a metal conductive paste containing a metal filler mainly composed of Ni, a co-material, a binder, a solvent, etc. was applied to both ends and each side of the laminate for the underlayer, and dried. The metal conductive paste for the underlayer was then fired simultaneously with the laminate in a reducing atmosphere at 1100°C to 1300°C for 10 minutes to 2 hours to obtain a sintered body. The shape and dimensions of the obtained sintered body were 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height.

Then, a reoxidation treatment was performed. First, the product was held at 950°C for 1 hour in an _N2 gas atmosphere. Then, the product was cooled to 500°C in the _N2 gas atmosphere, the atmosphere was switched to air, and the product was held at 500°C for 24 hours, and then cooled to room temperature. Then, a plating treatment was performed to form a Cu plating layer, a Ni plating layer, and a Sn plating layer on the surface of the underlayer, thereby obtaining a multilayer ceramic capacitor 100. The thickness of the dielectric green sheet was adjusted so that the average thickness of the dielectric layer 11 confirmed from the cross section of the product was 1.2 μm.

Example 2
In Example 2, compared to Example 1, the temperature holding condition after switching the atmosphere to air was changed to 500° C. for 20 hours. The other conditions were the same as in Example 1.

Example 3
In Example 3, compared to Example 1, the temperature holding condition after switching the atmosphere to air was changed to holding at 500° C. for 30 hours. The other conditions were the same as those in Example 1.

Example 4
In Example 4, compared to Example 1, the number of laminated layers of the dielectric layer 11 was changed to 1100 layers, and the average thickness of the dielectric layer 11 confirmed from the cross section of the product was changed to 0.7 μm. The other conditions were the same as those in Example 1.

Example 5
In Example 5, compared to Example 1, the number of laminated dielectric layers 11 was changed to 100, and the average thickness of the dielectric layers 11 confirmed from the cross section of the product was changed to 3.6 μm. The other conditions were the same as in Example 1.

(Comparative Example 1)
In Comparative Example 1, in the reoxidation treatment, the sample was held at 950°C for 1 hour in a _N2 gas atmosphere, then cooled to 500°C in the _N2 gas atmosphere, and then cooled to room temperature by switching the atmosphere to air. In other words, the sample was not held at 500°C. The other conditions were the same as those in Example 1.

(Comparative Example 2)
In Comparative Example 2, in the reoxidation treatment, the sample was held at 950°C for 1 hour in an _N2 gas atmosphere, cooled to 500°C while still in the _N2 gas atmosphere, switched to air, held at 500°C for 5 hours, and then cooled to room temperature. That is, the holding time at 500°C was shorter than in Example 1. The other conditions were the same as in Example 1.

(Comparative Example 3)
In Comparative Example 3, in the reoxidation treatment, the sample was held at 950°C for 1 hour in an _N2 gas atmosphere, cooled to 500°C while still in the _N2 gas atmosphere, switched to air, held at 500°C for 15 hours, and then cooled to room temperature. That is, the holding time at 500°C was shorter than in Example 1. The other conditions were the same as in Example 1.

(Analysis 1)
For Examples 1 to 5 and Comparative Examples 1 to 3, I A /I B was measured in TSDC with a polarization temperature of 150° C., a polarization time of 60 min, a polarization electric field of 20 V/μm, and a temperature rise rate of 10° C./min. In addition, an accelerated life test ( _{HALT )} was performed at a high temperature and high electric field of 150° C. and 40 V/μm. The results are shown in Table 1. For MTTF (Mean Time To Failure), the time until conduction was measured for 20 pieces each of Examples 1 to 5 and Comparative Examples 1 to 3, and the average value of the obtained life times was taken as MTTF.

In addition, for Examples 1 to 5 and Comparative Examples 1 to 3, the average number of crystal grains in the thickness direction of the dielectric layer was 3 to 10.

As shown in Table 1, in Example 1, I _A /I _B was 0.35, and I _B was 90 pA/mm ^2. In Example 2, I _A /I _B was 0.70, and I _B was 95 pA/mm ^2. In Example 3, I _A /I _B was 2.00, and I _B was 20 pA/mm ^2. In Example 4, I _A /I _B was 0.50, and I _B was 80 pA/mm ^2. In Example 5, I _A /I _B was 3.00, and I _B was 20 pA/mm ^2. In Comparative Example 1, I _A /I _B was 0.15, and I _B was 500 pA/mm ^2. In Comparative Example 2, I _A /I _B was 0.35, and I _B was 250 pA/mm ² . In Example 3, I _A /I _B was 1.50 and I _B was 105 pA/mm ² .

In Examples 1 to 5, the MTTF exceeded 2000 min, and a long life was obtained. This is believed to be because the relationship I _A /I _B >0.30 was established, and the peak current I _B generated at the highest temperature was 100 pA/mm ² or less. In contrast, in Comparative Example 1, the MTTF was short at 100 min. This is believed to be because I _A /I _B was low at 0.15, and I _B could not be made sufficiently small. In Comparative Example 2, the MTTF was short at 500 min. This is believed to be because although I _A /I _B was high at 0.35, I _B was high at 250 pA/mm ² , and I _B could not be made sufficiently small. In Comparative Example 3, the MTTF was short at 2000 min. This is believed to be because although I _A /I _B increased to 1.50, I _B was high at 105 pA/mm ² and I _B could not be made sufficiently small.

Example 6
In Example 6, the same manufacturing method and specifications as those in Example 1 were used.

(Example 7)
In Example 7, the same manufacturing method and specifications as in Example 2 were used.

(Example 8)
In Example 8, the same manufacturing method and specifications as in Example 3 were used.

(Example 9)
In Example 9, the same manufacturing method and specifications as in Example 4 were used.

(Example 10)
In Example 10, the same manufacturing method and specifications as in Example 5 were used.

(Comparative Example 4)
In Comparative Example 4, in the reoxidation treatment, the sample was held at 950° C. for 1 hour in a N ₂ gas atmosphere, then cooled to 500° C. in the N ₂ gas atmosphere, and then cooled to room temperature by switching the atmosphere to air. In other words, the sample was not held at 500° C. The other conditions were the same as those in Example 1.

(Comparative Example 5)
In Comparative Example 5, in the reoxidation treatment, the sample was held at 950°C for 1 hour in an _N2 gas atmosphere, cooled to 500°C while still in the _N2 gas atmosphere, switched to air, held at 500°C for 10 hours, and then cooled to room temperature. That is, the holding time at 500°C was shorter than in Example 1. The other conditions were the same as in Example 1.

(Analysis 2)
For Examples 6 to 10 and Comparative Examples 4 and 5, the polarization time was set to 60 min, the polarization electric field was set to 10 V/μm, the polarization temperature was changed in the range of 150 ° C. to 210 ° C., and the temperature was increased at a rate of 10 ° C./min after cooling to 130 ° C. In the TSDC, J150 and J170 were measured to measure ΔJ = (J170 - J150) / J150. In addition, an accelerated life test (HALT) was performed at a high temperature and high electric field of 150 ° C. and 40 V / μm. The results are shown in Table 1. For MTTF (Mean Time To Failure), the time until conduction was measured for 20 pieces each of Examples 6 to 10 and Comparative Examples 4 and 5, and the average value of the obtained life times was taken as MTTF.

In addition, for Examples 6 to 10 and Comparative Examples 4 and 5, the average number of crystal grains in the thickness direction of the dielectric layer was 3 to 10.

As shown in FIG. 6, in Example 6, the MTTF was 15,000 min and the ΔJ was 0.07. In Example 7, the MTTF was 12,500 min and the ΔJ was 0.04. In Example 8, the MTTF was 23,000 and the ΔJ was 0.18. In Example 9, the MTTF was 12,000 and the ΔJ was 0.02. In Example 10, the MTTF was 30,000 and the ΔJ was 0.3. In Comparative Example 4, the MTTF was 100 min and the ΔJ was -0.2. In Comparative Example 5, the MTTF was 1,200 min and the ΔJ was -0.05.

In Examples 6 to 10, the MTTF exceeded 2000 min, and a long life was obtained. This is believed to be because ΔJ was 0 or greater. In contrast, in Comparative Examples 4 and 5, the MTTF fell below 2000 min. This is believed to be because ΔJ was below 0.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as described in the claims.

REFERENCE SIGNS LIST 10 laminated chip 11 dielectric layer 12 internal electrode layer 13 cover layer 14 oxygen defects 15 crystal grain 16 crystal grain boundary 20a, 20b external electrode 100 laminated ceramic capacitor

Claims (15)

The ceramic-based dielectric layer and the internal electrode layer are alternately laminated to form a laminate structure.
A ceramic electronic component characterized in that, in a TSDC in which the polarization temperature for the dielectric layer is 150°C, the polarization electric field is 15V/μm to 20V/μm, the polarization time is 60 min, and the temperature rise rate is 10°C/min, when a low-temperature peak current value of 160°C or higher and lower than 230°C is I _A and a high-temperature peak current value of 230°C or higher and 350°C or lower is I _B , a relationship of I _A /I _B > 0.30 is established and I _B is 100 pA/mm2 or ^less . 2. The ceramic electronic component according to claim 1, wherein I _A and I _B satisfy I _A /I _B ≧0.50. 2. The ceramic electronic component according to claim 1, wherein I _A and I _B satisfy I _A /I _B ≧0.70. 2. The ceramic electronic component according to claim 1, wherein I _A and I _B satisfy I _A /I _B ≧2.00. 2. The ceramic electronic component according to claim 1, wherein the I _B is 95 pA/mm ² or less. 2. The ceramic electronic component according to claim 1, wherein the I _B is 90 pA/mm ² or less. 2. The ceramic electronic component according to claim 1, wherein the I _B is 80 pA/mm ² or less. The ceramic-based dielectric layer and the internal electrode layer are alternately laminated to form a laminate structure.
The dielectric layer is polarized for a polarization time of 60 min, a polarization electric field of 10 V/μm, and a polarization temperature of 150° C. or 170° C., and then cooled to 130° C. and heated at a rate of 10° C./min. In this TSDC, the peak current value of the peak occurring at the lowest temperature side when the temperature is raised to 350° C. is defined as J150 when the peak current value is polarized at 150° C., and as J170 when the peak current value is polarized at 170° C., and the relationship (J170-J150)/J150≧0 is established. The ceramic electronic component according to any one of claims 1 to 8, characterized in that the average thickness of the dielectric layer is 1 μm or more. The ceramic electronic component according to any one of claims 1 to 9, characterized in that the average thickness of the dielectric layer is 3.5 μm or more. The ceramic electronic component according to any one of claims 1 to 10, characterized in that the average number of crystal grains in the thickness direction of the dielectric layer is 3 or more. The ceramic electronic component according to any one of claims 1 to 11, characterized in that the number of laminated dielectric layers is 1000 or more. The ceramic electronic component according to any one of claims 1 to 12, characterized in that a main component of the dielectric layer is _BaTiO3 . The ceramic electronic component according to any one of claims 1 to 7, characterized in that there are two or more TSDC peaks occurring in the temperature range of 130°C or higher and 350°C or lower. 8. The ceramic electronic component according to claim 1, wherein three or more TSDC peaks are generated in a temperature range of 130° C. or higher and 350° C. or lower.

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