JP7617762B2 - Image sensor - Google Patents

Description

The present invention relates to an imaging element with a binning function.

A CMOS image sensor has pixels arranged in an array on a single plane (see, for example, pixel array region 300B shown in FIG. 8(A)), and each pixel has a photoelectric conversion unit 123 and multiple transistors (TG, RST, SF, SL) as shown in FIG. 8(B). The signal charge generated according to the amount of light input to each pixel is converted into a voltage according to the signal charge by a charge-voltage conversion unit arranged within the pixel, and this voltage signal (pixel signal) is output outside the element via an in-pixel amplifier and an AD conversion unit (for example, CDS/ADC in FIG. 8(A)) 230.

Here, the supply of drive signals to each pixel and the output of pixel signals from each pixel are performed through signal lines, and readout scanning is generally performed using a column-parallel method in which a group of pixels arranged horizontally on the screen (hereinafter referred to as a "row") are driven collectively, and signals from the pixels are transmitted to the AD conversion unit 230 via vertical signal lines wired vertically on the screen.
A single vertical signal line is connected to many pixels in the vertical direction of the screen, but a time-division method is adopted in which the row drive circuit that drives the pixel array drives the rows while scanning them, thereby driving only one pixel per vertical signal line at a time. This makes it possible to obtain image data by sequentially reading out pixel signals from all pixels in a chronological order.
As a result of arranging the signal lines in this manner, rows in the horizontal direction are driven collectively by a common drive signal line, so that all pixels in a row perform the same readout operation.

On the other hand, in recent years, due to the demand for smaller pixels, pixel sharing structures have been widely adopted in which multiple pixels (photodiodes) share one charge-voltage conversion unit. As an example, FIG. 9 shows a four-pixel sharing structure 302 in which four photodiodes 321 to 324, which are two pixels horizontally and two pixels vertically, share a charge-voltage conversion unit. FIG. 9 also shows how the four-pixel sharing structure 302 is arranged vertically and horizontally. In this configuration, in normal shooting, it is desirable to transfer the signal charges accumulated in the four photodiodes 321 to 324 in order to the charge-voltage conversion unit, read each of them out via a vertical signal line, and perform A/D conversion. On the other hand, in shooting under low illuminance, it is desirable to adopt a process called binning, in which the signal charges accumulated in the four photodiodes 321 to 324 are simultaneously transferred to the charge-voltage conversion unit, and the added signal is read out via a vertical signal line and A/D converted. Although binning reduces the image resolution, it is possible to improve the signal-to-noise ratio (S/N ratio) of the image being read out.

JP 2008-288903 A JP 2020-31347 A

In general image capture, the illuminance and spatial frequency components within the image capture range are not necessarily uniform across the range. For example, it is common for both areas containing relatively bright, high-definition subjects and areas containing relatively dark, low-definition subjects to exist within a single image capture range.
In such a case, it is desirable to improve the subjective image quality of the entire screen by capturing the former area at high resolution without binning and capturing the latter area at low noise with binning.
However, in order to perform such imaging, it is necessary to perform an operation of performing or not performing binning depending on the area to be imaged.

As such, a technique for changing pixel drive depending on the region to be photographed is known, for example, from the technique described in Patent Document 1. This technique suppresses blooming by performing an electronic shutter operation on a specific row, but since all pixels in one row perform the same operation, it is not possible to determine whether or not to perform binning for each region.
Furthermore, Patent Document 2 discloses a technology for controlling each pixel block. Although this technology has a function for driving all pixels according to whether they are responsible for short-second exposure or long-second exposure, and a function for cooperatively controlling the gain during readout in accordance with the type of pixel, it is not configured to add or not add accumulated signals in adjacent pixels to each other depending on the situation, making it difficult to control binning.

The present invention has been made in consideration of the above circumstances, and aims to provide an image sensor that can switch between enabling and disabling binning for each pixel or for each pixel group set to an arbitrary size in a pixel group that is driven and read out at the same timing.

The imaging element of the present invention comprises:
An image sensor in which a pixel group, in which a plurality of pixels each having a photoelectric conversion unit are arranged in an array, is divided into pixel portion regions each having a predetermined number of pixels, and charges accumulated in each of the pixels arranged in a predetermined direction in the pixel group are read out as a signal by driving the pixels,
a binning process drive instruction unit that outputs a binning process drive instruction signal that instructs whether or not to perform a binning process for each pixel section region control unit, the pixel section region being arranged one by one or a plurality of pixel section regions being arranged in the predetermined direction, based on binning process decision information relating to whether or not to perform a binning process for each pixel section region control unit ,
the predetermined direction is a row direction,
the binning process determination information is a row selection signal that is set to a high potential for either a selected row or a non-selected row and to a low potential for the other, and a pixel operation timing signal that is set to a high potential at one of on and off timings and to a low potential at the other timing for each gate of at least a transfer gate transistor in the pixel portion region,
The binning process drive instruction signal is a gate drive signal for driving at least the transfer gate transistor .
The "binning process determination information" may be automatically generated based on predetermined information, or may be information generated by a human operation from a keyboard or the like.

The gate drive signal is preferably a signal for turning on/off a gate for at least each of the transfer gate transistors provided for each of the photoelectric conversion sections constituting the pixel section region.
Furthermore, it is preferable that the binning process drive instruction section is provided for at least each of the transfer gate transistors constituting the pixel section region.

It is also preferable that the binning process drive instruction section includes an inverter circuit, which is made up of a pair of an NMOS transistor and a PMOS transistor, for at least each of the transfer gate transistors constituting the pixel section region.
It is also preferable that the binning process drive instruction section includes at least one NMOS transistor or PMOS transistor for each of the transfer gate transistors constituting the pixel section region.
Moreover, the at least one transfer gate transistor may be the transfer gate transistor and a reset transistor.
Furthermore, it is preferable that, for each of the pixel area control units, the signal conversion period by an AD conversion circuit provided in the signal output section is set to be longer when the binning process is performed than when the binning process is not performed.
In this case, it is preferable that the number of sampling operations is increased as the signal conversion period by the AD conversion circuit becomes longer.

According to the imaging element of the present invention, the pixel group is divided into pixel section regions each having a predetermined number of pixels, and a binning process drive instruction unit is provided that outputs a binning process drive instruction signal that instructs whether or not to perform binning process for each pixel section region control unit formed by arranging one of these pixel sections or by arranging a plurality of these pixel sections in a predetermined direction in the pixel group. Binning process decision information relating to whether or not to perform binning process is input to this binning process drive instruction unit, and a binning process drive instruction signal that instructs whether or not to perform binning process for each pixel section region control unit based on this binning process decision information is output.

As a result, with the imaging element of the present invention, in a pixel group that is driven and read out at the same timing, it becomes possible to switch between enabling and disabling binning for each pixel area control unit consisting of one pixel area or multiple pixel areas arranged in the specified direction.
Therefore, for example, even if an area (pixel area control unit) containing a relatively bright, high-definition subject and an area (pixel area control unit) containing a relatively dark, low-definition subject are both present within a single imaging range, the former area can be photographed at high resolution without binning, and the latter area can be photographed with low noise by binning, thereby improving the subjective image quality of the entire screen.

1 is a schematic diagram showing an imaging element according to an embodiment of the present invention. 2 is a schematic diagram showing a main part of a pixel portion region control unit of the image sensor according to the embodiment. FIG. 1 is a partial circuit diagram for explaining the operation of the in-pixel drive signal generation circuit of the image sensor according to the embodiment, and a graph showing the input/output signal state (when a row is selected (VDD side is connected to high voltage (VGH))). 1 is a partial circuit diagram for explaining the operation of an in-pixel drive signal generation circuit of an image sensor according to the present embodiment, and a graph showing input/output signal states (when a row is not selected (VDD side is connected to a low voltage (VGL))). FIG. 13 shows timing charts of each driving mode in a four-pixel sharing structure in an image sensor according to this embodiment ((A) readout without binning, (B) four-pixel binning, (C) horizontal two-pixel binning, and (D) vertical two-pixel binning). 1 is a schematic diagram showing an imaging device having a feedback control function for an imaging element according to an embodiment of the present invention. 3 is a schematic diagram showing a modification of the intra-pixel drive signal generating circuit of the image sensor shown in FIG. 2. 13A and 13B show timing charts of each driving mode in a four-pixel sharing structure in an image sensor according to a modified embodiment of this embodiment ((A) readout without binning, (B) four-pixel binning, (C) horizontal two-pixel binning, and (D) vertical two-pixel binning). 1A is a schematic diagram showing the structure of a CMOS image sensor according to prior art 1 and FIG. 1B is a schematic diagram showing the circuit of each pixel. FIG. 1 is a schematic diagram showing a pixel sharing structure of a CMOS image sensor according to prior art 2.

Hereinafter, an imaging device according to an embodiment of the present invention will be described with reference to the drawings.
First, the basic configuration of the image sensor according to this embodiment will be listed with reference to FIG.
That is, the image sensor 100 according to the present embodiment is configured to virtually divide a pixel group, which is an array of a plurality of pixels each having a photoelectric conversion unit 21 to 24, into pixel region control units 200 each having a plurality of pixel region 2 (or one pixel region) each having four pixels arranged in the row direction, and to read out the charge accumulated in the pixel as a signal by driving the pixels arranged in the row direction collectively. Also, the image sensor 100 includes an intra-pixel drive signal generating circuit (binning process drive instruction unit) 1 that outputs a gate drive signal (binning process drive instruction signal) based on binning process decision information regarding whether or not to perform binning process for each pixel region control unit 200. This gate drive signal uniformly instructs all pixel regions 2 in the pixel region control unit 200 whether or not to perform binning process for each pixel region control unit 200.

The binning process determination information input to the pixel drive signal generation circuit 1 is a row selection signal that is set to a high potential for the selected row and a low potential for the non-selected row (it is also possible to configure the high and low potentials to be reversed), and a pixel operation timing signal that is set to a high potential when the gates of the transfer gate transistors TG1 to TG4 and the reset transistor RST in the pixel region 2 are either on or off, and a low potential when the gates are the other way around (it is also possible to configure the high and low potentials to be reversed).

Moreover, a gate drive signal, which is an output signal from the intra-pixel drive signal generation circuit 1, drives the gates of the transfer gate transistors TG1 to TG4 and the reset transistor RST.
The in-pixel drive signal generation circuit 1 is provided for each of the transfer transistors TG1 to TG4 associated with the photoelectric conversion units 21 to 24 constituting the pixel region 2, and for one reset transistor RST for the pixel region 2.

Furthermore, the pixel drive signal generating circuit 1 includes an inverter circuit consisting of a pair of PMOS (P-type field effect transistor) and NMOS (N-type field effect transistor) for each of the transfer transistors TG1 to TG4 related to the photoelectric conversion units 21 to 24 constituting the pixel region 2, and for one reset transistor RST for the pixel region 2. The source of the PMOS 11 is connected to a row selection signal line, the source of the NMOS 12 is connected to signal lines (VSSTG, VSSRT) that supply gate voltages when the transfer transistors TG1 to TG4 and the reset transistor RST are off, and the drains of the PMOS 11 and NMOS 12 are connected to each other. The gates of both the PMOS 11 and NMOS 12 are connected so that the pixel operation timing signal is input.

That is, as shown in FIG. 1, in the image sensor according to this embodiment, an in-pixel drive signal generation circuit 1 is formed in each pixel region control unit 200 including a plurality of pixel regions 2 .
This in-pixel drive signal generation circuit 1 is configured to receive as input row selection signals (TG(n), RT(n), SL(n)) that are output from the row drive circuit 10 and that apply a gate drive voltage when turned on to the transfer gate transistors TG1 to TG4 in the pixel at the same time as row selection, and pixel operation timing signals (TG1CTL to TG4CTL, RTCTL) that provide the timing for turning on the gates for each column or for multiple columns, and is also configured to output gate drive signals (TG1_LOCAL to TG4_LOCAL, RT_LOCAL) that drive the gates of the in-pixel transistors based on these input signals.

The row selection signal is controlled so that, for each pixel region 2 arranged in a selected row, an on-voltage that drives the target in-pixel transistor is supplied during the selected period, while, for each pixel region 2 arranged in a non-selected row, a voltage equal to an off-voltage that does not drive the target in-pixel transistor is supplied during the non-selected period.
The pixel operation timing signal is controlled so that a so-called CMOS logic signal is supplied, in which VSS (low voltage) is supplied during the period when the transistor in the pixel is to be controlled to be on, and VDD (high voltage) is supplied during the period when the transistor is to be controlled to be off. By supplying this pixel operation timing signal, it is possible to set different operation modes for binning (including a mode in which binning is enabled or disabled: the operation modes will be described in the explanation of FIG. 5 below) for each pixel portion region control unit 200.

As described above, the number of such in-pixel drive signal generation circuits 1 is set according to the number of transfer gate transistors (TG) and reset transistors (RST) included in the pixel region 2. As described later, it is also possible to configure the reset transistors (RST) not to be controlled for each pixel region control unit 200, and in that case, the number of in-pixel drive signal generation circuits 1 is set according to the number of transfer gate transistors (TG).
The number of pixel areas 2 included in the pixel area control unit 200 is set to an arbitrary number.
1, the output signal from the image sensor 100 is output to the outside via an AD conversion circuit 30. At this time, a timing signal corresponding to the operation mode is supplied from the timing generation circuit 20 to the AD conversion circuit 30, and based on this, AD conversion processing and signal external output processing are performed.

The operation of the image sensor according to this embodiment will be described below with reference to FIGS.
During a period in which the row selection signals (TG(n), RT(n), SL(n)) are on, in the intra-pixel drive signal generation circuit 1, as shown in FIGS. 3A(a) and 3B, VDD is supplied to the source of the PMOS 11 and VSSTG (see FIG. 1) is supplied to the source of the NMOS 12.

In this state, when a pixel operation timing signal (TG1CTL to TG4CTL, RTCTL) having a sufficient amplitude to drive an inverter (consisting of a PMOS 11 and an NMOS 12) is supplied, the output gate drive signal (TG1_LOCAL to TG4_LOCAL, RT_LOCAL) is made to be an inverted state of the pixel operation timing signal, and becomes a signal having the amplitude of the on voltage and off voltage supplied by the row selection signal.
In addition, since the transition operation has a configuration as an inverter, the transition state of the pixel operation timing signal is changed to a signal state having a low delay and a steep edge.
Therefore, using this gate drive signal, it is possible to drive the gates of the transfer transistors TG1 to TG4 and the gate of the reset transistor RST in the pixel at high speed.

In addition, during the period when the row selection signal is off, as shown in Figures 3B (a) and (b), when the pixel operation timing signal is on the VDD side, the NMOS 12 is conductive, so the gate drive signal is fixed to the off voltage, and when the pixel operation timing signal is on the VSS side, both NMOS 12 and PMOS 11 are non-conductive, so the gate is not driven by the gate drive signal and the off voltage is maintained by resistor 13 connecting the source and drain of NMOS 12.

In this way, when the row in question is not selected, as shown in FIG. 3B, the gate drive signal is maintained at the off voltage regardless of whether the pixel operation timing signal is set to the VDD side or the VSS side, making it possible to drive only that particular row in the pixel array.
As mentioned above, resistor 13 is provided for the purpose of preventing the voltage at the corresponding node from fluctuating when the gate drive signal is not sent from the inverter section, and is an element with a high resistance value sufficient to achieve this purpose.

Furthermore, if the effects of parasitic capacitance and junction capacitance between the gate and source are minor and fluctuations in the voltage of the relevant node do not pose a problem, the resistor 13 can be omitted.
The same effect can be obtained by providing a capacitance (a capacitor or the like) instead of the resistance.

The high and low potentials of the gate drive signal, VGH and VGL, can be set to appropriate values capable of driving the corresponding in-pixel transistors TG1 to TG4, and are generally set to maximize pixel performance. However, VGH and VGL must be set so that the inverter operates properly and within a range where the through current does not cause problems for the inverter operation.

In other words, when the threshold voltage of the PMOS 11 is VTHP and the threshold voltage of the NMOS 12 is VTHN, it is desirable to simultaneously satisfy the following inequalities (1) to (4) in order for the inverter to operate properly. Here, the high voltage of the gate drive signal is VGH, and the low voltage of the gate drive signal is VGL.
VGH<VDD+VTHP (1)
VGH>VSS+VTHP (2)
VGL>VSS-VTHN (3)
VGL<VDD-VTHN (4)
In addition, it is desirable to supply a drive signal so that the transition of the input voltage VIN between VDD and VSS occurs in a sufficiently short time so that a shoot-through current does not affect the inverter operation.
In addition, by sharing the VGL with the pixel ground, it is possible to reduce the number of wirings.

In the image sensor of this embodiment, in a four-pixel shared pixel arrangement of two pixels vertically and two pixels horizontally, switching between reading out signals without binning and reading out signals with binning is performed based on binning process decision information. FIG. 4(A) shows each drive signal in a drive pattern in which signals are read out without binning, and FIG. 4(B) shows each drive signal in a drive pattern in which signals are read out with four-pixel binning.

These drive patterns each indicate pixel operation timing signals and gate drive signals during the period in which the nth row is selected when scanning a pixel group.
As is clear from a comparison between Figures 4(A) and (B), when binning is not performed, for each pixel, each time a gate drive signal RTCTL that drives the reset transistor RST is output, gate drive signals TG1CTL to TG4CTL that drive the transfer gate transistors TG1 to TG4 are output in sequence, whereas when 4-pixel binning is performed, for each pixel, after one pulse of the gate drive signal RTCTL that drives the reset transistor RST is output, a predetermined period is elapsed, and then the gate drive signals TG1CTL to TG4CTL that drive all of the transfer gate transistors TG1 to TG4 are output simultaneously.

Regarding the operation of the ADC, the processing period of one AD conversion is represented by a rectangular block, and the numbers indicate the corresponding pixel number (which corresponds to the numbering of the photoelectric conversion unit minus 20), with R indicating that the reset voltage is being processed and S indicating that the signal voltage after charge transfer is being processed.

As described above, in the operation mode in which four pixels are binned to read out signals, during the period in which a row is selected, a reset operation is performed once, the transfer gate transistors TG of all four pixels are turned ON, and the accumulated charges are then summed up and a charge transfer operation is performed once to read out the signal. In this way, by summing up and reading out the signals of the four pixels, it is possible to obtain four times the signal value, improving the S/N ratio.

In addition, since the AD conversion circuit only needs to perform one conversion operation on the reset voltage and one conversion operation on the signal voltage during this period, it is possible to use four times the time for AD conversion compared to when binning is not performed. By using this free time to perform multiple AD conversion operations on each voltage and taking the average value of these multiple voltage values, it is possible to further improve the S/N ratio.
In addition, when an oversampling type AD conversion circuit is used or when a multi-sampling circuit is present between the AD conversion circuit, the free time can be utilized in this manner to increase the number of samplings, thereby improving the S/N ratio.

On the other hand, when using 4-pixel binning as described above, it is possible to significantly improve the S/N ratio as described above, but on the other hand, there is a problem that the resolution decreases. For this reason, it is also possible to perform 2-pixel binning, which can improve the S/N ratio while preventing a significant decrease in resolution.

4C and 4D show drive signals when binning is performed on two horizontal pixels and when binning is performed on two vertical pixels, respectively.
When these two pixels are binned, the operation of reading out two of the four pixels is performed twice during the period in which row selection is performed, so that the signal charge can be doubled and the time that can be spent on AD conversion can also be doubled compared to when binning is not performed.
In addition, when binning is performed on two horizontal pixels, it is possible to suppress the effect of binning on the vertical resolution of the screen (resolution for horizontal stripe patterns), and when binning is performed on two vertical pixels, it is possible to suppress the effect of binning on the horizontal resolution of the screen (resolution for vertical stripe patterns).

In the above embodiment, a four-pixel sharing structure consisting of two vertical pixels and two horizontal pixels has been described as an example, but it is possible to obtain the same effect as the above embodiment by using other pixel sharing structures, such as a two-vertical pixel sharing structure consisting of only two vertical pixels, a two-horizontal pixel sharing structure consisting of only two horizontal pixels, or a two-diagonal pixel sharing structure consisting of only two diagonal pixels.

As shown in the ADC operation column in Fig. 4, each reset voltage and signal voltage are configured to be AD converted sequentially, and it is possible to obtain a signal value of each pixel from which noise components have been removed by calculating the difference between the AD conversion results of the corresponding reset voltage and signal voltage. Also, instead of performing AD conversion operations on both the reset voltage and the signal voltage, a CDS circuit that takes the difference in the analog domain may be provided to calculate the difference between the two, and AD conversion may be performed once on the result.
Similarly to the case of "four-pixel binning" shown in FIG. 4B, one AD conversion period (signal conversion period) in the "horizontal two-pixel binning" shown in FIG. 4C and one AD conversion period (signal conversion period) in the "vertical two-pixel binning" shown in FIG. 4D can be extended to twice the one AD conversion period (signal conversion period) in the "readout without binning" shown in FIG. 4A, and the surplus period obtained by this extension can be used to increase the number of samplings and perform multi-sampling processing, thereby making it possible to improve noise characteristics.

In this way, during the period when row selection is being performed, various operating modes can be set depending on the presence or absence of pixel binning and the combination of these. In addition, this operating mode can be set for each pixel region 2 that can be configured as a pixel sharing structure unit of at least 2 pixels x 2 pixels. The configuration for controlling such settings is, for example, the structure shown in Figure 5.

The imaging device shown in Fig. 5 is provided with an image analysis section 40 that receives an image signal from the imaging element 100A and analyzes the characteristics of the image to be formed. Based on the image signal from the imaging element 100A, the image analysis section 40 analyzes the brightness of each region of the image, the characteristics of spatial frequency, the arrangement tendency of regions with high spatial frequency, etc., to divide the screen into regions of a predetermined shape and select the optimal drive mode for each region. Region control information related to the selected drive mode information is output from the image analysis section 40 to the timing generation circuit 20A.
As shown in FIG. 5, pixel area control units 200A are arranged vertically and horizontally within a pixel array area (pixel area control unit) 300, and a row selection signal and a pixel operation timing signal are input to each pixel area control unit 200A as binning processing determination information.

The pixel operation timing signal is output directly from the timing generation circuit 20A, but the row selection signal is output from the row drive circuit 10A based also on the row number information output from the timing generation circuit 20A.
As in the pixel portion area control unit 200 described above, an intra-pixel drive signal generation circuit 1 and one or more pixel portion areas 2 are arranged within the pixel portion area control unit 200A, and this intra-pixel drive signal generation circuit 1 is configured to uniformly control whether or not to perform binning (and further control various operation modes related to binning) for all pixel portion areas 2 within each pixel portion area control unit 200A based on the row selection signal and the pixel operation timing signal.

In the figure, below the pixel area control unit 300A, an AD conversion circuit 30A corresponding to each pixel area control unit 200A is arranged, and is configured to perform AD conversion processing of the output signal from each pixel area control unit 200A. An image signal is output from the AD conversion circuit 30A to the image analysis unit 40, and the image analysis unit 40 performs a feedback operation in which the screen is divided into areas based on brightness information for each screen area obtained from the previous shooting frame, and the drive mode is changed for each area.

As described above, the image signal output from the AD conversion circuit 30A is output to the image analysis section 40, and is also output to the outside of the image sensor 100A (not shown).
The image analysis unit 40 may be provided inside or outside the imaging device.

(Modifications)
The intra-pixel drive signal generation circuit (binning process drive instruction unit) may be configured to have an inverter structure consisting of a pair of NMOS and PMOS as described in the above embodiment, but various other configurations may also be adopted.
For example, as shown in FIG. 6, for a pixel region 2' consisting of photoelectric conversion units 21' to 24' and four types of transistors (TG1 to TG4, RST, SF, SL), each in-pixel drive signal generation circuit 1' can be configured with five NMOS transistors 14A to 14E that function as ON/OFF switches for the gate drive signal.

Specifically, the output of each of the NMOS transistors 14A-D functions as a gate switch (TG_SW) for each of the transfer gate transistors TG1-4, and the NMOS transistor 14E functions as a gate switch (RT_SW) for the reset transistor RST.

The NMOS transistors 14A to 14D switch ON/OFF of the gate drive signal to the transfer gate transistors TG1 to TG4 based on the row selection signal TG(n) and the pixel operation timing signals TG1CTL to TG4CTL, and the NMOS transistor 14E switches ON/OFF of the gate drive signal to the reset transistor RST based on the row selection signal RT(n) and the pixel operation timing signal RTCTL.
The pixel operation timing signals TG1CTL to TG4CTL and RTCTL have polarities opposite to those of the pixel operation timing signals TG1CTL to TG4CTL and RTCTL shown in FIG.

That is, in this modified embodiment, the pixel operation timing signal is set to a high potential (VDD) during the period in which it is desired to turn on the transfer gate transistors TG1 to TG4 or the reset transistor RT, whereas in the embodiment shown in FIG. 1, the pixel operation timing signal is set to a low potential (VSS) during the period in which it is desired to turn on the transistors TG1 to TG4 or the reset transistor RT.
It is also possible to configure the polarity of this modified embodiment to be the same as that of the embodiment shown in FIG.

In addition, in this modified embodiment, the high potential of the pixel operation timing signals TG1CTL to TG4CTL and RTCTL is set to the voltage to be applied to the gates of the transfer gate transistors TG1 to 4 or the reset transistor RT when they are on, and the low potential of the pixel operation timing signals TG1CTL to TG4CTL and RTCTL is set to the voltage to be applied to the gates of the transfer gate transistors TG1 to 4 or the reset transistor RT when they are off.

The high potentials of the row selection signals TG(n) and RT(n) are set to a voltage higher than the high potential of the pixel operation timing signals TG1CTL to TG4CTL and RTCTL plus the threshold voltages of the gate switches of the transfer gate transistors TG1 to TG4 and the reset transistor RT, respectively. On the other hand, the low potentials of the row selection signals TG(n) and RT(n) are set to a voltage lower than the voltage to be applied when the transfer gate transistors TG1 to TG4 and the reset transistor RT are turned off plus the threshold voltages of the gate switches of the transfer gate transistors TG1 to TG4 and the reset transistor RT, respectively.

The in-pixel drive signal generating circuit 1' shown in FIG. 6 can reduce the number of transistors compared to the in-pixel drive signal generating circuit 1 shown in FIG. 2, and the space required for the in-pixel drive signal generating circuit 1' can be reduced, so the aperture ratio of the image sensor can be improved.

The imaging element of the present invention is not limited to the configuration of the above embodiment, and various other modifications are possible.
For example, in the above embodiment, the binning process drive instruction signal is a gate drive signal that drives the transfer gate transistor and the reset transistor, but the binning process drive instruction signal may be a gate drive signal that drives at least the transfer gate transistor, and it is also possible to adopt an embodiment in which a binning process drive instruction unit for the reset transistor is not provided. In such an embodiment in which a binning process drive instruction unit for the reset transistor is not provided, there is no need to control the reset transistor. Specifically, for example, a predetermined pulse may be input directly to the gate of the reset transistor from a row drive circuit (row drive circuit 10 shown in FIG. 1).

Here, the timing chart of the embodiment in which the reset transistor is configured to always perform the same operation without providing a binning process drive instruction unit is shown in FIG. 7 ((A) is readout without binning, (B) is 4-pixel binning readout, (C) is horizontal 2-pixel binning readout, and (D) is vertical 2-pixel binning readout). According to the timing chart shown in FIG. 7, the operation timing of the transfer gate transistor drive signal is changed to switch between binning and not binning, but the timing when the reset transistor turns ON is the same in the four modes (see the RT timing charts in FIG. 7 (A) to (D)). In this embodiment, the AD conversion period (signal conversion cycle) cannot be made as long as in the embodiment in which binning is performed, and the effect of reducing noise is weakened, but it is possible to improve the effect of improving the S/N ratio by signal addition during binning.

In addition, the binning process determination information input to the intra-pixel drive signal generation circuit may be information that is automatically generated based on the image signal from the imaging element, as in the above-described embodiment, or may be information that is manually input using a keyboard, joystick, or the like.
Furthermore, the configuration of the in-pixel drive signal generating circuit is not limited to that of the above embodiment.

In addition, since it is necessary to arrange transistors used in the in-pixel drive signal generation circuit for each control unit, it is desirable to select and set the size of the pixel section region appropriately in consideration of the trade-off between the desired size of the control unit and the area (aperture ratio) that is allowable for the in-pixel drive signal generation circuit due to the pixel pitch, the fineness of the manufacturing process, etc.
In the above embodiment, the charge is read out by line-sequential scanning in the row direction, but this direction may be the column direction. Furthermore, the scanning of the pixels is not limited to line-sequential scanning, and other scanning methods such as interlaced scanning may be used.

1, 1' In-pixel drive signal generating circuit 2, 2', 202, 302 Pixel area 10, 10A Row drive circuit 11 PMOS
12, 14A~E NMOS
13 Resistor 20, 20A Timing generation circuits 21 to 24, 21' to 24', 123, 321 to 324 Photoelectric conversion unit 30, 30A, 230 AD conversion circuit 40 Image analysis unit 100, 100A Imaging element 200, 200', 200A Pixel area control unit 300, 300B Pixel array area (pixel area control unit)
TG, TG1 to TG4 Transfer gate transistors
RST Reset transistor
SF Source follower amplifier transistor
SL Select transistor

Claims (8)

An image sensor in which a pixel group, in which a plurality of pixels each having a photoelectric conversion unit are arranged in an array, is divided into pixel portion regions each having a predetermined number of pixels, and charges accumulated in each of the pixels arranged in a predetermined direction in the pixel group are read out as a signal by driving the pixels,
a binning process drive instruction unit that outputs a binning process drive instruction signal that instructs whether or not to perform a binning process for each pixel section region control unit, the pixel section region being arranged one by one or a plurality of pixel section regions being arranged in the predetermined direction, based on binning process decision information relating to whether or not to perform a binning process for each pixel section region control unit ,
the predetermined direction is a row direction,
the binning process determination information is a row selection signal that is set to a high potential for either a selected row or a non-selected row and to a low potential for the other, and a pixel operation timing signal that is set to a high potential at one of on and off timings and to a low potential at the other timing for each gate of at least a transfer gate transistor in the pixel portion region,
The imaging device , wherein the binning process drive instruction signal is a gate drive signal for driving at least the transfer gate transistor . 2. The image sensor according to claim 1 , wherein the gate drive signal is a signal for turning on/off a gate for at least each of the transfer gate transistors provided for each of the photoelectric conversion units constituting the pixel region. 3. The image sensor according to claim 1 , wherein the binning process drive instruction section is provided for at least each of the transfer gate transistors constituting the pixel region. 4. The image sensor according to claim 3 , wherein the binning process drive instruction unit includes an inverter circuit, which is composed of a pair of an NMOS transistor and a PMOS transistor, for at least each of the transfer gate transistors constituting the pixel region. 4. The image sensor according to claim 3 , wherein the binning process drive instruction section includes one NMOS transistor or one PMOS transistor for at least each of the transfer gate transistors constituting the pixel section region. 6. The image sensor according to claim 1, wherein the at least one transfer gate transistor comprises a transfer gate transistor and a reset transistor. The imaging element according to any one of claims 1 to 6, characterized in that, for each of the pixel area control units , a signal conversion period by an AD conversion circuit provided in a signal output section is set to be longer when the binning process is performed than when the binning process is not performed. 8. The image pickup device according to claim 7 , wherein the number of sampling operations increases as the signal conversion period by said AD conversion circuit becomes longer.

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