JP7617801B2 - Phase locked loop, transmitter, receiver, and method for controlling phase locked loop - Google Patents

Description

This disclosure relates to a phase locked loop, a transmitter, a receiver, and a method for controlling a phase locked loop.

Transmitters that use digital modulation include a modulation section that performs quadrature amplitude modulation, an up-converter section that converts baseband signals into signals in the carrier frequency band, and a band pass filter (BPF) that suppresses unnecessary frequency components.

In digital modulation, as the modulated signal becomes more multi-valued, the constellation at the transmitter output becomes more likely to become distorted, resulting in degradation of communication quality. In particular, the modulation section that performs constellation mapping is susceptible to frequency fluctuations, phase fluctuations, and phase noise in the reference clock signal, which can easily lead to degradation of communication quality.

Therefore, it is necessary to use a phase locked loop (PLL) circuit to remove the frequency and phase fluctuations and noise components caused by the oscillator and clean up the clock signal. However, there is a problem in that the output signal frequency of the PLL circuit changes with the temperature change around the PLL circuit.

The PLL circuit disclosed in JP 2012-044545 A (Patent Document 1) includes a temperature compensation loop that compensates for the temperature characteristics of the voltage controlled oscillator (VCO) in addition to the main PLL loop. Specifically, the temperature compensation loop compares the control voltage generated by the main PLL loop with a reference voltage, and generates a temperature compensation voltage using a charge pump circuit and a temperature compensation loop filter based on the difference between the two. The oscillation frequency of the voltage controlled oscillator is then fine-tuned using this temperature compensation voltage.

JP 2012-044545 A

When a temperature compensation loop is provided as disclosed in the above-mentioned JP 2012-044545 A (Patent Document 1), depending on the time constant of the temperature compensation loop, the temperature compensation loop may compete with the main loop. As a result of the competition, the main loop of the PLL may lose lock, or the frequency of the output signal may fluctuate. As a result, it becomes difficult to ensure good communication conditions in a transmitter equipped with a PLL circuit.

This disclosure has been made in consideration of the above problems, and one of its objectives is to provide a phase-locked loop circuit that can stabilize the oscillation frequency even when the ambient temperature changes. Note that, although the above describes the problems of the conventional technology using a transmitter that uses digital modulation as an example, the technology of this disclosure can also be applied to other devices that use a PLL circuit.

The phase-locked loop circuit of one embodiment includes a voltage-controlled oscillator, a frequency divider, a phase comparator, a charge pump, a loop filter, and a control circuit. The voltage-controlled oscillator generates an output signal having a frequency according to a first control parameter and a first control voltage. The frequency divider divides the output signal of the voltage-controlled oscillator. The phase comparator detects a phase difference between a reference clock signal and the divided output signal. The charge pump outputs a current according to the detected phase difference. The loop filter generates a first control voltage based on the output current of the charge pump. The control circuit adjusts the first control parameter based on a temperature detected by a temperature sensor provided around the phase-locked loop circuit.

According to the above embodiment, the first control parameter is adjusted based on the temperature detected by the temperature sensor provided around the phase locked loop, thereby stabilizing the oscillation frequency even when the ambient temperature changes.

1 is a block diagram showing the overall configuration of a transmitter 1 according to a first embodiment. FIG. 2 is a diagram illustrating an example of the configuration of a loop filter in FIG. 1 . 10 is a diagram showing, in table form, an example of the relationship between the control parameters of the loop filter, the control signal of the variable resistor, and the control voltage of the variable capacitance. FIG. FIG. 2 is a diagram illustrating a configuration example of the voltage-controlled oscillator of FIG. 1 . 1 is a diagram showing, in table form, an example of the relationship between the control parameters of a voltage-controlled oscillator and the control voltage of a variable capacitance; 4 is a diagram showing the relationship between a control voltage output from a loop filter and an oscillation frequency of a voltage-controlled oscillator. FIG. 2 is a block diagram showing a configuration example of a temperature monitoring unit in FIG. 1 . 11A and 11B are diagrams illustrating an example of output of temperature range information corresponding to a change over time in the detected temperature of a temperature sensor. 11 is a diagram showing an example of output of temperature fluctuation information corresponding to a change over time in the temperature detected by a temperature sensor. FIG. 4 is a block diagram showing an example of the configuration of a PLL capture monitoring unit; 11 is a timing diagram showing an example of the operation of a PLL capture monitoring unit. FIG. 4 is a block diagram showing an example of the configuration of a parameter adjustment unit; FIG. 4 is a flowchart showing a control method of the PLL circuit. FIG. 11 is a block diagram showing the overall configuration of a transmitter 1A according to a second embodiment. FIG. 15 is a block diagram showing an example of the configuration of a parameter adjustment unit 33A in FIG. 14. FIG. 15 is a block diagram showing a configuration example of a frequency divider in FIG. 14 . FIG. 2 is a diagram showing, in table form, the relationship between the control parameters of the frequency divider and the frequency division ratio. 13 is a diagram showing the relationship between the control voltage output from the loop filter and the oscillation frequency of the voltage controlled oscillator in the PLL circuit of the second embodiment. FIG. 13 is a diagram illustrating a modified example of the reference clock generating circuit. 10 is a flowchart showing a control method of the PLL circuit according to the second embodiment. FIG. 11 is a block diagram showing the overall configuration of a transmitter 1B according to a third embodiment. 13 is a flowchart showing a control method of the PLL circuit according to the third embodiment. FIG. 13 is a diagram showing an example of a conversion table of control parameters of a voltage-controlled oscillator before and after updating; FIG. 13 is a block diagram showing the overall configuration of a transmitter 1C according to a fourth embodiment. 13 is a flowchart showing a control method of the PLL circuit according to the fourth embodiment. A block diagram showing the overall configuration of a receiver 2 of embodiment 5.

Each embodiment will be described in detail below with reference to the drawings. Note that the same or corresponding parts will be given the same reference symbols and their description will not be repeated.

Embodiment 1.
[Overall configuration of transmitter]
Fig. 1 is a block diagram showing an overall configuration of a transmitter 1 according to a first embodiment. The transmitter 1 receives a baseband signal BS, generates a modulated signal MS by modulating the received baseband signal BS, and outputs the generated modulated signal MS. As shown in Fig. 1, the transmitter 1 includes a transmission circuit 10, a control circuit 30 for controlling a PLL circuit 11, a temperature sensor 34, and a memory 35. In the present disclosure, the control circuit 30 may be one of the components of the PLL circuit 11.

The transmission circuit 10 includes a reference clock generation circuit 12, a PLL circuit 11, and a modulation circuit 13. The reference clock generation circuit 12 generates a reference clock CLKref used by the PLL circuit 11. For example, a temperature compensated crystal oscillator (TCXO) is used as the reference clock generation circuit 12.

The PLL circuit 11 receives a reference clock CLKref and performs processing for cleaning up the received reference clock CLKref. As shown in FIG. 1, the PLL circuit 11 includes a phase comparator (PFD: Phase Frequency Detector) 20, a charge pump (CP: Charge Pump) 21, a loop filter (Loop Filter) 22, a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) 23, and a frequency divider (DIV: Divider) 24.

Specifically, the phase comparator 20 detects the phase difference between the reference clock CLKref and the divided clock CLKdiv output from the frequency divider 24, and outputs a voltage according to the phase difference. The charge pump 21 converts the voltage according to the phase difference output from the phase comparator 20 into a current. The loop filter 22 converts the output current of the charge pump 21 into a control voltage for the voltage-controlled oscillator 23, and removes high-frequency components. The voltage-controlled oscillator 23 is an oscillator whose oscillation frequency changes according to the control voltage output from the loop filter 22. The frequency divider 24 divides the output clock CLKout output from the voltage-controlled oscillator 23.

In the PLL circuit 11 configured as above, the frequency characteristics of the loop filter 22 change according to the control parameter P_LF output from the control circuit 30. Also, the oscillation frequency of the voltage-controlled oscillator 23 changes according to the control parameter P_VCO output from the control circuit 30. A more detailed configuration example and operation of the loop filter 22 will be described later with reference to Figures 2 and 3. Also, a more detailed configuration example and operation of the voltage-controlled oscillator 23 will be described later with reference to Figures 4 to 6.

The modulation circuit 13 receives the baseband signal BS and the output clock CLKout of the PLL circuit 11, and modulates the baseband signal BS using the output clock CLKout as a carrier signal. The modulation circuit 13 generates a modulated signal MS by performing digital modulation such as amplitude shift keying (ASK), phase shift keying (PSK), frequency shift keying (FSK), and quadrature amplitude modulation (QAM).

The control circuit 30 includes a temperature monitoring unit 31, a PLL capture monitoring unit 32, and a parameter adjustment unit 33.

The temperature monitoring unit 31 determines the temperature range that includes the detected temperature Temp and the amount of time change of the detected temperature Temp based on information on the detected temperature Temp from the temperature sensor 34 that detects the temperature around the PLL circuit 11.The PLL capture monitoring unit 32 determines the PLL capture time at the start of operation of the PLL circuit 11 (i.e., the time until the reference clock CLKref and the divided clock CLKdiv are synchronized) based on the reference clock CLKref and the divided clock CLKdiv.The parameter adjustment unit 33 sets the control parameters P_LF and P_VCO of the loop filter 22 and the voltage controlled oscillator 23 based on the determination results of the temperature monitoring unit 31 and the PLL capture monitoring unit 32.The set control parameters P_LF and P_VCO are output to the PLL circuit 11 and stored in the memory 35.

The control circuit 30 may be configured based on a computer including a CPU (Central Processing Unit) and memory, may be configured using an FPGA (Field Programmable Gate Array), or may be configured by a dedicated circuit such as an ASIC (Application Specific Integrated Circuit). Alternatively, the control circuit 30 may be configured by combining at least two of a CPU, an FPGA, and an ASIC. For example, a non-volatile memory such as a flash memory is used as the memory 35.

A more detailed configuration and operation of the control circuit 30 will be described later with reference to Figures 7 to 13. The control circuit 30 may be one of the components of the PLL circuit 11.

[Example of loop filter configuration and operation]
Fig. 2 is a diagram showing a configuration example of the loop filter of Fig. 1. Referring to Fig. 2, the loop filter 22 includes a variable resistor 40, variable capacitances 44 and 45, and a conversion circuit 46. Variable capacitance diodes (also called varactors) can be used as the variable capacitances 44 and 45. As an example, the variable resistor 40 may be configured such that one of resistance elements 41 and 42 connected in parallel as shown in Fig. 2 is separated by a switch 43.

The variable resistor 40 and the variable capacitance 44 are connected in series between a signal line 47 for supplying a control voltage to the voltage-controlled oscillator 23 and ground GND. The variable capacitance 45 is connected in parallel with the entire series connection of the variable resistor 40 and the variable capacitance 44.

The conversion circuit 46 generates a control signal SW_LF for the switch 43 of the variable resistor 40, a control voltage V_LF1 for the variable capacitance 44, and a control voltage V_LF2 for the variable capacitance 45 based on the control parameter P_LF received from the control circuit 30. The on/off of the switch 43 is controlled by the control signal SW_LF, the capacitance value of the variable capacitance 44 is controlled by the control voltage V_LF1, and the capacitance value of the variable capacitance 45 is controlled by the control voltage V_LF2. The conversion circuit 46 stores a conversion table (also called a parameter table) that indicates the correspondence between the control parameter P_LF and the control signal SW_LF and the control voltages V_LF1 and V_LF2.

Figure 3 is a diagram showing, in table form, an example of the relationship between the control parameters of the loop filter and the control signals of the variable resistor and the control voltages of the variable capacitance. In Figure 3, the on (ON) and off (OFF) states of the switch 43, the control voltage V_LF1 [V] of the variable capacitance 44, and the control voltage V_LF2 [V] of the variable capacitance 45, which correspond respectively to the control parameters P_LF1 to P_LF4 of the loop filter 22, are shown. In the example of Figure 3, the cutoff frequency of the loop filter 22 changes from fc to 4fc [Hz] depending on the set values of these control signals and control voltages.

To remove higher-frequency noise, the number of variable resistors and the number of variable capacitances may be increased from that shown in FIG. 2. Also, switched capacitors may be used instead of the variable capacitances 44 and 45.

[Example of the configuration and operation of a voltage-controlled oscillator]
Fig. 4 is a diagram showing an example of the configuration of the voltage-controlled oscillator of Fig. 1. Referring to Fig. 4, the voltage-controlled oscillator 23 includes variable capacitances 50 and 51, an inductor 52, and a conversion circuit 53. The variable capacitances 50 and 51 and the inductor 52 are connected in parallel with each other. Variable capacitance diodes can be used as the variable capacitances 50 and 51.

The conversion circuit 53 generates a control voltage V_VCO for controlling the capacitance value of the variable capacitance 50 based on the control parameter P_VCO received from the control circuit 30. The capacitance value of the variable capacitance 51 is controlled by the control voltage output from the loop filter 22. The oscillation frequency of the voltage-controlled oscillator 23 is adjusted based on the capacitance values of the variable capacitances 50 and 51. The conversion circuit 53 stores a conversion table indicating the correspondence between the control parameter P_VCO and the control voltage V_VCO.

Figure 5 is a diagram showing, in table form, an example of the relationship between the control parameters of the voltage-controlled oscillator and the control voltage of the variable capacitance. In Figure 5, the control voltage V_VCO [V] of the variable capacitance 50 corresponding to each of the control parameters P_VCO1 to P_VCO4 of the voltage-controlled oscillator 23 is shown. In the example of Figure 5, the upper limit value of the oscillation frequency of the voltage-controlled oscillator 23 changes from fmax to 4fmax [Hz] depending on the control voltage V_VCO of the variable capacitance 50.

Figure 6 is a diagram showing the relationship between the control voltage output from the loop filter and the oscillation frequency of the voltage-controlled oscillator. As shown in Figure 6, the control voltage output from the loop filter 22 varies between a lower limit value V1 and an upper limit value V2. Specifically, when the output voltage of the loop filter 22 is the lower limit value V1, the oscillation frequency of the voltage-controlled oscillator 23 is the lower limit value, and when the output voltage of the loop filter 22 is the upper limit value V2, the oscillation frequency of the voltage-controlled oscillator 23 is the upper limit value.

The oscillation frequency of the voltage-controlled oscillator 23 also changes depending on the control parameters P_VCO1 to P_VCO4 output from the control circuit 30. In the example of FIG. 6, when the control parameter is P_VCO1, the upper limit of the oscillation frequency corresponding to the upper limit V2 of the output voltage of the loop filter 22 is fmax. When the control parameter is P_VCO4, the upper limit of the oscillation frequency corresponding to the upper limit V2 of the output voltage of the loop filter 22 is 4fmax.

In the configuration example of the voltage-controlled oscillator 23 shown in FIG. 4, a tank-type configuration using an LC resonant circuit is shown. Alternatively, the voltage-controlled oscillator may be configured based on an oscillator circuit of another configuration, such as a Colpitts type.

[Example of configuration and operation of control circuit]
Next, a detailed description will be given of a configuration example and operation of the control circuit 30. As described in Fig. 1, the control circuit 30 receives a signal indicating the detected temperature Temp from the temperature sensor 34, and receives the reference clock CLKref and the divided clock CLKdiv from the PLL circuit 11. Based on these received signals, the control circuit 30 sets control parameters P_LF and P_VCO for controlling the loop filter 22 and the voltage controlled oscillator 23, and outputs them to the PLL circuit 11. Below, a description will be given of configuration examples and operations of the temperature monitoring unit 31, the PLL capture monitoring unit 32, and the parameter adjustment unit 33 that constitute the control circuit 30.

(Configuration example and operation of temperature monitoring unit)
Fig. 7 is a block diagram showing an example of the configuration of the temperature monitoring unit shown in Fig. 1. Referring to Fig. 7, temperature monitoring unit 31 includes a temperature range determination unit 56, a delay circuit 55, and a temperature fluctuation determination unit 57.

The temperature range determination unit 56 determines which of the multiple temperature ranges includes the detected temperature Temp based on the information on the detected temperature Temp received from the temperature sensor 34. The temperature range determination unit 56 outputs information D_temp (hereinafter referred to as temperature range information D_temp) indicating the temperature range that includes the detected temperature Temp. How the multiple temperature ranges are defined can be set arbitrarily, and it is desirable to change the temperature range appropriately depending on the configuration of the transmitter and the usage environment.

The temperature fluctuation determination unit 57 determines the amount of time fluctuation of the detected temperature Temp based on the difference between the current detected temperature Temp received from the temperature sensor 34 and the previous detected temperature Temp that has passed through the delay circuit 55. Specifically, the temperature fluctuation determination unit 57 determines temperature fluctuation information D_deltatemp, which indicates which of multiple fluctuation ranges the amount of fluctuation of the detected temperature Temp falls within. How the multiple temperature fluctuation ranges are defined can be set arbitrarily, and it is desirable to change the temperature fluctuation range as appropriate depending on the configuration of the transmitter and the usage environment.

Figure 8 is a diagram showing an example of temperature range information output according to the change over time in the detected temperature of the temperature sensor. In Figure 8, the temperature range information D_temp when the temperature range of the detected temperature Temp is 30°C to 40°C is Dt1. The temperature range information D_temp when the temperature range of the detected temperature Temp is 20°C to 30°C is Dt2. The temperature range information D_temp when the temperature range of the detected temperature Temp is 10°C to 20°C is Dt3.

At times T0 and T1 in FIG. 8, the detected temperature Temp is in the range from 30°C to 40°C, so the temperature range determination unit 56 outputs Dt1 as the temperature range information D_temp. At times T2, T3, and T4, the detected temperature Temp is in the range from 20°C to 30°C, so the temperature range determination unit 56 outputs Dt2 as the temperature range information D_temp. At times T5 and T6, the detected temperature Temp is in the range from 10°C to 20°C, so the temperature range determination unit 56 outputs Dt3 as the temperature range information D_temp.

As described above, by setting parameters according to the temperature range, the number of parameters to be stored can be reduced, and memory storage capacity can be reduced.

Figure 9 is a diagram showing an example of the output of temperature fluctuation information according to the change over time in the detected temperature of the temperature sensor. In Figure 9, the temperature fluctuation information D_deltatemp when the temperature fluctuation amount of the detected temperature Temp is from 0°C to 10°C is set to Ddt0. The temperature fluctuation information D_deltatemp when the temperature fluctuation amount of the detected temperature Temp is from 10°C to 20°C is set to Ddt1. The temperature fluctuation information D_deltatemp when the temperature fluctuation amount of the detected temperature Temp is from 20°C to 30°C is set to Ddt2.

The temperature fluctuation from time T0 to time T1 in Figure 9 is less than 10°C (temperature range is 40°C to 50°C), so at time T1 the temperature fluctuation determination unit 57 outputs Ddt0 as the temperature fluctuation information D_deltatemp. Similarly, the temperature fluctuation at times T2 and T3 is stable at less than 10°C, so the temperature fluctuation determination unit 57 outputs Ddt0 as the temperature fluctuation information D_deltatemp.

The temperature changes significantly between time T3 and time T4, with the temperature fluctuation amount ΔT being greater than or equal to 20°C and less than 30°C. Therefore, at time T4, the temperature fluctuation determination unit 57 outputs Ddt2 as the temperature fluctuation information D_deltatemp. At the next times T5 and T6, the temperature fluctuation amount is stable at less than 10°C (temperature range is 20°C to 30°C), so the temperature fluctuation determination unit 57 again outputs Ddt0 as the temperature fluctuation information D_deltatemp.

(Configuration example and operation of PLL capture monitoring unit)
The PLL capture monitor 32 receives the reference clock CLKref and the divided clock CLKdiv from the reference clock generating circuit 12 and the PLL circuit 11 in the transmission circuit 10. Based on these clock signals, the PLL capture monitor 32 detects the time required for the reference clock CLKref and the divided clock CLKdiv to be synchronized when the PLL circuit 11 starts operating, that is, the PLL capture time. The PLL capture monitor 32 outputs PLL capture information D_locktime as information representing the PLL capture time.

Figure 10 is a block diagram showing an example of the configuration of the PLL capture monitoring unit. Referring to Figure 10, the PLL capture monitoring unit 32 includes JK flip-flops (JKFF1, JKFF2) 61, 62, a NAND circuit 63, a synchronization determination unit 64, and a counter 65.

As shown in FIG. 10, the J terminals of the JK flip-flops 61 and 62 are fixed to a high level. The K terminals of the JK flip-flops 61 and 62 are fixed to ground potential (i.e., a low level). The reference clock CLKref is input to the clock terminal of the JK flip-flop 61, and the divided clock CLKdiv is input to the clock terminal of the JK flip-flop 62. The Q outputs of the JK flip-flops 61 and 62 change at the falling edge of the input clock signal. When the input to the CLR terminals of the JK flip-flops 61 and 62 is at a low level, the Q outputs are reset to a low level.

The NAND circuit 63 performs a NAND operation on the output FFOUT1 of the Q terminal of the JK flip-flop 61 and the output FFOUT2 of the Q terminal of the JK flip-flop 62, and inputs the result of the NAND operation to the CLR terminals of the JK flip-flops 61 and 62.

The synchronization judgment unit 64 measures the period during which the output of the Q terminal of the JK flip-flop 61 is at a high level when the phase of the reference clock CLKref leads the phase of the divided clock CLKdiv. On the other hand, the synchronization judgment unit 64 measures the period during which the output of the Q terminal of the JK flip-flop 62 is at a high level when the phase of the divided clock CLKdiv leads the phase of the reference clock CLKref. In either case, when the period during which the output of the Q terminal is at a high level falls below a threshold, the synchronization judgment unit 64 changes the output PLL_LOCK from a low level to a high level.

The PLL capture monitoring unit 32 counts from the start of the capture operation of the PLL circuit 11 until the output PLL_LOCK of the synchronization determination unit 64 goes high. The count result of the counter 65 is output to the parameter adjustment unit 33 as PLL capture information D_locktime, which indicates the PLL capture time.

Figure 11 is a timing diagram showing an example of the operation of the PLL capture monitoring unit. The operation of the PLL capture monitoring unit 32 will be further described below with reference to Figure 11.

At time T10 in FIG. 11, the capture operation of the PLL circuit 11 starts, and the count of the counter 65 starts. FIG. 11 shows a case where the phase of the reference clock CLKref leads the phase of the divided clock CLKdiv.

At time T11, the reference clock CLKref falls, causing the Q terminal output FFOUT1 of the JK flip-flop 61 to switch from low to high.

At time T12, the divided clock CLKdiv falls, causing the Q terminal output FFOUT2 of the JK flip-flop 62 to switch from low to high. However, this causes the output of the NAND circuit 63 to go low, so that the Q terminal outputs FFOUT1 and FFOUT2 of the JK flip-flops 61 and 62 both return to low.

The synchronization determination unit 64 detects the period Td1 during which the Q terminal output of the JK flip-flop 61 is at a high level. This period Td1 corresponds to the phase difference between the reference clock CLKref and the divided clock CLKdiv. Because the detected period Td1 exceeds the threshold, the synchronization determination unit 64 does not change the output PLL_LOCK and keeps it at a low level.

At the next time T13, the reference clock CLKref falls, causing the Q terminal output FFOUT1 of the JK flip-flop 61 to switch from low to high.

At the next time T14, the divided clock CLKdiv falls, causing the Q terminal output FFOUT2 of the JK flip-flop 62 to switch from low to high. However, this causes the output of the NAND circuit 63 to go low, so that the Q terminal outputs FFOUT1 and FFOUT2 of the JK flip-flops 61 and 62 both return to low.

The synchronization determination unit 64 detects the period Td2 during which the Q terminal output of the JK flip-flop 61 is at a high level. Because the detected period Td2 is equal to or less than the threshold, the synchronization determination unit 64 changes the output PLL_LOCK from a low level to a high level. This causes the counter 65 to stop counting up.

(Example of configuration and operation of parameter adjustment unit)
The parameter adjustment unit 33 receives the temperature range information D_temp and the temperature fluctuation information D_deltatemp from the temperature monitoring unit 31, and receives the PLL capture information D_locktime from the PLL capture monitoring unit 32. The parameter adjustment unit 33 sets the control parameters P_LF and P_VCO of the loop filter 22 and the voltage controlled oscillator 23 based on this information, and outputs them to the PLL circuit 11.

FIG. 12 is a block diagram showing an example of the configuration of the parameter adjustment unit. Referring to FIG. 12, the parameter adjustment unit 33 includes parameter update determination units 70 and 72 and selectors 71 and 73.

The parameter update determination unit 70 determines whether or not the control parameter P_VCO that controls the voltage-controlled oscillator 23 needs to be changed based on the temperature range information D_temp and the temperature fluctuation information D_deltatemp. For example, the parameter update determination unit 70 determines that the control parameter P_VCO needs to be changed when the temperature fluctuation amount is so large that it exceeds the threshold value, or when the temperature range of the temperature Temp detected by the temperature sensor 34 is equal to or greater than the threshold temperature even if the temperature fluctuation amount is not large. In this case, the parameter update determination unit 70 selects a setting value corresponding to the temperature range information D_temp and the temperature fluctuation information D_deltatemp from among the multiple setting values P_VCO1 to P_VCON of the control parameter by the selector 71. The selector 71 outputs the selected setting value P_VCO* to the PLL circuit 11.

Similarly, the parameter update determination unit 72 determines whether or not the control parameter P_LF that controls the loop filter 22 needs to be changed based on the PLL capture information D_locktime. If the parameter update determination unit 72 determines that the control parameter P_LF needs to be updated, the selector 73 selects a setting value corresponding to the PLL capture information D_locktime from among the multiple setting values P_LF1 to P_LFN of the control parameter. The selector 73 outputs the selected setting value P_LF* to the PLL circuit 11.

[Processing flow of control circuit]
13 is a flow chart showing a method for controlling the PLL circuit. The process flow in the control circuit 30 described above will be summarized below with reference to FIG.

The process flow in FIG. 13 begins with the start of the PLL circuit 11. In step S100, the control circuit 30 determines whether the capture operation of the PLL circuit 11 is the first time.

If the PLL capture operation is not the first time (NO in step S100), this is the case when the PLL is out of sync due to a temporary shutdown of the transmitter 1 or the transmission circuit 10. In this case, the time until the operation of the PLL circuit 11 stabilizes can be shortened by reusing the parameters from the previous PLL capture operation. That is, in step S110, the parameter adjustment unit 33 of the control circuit 30 reads out the control parameters P_LF and P_VCO of the loop filter 22 and the voltage controlled oscillator 23 from the memory 35 at the time of the previous capture. In the next step S120, the parameter adjustment unit 33 sets the control parameter P_LF of the loop filter 22. Furthermore, in the next step S160, the parameter adjustment unit 33 sets the control parameter P_VCO of the voltage controlled oscillator 23 for the first time (#1).

On the other hand, if the PLL capture operation is the first time (YES in step S100), in step S130, the parameter adjustment unit 33 acquires PLL capture information D_locktime from the PLL capture monitoring unit 32. In the next step S140, the parameter adjustment unit 33 sets the control parameter P_LF of the loop filter 22 based on the acquired PLL capture information D_locktime, and stores the set value in the memory 35. Furthermore, in the next step S150, the parameter adjustment unit 33 reads the temperature range information D_temp and the temperature fluctuation information D_deltatemp from the temperature monitoring unit 31. In the next step S160, the parameter adjustment unit 33 sets the control parameter P_VCO of the voltage controlled oscillator 23 for the first time (#1) based on the acquired temperature range information D_temp and temperature fluctuation information D_deltatemp, and stores the set value in the memory 35.

The following steps S170 to S200 are executed repeatedly. In this repeat loop, the determination of temperature fluctuation takes priority. That is, in step S170, the parameter adjustment unit 33 reads the temperature range information D_temp and the temperature fluctuation information D_deltatemp from the temperature monitoring unit 31. In the next step S180, the parameter adjustment unit 33 determines whether the temperature fluctuation amount is large enough to exceed the threshold value. If the temperature fluctuation amount is large (YES in step S180), the parameter adjustment unit 33 proceeds to step S200. In step S200, the parameter adjustment unit 33 sets the control parameter P_VCO of the voltage controlled oscillator 23 for the second and subsequent times (#2, #3, ...) based on the temperature range information D_temp and the temperature fluctuation information D_deltatemp, and stores the set value in the memory 35.

On the other hand, even if the temperature change amount is not large enough to exceed the threshold value (NO in step S180), if the temperature range of the detected temperature Temp of the temperature sensor 34 exceeds the threshold value (YES in step S190), the parameter adjustment unit 33 proceeds to the above-mentioned step S200. Thereafter, the processing from step S170 onwards is repeated.

The reason that temperature fluctuation judgment is prioritized in this way is that when a sudden temperature fluctuation occurs, the fluctuation in frequency of the output clock CLKout of the PLL circuit 11 becomes larger than when the temperature fluctuation occurs gradually, and as a result, there is a high possibility that the PLL circuit 11 will lose lock.

[Effects of the First Embodiment]
The PLL circuit 11 of the first embodiment is configured so that the frequency characteristics of the loop filter 22 and the oscillation frequency of the voltage controlled oscillator 23 can be changed. The oscillation frequency of the voltage controlled oscillator 23 is adjusted according to the detected temperature Temp around the PLL circuit 11. This makes it possible to stabilize the oscillation frequency of the PLL circuit 11 even when the ambient temperature changes. The frequency characteristics of the loop filter 22 are adjusted based on the PLL capture time. Furthermore, by using the PLL circuit 11 configured as described above in a transmitter, a good communication state can be achieved.

Embodiment 2.
In the second embodiment, a case in which the division ratio of the frequency divider 24 is controlled based on the control parameter P_DIV will be described with reference to FIGS.

[Overall configuration of transmitter]
Fig. 14 is a block diagram showing the overall configuration of a transmitter 1A according to embodiment 2. Parameter adjustment unit 33A in Fig. 14 differs from parameter adjustment unit 33 in Fig. 1 in that it outputs control parameters P_LF and P_VCO based on PLL capture information D_locktime, temperature range information D_temp, and temperature fluctuation information D_deltatemp, and further outputs a control parameter P_DIV.

Furthermore, the divider 24A in FIG. 14 differs from the divider 24 in FIG. 1 in that the oscillation frequency can be changed based on the control parameter P_DIV. Since the other points in FIG. 14 are the same as those in FIG. 1, the same reference characters are used for the same or corresponding parts and the description will not be repeated.

[Example of configuration and operation of parameter adjustment unit]
Fig. 15 is a block diagram showing an example of the configuration of parameter adjustment unit 33A of Fig. 14. Parameter adjustment unit 33A of Fig. 15 differs from parameter adjustment unit 33 of Fig. 12 in that it further includes a selector 74.

The parameter update determination unit 70 determines whether or not it is necessary to change the control parameter P_DIV of the frequency division ratio of the frequency divider 24 in order to suppress fluctuations in the frequency of the output signal of the PLL circuit 11, based on the temperature range information D_temp and the temperature fluctuation information D_deltatemp. Then, if it is determined that it is necessary to change the control parameter P_DIV, the selector 74 outputs the setting value P_DIV* selected by the parameter update determination unit 70 from the multiple setting values P_DIV1 to P_DIVM of the control parameter to the PLL circuit 11. Since the other points in FIG. 15 are the same as those in FIG. 12, the same reference characters are used for the same or corresponding parts, and the description will not be repeated.

[Example of frequency divider configuration and operation]
Fig. 16 is a block diagram showing an example of the configuration of the frequency divider of Fig. 14. Referring to Fig. 16, frequency divider 24A includes a prescaler 80, counters 81 and 82, and a conversion circuit 83. Frequency divider 24A of Fig. 16 is a pulse swallow type frequency divider. The upper limit values of the count values of counters 81 and 82 are A and N, respectively.

First, the division ratio of the prescaler 80 is set to P+1, and the counters 81 and 82 start counting. When the count value of the counter 81 reaches the upper limit value A, the division ratio of the prescaler 80 is switched to P, and the remaining N-A counts are counted. Therefore, the division ratio Nt is expressed as follows:
Nt=(P+1)・A+P・(NA)=N・P+A…(1)
It is expressed as:

The conversion circuit 83 outputs the upper limit values A and N of the counters 81 and 82 that correspond to the control parameter P_DIV based on the conversion table. By using the control parameter P_DIV, the division ratio of the divider 24A can be set more precisely.

Figure 17 is a diagram showing in table form the relationship between the control parameters of the divider and the division ratio. The division ratio Nt is set according to the control parameter P_DIV of the divider 24A, and the upper limit of the oscillation frequency of the PLL circuit 11 is determined according to the division ratio Nt. In the case of Figure 17, the upper limit of the oscillation frequency corresponding to the control parameter setting value P_DIV1 is fmax, and as the control parameter setting value changes from P_DIV1 to P_DIV2, P_DIV3, P_DIV4, ... the upper limit of the oscillation frequency is increased by 1 Hz.

Figure 18 is a diagram showing the relationship between the control voltage output from the loop filter and the oscillation frequency of the voltage-controlled oscillator in the PLL circuit of embodiment 2. The graph in Figure 18 corresponds to the graph in Figure 6.

As explained in FIG. 6, the control voltage output from the loop filter 22 varies between a lower limit V1 and an upper limit V2. When the output voltage of the loop filter 22 is the upper limit V2, the oscillation frequency of the voltage-controlled oscillator 23 is at the upper limit. By changing the set value of the control parameter of the voltage-controlled oscillator 23 from P_VCO1 to P_VCO2, the upper limit of the oscillation frequency of the voltage-controlled oscillator 23 can be changed from fmax to 2·fmax. Furthermore, by using the control parameter P_DIV of the frequency divider 24A in combination, the oscillation frequency of the voltage-controlled oscillator 23 can be finely adjusted more precisely. That is, as shown in FIG. 18, the upper limit of the oscillation frequency can be finely set between fmax and 2fmax.

The above describes the case where the division ratio of divider 24A is an integer, but a fractional division type divider may be used to set the division ratio more precisely.

[Modification of the Reference Clock Generation Circuit]
If the division ratio of the frequency divider 24A is programmable, the generated frequency of the reference clock generating circuit 12 may be made changeable.

Figure 19 is a diagram showing a modified example of a reference clock generation circuit. In Figure 19, two reference clock generation circuits (1, 2) 14_1 and 14_2 with different oscillation frequencies are provided. Of the reference clock CLKref1 generated by the reference clock generation circuit 14_1 and the reference clock CLKref2 generated by the reference clock generation circuit 14_2, the reference clock selected by the switch (SW) 15 is output to the PLL circuit 11.

For example, the clock frequency of the reference clock generation circuit 14_1 is set to 10 MHz, and the clock frequency of the reference clock generation circuit 14_2 is set to 15 MHz. It is desirable to set the clock frequency so that it does not match the operating clock frequency of the peripheral devices of the transmitter 1. If the operating clock frequency of the peripheral devices of the transmitter 1 is 10 MHz, and the clock frequency of the reference clock generation circuit is also set to 10 MHz, the PLL circuit 11 will be easily affected by electromagnetic noise. Therefore, the clock frequency of the reference clock generation circuit is switched to 15 Hz. In this case, by changing the control parameter P_DIV of the frequency divider 24A, the desired output clock CLKout can be obtained without changing the control parameters P_LF, P_VCO of the loop filter 22 and the voltage controlled oscillator 23.

[Processing flow of control circuit]
Fig. 20 is a flowchart showing a method for controlling a PLL circuit according to embodiment 2. The flowchart in Fig. 20 differs from the flowchart in Fig. 13 in that steps S110 and S160 are changed to steps S110A and S160A, respectively, and step S210 is added.

Specifically, in step S110A, the parameter adjustment unit 33 reads from the memory 35 the control parameters P_LF and P_VCO of the loop filter 22 and the voltage controlled oscillator 23 at the time of the previous capture, as well as the control parameter P_DIV of the frequency divider 24A.

In step S160A, the parameter adjustment unit 33 sets the control parameter P_VCO of the voltage controlled oscillator 23 for the first time (#1) and the control parameter P_DIV of the frequency divider 24A based on the acquired temperature range information D_temp and temperature fluctuation information D_deltatemp, and stores the set values in the memory 35.

Furthermore, even if the temperature fluctuation amount is not large enough to exceed the threshold value (NO in step S180), if the temperature range of the detected temperature Temp of the temperature sensor 34 exceeds the threshold value (YES in step S190), the parameter adjustment unit 33 proceeds to step S210. In step S210, the parameter adjustment unit 33 sets the control parameter P_DIV of the frequency divider 24A for the second and subsequent times (#2, #3, ...) based on the temperature range information D_temp. This allows the oscillation frequency of the voltage controlled oscillator 23 to be adjusted more finely.

The other steps in Figure 20 are similar to those in Figure 13, so the same or corresponding steps are given the same reference symbols and will not be described repeatedly.

[Effects of the second embodiment]
The PLL circuit 11 of the second embodiment is configured to change the division ratio of the frequency divider 24A. This allows the oscillation frequency of the voltage controlled oscillator 23 to be more finely adjusted in response to changes in the temperature around the PLL circuit 11. Furthermore, by making the division ratio of the frequency divider 24A programmable, it is possible to generate output clocks CLKout with desired frequencies for a plurality of reference clock generating circuits with different oscillation frequencies.

Embodiment 3.
In the third embodiment, a case where a conversion table indicating the correspondence relationship between the setting value of the control parameter P_VCO of the voltage controlled oscillator 23 and the setting value V_VCO of the control voltage is changed will be described with reference to FIGS.

[Overall configuration of transmitter and operation of parameter update unit]
Fig. 21 is a block diagram showing the overall configuration of a transmitter 1B according to embodiment 3. The control circuit 30 in Fig. 21 differs from the control circuit 30 in Fig. 14 in that a parameter update unit 36 is further provided.

When there is a setting value that is infrequently used and rarely used among the multiple setting values of the control parameters P_VCO and P_DIV, the parameter update unit 36 changes the conversion table that represents the correspondence between the multiple setting values of the control parameter P_VCO and the value of the control voltage V_VCO or the conversion table that represents the correspondence between the setting value of the control parameter P_DIV and the counter upper limit values A and N. The changed conversion table is stored in the conversion circuit 53 of the voltage controlled oscillator 23 of the PLL circuit 11 or the conversion circuit 83 of the divider 24A. This allows the change step of the control voltage V_VCO or the change step of the upper limit values of the counters 81 and 82 to be set more finely, thereby improving the controllability of the oscillation frequency of the voltage controlled oscillator 23.

Other aspects of Figure 21 are similar to those of Figure 14, so the same or corresponding parts are given the same reference symbols and will not be described repeatedly.

[Processing flow of control circuit]
Fig. 22 is a flowchart showing a method for controlling a PLL circuit according to embodiment 3. The flowchart in Fig. 22 differs from the flowchart in Fig. 20 in that it further includes steps S220 to S240.

Referring to FIG. 22, after changing the setting of the control parameter P_VCO of the voltage-controlled oscillator 23 (step S200) or the control parameter P_DIV of the frequency divider 24A (step S210), the parameter update unit 36 counts the number of times the setting value of the control parameter is updated (step S220). If the count value is equal to or less than the threshold value (K) (YES in step S230), the parameter update unit 36 updates the conversion table of the control parameter (step S240). The updated conversion table is transmitted to the conversion circuit 53 of the voltage-controlled oscillator 23 of the PLL circuit 11 or the conversion circuit 83 of the frequency divider 24A.

Figure 23 shows an example of a conversion table of control parameters of a voltage-controlled oscillator before and after updating. In the conversion table before updating shown in Figure 23 (A), the value of the control voltage V_VCO is set between 1.0 [V] and 1.9 [V] corresponding to the control parameter setting values P_VCO1 to P_VCO4, respectively.

On the other hand, in the updated conversion table shown in FIG. 23(B), the value of the control voltage V_VCO is set between 1.0 [V] and 1.6 [V] corresponding to the control parameter setting values P_VCO1 to P_VCO4, respectively. This allows the step width of the oscillation frequency to be set more finely, thereby improving the controllability of the oscillation frequency of the voltage-controlled oscillator 23.

[Effects of the Third Embodiment]
According to the above embodiment, the correspondence between the multiple setting values of the control parameters P_LF, P_VCO, and P_DIV for controlling the loop filter 22, the voltage controlled oscillator 23, and the frequency divider 24A and the control voltages and the like is changed according to the frequency of use of the multiple setting values of the control parameters. This allows the variation range of the oscillation frequency of the voltage controlled oscillator 23 to be controlled in finer step widths, thereby improving the controllability of the PLL circuit 11.

Embodiment 4.
In the fourth embodiment, an error vector amplitude (EVM) detection circuit 17 is further provided inside the transmission circuit 10 of the transmitter 1C. This will be specifically described below with reference to Figs.

[Overall configuration of transmitter]
Fig. 24 is a block diagram showing an overall configuration of a transmitter 1C according to embodiment 4. The transmission circuit 10 in Fig. 24 differs from the transmission circuit 10 in Fig. 14 in that it further includes an EVM detection circuit 17.

The EVM detection circuit 17 detects the error vector amplitude of the modulated signal MS and outputs information D_emv on the detected error vector amplitude to the control circuit 30. If the detected error vector amplitude exceeds a threshold (M), the control circuit 30 changes the control parameter P_LF of the loop filter 22. This removes noise in the high frequency band and improves the phase noise characteristics of the PLL circuit 11.

Other aspects of Figure 24 are similar to those of Figure 14, so the same or corresponding parts are given the same reference symbols and will not be described repeatedly.

[Processing flow of control circuit]
Fig. 25 is a flowchart showing a method for controlling a PLL circuit according to embodiment 4. The flowchart in Fig. 25 differs from the flowchart in Fig. 20 in that steps S250 and S260 are further added.

If the temperature change amount is not large enough to exceed the threshold value (NO in step S180) and the temperature range of the detected temperature Temp of the temperature sensor 34 does not exceed the threshold value (NO in step S190), the parameter adjustment unit 33A proceeds to step S250.

In step S250, the parameter adjustment unit 33A determines whether the error vector amplitude of the modulated signal MS received from the EVM detection circuit 17 exceeds the threshold value (M). If the error vector amplitude exceeds the threshold value (M) (YES in step S250), the parameter adjustment unit 33A sets the control parameter P_LF of the loop filter 22 to a value corresponding to the error vector amplitude and stores the set value in the memory 35.

Other aspects of Figure 25 are similar to those of Figure 20, so the same or corresponding steps are given the same reference symbols and will not be described repeatedly.

[Effects of the Fourth Embodiment]
In the fourth embodiment, the modulation method of the modulation circuit 13 is assumed to be phase shift keying (PSK) or quadrature phase shift keying (QPSK). In the case of such a modulation method, the phase noise characteristic of the modulated signal MS output from the transmission circuit 10 can be known based on the information of the error vector amplitude. Then, when the error vector amplitude exceeds the threshold value (M), the noise in the high frequency band can be further removed by adjusting the control parameter P_LF of the loop filter 22. As a result, the phase noise characteristic of the PLL circuit 11 can be improved.

In the PLL circuit 11 of the second embodiment, the control parameter P_LF of the loop filter 22 is adjusted to improve the response characteristics on the time axis when the PLL is captured. In contrast, in the case of the fourth embodiment, it is possible to improve both the time response characteristics and the phase noise characteristics of the PLL circuit 11.

[Modification of the fourth embodiment]
In the transmitter 1C in Fig. 24, the error vector amplitude is detected from the output constellation of the modulation circuit 13. Alternatively, the error vector amplitude may be detected from the pre-demodulation modulated signal MS in the receiver opposite to the transmitter 1C. By adjusting the control parameter P_LF of the loop filter 22 based on the error vector amplitude on the receiver side, there is an advantage that the control parameter P_LF can be adjusted taking into account the communication environment around the receiver. Note that, instead of the error vector amplitude (EVM), a bit error rate (BER) may be used as a measure of communication quality on the receiver side.

In addition, in the transmitter 1C of FIG. 24, a baseband signal BS is input to the transmitter 1C. Alternatively, the baseband signal may be generated in a baseband circuit inside the transmitter 1C. This makes it possible to omit the procedure of inputting the baseband signal BS to the transmitter 1C when performing calibration before starting communication, thereby simplifying the calibration procedure.

Embodiment 5.
The features of the PLL circuit 11 and the control circuit 30 of the first to fourth embodiments described above can also be applied to the receiver 2, and provide substantially the same effects as those of the transmitters 1, 1A to 1C described thus far.

Figure 26 is a block diagram showing the overall configuration of a receiver 2 according to the fifth embodiment. The receiver 2 receives a modulated signal MS, demodulates the received modulated signal MS to generate a baseband signal BS, and outputs the generated baseband signal BS. As shown in Figure 26, the receiver 2 includes a receiving circuit 90, a control circuit 30, a temperature sensor 34, and a memory 35. The receiving circuit 90 includes a demodulation circuit 91, a PLL circuit 11, a reference clock generating circuit 12, and an EVM detection circuit 17.

The demodulation circuit 91 receives the modulated signal MS and the output clock CLKout of the PLL circuit 11, and generates a baseband signal BS by demodulating the modulated signal MS based on the output clock CLKout. Since other points in FIG. 26 are the same as those in FIG. 24, the same reference symbols are used for the same or corresponding parts, and the description will not be repeated.

The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. For example, two or more embodiments may be implemented in combination. Each embodiment may be implemented in part, or two or more embodiments may be implemented in partial combination. The scope of this application is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

1, 1A, 1B, 1C transmitter, 2 receiver, 10 transmission circuit, 11 PLL circuit, 12, 14 reference clock generation circuit, 13 modulation circuit, 17 EVM detection circuit, 20 phase comparator, 21 charge pump, 22 loop filter, 23 voltage controlled oscillator, 24, 24A frequency divider, 30 control circuit, 31 temperature monitoring unit, 32 PLL capture monitoring unit, 33, 33A parameter adjustment unit, 34 temperature sensor, 35 memory, 36 parameter update unit, 40 variable resistor, 41, 42 resistance element, 43 switch, 44, 45, 50, 51 variable capacitance, 46, 53, 83 conversion circuit, 47 signal line, 52 inductor, 55 delay circuit, 56 temperature range determination unit, 57 temperature fluctuation determination unit, 61, 62 JK flip-flop, 63 NAND circuit, 64 synchronization determination unit, 65, 81, 82 counters, 70, 72 parameter update determination unit, 71, 73, 74 selector, 80 prescaler, 90 receiving circuit, 91 demodulation circuit, BS baseband signal, CLKdiv divided clock, CLKout output clock, CLKref, CLKref1, CLKref2 reference clock, D capture information, D_temp temperature range information, D_deltatemp temperature fluctuation information, GND ground, MS modulation signal, Temp detection temperature.

Claims (7)

A phase locked loop circuit, comprising:
a voltage controlled oscillator that generates an output signal having a frequency responsive to a first control parameter and a first control voltage;
a frequency divider that divides the output signal of the voltage controlled oscillator by a frequency division ratio according to a second control parameter ;
a phase comparator for detecting a phase difference between a reference clock signal and the divided output signal;
a charge pump that outputs a current corresponding to the detected phase difference;
a loop filter that generates the first control voltage based on an output current of the charge pump;
a control circuit that adjusts the first control parameter and the second control parameter based on a detected temperature by a temperature sensor provided around the phase locked loop ;
The control circuit adjusts the first control parameter based on a time variation of the detected temperature of the temperature sensor, and adjusts the second control parameter based on a temperature range of the detected temperature of the temperature sensor . an oscillation frequency of the voltage controlled oscillator varies in response to the first control voltage and the second control voltage;
the voltage controlled oscillator varies the second control voltage in accordance with a table indicating a correspondence relationship between a plurality of set values of the first control parameter and a value of the second control voltage;
2. The phase locked loop according to claim 1 , wherein said control circuit updates said table when any of said plurality of setting values of said first control parameter has a frequency of use lower than a threshold value. the frequency characteristic of the loop filter varies in response to a third control parameter;
3. The phase locked loop according to claim 1, wherein the control circuit adjusts the third control parameter based on an acquisition time at the start-up of the phase locked loop. A phase locked loop circuit according to claim 3 ;
a modulation circuit that generates a modulated signal by modulating a baseband signal using the output signal of the voltage controlled oscillator. a detection circuit for detecting an error vector magnitude of the modulated signal;
The transmitter of claim 4 , wherein the control circuit adjusts the third control parameter based on the detected value of the error vector magnitude. A phase locked loop circuit according to claim 3 ;
a demodulation circuit that utilizes the output signal of the voltage controlled oscillator to demodulate a modulated signal to generate a baseband signal. A method for controlling a phase locked loop, comprising the steps of:
The phase locked loop circuit includes:
a voltage controlled oscillator that generates an output signal having a frequency responsive to a first control parameter and a first control voltage;
a frequency divider that divides the output signal of the voltage controlled oscillator by a frequency division ratio according to a second control parameter ;
a phase comparator for detecting a phase difference between a reference clock signal and the divided output signal;
a charge pump that outputs a current corresponding to the detected phase difference;
a loop filter that generates the first control voltage based on an output current of the charge pump;
The control method includes:
acquiring information on a temperature detected by a temperature sensor provided around the phase locked loop;
adjusting the first control parameter and the second control parameter based on the detected temperature of the temperature sensor ;
A method for controlling a phase-locked loop, wherein in the adjusting step, the first control parameter is adjusted based on a time variation of the detected temperature of the temperature sensor, and the second control parameter is adjusted based on a temperature range of the detected temperature of the temperature sensor .

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