JP7618356B2 - SLOPE SIGNAL GENERATION CIRCUIT, PWM SIGNAL GENERATION CIRCUIT, DISPLAY DEVICE, AND SLOPE SIGNAL GENERATION METHOD - Google Patents

Description

The present invention relates to a slope signal generating circuit, a PWM signal generating circuit, a display device, and a slope signal generating method, and more particularly to a slope signal generating circuit, a PWM signal generating circuit, a display device, and a slope signal generating method capable of generating a highly accurate slope signal, for example.

In recent years, development of display devices has progressed in which self-emitting light-emitting elements such as OLEDs (organic light-emitting diodes) and tiny LEDs (hereinafter referred to as micro LEDs) are mounted in a two-dimensional matrix. When micro LEDs are used as light-emitting elements, the gradation expression of the light-emitting elements is often performed by PWM (Pulse Width Modulation) driving from the viewpoint of suppressing color shift of the light emission. In PWM driving, the light-emitting elements are driven using a PWM signal with a pulse width according to the video signal, which is generated by comparing the video signal with a slope signal, which is a voltage signal with a sawtooth wave or triangular wave shape. Therefore, in order to make the light-emitting elements emit light with high accuracy, it is necessary to use a highly accurate slope signal.

Technology relating to a slope signal generating circuit that generates a slope signal is disclosed, for example, in Patent Document 1 and Non-Patent Document 1. Patent Document 1 discloses a slope wave generator that generates a slope wave and is configured with a constant current source and a capacitive element. Non-Patent Document 1 also discloses an integrating circuit that generates a triangular wave and is configured with an operational amplifier, a resistive element, and a capacitive element.

JP 2011-211509 A

indexpro, "Analog Circuit Design: Application of Op-Amps - Integration Circuits", [online], [Retrieved February 4, 2021], <URL: https://www.indexpro.co.jp/article/detail/11/13>

However, the related technology configuration has an issue in that the inclination of the slope signal waveform varies due to variations in the resistance value of the resistive element and the capacitance value of the capacitive element. In other words, the related technology configuration has an issue in that it is not possible to generate a highly accurate slope signal.

The present invention has been made in consideration of the above problems, and aims to provide a slope signal generation circuit, a PWM signal generation circuit, a display device, and a slope signal generation method that are capable of generating a highly accurate slope signal.

A slope signal generating circuit according to one aspect of the present invention includes an integrating circuit that, in a first mode among operation modes including at least a first mode and a second mode, integrates a potential difference between a first reference potential and a second reference potential, and, in the second mode, integrates a potential difference between the integration result in the first mode and a third reference potential to output a slope signal. This slope signal generating circuit can suppress the variation in the slope signal by offsetting the variation in the integration result in the first mode due to the variation in the resistance value of a resistive element, which is a component of the integrating circuit, and the variation in the capacitance value of a capacitive element, which is a component of the integrating circuit, in the integration in the second mode. In other words, this slope signal generating circuit can generate a highly accurate slope signal.

A slope signal generating method according to one aspect of the present invention is a slope signal generating method using an integrating circuit, which uses the integrating circuit to integrate a potential difference between a first reference potential and a second reference potential, holds a result of integrating the potential difference between the first reference potential and the second reference potential, and uses the integrating circuit to integrate a potential difference between the held integration result and a third reference potential to output a slope signal. This slope signal generating method can suppress the variation in the slope signal because it can offset the variation in the integration result in the first mode due to the variation in the resistance value of the resistive element, which is a component of the integrating circuit, and the variation in the capacitance value of the capacitive element, which is a component of the integrating circuit, in the integration in the second mode. In other words, this slope signal generating method can generate a highly accurate slope signal.

The present invention provides a slope signal generating circuit, a PWM signal generating circuit, a display device, and a slope signal generating method that are capable of generating a highly accurate slope signal.

1 is a circuit diagram showing a configuration example of a slope signal generating circuit according to a first embodiment; 2 is a timing chart showing an operation of the slope signal generating circuit shown in FIG. 1 . FIG. 11 is a circuit diagram showing a configuration example of a slope signal generating circuit according to a comparative example. 2 is a diagram showing the relationship between RC variation in the slope signal generating circuit shown in FIG. 1 and variation in the potential of the slope signal; 2 is a diagram illustrating an application example of the slope signal generating circuit shown in FIG. 1; 2 is a diagram illustrating an application example of the slope signal generating circuit shown in FIG. 1; 2 is a circuit diagram showing a modified example of the slope signal generating circuit shown in FIG. 1. 8 is a timing chart showing an operation of the slope signal generating circuit shown in FIG. 7 . FIG. 11 is a circuit diagram showing a configuration example of a slope signal generating circuit according to a second embodiment. 10 is a timing chart showing an operation of the slope signal generating circuit shown in FIG. 9 . FIG. 10 is a circuit diagram showing a first modified example of the slope signal generating circuit shown in FIG. 9 . 12 is a timing chart showing an operation of the slope signal generating circuit shown in FIG. 11 . FIG. 10 is a circuit diagram showing a second modified example of the slope signal generating circuit shown in FIG. 9 . 14 is a timing chart showing an operation of the slope signal generating circuit shown in FIG. 13 .

<First embodiment>
FIG. 1 is a circuit diagram showing a configuration example of a slope signal generating circuit 1 according to a first embodiment.
The slope signal generating circuit 1 is an integrating circuit that generates a sawtooth-shaped slope signal that rises gently and falls steeply. Here, the slope signal generating circuit 1 can cancel out the variation in the integration result in the first mode caused by the variation in the resistance value of the resistive element, which is a component of the integrating circuit, and the variation in the capacitance value of the capacitive element, which is a component of the integrating circuit, in the integration in the second mode, thereby suppressing the variation in the slope signal. In other words, the slope signal generating circuit 1 can generate a highly accurate slope signal. A specific description will be given below.

As shown in FIG. 1, the slope signal generating circuit 1 includes an integrator (first integrator) 11, an integrator (second integrator) 12, and switches SW13, SW14, and SW15. The integrator 11 includes an operational amplifier (amplifier) A11, a resistive element R11, a capacitive element C11, and a switch SW11. The integrator 12 includes an operational amplifier (amplifier) A12, a resistive element R12, a capacitive element C12, and a switch SW12.

In this embodiment, the switches SW11 to SW15 are all N-channel MOS transistors. Therefore, the switches SW11 to SW15 are turned on when the potential (gate potential) of the control signal is at H level, and turned off when it is at L level.

In the integrator 11, the resistive element R11 is provided between one input terminal (node N13) of the integrator 11 and the inverting input terminal (- terminal) of the operational amplifier A11. The capacitive element C11 is provided between the output terminal of the operational amplifier A11 and the inverting input terminal of the operational amplifier A11. The switch SW11 is provided in parallel with the capacitive element C11 and switches on and off in response to a control signal Set. The non-inverting input terminal (+ terminal) of the operational amplifier A11 is connected to the other input terminal (node N14) of the integrator 11. The output terminal of the operational amplifier A11 is connected to the output terminal (node N11) of the integrator 11.

In the integrator 12, the resistive element R12 is provided between one input terminal (node N15) of the integrator 12 and the inverting input terminal (- terminal) of the operational amplifier A12. The capacitive element C12 is provided between the output terminal of the operational amplifier A12 and the inverting input terminal of the operational amplifier A12. The switch SW12 is provided in parallel with the capacitive element C12 and switches on and off according to a control signal Set2_ (inverted signal of Set2). The non-inverting input terminal (+ terminal) of the operational amplifier A12 is connected to the other input terminal (node N16) of the integrator 12. The output terminal of the operational amplifier A12 is connected to the output terminal (node N12) of the integrator 12. In addition, the output terminal (node N12) of the integrator 12 is connected to the output terminal of the slope signal generating circuit 1 (hereinafter referred to as the output terminal Vout2).

The switch SW13 is provided between one input terminal (node N13) of the integrator 11 and a reference potential terminal (hereinafter referred to as reference potential terminal V1) to which a reference potential V1 is supplied, and switches on and off according to a control signal Set1. The switch SW14 is provided between one input terminal (node N13) of the integrator 11 and the other input terminal (node N14) of the integrator 11, and switches on and off according to a control signal Set1_ (an inverted signal of Set1). The other input terminal (node N14) of the integrator 11 is connected to a reference potential terminal (hereinafter referred to as reference potential terminal V2) to which a reference potential V2 is supplied.

Switch SW15 is provided between the output terminal (node N11) of integrator 11 and the input terminal (node N15) of integrator 12, and switches on and off in response to control signal Set2.

Here, the reference potentials V1, V2, and V3 are adjusted so that the relationship V1<V2<Vout1<V3 holds between the reference potentials V1 to V3 and the integration result (final potential) Vout1 of the integrator 11. In the example of FIG. 1, the reference potential V1 is adjusted to 1.7 V, the reference potential V2 is adjusted to 1.8 V, and considering that the integration result of the integrator 11 is 1.9±0.01 V, the reference potential V3 is adjusted to 2.0 V.

In addition, the resistor elements R11 and R12 are constructed using the same material within the same chip. Therefore, the tendency of variation in the resistor elements R11 and R12 is substantially the same. In this embodiment, an example will be described in which the resistance values of the resistor elements R11 and R12 are substantially the same.

Similarly, the capacitive elements C11 and C12 are constructed using the same material within the same chip. Therefore, the tendency of variation in the capacitive elements C11 and C12 is substantially the same. In this embodiment, the case where the capacitance values of the capacitive elements C11 and C12 are substantially the same will be described as an example.

(Operation of Slope Signal Generating Circuit 1)
Next, the operation of the slope signal generating circuit 1 will be described with reference to FIG.
Fig. 2 is a timing chart showing the operation of the slope signal generating circuit 1. Note that Fig. 2 shows the waveform of the slope signal for one period of the sawtooth wave.

First, the operating mode is set to the initialization mode. In the initialization mode, the integrators 11 and 12 are initialized.

Specifically, in the initialization mode, the control signal Set1 is set to the L level, the control signal Set2 is set to the L level, and the control signal Set is set to the H level (time t10). As a result, switch SW11 is turned on, switch SW12 is turned on, switch SW13 is turned off, switch SW14 is turned on, and switch SW15 is turned off.

As a result, the integrators 11 and 12 are separated from each other and are initialized. In the example of FIG. 2, the output potential Vout1 of the integrator 11 (and the potentials of the two input terminals) indicates 1.8 V, which is the same as the reference potential V2, and the output potential Vout2 of the integrator 12 (and the potentials of the two input terminals) indicates 2.0 V, which is the same as the reference potential V3.

Then, the operation mode transitions from the initialization mode to the first mode. In the first mode, integration is performed by the integrator 11 (times t11 to t12).

Specifically, first, the control signal Set1 switches from L level to H level, and the control signal Set switches from H level to L level (time t11). As a result, the switch SW11 switches from on to off, the switch SW12 maintains the on state, the switch SW13 switches from off to on, the switch SW14 switches from on to off, and the switch SW15 maintains the off state.

As a result, the integrator 11 becomes capable of integration, and begins to integrate the potential difference between the reference potential V1 input to one input terminal (node N13) and the reference potential V2 input to the other input terminal (node N14) and output it as the output potential Vout1. Here, the output potential Vout1 increases monotonically in the first mode.

In contrast, integrator 12 is separated from integrator 11 and remains initialized. Therefore, the output potential Vout2 of integrator 12 remains at 2.0 V, which is the same as the reference potential V3.

When the output potential Vout1 of the integrator 11 increases monotonically and reaches a maximum value, the integration by the integrator 11 is completed and the operation mode transitions from the first mode to the second mode. In the second mode, the integration by the integrator 12 is performed while the integration result (reached potential) by the integrator 11 is held (time t12 to t13).

Specifically, the control signal Set1 switches from H level to L level, and the control signal Set2 switches from L level to H level (time t12). As a result, the switch SW11 remains in the off state, the switch SW12 switches from on to off, the switch SW13 switches from on to off, the switch SW14 switches from off to on, and the switch SW15 switches from off to on.

As a result, the switch SW14 (output fixing unit) of the integrator 11 turns on and shorts the two input terminals together, so that the output potential Vout1 is fixed to the integration result (attainment potential) in the first mode. Here, the output potential Vout1 is ideally 1.9V, but varies by, for example, about ±10% due to variations in the resistance value of the resistive element R11 and the capacitance value of the capacitive element C11. In other words, the output potential Vout1 varies in the range of 1.89V to 1.91V.

Meanwhile, integrator 12 is connected to integrator 11 and is in a state in which it can integrate. As a result, integrator 12 integrates the potential difference between output potential Vout1 (the integration result of integrator 11 in the first mode) input to one input terminal (node N15) and reference potential V3 input to the other input terminal (node N16), and starts outputting it as output potential Vout2. Here, output potential Vout2 increases monotonically in the second mode.

This output potential Vout2 is output as a slope signal from the external output terminal Vout2 to the outside of the slope signal generating circuit 1.

Here, the integrator 12 performs negative feedback operation to offset the variation in the output potential Vout1 of the integrator 11 caused by the variation in the resistance value of the resistive element R11 and the variation in the capacitance value of the capacitive element C11 with the variation in the resistance value of the resistive element R12 and the variation in the capacitance value of the capacitive element C12, thereby suppressing the variation in the output potential Vout2 (i.e., the slope signal) (details will be described later).

When the output potential Vout2 of the integrator 12 increases monotonically and reaches a predetermined value, the integration by the integrator 12 is completed and the operation mode transitions from the second mode to the initialization mode. In the initialization mode, as already described, the integrators 11 and 12 are initialized.

Specifically, the control signal Set2 switches from H level to L level, and the control signal Set switches from L level to H level (time t13). As a result, the switch SW11 switches from off to on, the switch SW12 switches from off to on, the switch SW13 maintains the off state, the switch SW14 maintains the on state, and the switch SW15 switches from on to off.

As a result, the output potential Vout1 of the integrator 11 falls sharply to 1.8 V, which is the same as the reference potential V2, and the output potential Vout2 (i.e., the slope signal) of the integrator 12 falls sharply to 2.0 V, which is the same as the reference potential V3.

By repeating this operation, the slope signal generating circuit 1 generates a sawtooth slope signal that rises gradually and falls sharply.

Here, the resistor elements R11 and R12 are constructed using the same material within the same chip. Therefore, the tendency of variation of the resistor elements R11 and R12 is substantially the same. Also, the resistance values of the resistor elements R11 and R12 are substantially the same. Therefore, if the resistance value of each of the resistor elements R11 and R12 is R0, the capacitance value of each of the capacitance elements C11 and C12 is C0, the integration period (time t11 to t12) by the integrator 11 in the first mode is t1, the integration period (t12 to t13) by the integrator 12 in the second mode is k, the variation coefficient of the resistor elements and the capacitance elements, the output potential Vout1 is Vout1, and the output potential Vout2 is Vout2, Vout1 and Vout2 can be expressed as the following formulas (1) and (2), respectively.

Referring to equations (1) and (2), for example, if the resistance value R0 of the resistive element and the capacitance value C0 of the capacitive element are 10% smaller than their ideal values, Vout1 will exhibit approximately 1.91 V, which is larger than the ideal potential of 1.9 V. However, the potential difference between the reference potential V3 (= 2.0 V) and the output potential Vout1 (= 1.91 V) will be 0.09 V, which is 0.01 V smaller than the ideal state, and the output potential Vout2 will have reduced variation and will approach the ideal potential. Furthermore, if the resistance value R0 of the resistive element and the capacitance value C0 of the capacitive element are 10% greater than the ideal values, Vout1 will show approximately 1.89V, which is smaller than the ideal potential of 1.9V. However, the potential difference between the reference potential V3 (=2.0V) and the output potential Vout1 (=1.89V) will be 0.11V, which is 0.01V greater than the ideal state, so the output potential Vout2 will have less variation and will approach the ideal potential.

To explain in more detail, by substituting equation (1) into equation (2), Vout2 can be expressed as the following equation (3).

Now, if the integration period t1 by the integrator 11 in the first mode is adjusted as shown in the following equation (4), Vout2 can be expressed as shown in the following equation (5).

By transforming equation (5), Vout2 can be expressed as the following equation (6).

By transforming equation (6), Vout2 can be expressed as the following equation (7).

Assuming k<<1, Vout2 can be expressed as the following equation (8) by first-order approximation.

By transforming equation (8), Vout2 can be expressed as the following equation (9).

As can be seen from equation (9), the output potential Vout2 (i.e., the slope signal) does not depend on the variation coefficient k. In other words, the slope signal generating circuit 1 can generate a highly accurate slope signal without depending on the variation in the resistance values of the resistive elements R11 and R12 or the variation in the capacitance values of the capacitive elements C11 and C12.

Figure 3 is a circuit diagram showing an example of the configuration of a slope signal generating circuit 50 according to a comparative example. As shown in Figure 3, the slope signal generating circuit 50 includes only the front-stage integrator 11 among the components of the slope signal generating circuit 1, and outputs the output potential Vout1 of the integrator 11 as a slope signal. Here, the output potential Vout1 can be expressed as in the above-mentioned formula (1).

As can be seen from equation (1), the output potential of the slope signal generating circuit 50 depends on the variation coefficient k. That is, in the slope signal generating circuit 50, the potential of the slope signal varies depending on the variation in the resistance value of the resistive element R11 and the variation in the capacitance value of the capacitive element C11.

Figure 4 shows the relationship between the RC variation (variation of resistive and capacitive elements) in the slope signal generating circuit 1 and the variation in the potential of the slope signal. For comparison, Figure 3 also shows the relationship between the RC variation in the slope signal generating circuit 50 and the variation in the potential of the slope signal.

As can be seen from FIG. 4, in the slope signal generating circuit 50, the greater the RC variation, the greater the variation in the potential of the slope signal, whereas in the slope signal generating circuit 1 of this embodiment, the variation in the potential of the slope signal is kept small regardless of the RC variation.

In this way, the slope signal generating circuit 1 according to this embodiment includes two stages of integrators 11 and 12, and the variation in the output potential Vout1 of the integrator 11 caused by the variation in the resistance value of the resistive element R11 and the variation in the capacitance value of the capacitive element C11 can be offset by the variation in the resistance value of the resistive element R12 and the variation in the capacitance value of the capacitive element C12 during integration by the integrator 12, thereby suppressing the variation in the slope signal (output potential Vout2). In other words, the slope signal generating circuit 1 according to this embodiment can generate a highly accurate slope signal.

(Application Example of Slope Signal Generating Circuit 1)
In recent years, the development of display devices in which self-emitting light-emitting elements such as OLEDs (organic light-emitting diodes) and tiny LEDs (hereinafter referred to as micro LEDs) are mounted in a two-dimensional matrix is progressing. Here, when micro LEDs are used as light-emitting elements, the gradation expression of the light-emitting elements is often performed by PWM (Pulse Width Modulation) driving from the viewpoint of suppressing color shift of light emission. In PWM driving, a light-emitting element is driven using a PWM signal having a pulse width according to a video signal, which is generated by comparing a video signal with a slope signal, which is a voltage signal of a sawtooth wave or a triangular wave. Therefore, in order to precisely emit light from the light-emitting element, it is necessary to use a highly accurate slope signal.

Therefore, for example, the slope signal generated by the slope signal generating circuit 1 is used to generate a PWM signal for driving a self-emitting light-emitting element in the display device described above. This allows the display device to display high-quality images.

The slope signal generating circuit 1 may be provided outside the pixel circuit (drive circuit) that drives the self-luminous light-emitting element, but may also be built into the pixel circuit to prevent waveform delay and transient degradation inside the panel. Below, an example in which the slope signal generating circuit 1 is built into the pixel circuit is described.

FIG. 5 is a diagram showing an overview of a display device 100 to which the slope signal generating circuit 1 is applied.
As shown in Fig. 5, a plurality of self-emitting light-emitting elements are arranged in a two-dimensional matrix on the panel portion of the display device 100. In the example of Fig. 5, each light-emitting element is a micro LED. In addition, in the example of Fig. 5, one pixel circuit 10 is arranged for twelve light-emitting elements D1 to D12. In other words, one pixel circuit 10 performs PWM driving of the twelve light-emitting elements D1 to D12.

Figure 6 is a block diagram showing an example of the configuration of the pixel circuit 10. The pixel circuit 10 is also called a microcontroller (μIC), and in this example, performs PWM driving of 12 light-emitting elements D1 to D12.

Specifically, the pixel circuit 10 includes a slope signal generating circuit 1 and 12 PWM signal generating circuits 20_1 to 20_12 corresponding to the 12 light emitting elements D1 to D12. Each PWM signal generating circuit 20_1 to 20_12 generates a PWM signal with a pulse width according to the video signal by comparing the video signal with the slope signal generated by the slope signal generating circuit 1. The PWM signals generated by the PWM signal generating circuits 20_1 to 20_12 are supplied to the light emitting elements D1 to D12, respectively. As a result, each light emitting element D1 to D12 emits light with a luminance according to the video signal.

As already explained, the slope signal generating circuit 1 can generate a highly accurate slope signal regardless of RC variations. Therefore, each of the light emitting elements D1 to D12 can emit light with high accuracy.

Furthermore, even if the RC variations of the multiple slope signal generating circuits 1 provided in each of the multiple pixel circuits 10 are different, each slope signal generating circuit 1 can generate a highly accurate slope signal regardless of the RC variations. Therefore, the display device 100 can cause multiple light-emitting elements arranged in a two-dimensional matrix to emit light with high accuracy. In other words, the display device 100 can display high-quality images.

(Modification of Slope Signal Generating Circuit 1)
7 is a circuit diagram showing a slope signal generating circuit 1a which is a modified example of the slope signal generating circuit 1. The slope signal generating circuit 1 generates a sawtooth-shaped slope signal which rises gently and falls sharply. In contrast, the slope signal generating circuit 1a generates a sawtooth-shaped slope signal which falls gently and rises sharply.

Specifically, the reference potentials V1, V2, and V3 are adjusted so that the relationship V1>V2>Vout1>V3 holds between the reference potentials V1 to V3 and the integration result (final potential) Vout1 of the integrator 11. In the example of FIG. 7, the reference potential V1 is adjusted to 3.3 V, the reference potential V2 is adjusted to 3.2 V, and considering that the integration result of the integrator 11 is 3.1±0.01 V, the reference potential V3 is adjusted to 3.0 V.

The rest of the configuration of the slope signal generating circuit 1a is the same as that of the slope signal generating circuit 1, so the description will be omitted.

(Operation of Slope Signal Generating Circuit 1a)
Next, the operation of the slope signal generating circuit 1a will be described with reference to FIG.
Fig. 8 is a timing chart showing the operation of the slope signal generating circuit 1. Note that Fig. 8 shows the waveform of a slope signal for one period of a sawtooth wave.

First, the operating mode is set to the initialization mode. In the initialization mode, the integrators 11 and 12 are initialized.

Specifically, in the initialization mode, the control signal Set1 is set to the L level, the control signal Set2 is set to the L level, and the control signal Set is set to the H level (time t20). As a result, switch SW11 is turned on, switch SW12 is turned on, switch SW13 is turned off, switch SW14 is turned on, and switch SW15 is turned off.

As a result, the integrators 11 and 12 are separated from each other and are initialized. In the example of FIG. 2, the output potential Vout1 of the integrator 11 (and the potentials of the two input terminals) indicates 3.2 V, which is the same as the reference potential V2, and the output potential Vout2 of the integrator 12 (and the potentials of the two input terminals) indicates 3.0 V, which is the same as the reference potential V3.

Then, the operation mode transitions from the initialization mode to the first mode. In the first mode, integration is performed by the integrator 11 (times t21 to t22).

Specifically, first, the control signal Set1 switches from L level to H level, and the control signal Set switches from H level to L level (time t21). As a result, the switch SW11 switches from on to off, the switch SW12 maintains the on state, the switch SW13 switches from off to on, the switch SW14 switches from on to off, and the switch SW15 maintains the off state.

As a result, the integrator 11 becomes capable of integration, and begins to integrate the potential difference between the reference potential V1 input to one input terminal (node N13) and the reference potential V2 input to the other input terminal (node N14) and output it as the output potential Vout1. Here, the output potential Vout1 monotonically decreases in the first mode.

In contrast, integrator 12 is separated from integrator 11 and remains initialized. Therefore, the output potential Vout2 of integrator 12 remains at 3.0 V, which is the same as the reference potential V3.

When the output potential Vout1 of the integrator 11 decreases monotonically and reaches a minimum value, the integration by the integrator 11 is completed and the operation mode transitions from the first mode to the second mode. In the second mode, the integration by the integrator 12 is performed while the integration result (reached potential) by the integrator 11 is held (time t22 to t23).

Specifically, the control signal Set1 switches from H level to L level, and the control signal Set2 switches from L level to H level (time t22). As a result, the switch SW11 remains in the off state, the switch SW12 switches from on to off, the switch SW13 switches from on to off, the switch SW14 switches from off to on, and the switch SW15 switches from off to on.

As a result, the switch SW14 (output fixing unit) of the integrator 11 turns on and shorts the two input terminals together, so that the output potential Vout1 is fixed to the integration result (attainment potential) in the first mode. Here, the output potential Vout1 is ideally 3.1 V, but varies by, for example, about ±10% due to variations in the resistance value of the resistive element R11 and the capacitance value of the capacitive element C11. In other words, the output potential Vout1 varies in the range of 3.09 V to 3.11 V.

Meanwhile, integrator 12 is connected to integrator 11 and is in a state in which it can integrate. As a result, integrator 12 integrates the potential difference between output potential Vout1 (the integration result of integrator 11 in the first mode) input to one input terminal (node N15) and reference potential V3 input to the other input terminal (node N16), and starts outputting it as output potential Vout2. Here, output potential Vout2 monotonically decreases in the second mode.

This output potential Vout2 is output as a slope signal from the external output terminal Vout2 to the outside of the slope signal generating circuit 1.

Here, the integrator 12 performs negative feedback operation to offset the variation in the output potential Vout1 of the integrator 11 caused by the variation in the resistance value of the resistive element R11 and the variation in the capacitance value of the capacitive element C11 with the variation in the resistance value of the resistive element R12 and the variation in the capacitance value of the capacitive element C12, thereby suppressing the variation in the output potential Vout2 (i.e., the slope signal).

When the output potential Vout2 of the integrator 12 decreases monotonically and reaches a predetermined value, the integration by the integrator 12 is completed and the operation mode transitions from the second mode to the initialization mode. In the initialization mode, as already described, the integrators 11 and 12 are initialized.

Specifically, the control signal Set2 switches from H level to L level, and the control signal Set switches from L level to H level (time t23). As a result, the switch SW11 switches from off to on, the switch SW12 switches from off to on, the switch SW13 maintains the off state, the switch SW14 maintains the on state, and the switch SW15 switches from on to off.

As a result, the output potential Vout1 of the integrator 11 rises steeply to 3.2 V, which is the same as the reference potential V2, and the output potential Vout2 (i.e., the slope signal) of the integrator 12 rises steeply to 3.0 V, which is the same as the reference potential V3.

By repeating this operation, the slope signal generating circuit 1 generates a sawtooth slope signal that falls gently and rises sharply.

In this way, the slope signal generating circuit 1a according to this embodiment includes two stages of integrators 11 and 12, and the variation in the output potential Vout1 of the integrator 11 caused by the variation in the resistance value of the resistive element R11 and the variation in the capacitance value of the capacitive element C11 can be offset by the variation in the resistance value of the resistive element R12 and the variation in the capacitance value of the capacitive element C12 during integration by the integrator 12, thereby suppressing the variation in the slope signal (output potential Vout2). In other words, the slope signal generating circuit 1a according to this embodiment can generate a highly accurate slope signal.

<Embodiment 2>
FIG. 9 is a circuit diagram showing an example of the configuration of a slope signal generating circuit 2 according to the second embodiment.
The slope signal generating circuit 2 is an integrating circuit that generates a sawtooth-shaped slope signal that rises gently and falls steeply. Here, the slope signal generating circuit 1 can cancel out the variation in the integration result in the first mode caused by the variation in the resistance value of the resistive element, which is a component of the integrating circuit, and the variation in the capacitance value of the capacitive element, which is a component of the integrating circuit, in the integration in the second mode, thereby suppressing the variation in the slope signal. In other words, the slope signal generating circuit 1 can generate a highly accurate slope signal. A specific description will be given below.

As shown in FIG. 9, the slope signal generating circuit 2 includes an integrator 21, a holding circuit 22, a selection circuit 23, and a switch SW24. The integrator 21 includes an operational amplifier (amplifier) A21, a resistive element R21, a capacitive element C21, and a switch SW21. The holding circuit 22 includes an operational amplifier (amplifier) A22, a capacitive element C22, and a switch SW22. The selection circuit 23 includes switches SW31 to SW34.

In this embodiment, the switches SW21, SW22, SW24, SW31 to SW33 are all N-channel MOS transistors. Therefore, the switches SW21, SW22, SW24, SW31 to SW33 are turned on when the potential (gate potential) of the control signal is at H level, and turned off when it is at L level.

In the integrator 21, the resistive element R21 is provided between one input terminal (node N23) of the integrator 21 and the inverting input terminal (- terminal) of the operational amplifier A21. The capacitive element C21 is provided between the output terminal of the operational amplifier A21 and the inverting input terminal of the operational amplifier A21. The switch SW21 is provided in parallel with the capacitive element C21 and switches on and off according to the control signal Res. The non-inverting input terminal (+ terminal) of the operational amplifier A21 is connected to the other input terminal (node N24) of the integrator 21. The output terminal of the operational amplifier A21 is connected to the output terminal (node N21) of the integrator 21. In addition, the output terminal (node N21) of the integrator 21 is connected to the output terminal of the slope signal generating circuit 2 (hereinafter referred to as the output terminal Vout).

In the holding circuit 22, the switch SW22 is provided between the input terminal (node N21) of the holding circuit 22 and the non-inverting input terminal (+ terminal) of the operational amplifier A22, and switches on and off in response to the control signal Set1. The capacitive element C22 is provided between the non-inverting input terminal of the operational amplifier A11 and the ground voltage terminal. The inverting input terminal (- terminal) of the operational amplifier A22 is connected to the output terminal of the operational amplifier A22. The output terminal of the operational amplifier A22 is connected to the output terminal (node N22) of the holding circuit 22.

In the selection circuit 23, the switch SW31 is provided between a reference potential terminal (hereinafter referred to as the reference potential terminal V1) to which a reference potential V1 is supplied and one output terminal (node N23) of the selection circuit 23, and switches on and off in response to a control signal Set1. The switch SW32 is provided between the output terminal (node N22) of the holding circuit 22 and one output terminal (node N23) of the selection circuit 23, and switches on and off in response to a control signal Set2. The switch SW33 is provided between a reference potential terminal (hereinafter referred to as the reference potential terminal V2) to which a reference potential V2 is supplied and the other output terminal (node N24) of the selection circuit 23, and switches on and off in response to a control signal Set1. The switch SW34 is provided between a reference potential terminal (hereinafter referred to as the reference potential terminal V3) to which a reference potential V3 is supplied and the other output terminal (node N24) of the selection circuit 23, and switches on and off in response to a control signal Set2. One output terminal of the selection circuit 23 is connected to one input terminal of the integrator 21 via node N23. The other output terminal of the selection circuit 23 is connected to the other input terminal of the integrator 21 via node N24.

The switch SW24 is provided between the output terminal (node N21) of the integrator 21 and the reference potential terminal V3, and is switched on and off according to the control signal Set.

Here, if the integration result (final potential) Vout of the integrator 21 in the first mode is Vout1, the reference potentials V1, V2, and V3 are adjusted so that the relationship V1<V2<Vout1<V3 holds between the reference potentials V1 to V3 and Vout1. In the example of FIG. 9, the reference potential V1 is adjusted to 1.7V, the reference potential V2 is adjusted to 1.8V, and considering that the integration result Vout1 of the integrator 21 in the first mode is 1.9±0.01V, the reference potential V3 is adjusted to 2.0V.

(Operation of Slope Signal Generating Circuit 2)
Next, the operation of the slope signal generating circuit 2 will be described with reference to FIG.
Fig. 10 is a timing chart showing the operation of the slope signal generating circuit 2. Note that Fig. 10 shows the waveform of the slope signal for one period of the sawtooth wave.

First, the operation mode is set to the initialization mode. In the initialization mode, the integrator 21 is initialized (times t30 to t32).

Specifically, first, the control signal Set is set to H level, the control signal Res is set to L level, the control signal Set1 is set to L level, and the control signal Set2 is set to L level (time t30). As a result, the switch SW21 is turned off, the switch SW22 is turned off, the switch SW24 is turned on, the switches SW31 and SW33 are turned off, and the switches SW32 and SW34 are turned off. As a result, the output potential Vout of the integrator 21 indicates 2.0 V, which is the same as the reference voltage V3.

After that, the control signal Set switches from H level to L level, the control signal Res switches from L level to H level, and the control signal Set1 switches from L level to H level (time t31). As a result, the switch SW21 switches from off to on, the switch SW22 switches from off to on, the switch SW24 switches from on to off, and the switches SW31 and SW33 switch from off to on. Meanwhile, the switches SW32 and SW34 maintain the off state.

As a result, the selection circuit 23 outputs a reference potential V1 from one output terminal and outputs a reference potential V2 from the other output terminal. The reference potential V1 output from one output terminal of the selection circuit 23 is input to one input terminal of the integrator 21 via node N23. The reference potential V3 output from the other output terminal of the selection circuit 23 is input to the other input terminal of the integrator 21 via node N24. Here, since the switch SW21 is in the on state, the output potential Vout of the integrator 21 indicates 1.8 V, which is the same as the reference potential V2. Therefore, the output potential Vbuf of the holding circuit 22 also indicates 1.8 V.

Then, the operation mode transitions from the initialization mode to the first mode. In the first mode, the integrator 21 performs the first integration (time t32 to t33).

Specifically, the control signal Res switches from H level to L level (time t32). This switches the switch SW21 from on to off. Meanwhile, the switches SW22, SW31, and SW33 maintain the on state, and the switches SW24, SW32, and SW34 maintain the off state.

As a result, the integrator 21 enters an integration-enabled state, and begins integrating the potential difference between the reference potential V1 input to one input terminal (node N23) and the reference potential V2 input to the other input terminal (node N24) to output the result as the output potential Vout. Here, the output potential Vout increases monotonically in the first mode. Therefore, the output potential Vbuf of the holding circuit 22 also increases monotonically in the first mode, just like Vout.

When the output potential Vout of the integrator 21 increases monotonically and reaches its maximum value in the first mode, the integration by the integrator 21 is completed and the operation mode transitions from the first mode to the preparation mode. In the preparation mode, the integrator 21 prepares for the second integration (times t33 to t35).

Specifically, first, the control signal Set1 switches from H level to L level (time t33). As a result, the switch SW22 switches from on to off, and the switches SW31 and SW33 switch from on to off. Meanwhile, the switches SW21, SW24, SW32, and SW34 all remain in the off state.

As a result, the two output terminals of the selection circuit 23 are in an open state. Therefore, the output potential Vout of the integrator 21 is fixed to the integration result (Vout1) of the integrator 21 in the first mode. At this time, the holding circuit 22 holds the integration result (Vout1) of the integrator 21 in the first mode and outputs it as the output potential Vbuf.

The integration result (Vout1) of the integrator 21 in the first mode is ideally 1.9V, but varies by, for example, about ±10% due to variations in the resistance value of the resistive element R11 and the capacitance value of the capacitive element C11. In other words, the integration result (Vout1) of the integrator 21 in the first mode varies in the range of 1.89V to 1.91V. Therefore, the output potential Vbuf of the holding circuit 22 also varies in the range of 1.89V to 1.91V.

After that, the control signal Res switches from L level to H level, and the control signal Set2 switches from L level to H level (time t34). As a result, the switch SW21 switches from OFF to ON, and the switches SW32 and SW34 switch from OFF to ON. Meanwhile, the switches SW22, SW24, SW31, and SW33 maintain the OFF state.

As a result, the selection circuit 23 outputs the potential Vbuf (the integration result of the integrator 21 in the first mode) from one output terminal and outputs the reference potential V3 from the other output terminal. The potential Vbuf output from one output terminal of the selection circuit 23 is input to one input terminal of the integrator 21 via node N23. The reference potential V3 output from the other output terminal of the selection circuit 23 is input to the other input terminal of the integrator 21 via node N24. Here, since the switch SW21 is in the on state, the output potential Vout of the integrator 21 indicates 2.0 V, which is the same as the reference potential V3. On the other hand, since the switch SW22 is maintained in the off state, the holding circuit 22 continues to output the integration result of the integrator 21 in the first mode as the output potential Vbuf. In other words, the holding circuit 22 continues to output the output potential Vbuf that varies in the range of 1.89 V to 1.91 V.

Then, the operation mode transitions from the preparation mode to the second mode. In the second mode, the integrator 21 performs a second integration (time t35 to t36).

Specifically, the control signal Res switches from H level to L level (time t35). This switches the switch SW21 from on to off. Meanwhile, the switches SW32 and SW34 maintain the on state, and the switches SW22, SW24, SW31, and SW33 maintain the off state.

As a result, the integrator 21 becomes capable of integration, and begins to integrate the potential difference between the potential Vbuf input to one input terminal (node N23) and the reference potential V3 input to the other input terminal (node N24) and output it as the output potential Vout. Here, the output potential Vout increases monotonically in the second mode.

This output potential Vout is output as a slope signal from the external output terminal Vout to the outside of the slope signal generating circuit 2.

The integrator 21 performs negative feedback operation so that the variation in the first integration result (Vout1) caused by the variation in the resistance value of the resistor element R11 and the variation in the capacitance value of the capacitor C11 is offset by the variation in the resistance value of the resistor element R11 and the variation in the capacitance value of the capacitor C11 during the second integration, thereby suppressing the variation in the output potential Vout in the second mode.

When the output potential Vout of the integrator 21 increases monotonically and reaches a predetermined value, the integration by the integrator 21 is completed and the operation mode transitions from the second mode to the initialization mode. In the initialization mode, as already described, the integrator 21 is initialized.

Specifically, the control signal Set switches from L level to H level, and the control signal Set2 switches from H level to L level (time t36). As a result, the switch SW24 switches from OFF to ON, and the switches SW32 and SW34 switch from ON to OFF. Meanwhile, the switches SW21, SW22, SW31, and SW33 maintain the OFF state.

As a result, the output potential Vout of the integrator 21 falls sharply to 2.0 V, which is the same as the reference potential V3.

By repeating this operation, the slope signal generating circuit 2 generates a sawtooth slope signal that rises gradually and falls sharply.

In this way, the slope signal generating circuit 2 according to this embodiment performs integration in two stages using one integrator 21, so that the variation in the first integration result due to the variation in the resistance value of the resistive element R11 and the variation in the capacitance value of the capacitive element C11 is offset by the variation in the resistance value of the resistive element R11 and the variation in the capacitance value of the capacitive element C11 during the second integration. As a result, the slope signal generating circuit 2 according to this embodiment can suppress the variation in the slope signal even more than the slope signal generating circuit 1. In other words, the slope signal generating circuit 2 according to this embodiment can generate a slope signal with higher accuracy.

In addition, the slope signal generating circuit 2 according to this embodiment can reduce the number of resistive elements and capacitive elements compared to the slope signal generating circuit 1, thereby reducing the circuit size.

(First Modification of Slope Signal Generating Circuit 2)
11 is a circuit diagram showing a slope signal generating circuit 2a as a first modified example of the slope signal generating circuit 2. Compared to the slope signal generating circuit 2, the slope signal generating circuit 2a does not include the switch SW24. Also, the switch SW34 is switched on and off in response to a control signal Set3 instead of the control signal Set2.

Figure 12 is a timing chart showing the operation of the slope signal generating circuit 2a. Below, only the differences from the slope signal generating circuit 2 will be explained.

In the first half of the initialization mode (time t30 to t31), the control signal Res is set to the H level, and the control signal Set3 is set to the H level. This turns on the switch SW21 and the switch SW34. This causes the reference potential V3 to propagate to the output terminal of the integrator 21 via the switches SW34 and SW21 in the ON state, so that the output potential Vout of the integrator 21 indicates 2.0 V, which is the same as the reference potential V3. The operation of the slope signal generating circuit 2a after time t31 is the same as that of the slope signal generating circuit 2, so a description thereof will be omitted.

The slope signal generating circuit 2a can achieve the same effect as the slope signal generating circuit 2. In addition, the slope signal generating circuit 2a can reduce the number of switches SW24.

(Second Modification of Slope Signal Generating Circuit 2)
13 is a circuit diagram showing a second modified example of the slope signal generating circuit 2 as a slope signal generating circuit 2b. The slope signal generating circuit 2 generates a sawtooth wave slope signal that rises gently and falls sharply. In contrast, the slope signal generating circuit 2b generates a sawtooth wave slope signal that falls gently and rises sharply.

Specifically, if the integration result (final potential) Vout of the integrator 21 in the first mode is Vout1, the reference potentials V1, V2, and V3 are adjusted so that the relationship V1>V2>Vout1>V3 holds between the reference potentials V1 to V3 and Vout1. In the example of FIG. 12, the reference potential V1 is adjusted to 3.3 V, the reference potential V2 is adjusted to 3.2 V, and considering that the integration result Vout1 of the integrator 21 in the first mode is 3.1±0.01 V, the reference potential V3 is adjusted to 3.0 V.

The rest of the configuration of the slope signal generating circuit 2b is the same as that of the slope signal generating circuit 2, so its description is omitted.

(Operation of Slope Signal Generating Circuit 2b)
Next, the operation of the slope signal generating circuit 2b will be described with reference to FIG.
14 is a timing chart showing the operation of the slope signal generating circuit 2b, which illustrates the waveform of the slope signal for one period of the sawtooth wave.

First, the operation mode is set to the initialization mode. In the initialization mode, the integrator 21 is initialized (times t40 to t42).

Specifically, first, the control signal Set is set to H level, the control signal Res is set to L level, the control signal Set1 is set to L level, and the control signal Set2 is set to L level (time t40). As a result, the switch SW21 is turned off, the switch SW22 is turned off, the switch SW24 is turned on, the switches SW31 and SW33 are turned off, and the switches SW32 and SW34 are turned off. As a result, the output potential Vout of the integrator 21 indicates 3.0 V, which is the same as the reference voltage V3.

After that, the control signal Set switches from H level to L level, the control signal Res switches from L level to H level, and the control signal Set1 switches from L level to H level (time t41). As a result, the switch SW21 switches from off to on, the switch SW22 switches from off to on, the switch SW24 switches from on to off, and the switches SW31 and SW33 switch from off to on. Meanwhile, the switches SW32 and SW34 maintain the off state.

As a result, the selection circuit 23 outputs a reference potential V1 from one output terminal and outputs a reference potential V2 from the other output terminal. The reference potential V1 output from one output terminal of the selection circuit 23 is input to one input terminal of the integrator 21 via node N23. The reference potential V3 output from the other output terminal of the selection circuit 23 is input to the other input terminal of the integrator 21 via node N24. Here, since the switch SW21 is in the on state, the output potential Vout of the integrator 21 indicates 3.2 V, which is the same as the reference potential V2. Therefore, the output potential Vbuf of the holding circuit 22 also indicates 3.2 V.

Then, the operation mode transitions from the initialization mode to the first mode. In the first mode, the integrator 21 performs the first integration (time t42 to t43).

Specifically, the control signal Res switches from H level to L level (time t42). This switches the switch SW21 from on to off. Meanwhile, the switches SW22, SW31, and SW33 maintain the on state, and the switches SW24, SW32, and SW34 maintain the off state.

As a result, the integrator 21 enters an integration-enabled state, and begins integrating the potential difference between the reference potential V1 input to one input terminal (node N23) and the reference potential V2 input to the other input terminal (node N24) to output the result as the output potential Vout. Here, the output potential Vout monotonically decreases in the first mode. Therefore, the output potential Vbuf of the holding circuit 22 also monotonically decreases in the first mode, just like Vout.

When the output potential Vout of the integrator 21 decreases monotonically and reaches the minimum value in the first mode, the integration by the integrator 21 is completed and the operation mode transitions from the first mode to the preparation mode. In the preparation mode, the integrator 21 prepares for the second integration (time t43 to t45).

Specifically, first, the control signal Set1 switches from H level to L level (time t43). As a result, the switch SW22 switches from on to off, and the switches SW31 and SW33 switch from on to off. Meanwhile, the switches SW21, SW24, SW32, and SW34 all remain in the off state.

As a result, the two output terminals of the selection circuit 23 are in an open state. Therefore, the output potential Vout of the integrator 21 is fixed to the integration result (Vout1) of the integrator 21 in the first mode. At this time, the holding circuit 22 holds the integration result (Vout1) of the integrator 21 in the first mode and outputs it as the output potential Vbuf.

The integration result (Vout1) of the integrator 21 in the first mode is ideally 3.1V, but varies by, for example, about ±10% due to variations in the resistance value of the resistive element R11 and the capacitance value of the capacitive element C11. In other words, the integration result (Vout1) of the integrator 21 in the first mode varies in the range of 3.09V to 3.11V. Therefore, the output potential Vbuf of the holding circuit 22 also varies in the range of 3.09V to 3.11V.

After that, the control signal Res switches from L level to H level, and the control signal Set2 switches from L level to H level (time t44). As a result, the switch SW21 switches from OFF to ON, and the switches SW32 and SW34 switch from OFF to ON. Meanwhile, the switches SW22, SW24, SW31, and SW33 remain in the OFF state.

As a result, the selection circuit 23 outputs the potential Vbuf (the integration result of the integrator 21 in the first mode) from one output terminal and outputs the reference potential V3 from the other output terminal. The potential Vbuf output from one output terminal of the selection circuit 23 is input to one input terminal of the integrator 21 via node N23. The reference potential V3 output from the other output terminal of the selection circuit 23 is input to the other input terminal of the integrator 21 via node N24. Here, since the switch SW21 is in the on state, the output potential Vout of the integrator 21 indicates 3.0 V, which is the same as the reference potential V3. On the other hand, since the switch SW22 is maintained in the off state, the holding circuit 22 continues to output the integration result of the integrator 21 in the first mode as the output potential Vbuf. In other words, the holding circuit 22 continues to output the output potential Vbuf that varies in the range of 3.09 V to 3.11 V.

Then, the operation mode transitions from the preparation mode to the second mode. In the second mode, the integrator 21 performs a second integration (time t45 to t46).

Specifically, the control signal Res switches from H level to L level (time t35). This switches the switch SW21 from on to off. Meanwhile, the switches SW32 and SW34 maintain the on state, and the switches SW22, SW24, SW31, and SW33 maintain the off state.

As a result, the integrator 21 becomes capable of integration, and begins to integrate the potential difference between the potential Vbuf input to one input terminal (node N23) and the reference potential V3 input to the other input terminal (node N24) and output it as the output potential Vout. Here, the output potential Vout decreases monotonically in the second mode.

This output potential Vout is output as a slope signal from the external output terminal Vout to the outside of the slope signal generating circuit 2.

The integrator 21 performs negative feedback operation so that the variation in the first integration result (Vout1) caused by the variation in the resistance value of the resistor element R11 and the variation in the capacitance value of the capacitor C11 is offset by the variation in the resistance value of the resistor element R11 and the variation in the capacitance value of the capacitor C11 during the second integration, thereby suppressing the variation in the output potential Vout in the second mode.

When the output potential Vout of the integrator 21 decreases monotonically and reaches a predetermined value, the integration by the integrator 21 is completed and the operation mode transitions from the second mode to the initialization mode. In the initialization mode, as already described, the integrator 21 is initialized.

Specifically, the control signal Set switches from L level to H level, and the control signal Set2 switches from H level to L level (time t46). As a result, the switch SW24 switches from OFF to ON, and the switches SW32 and SW34 switch from ON to OFF. Meanwhile, the switches SW21, SW22, SW31, and SW33 maintain the OFF state.

As a result, the output potential Vout of the integrator 21 rises sharply to 3.0 V, which is the same as the reference potential V3.

By repeating this operation, the slope signal generating circuit 2b generates a sawtooth-wave slope signal that falls gently and rises sharply.

In this way, the slope signal generating circuit 2b according to this embodiment performs integration in two stages using one integrator 21, so that the variation in the first integration result due to the variation in the resistance value of the resistive element R11 and the variation in the capacitance value of the capacitive element C11 is offset by the variation in the resistance value of the resistive element R11 and the variation in the capacitance value of the capacitive element C11 during the second integration. As a result, the slope signal generating circuit 2b according to this embodiment can suppress the variation in the slope signal even more than the slope signal generating circuit 1a. In other words, the slope signal generating circuit 2b according to this embodiment can generate a slope signal with higher accuracy.

In addition, the slope signal generating circuit 2b according to this embodiment can reduce the number of resistive elements and capacitive elements compared to the slope signal generating circuit 1a, thereby reducing the circuit size.

1 Slope signal generating circuit 1a Slope signal generating circuit 2 Slope signal generating circuit 2a Slope signal generating circuit 10 Pixel circuit 11 Integrator 12 Integrator 20_1 to 20_12 PWM signal generating circuit 21 Integrator 22 Holding circuit 23 Selection circuit 100 Display device A11 Operational amplifier A12 Operational amplifier A21 Operational amplifier A22 Operational amplifier C11 Capacitive element C12 Capacitive element C21 Capacitive element C22 Capacitive element D1 to D12 Light emitting element (diode)
R11 Resistor element R12 Resistor element R21 Resistor element SW11 to SW15 Switches SW21, SW22 Switches SW31 to SW34 Switches

Claims (16)

an integrating circuit that, in a first mode among operation modes including at least a first mode and a second mode, integrates a potential difference between a first reference potential and a second reference potential, and, in the second mode following the first mode , integrates a potential difference between a result of the integration in the first mode and a third reference potential to output a slope signal;
Slope signal generation circuit. The integrating circuit includes:
a first integrator that integrates a potential difference between the first reference potential and the second reference potential in the first mode;
an output fixing unit that fixes an integration result of the first integrator in the first mode;
a second integrator that integrates a potential difference between an integration result of the first integrator fixed by the output fixing unit and the third reference potential in the second mode to output the slope signal;
Equipped with
2. The slope signal generating circuit according to claim 1. When the first reference potential is V1, the second reference potential is V2, the third reference potential is V3, and the integration result of the first integrator in the first mode is Vout1, the relationship V1<V2<Vout1<V3 is satisfied.
3. The slope signal generating circuit according to claim 2. When the first reference potential is V1, the second reference potential is V2, the third reference potential is V3, and the integration result of the first integrator in the first mode is Vout1, the relationship V1>V2>Vout1>V3 is satisfied.
3. The slope signal generating circuit according to claim 2. The first integrator is
a first amplifier, the first reference potential being input to an inverting input terminal, the second reference potential being input to a non-inverting input terminal, and outputting an output signal of the first integrator from an output terminal;
a first resistor element provided between a first reference potential terminal to which the first reference potential is supplied and an inverting input terminal of the first amplifier;
a first capacitance element provided between an output terminal and an inverting input terminal of the first amplifier;
having
The output fixing unit is
a first switch element that is provided between the first reference potential terminal and a second reference potential terminal to which the second reference potential is supplied, the first switch element being turned off in the first mode and turned on in the second mode;
The second integrator is
a second amplifier, the integration result of the first integrator fixed by the output fixing unit being input to an inverting input terminal, the third reference potential being input to a non-inverting input terminal, and the slope signal being output from an output terminal;
a second resistor element provided between an output terminal of the first amplifier and an inverting input terminal of the second amplifier;
a second capacitance element provided between the output terminal and the inverting input terminal of the second amplifier;
having
5. The slope signal generating circuit according to claim 2, the first resistance element and the second resistance element are configured using the same material within a single chip;
The first capacitance element and the second capacitance element are configured using the same material within the same chip.
6. The slope signal generating circuit according to claim 5. the first resistor element and the second resistor element have substantially the same resistance value;
the first capacitance element and the second capacitance element have substantially the same capacitance value;
Let V1 be the first reference potential, V2 be the second reference potential, V3 be the third reference potential, R0 be the resistance value of each of the first resistive element and the second resistive element, C0 be the capacitance value of each of the first capacitive element and the second capacitive element, and t1 be the integration period by the first integrator in the first mode. t1 is expressed by the following formula:
is adjusted so that
7. The slope signal generating circuit according to claim 5 or 6. The integrating circuit includes:
a selection circuit which, in the first mode, selects the first reference potential and outputs it from a first output terminal, and selects the second reference potential and outputs it from a second output terminal, and which, in the second mode, selects a hold potential and outputs it from the first output terminal, and selects the third reference potential and outputs it from the second output terminal;
an integrator that integrates a potential difference between an output potential of the first output terminal of the selection circuit and an output potential of the second output terminal of the selection circuit and outputs the resulting potential as the slope signal;
a holding circuit that holds an integration result of the integrator in the first mode as the held potential;
Equipped with
2. The slope signal generating circuit according to claim 1. When the first reference potential is V1, the second reference potential is V2, the third reference potential is V3, and the integration result of the integrator in the first mode is Vout1, the relationship V1<V2<Vout1<V3 is satisfied.
9. The slope signal generating circuit according to claim 8. When the first reference potential is V1, the second reference potential is V2, the third reference potential is V3, and the integration result of the integrator in the first mode is Vout1, the relationship V1>V2>Vout1>V3 is satisfied.
9. The slope signal generating circuit according to claim 8. The integrator is
a first amplifier, which receives an output potential of a first output terminal of the selection circuit at an inverting input terminal, receives an output potential of a second output terminal of the selection circuit at a non-inverting input terminal, and outputs an output signal of the integrator from an output terminal;
a resistive element provided between a first output terminal of the selection circuit and an inverting input terminal of the first amplifier;
a capacitance element provided between an output terminal and an inverting input terminal of the first amplifier;
having
The slope signal generating circuit according to any one of claims 8 to 10. The holding circuit includes:
a second amplifier having a non-inverting input terminal to which the integration result of the integrator in the first mode is input and an inverting input terminal to which an output potential of the holding circuit is input;
The slope signal generating circuit according to claim 11. Let V1 be the first reference potential, V2 be the second reference potential, V3 be the third reference potential, R0 be the resistance value of the second resistive element, C0 be the capacitance value of the capacitive element, and t1 be the integration period by the integrator in the first mode. t1 is expressed by the following formula:
is adjusted so that
13. The slope signal generating circuit according to claim 11 or 12. A slope signal generating circuit according to any one of claims 1 to 13;
a PWM signal generating circuit that generates a PWM (Pulse Width Modulation) signal according to an external input signal by using the slope signal generated by the slope signal generating circuit;
Equipped with
PWM signal generation circuit. A light-emitting element;
a pixel circuit that drives the light emitting element by a PWM (Pulse Width Modulation) signal;
A display device comprising:
The pixel circuit includes:
A slope signal generating circuit according to any one of claims 1 to 13;
a PWM signal generating circuit that generates the PWM signal according to a video signal by using the slope signal generated by the slope signal generating circuit;
having
Display device. A method for generating a slope signal using an integrating circuit, comprising:
using the integrating circuit, integrating a potential difference between a first reference potential and a second reference potential;
A result of integrating a potential difference between the first reference potential and the second reference potential is held;
using the integration circuit, integrating a potential difference between the held integration result and a third reference potential, and outputting a slope signal;
Slope signal generation method.

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