JP7618951B2 - Power semiconductor devices and electronic equipment - Google Patents

Description

This application claims priority to Chinese Patent Application No. 202011379684.2, entitled “Power Semiconductor Device and Electronic Device,” filed with the State Intellectual Property Administration of China on November 30, 2020, which is hereby incorporated by reference in its entirety.

This application relates to the field of circuit technology, and in particular to power semiconductor devices and electronic devices.

With the technological development toward miniaturization of power integrated circuits and devices, power semiconductor devices, as one of the core electronics of power integrated circuits, also present development requirements for high integration, miniaturization, high performance, and low cost. For example, as a core component of the protection circuit of the battery management and charging system in electronic equipment, the power semiconductor device can effectively prevent the battery and charging load from over-discharging, over-charging, and over-current, thereby realizing output short circuit protection.

The power semiconductor devices in the protection circuit of the battery management and charging system are mainly switch devices made of metal oxide semiconductor field effect transistors (MOSFETs) fabricated with silicon materials. In addition, the field effect transistors used in the protection circuit of the battery management and charging system need to have bidirectional blocking and bidirectional turn-on functions to provide bidirectional protection for the lithium battery and the load circuit. A common solution in the industry is to symmetrically connect two MOSFETs of the same structure in series in common drain mode to form a common drain power semiconductor device. Figure 1 shows a semiconductor device in which two vertical MOSFETs are connected in series in common drain mode. The main structure of this power semiconductor device includes a substrate 4 and an epitaxial layer 3 disposed on the substrate 4, where the substrate 4 is a silicon substrate and the epitaxial layer 3 is a silicon epitaxial layer. Each MOSFET structure includes a gate 1 and a source 2 disposed on the surface of the epitaxial layer 3, and a channel (not shown) located in the epitaxial layer 3. A back metal is disposed on the bottom surface of the substrate as the common drain of the two MOSFETs. A drift region (not shown) corresponding to each MOSFET is disposed in the epitaxial layer 3. Two sources 2 are used as the input and output ends of the power semiconductor device, respectively, and two gates 1 control the input MOSFET and the output MOSFET to turn on or off, respectively.

When turned off, the gate of the MOSFET at the output end (or input end) is at a high level, the MOSFET at the input end (or output end) is turned on, but the gate of the MOSFET at the input end (or output end) is at a low level, and the MOS structure at the input end (or output end) is turned off to realize bidirectional withstand voltage blocking from the source of one (output end) MOSFET to the source of the other (input end) MOSFET. When turned on, both the gate of the MOSFET at the input end and the gate of the MOSFET at the output end are at a high level, and both the MOSFET at the input end and the MOSFET at the output end are turned on. In the direction of current flow indicated by the arrows in FIG. 1, the current flows from the source 2 of one MOSFET through the channel and drift region (located in the epitaxial layer 3 but not shown) to the substrate 4, and then through the drift region and channel of the other MOSFET to the source 2.

When the above-mentioned power semiconductor device is turned on, the current flows twice through the drift region in the epitaxial layer 3 and once through the substrate 4. The resistance of the drift region in the epitaxial layer 3 and the substrate resistance of the substrate 4 increase the on-resistance of the entire power semiconductor device. In addition, as the process size of the metal-oxide-semiconductor field-effect transistor is continuously reduced, the ratio of the resistance of the drift region and the resistance of the substrate to the total resistance also increases. Furthermore, since structures such as the gate 1 and source 2 are disposed on the surface of the epitaxial layer and arranged horizontally, it causes a waste of chip area of the power semiconductor device, which further increases the specific on-resistance per unit area and the cost per unit area of the device, and makes it difficult to miniaturize the power semiconductor device. With the same device area, the loss and temperature rise of the battery management and charging system protection circuitry are increased, and the charging efficiency is reduced.

This application provides a power semiconductor device and electronic device for improving the specific on-resistance per unit area of a power semiconductor device while satisfying the device's specific withstand voltage requirements, so that power semiconductor devices can progress toward miniaturization.

According to a first aspect, a power semiconductor device is provided. The power semiconductor device includes an epitaxial layer of a first doping type and two common drain metal oxide semiconductor field effect transistors, a trench is disposed in the epitaxial layer of the first doping type, and the two common drain metal oxide semiconductor field effect transistors are symmetrically connected back to back in parallel to form a cell. Each common drain metal oxide semiconductor field effect transistor includes a first metal oxide semiconductor structure and a second metal oxide semiconductor structure disposed along the depth direction of the trench, and the first metal oxide semiconductor structure and the second metal oxide semiconductor structure are connected in series with a common drain. The first metal oxide semiconductor structure includes a first source, a first channel, and a first gate. The first channel is disposed in the epitaxial layer of the first doping type, the first source is connected to the first channel, and the first source and the first channel are located on the same side of the trench. The first channel is a region of a second doping type disposed in the epitaxial layer of the first doping type. The first gate is disposed in the trench and is configured to control the first channel to turn on. The second metal oxide semiconductor structure includes a second source, a second channel, and a second gate. The second source is located at the bottom of the trench, and the second channel is located in the epitaxial layer of the first doping type and connected to the second channel. The second channel is a region of a second doping type disposed in the epitaxial layer of the first doping type. The second gate is disposed in the trench and is configured to control the second channel to turn on. When the above structure is specifically arranged, the first channel and the second channel are spaced apart from each other along the depth direction of the trench, and the portion of the epitaxial layer of the first doping type between the first channel and the second channel is a drift region, and the drift region and the first channel are located on the same side of the trench and are arranged above and below the first channel. The second gate and the first gate are spaced apart from each other along the depth direction of the trench. When the first gate and the second gate control the first channel and the second channel to turn on, respectively, a current flows along or in the opposite direction to the arrangement direction of the first source, the first channel, the part of the epitaxial layer of the first doping type between the first channel and the second channel (drift region), the second channel, and the second source. In addition, when the two common drain metal oxide semiconductor field effect transistors are specifically arranged, the two common drain metal oxide semiconductor field effect transistors share the second source, the two first channels of the two common drain metal oxide semiconductor field effect transistors are arranged on both sides of the trench, and the two first sources are arranged on both sides of the trench. In the above technical solution, the first gate and the second gate are arranged up and down along the depth direction of the trench, thereby reducing the size occupied by each common drain metal oxide semiconductor field effect transistor in the horizontal direction. In addition, the first metal oxide semiconductor structure and the second metal oxide semiconductor structure share the drift region, thereby reducing the resistance of the drift region and further reducing the specific on-resistance of the power semiconductor device per unit area.

In one particular implementation solution, each common drain metal oxide semiconductor field effect transistor further includes a first gate oxide layer insulating the first channel from the first gate and a second gate oxide layer insulating the second channel from the second gate, where the thickness of the first gate oxide layer and the thickness of the second gate oxide layer are essentially the same. The first gate oxide layer and the second gate oxide layer are used to reduce gate leakage, improve the voltage endurance capability of the gate, and improve the drive capability of the gate.

In one particular possible solution, the first gate oxide layer and the second gate oxide layer are disposed on the sidewalls of the trench. The first gate oxide layer disposed on the sidewalls of the trench is used to form a first gate structure disposed along the depth of the trench, thereby reducing the horizontal size of the power semiconductor device.

In one particular possible solution, the trench is filled with a fill layer that encases the first gate, the second gate, and the second source. The first gate, the second gate, and the second source are insulated by the fill layer.

In one particular possible solution, the second source is exposed outside the fill layer, and the portion of the second source exposed outside the fill layer is used as a connection end to facilitate connection to an external circuit.

In one particular possible solution, the first source portion is exposed outside the epitaxial layer of the first doping type, and the portion of the first source exposed outside the epitaxial layer of the first doping type is used as a connection end to facilitate connection to an external circuit.

In one particular implementation solution, a first source contact region is disposed on the epitaxial layer of the first doping type, and the first channel is connected to the first source via the first source contact region. By using the disposed first source contact region, the effect of the contact between the first source and the first channel is improved.

In one particular possible solution, the first source contact region includes a highly doped region of a first doping type and a highly doped region of a second doping type.

In one particular implementation solution, a second source contact region is disposed on the epitaxial layer of the first doping type, and the second channel is connected to the second source via the second source contact region. By using the disposed second source contact region, the effect of the contact between the second source and the second channel is improved.

In one particular possible solution, the second source contact region includes a highly doped region of a first doping type and a highly doped region of a second doping type.

In one particular implementation solution, the heavily doped region of the second doping type in the second source contact region is located below the bottom of the trench of the second source, and the heavily doped region of the first doping type in the second source contact region is located on one side of the second source.

In one particular possible solution, to reduce the size of the common drain metal oxide semiconductor field effect transistor and improve the device density, the trench is a linear trench and the first and second gates are disposed one above the other along the depth of the trench.

In one particular possible solution, the first gate and the second gate are staggered along the depth of the trench. This facilitates the placement of the first gate oxide layer, the second gate oxide layer, the first gate, and the second gate.

In one particular implementation solution, the trench is a T-trench, the second gate is located at the bottom of the T-trench, and the first gate is located at the step side of the T-trench. This facilitates the placement of the first and second gates.

According to a second aspect, an electronic device is provided. The electronic device includes a battery and a charging protection circuit connected to the battery, and the charging protection circuit includes any one of the power semiconductor devices described above. In the above technical solution, the drift region, the first gate, and the second gate are arranged vertically along the depth direction of the trench, thereby reducing the size occupied by each common drain metal oxide semiconductor field effect transistor in the horizontal direction. Furthermore, the first metal oxide semiconductor structure and the second metal oxide semiconductor structure share the drift region, thereby reducing the resistance of the drift region and further reducing the specific on-resistance of the power semiconductor device per unit area.

FIG. 1 is a schematic diagram of a structure of a power semiconductor device in the prior art; FIG. 2 is a schematic diagram of an application scenario of a power semiconductor device according to an embodiment of the present application. FIG. 1 is a cross-sectional view of a power semiconductor device according to an embodiment of the present application. FIG. 2 is a top view of a power semiconductor device according to an embodiment of the present application. FIG. 2 is a schematic diagram of a current of a power semiconductor device according to an embodiment of the present application. FIG. 2 is a schematic diagram of an application scenario of a power semiconductor device according to an embodiment of the present application. FIG. 2 is a schematic diagram of a simulation structure of a power semiconductor device according to an embodiment of the present application. 4 illustrates breakdown characteristics from a second MOS structure to a first MOS structure according to one embodiment of the present application. 2 illustrates breakdown characteristics from a first MOS structure to a second MOS structure according to one embodiment of the present application. 4 illustrates a changeover switch characteristic from a second MOS structure to a first MOS structure according to one embodiment of the present application. 2 illustrates a switching characteristic from a first MOS structure to a second MOS structure according to one embodiment of the present application. FIG. 1 is a cross-sectional view of a power semiconductor device according to an embodiment of the present application. FIG. 2 is a top view of a power semiconductor device according to an embodiment of the present application. FIG. 2 is a schematic diagram of a current of a power semiconductor device according to an embodiment of the present application. FIG. 2 is a schematic diagram of a simulation structure of a power semiconductor device according to an embodiment of the present application. 4 illustrates breakdown characteristics from a second MOS structure to a first MOS structure according to one embodiment of the present application. 2 illustrates breakdown characteristics from a first MOS structure to a second MOS structure according to one embodiment of the present application. 4 illustrates a changeover switch characteristic from a second MOS structure to a first MOS structure according to one embodiment of the present application. 2 illustrates a switching characteristic from a first MOS structure to a second MOS structure according to one embodiment of the present application.

The embodiments of this application will be described in further detail below with reference to the attached drawings.

In order to facilitate understanding of the power semiconductor device used in the embodiments of this application, the application scenario of the power semiconductor device provided in the embodiments of this application will be described first. The power semiconductor device provided in the embodiments of this application can be applied to a battery management and charging protection system of a portable electronic device such as a smartphone, a smart watch, or a tablet computer, or can be further applied to different scenarios such as a protection current conversion system and a power supply IC. In the battery protection system scenario shown in FIG. 2, a battery 5 is configured to supply power to a load 6, and a protection circuit is arranged between the battery 5 and the load 6. The protection circuit includes a power semiconductor device 7 and a control chip 8, and the power semiconductor device 7 includes two MOS structures 9 connected in series. In use, the control chip 8 can be configured to control the two MOS structures 9 to turn on. The power semiconductor device 7 can effectively prevent the battery from over-discharging, over-charging, and over-current (current exceeding the design range). However, the power semiconductor device in the prior art has an excessively large size and a relatively large specific on-resistance per unit area. In view of this, the embodiments of this application provide a power semiconductor device for appropriately improving the structure and layout of the power semiconductor device in order to facilitate miniaturization of the power semiconductor device and improve the specific on-resistance per unit area. The power semiconductor device will be described in detail below with reference to the attached drawings and embodiments.

To facilitate understanding of the power semiconductor device provided in the embodiments of this application, the following first explains the terms related to this application.

PN junction: P-type and N-type semiconductors are fabricated in the same semiconductor substrate (usually silicon or germanium) by using different doping processes through diffusion, and a space charge region is formed at the interface between the P-type and N-type semiconductors. The space charge region is known as a PN junction, and a PN junction is unidirectionally conductive.

Channel: The thin semiconductor layer between the source and drain regions in a field-powered semiconductor device.

Drift region: A highly resistive region within a power semiconductor device where only a very small number of carriers exist under the influence of both drift motion and diffusion.

Epitaxial layer: A semiconductor layer epitaxially grown on a substrate.

On-resistance: The resistance value of a power semiconductor device operating in the linear region.

Threshold voltage: Generally, the input voltage corresponding to the midpoint of the change region where the output current changes sharply with the input voltage in the transfer characteristic curve of a power semiconductor device is called the threshold voltage.

The first doping type and the second doping type in this embodiment of this application are P-type and N-type, respectively. For example, if the power semiconductor device is an electron conduction type, the first doping type is N-type and the second doping type is P-type, or if the power semiconductor device is a hole conduction type, the first doping type is P-type and the second doping type is N-type. In the following examples of this application, an example in which the first doping type is N-type and the second doping type is P-type is used for explanation. The description of the embodiment of this application is also applicable to the case in which the first doping type is P-type and the second doping type is N-type.

To facilitate understanding of the power semiconductor device provided in the embodiments of this application, the horizontal and vertical directions are defined. The vertical direction refers to the stacking direction of the layer structure of the power semiconductor device, and may also be referred to as the thickness direction of the power semiconductor device. The horizontal direction refers to a direction perpendicular to the vertical direction and parallel to the arrangement direction of two common drain metal oxide semiconductor field effect transistors in the power semiconductor device.

Figure 3 is a cross-sectional view of a power semiconductor device. The power semiconductor device includes at least a substrate 11 and an epitaxial layer 12 disposed on the substrate 11, where the substrate 11 and the epitaxial layer 12 are the two main layer structures on which the power semiconductor device is stacked. The power semiconductor device provided in this embodiment of the application may further include other layer structures (such as a passivation layer, an interconnect metal layer, and a back metal layer) that are conventionally disposed. To facilitate the description of the structure of the power semiconductor device, the other layer structures are omitted in this application.

The substrate 11 and the epitaxial layer 12 are arranged one above the other, the substrate 11 being a substrate of a first doping type, and the epitaxial layer 12 being an epitaxial layer of a first doping type. A trench 31 is disposed in the epitaxial layer 12, and the depth of the trench 31 extends vertically (in the thickness direction of the power semiconductor device). The substrate 11 and the epitaxial layer 12 form the device body of the power semiconductor device, and the epitaxial layer 12 is used as the main mechanical part for carrying the power semiconductor device.

According to the functional division, the power semiconductor device provided in this embodiment of the application includes two common drain metal oxide semiconductor field effect transistors (field effect transistors for short). For ease of explanation, the two common drain metal oxide semiconductor field effect transistors are referred to as a first field effect transistor 100 and a second field effect transistor 101, respectively. In one example, when the first field effect transistor 100 and the second field effect transistor 101 are arranged, the first field effect transistor 100 and the second field effect transistor 101 are arranged symmetrically along the center line of the trench 31, and the first field effect transistor 100 and the second field effect transistor 101 are connected in parallel to form a one-cell (not shown in FIG. 3) structure of the power semiconductor device. It should be understood that although FIG. 3 shows only one cell structure, the power semiconductor device provided in this embodiment of the application can include multiple cells, and the multiple cells can be arranged periodically. In this embodiment of the application, only one cell is used as an example for explanation.

The first field effect transistor 100 and the second field effect transistor 101 in this embodiment of the present application have a quasi-symmetric structure. Therefore, the first field effect transistor 100 is used as an example for explanation.

Please refer to FIG. 3. The field effect transistor 100 includes a first metal-oxide-semiconductor structure (first MOS structure) and a second metal-oxide-semiconductor structure (second MOS structure), and the first MOS structure 10 and the second MOS structure 20 are connected in series. When the first MOS structure 10 and the second MOS structure 20 are arranged, the first MOS structure 10 and the second MOS structure 20 are arranged one above the other. Between the first MOS structure 10 and the second MOS structure 20, there is a portion of the epitaxial layer of the first doping type. The portion of the epitaxial layer of the first doping type is used as a drift region 30 and is shared by the first MOS structure 10 and the second MOS structure 20.

The first MOS structure 10 includes a first gate 51, a first source 61, and a first channel 21, and the first gate 51 is used as a control component connected to the first MOS structure 10 and is configured to be connected to a control chip. The first gate 51 is configured to control the first channel 21 to be turned on or off under the control of the control chip.

The first source 61 of the first MOS structure 10 is used as a connection terminal of the first MOS structure 10 and can be made of a metal material or a metal-like material (such as TiN or silicide). When disposed, the first source 61 can be disposed on the surface of the epitaxial layer 12, or can be partially or completely buried in the epitaxial layer 12. FIG. 3 is only a schematic diagram of a structure in which the first source 61 is completely buried in the epitaxial layer 12. Other methods will not be described one by one here. When the first source 61 is completely buried in the epitaxial layer 12, the surface of the first source 61 is exposed outside the epitaxial layer 12, and the surface is used as the connection surface of the first source 61 to connect to other metal layers or interconnect metals (not shown in FIG. 3).

The first channel 21 is disposed in the epitaxial layer 12, and the first channel 21 and the first source 61 are disposed on the same side of the trench 31. The first channel 21 is close to the sidewall of the trench 31, and the first source 61 is far away from the sidewall of the trench 31.

The first channel 21 is a region of the second doping type. When the first channel 21 is formed, a doped region of the second doping type is disposed in the epitaxial layer 12 on the sidewall of the trench 31 to form the first channel 21. The first channel 21 extends vertically along the sidewall of the trench 31 and contacts the drift region 30. Since the first channel 21 is a region of the second doping type and the drift region 30 is a region of the first doping type, a PN junction can be formed between the drift region 30 and the first channel 21. When no voltage is applied to the first gate 51, or when a voltage of 0 or a negative voltage is applied to the first gate 51 with respect to the first source 61, the PN junction between the first channel 21 and the drift region 30 is turned off, and therefore the conduction channel from the first source 61 to the first channel 21 and thus to the drift region 30 is closed. Under the action of a voltage applied by the first gate 51, a portion of the region of the first channel 21 near the sidewall of the trench 31 may form an inversion layer and convert the second doping conductivity type to the first doping conductivity type, thereby turning on a conducting channel from the first channel 21 to the drift region 30. In this case, the first source 61, the first channel 21, and the drift region 30 are turned on.

The first gate 51 is disposed in the trench 31 and faces the first channel 21. When a voltage is applied to the first gate 51, the first channel 21 can be controlled to turn on.

In one optional solution, the first MOS structure 10 further includes a first gate oxide layer 41 insulating the first channel 21 from the first gate 51. The first gate oxide layer 41 is disposed on the sidewalls of the trench 31 and is located between the first gate 51 and the first channel 21. The disposed first gate oxide layer 41 suppresses an increase in leakage current between the first channel 21 and the first gate 51 and improves the voltage resistance capability of the gate.

In an optional solution, a first source contact region (not shown) is further arranged in the epitaxial layer 12, through which the first source 61 is connected to the first channel 21. The first source contact region includes a highly doped region 13 of a first doping type and a highly doped region 23 of a second doping type.

The heavily doped region 13 of the first doping type is disposed in the epitaxial layer 12 between the first source 61 and the trench 31, and between the first source 61 and the first channel 21. The heavily doped region 13 of the first doping type is in contact with both the first source 61 and the first channel 21 to form a conductive channel including the first source 61, the heavily doped region 13 of the first doping type, the first channel 21, and the drift region 30. The doping concentration of the heavily doped region 13 of the first doping type is generally at least one order of magnitude higher than the doping concentration of other doped regions (e.g., the epitaxial layer 12) so as to improve the resistance when the metal is connected to the semiconductor. When the heavily doped region 13 of the first doping type is connected to both the first source 61 and the first channel 21, the ohmic contact resistance between the first source 61 and the epitaxial layer 12 can be reduced by using the heavily doped region 13 of the first doping type.

The heavily doped region 23 of the second doping type is located in the epitaxial layer 12 between the first source 61 and the first channel 21 and without contacting the trench 31. The heavily doped region 23 of the second doping type is in contact with both the first source 61 and the first channel 21. The doping concentration of the heavily doped region 23 of the second doping type is generally at least one order of magnitude higher than the doping concentration of the other doped region (e.g., the first channel 21). By using the heavily doped region 23 of the second doping type, the contact between the first source 61 and the first channel 21 can be improved.

The second MOS structure 20 and the first MOS structure 10 are arranged one above the other. The second MOS structure 20 includes a second gate 52, a second source 62, and a second channel 22. The second gate 52 is used as a control component connected to the second MOS structure 20 and is configured to control the second channel 22. The second gate 52 is configured to control the second channel 22 to be turned on or off under the control of the control chip.

The second source 62 of the second MOS structure 20 is used as a terminal of the second MOS structure 20 and may be made of a metal material or a metal-like material. When the second source 62 is disposed, the second source 62 is disposed in the trench 31, extends along the bottom of the trench 31 to the outside of the trench 31, and is exposed to the surface of the epitaxial layer 12. The second source 62 extends to the surface of the epitaxial layer 12 as the connection surface of the second source 62.

The second channel 22 is a region of the second doping type. When the second channel 22 is formed, a doped region of the second doping type is disposed in the epitaxial layer 12 below the bottom of the trench 31 to form the second channel 22. Since the second channel 22 is a region of the second doping type and the drift region 30 is a region of the first doping type, a PN junction can be formed between the drift region 30 and the second channel 22. When no voltage is applied to the second gate 52, or when a voltage of 0 or a negative voltage is applied to the second gate 52 with respect to the second source 62, the PN junction between the second channel 22 and the drift region 30 is turned off, and therefore the conduction channel from the second source 62 to the second channel 22 and the drift region 30 is closed. Under the action of the voltage applied by the second gate 52, an inversion layer is formed in the part of the region of the second channel 22 near the bottom and sidewalls of the trench 31, and the second doping conductivity type is converted to the first doping conductivity type, so that a conductive channel from the second source 62 to the second channel 22 and the drift region 30 can be turned on. Referring to the case where the first channel 21 in the first MOS structure 10 is turned on, when the first gate 51 controls the first channel 21 to be turned on and the second gate 52 controls the second channel 22 to be turned on, a conductive channel including the first source 61, the first channel 21, the drift region 30, the second channel 22, and the second source 62 is formed.

The second gate 52 is disposed in the trench 31 and faces the second channel 22. When a voltage is applied to the second gate 52, the second channel 22 can be controlled to turn on.

In one optional solution, the second MOS structure 20 further includes a second gate oxide layer 43 that insulates the second channel 22 from the second gate 52. The second gate oxide layer 43 is disposed on the sidewalls and bottom of the trench 31 and is located between the second gate 52 and the second channel 22. The disposed second gate oxide layer 43 suppresses an increase in leakage current between the second channel 22 and the second gate 52 and improves the voltage resistance capability of the gate.

In an optional solution, a second source contact region (not shown) is further disposed in the epitaxial layer 12, through which the second source 62 is connected to the second channel 22. The second source contact region includes a heavily doped region 14 of the first doping type and a heavily doped region 24 of the second doping type.

The heavily doped region 14 of the first doping type is disposed in the epitaxial layer 12 at the bottom of the trench 31 and is located on one side of the second source 62. The heavily doped region 14 of the first doping type contacts both the second source 62 and the second channel 22 to form a conductive channel including the second source 62, the heavily doped region 14 of the first doping type, the second channel 22, and the drift region 30. The doping concentration of the heavily doped region 14 of the first doping type is generally at least one order of magnitude higher than the doping concentration of other doped regions (e.g., the epitaxial layer 12) so that the resistance when a metal is connected to a semiconductor can be improved. When the heavily doped region 14 of the first doping type is connected to both the second source 62 and the second channel 22, the ohmic contact resistance between the second source 62 and the epitaxial layer 12 can be reduced by using the heavily doped region 14 of the first doping type.

The second source contact region's highly doped region 24 of the second doping type is disposed at the bottom of the second source 62, and the highly doped region 24 of the second doping type contacts both the second source 62 and the second channel 22. The doping concentration of the highly doped region 24 of the second doping type is generally at least one order of magnitude higher than the doping concentration of the other doped region (e.g., the second channel 22). By using the highly doped region 24 of the second doping type, the contact between the second source 62 and the second channel 22 can be improved.

In one optional solution, the trench 31 is filled with a fill layer 42 that encases the first gate 51, the second gate 52, and the second source 62 to insulate and protect the above-mentioned components. It should be understood that, if the fill layer 42 is present, the second source 62 is exposed outside the fill layer to facilitate connection to another circuit.

Referring to FIG. 3, it can be seen that when the first MOS structure 10 and the second MOS structure 20 are specifically arranged, the first MOS structure 10 and the second MOS structure 20 are arranged vertically, and therefore the lateral size of the field effect transistor can be reduced. In addition, the first gate 51 and the second gate 52 are arranged at the upper limit along the depth direction of the trench 31, and therefore the first MOS structure 10 and the second MOS structure 20 can share the vertically arranged drift region 30. Furthermore, the drift region 30 is located between the first channel 21 and the second channel 22 and does not occupy the lateral size of the power semiconductor device, which further reduces the size of the power semiconductor device and improves the arrangement density of the device.

The structure of the second field effect transistor 101 is the same as that of the first field effect transistor 100. The two first channels of these two common drain metal oxide semiconductor field effect transistors are disposed on both sides of the trench, and the two first sources are disposed on both sides of the trench. In an optional solution, the first field effect transistor 100 and the second field effect transistor 101 share some components in order to reduce the size of the device to be disposed. As shown in FIG. 3, the two field effect transistors share the second source 62. The second channels 22 of the two field effect transistors can be connected to each other, but the second channels 22 of the two field effect transistors are controlled separately by using two different second gates 52 correspondingly.

Figure 4 is a top view of a power semiconductor device. With reference to Figures 3 and 4, it can be seen that the components of the power semiconductor device are arranged in a lateral direction, and the first field effect transistor 100 and the second field effect transistor 101 adjacent to each other are mirror symmetric (along the center line of the trench). The first source 61, the heavily doped region 13 of the first doping type, the first gate oxide layer 41, the filling layer 42, and the second source 62 extend in sequence on the surface of the epitaxial layer 12 along the lateral direction. Two adjacent field effect transistors are mirror symmetric to form a cell. When there are multiple cells, the multiple cells can be arranged periodically and repeatedly along the lateral direction.

5 is a schematic diagram of a current of a power semiconductor device according to an embodiment of this application. For the reference symbols in FIG. 5, please refer to the same symbols in FIG. 3. The first gate 51 and the second gate 52 are the control ports of the power semiconductor device. The first source 61 is the output port of the power semiconductor device, and the second source 62 is the input port of the power semiconductor device. When a positive voltage is applied to the first gate 51 and the second gate 52, the levels of the first gate 51 and the second gate 52 become high relative to the levels of the first source 61 and the second source 62, and both the first channel 21 and the second channel 22 are opened. As shown by the dashed arrow in FIG. 5, a current can flow along a first path, which refers to a path that passes through the first source 61, the first channel 21, the drift region between the first channel 21 and the second channel 22, the second channel 22, and the second source 62 in order. Alternatively, as shown by the solid arrow in FIG. 5, the current flows along the second path, which refers to a path that passes through the second source 62, the second channel 22, the drift region between the first channel 21 and the second channel 22, the first channel 21, and the first source 61 in this order. When no positive voltage is applied to the first gate 51, the level of the first gate 51 is low relative to the first source 61, and the first channel 21 is closed, or when no positive voltage is applied to the second gate 52, the level of the second gate 52 is low relative to the first source 61, and the second channel 22 is closed.

From the above description, it can be seen that in the power semiconductor device provided in this embodiment of the application, the first MOS structure 10 and the second MOS structure 20 are structures that share a drift region, and the two implanted body regions (first channel 21 and second channel 22) of the second doping type and the intermediate drift region of the first doping type can form a P-N-P common cathode back-to-back diode, and therefore the first MOS structure 10 and the second MOS structure 20 can form a common drain metal oxide semiconductor field effect transistor and realize a bidirectional withstand voltage. The power semiconductor device provided in this embodiment of the application uses a structural design in which the vertical drift region and two gates are arranged one above the other, thereby reducing the size occupied by each field effect transistor in the lateral direction. Also, the first MOS structure 10 and the second MOS structure 20 share a vertical drift region, so that the current does not pass through the substrate when it flows. Therefore, when the power semiconductor device is turned on, it does not have a substrate resistance but has a smaller channel resistance, thereby reducing the resistance of the power semiconductor device.

Figure 6 is a schematic diagram of an application scenario of a power semiconductor device according to an embodiment of this application. The cathode of a battery 200 is connected to a load 300 through a battery management and charging protection circuit. The power semiconductor device provided in this embodiment of this application is arranged on a circuit as a structure for protecting the battery 300. In the circuit, the first field effect transistor 100 and the second field effect transistor 101 of the power semiconductor device are connected in parallel, and the first MOS structure 10 and the second MOS structure 20 of the first field effect transistor 100 are connected in series. Both the first MOS structure 10 and the second MOS structure 20 are controlled by a control chip 400. The control chip 400 controls the levels of the first gate and the second gate to control the first MOS structure 10 and the second MOS structure 20 to turn on or off.

The power semiconductor device provided in this embodiment of the application also uses a planar device structure (as shown in FIG. 4), and the second MOS structure 20 may use a Laterally Diffused Metal Oxide Semiconductor (LDMOS) structure design to achieve Wafer Level Chip Scale Packaging (WLCSP) packaging.

To verify the technical effect of the power semiconductor device provided in this embodiment of this application, the power semiconductor device provided in this embodiment of this application is simulated using semiconductor TCAD (Technology Computer Aided Design, which is a tool used for semiconductor process simulation and device simulation).

In the example of simulating using an N-type common drain field effect transistor with a bidirectional blocking voltage of 15V, the structural parameters of the field effect transistor are shown in Table 1 and FIG. 7. The lateral size 1 of the single common drain effect transistor is 0.5 μm, that is, the size of the cell of the power semiconductor device is 1 μm. An N-type epitaxial layer with a doping concentration of 1.3e17 cm ⁻³ and a thickness 3 of 3 μm is disposed on an N-type substrate with a concentration of 1.8e19 cm ⁻³ and a thickness 2 of 1 μm to form the body of the power semiconductor device. A trench with a depth 12 of 1 μm and a half width of 0.35 μm is formed on the surface of the body of the field effect transistor. A first P-type channel (first channel) with a potential well depth 4 of 0.28 μm and a potential well width 6 of 0.16 μm is formed on the surface of the device body by P-type ion implantation, with an implantation dose of 1.35e13 cm ⁻³ . An N-type heavily doped region is formed using an N-type ion implantation and etching process with a depth 8 of 0.15 μm and a width 10 of 0.1 μm, and a P-type heavily doped region is formed using a P-type ion implantation and etching process with a depth 9 of 0.15 μm and a width 11 of 0.1 μm. At the bottom of the trench, a second P-type channel (second channel) is formed by P-type ion implantation with a potential well depth 5 of 0.45 μm, a potential well half width 13 of about 0.35 μm, and a channel length 7 of 0.18 μm, with implant doses of 1.2e13 cm ⁻³ and 6e13 cm ⁻³ . A gate oxide layer having a thickness of 250 Å (not shown in FIG. 7, but located between G1/G2 and the sidewall of the trench) is disposed on the sidewall of the trench and filled with polysilicon having a depth 14 of 0.35 μm and a width 16 of 0.18 μm, and polysilicon having a depth 15 of 0.18 μm and a width 10 of 0.18 μm to form gate G1 (first gate) and gate G2 (second gate), respectively. Gate G1 and gate G2 are insulated via a filling layer having a thickness 17 of 0.3 μm. The threshold voltage of the power field effect transistor, i.e., the threshold voltage of the power semiconductor device, depends on the thickness of the gate oxide layer and the concentration of the P-type channel. The breakdown voltage and on-resistance of the power field effect transistor, i.e., the breakdown voltage and on-resistance of the power semiconductor device, are determined by factors such as the concentration, depth, and length of the N-type drift region, the concentration and length of the P-type channel region, the thickness of the oxide layer, and the trench depth.

A simulation was performed for the power semiconductor device in Table 1, and the simulation results are shown in Figures 8a and 8b. Figures 8a and 8b are simulation curves of the breakdown voltage characteristics of the device. When the potentials of the first gate and the first source (source S1) are at a low level, the voltages of the second source and the second gate gradually increase from 0V, and the current of the second source (source S2) is gradually read out. When the current of the second source suddenly changes to 1 μA/mm, the corresponding voltage of the second source is the breakdown voltage of the second MOS structure, that is, the breakdown voltage from the second source to the first source. It can be seen from Figure 8a that the breakdown voltage of the second MOS structure is 15V. Similarly, the breakdown voltage of the first MOS structure is the breakdown voltage from the first source to the second source. It can be seen from Figure 8b that the breakdown voltage of the first MOS structure is 15V.

9a and 9b are simulation curves of the changeover switch characteristics of the power semiconductor device. When the potential of the first source is at a low level and the second source is connected to a fixed voltage of 0.1V, the current of the first gate and the current of the second gate gradually increase from 0V and 0.1V, respectively, and the current of the second source is gradually read out. The corresponding voltage of the first gate when the current of the second source suddenly increases to 1μA/mm is the threshold voltage of the first MOS structure. As shown in FIG. 9a, the simulation result of the threshold voltage of the first MOS structure is 0.8V. The corresponding voltage of the second gate when the first source current suddenly increases to 1μA/mm is the threshold voltage of the second MOS structure. As shown in FIG. 9b, the simulation result of the threshold voltage of the second MOS structure is 0.8V.

Also, as shown in FIGS. 9a and 9b, when the gate-source bias voltage of the power semiconductor device is 3.1 V, the specific on-resistance of the common-drain power semiconductor device in the embodiment of this application is only about 5 mΩ·mm ² .

It can be seen from the above experimental verification that in the power semiconductor device provided in the embodiment of this application, when the first MOS structure and the second MOS structure share a vertical drift region and the first gate and the second gate are distributed up and down, the breakdown characteristic of the device can meet 15V, and the on-resistance per unit area is only 5mΩ· ^mm2 . Meanwhile, in a power semiconductor device currently used in the industry in which two MOSFETs are connected back to back in series in common drain mode, when the breakdown voltage is 12V, the specific on-resistance per unit area of the power semiconductor device is 10.6mΩ· ^mm2 (data source: Panasonic product data FCAB21490L - Gate resistor installed Dual N-channel MOSFET For lithium-ion secondary battery protection circuits, 2016). Therefore, compared with the existing power semiconductor devices in the industry, the on-resistance per unit area of the power semiconductor device provided in the embodiment of this application can be reduced by 53%, and the breakdown voltage can be increased to 15V or higher.

In order to facilitate understanding of the power semiconductor device provided in the embodiment of this application, the manufacturing process of the power semiconductor device will be described in detail below. The formation of a field effect transistor is used as an example. The power semiconductor device can be manufactured based on conventional discrete trench MOS or integrated BCD (Bipolar CMOS DMOS, bipolar complementary metal oxide semiconductor double diffused metal oxide semiconductor) process technology. With reference to the structure shown in FIG. 3, the specific manufacturing method is as follows:

An N-type doped epitaxial layer 12 having a specific doping concentration is epitaxially grown on an N-type substrate 11, and the epitaxial layer 12 is then etched to form a trench 31.

A P-type doped region is formed by ion implantation in the epitaxial layer 12 below the bottom of the trench 31 to form the second channel 22, and a P-type doped region is formed in the epitaxial layer 12 outside the top of the trench 31 to form the first channel 21.

Thermal oxidation forms a gate oxide layer in the trench 31, which covers the bottom and sidewalls of the trench 31.

The trench is filled with polysilicon and an etching process is used to form the second gate 52. The second gate 52 faces the second channel 22 so that the second channel 22 can be controlled to turn on. The portion of the gate oxide layer that insulates the second gate 52 from the second channel 22 is the second gate oxide layer 43.

In the epitaxial layer 12, the N-type highly doped region 13 and the N-type highly doped region 14 are formed by ion implantation. A fill layer 42 is deposited in the trench 31 by chemical vapor deposition, and the oxide layer 42 is filled only in the trench using a CMP (chemical mechanical polishing) process. For example, the fill layer 42 can be an oxide layer.

A portion of the fill layer 42 is removed by etching, and the surface of the fill layer remaining after etching is the surface for supporting the first gate 51. When the fill layer 42 is etched, a portion of the gate oxide layer is also etched away.

Thermal oxidation recreates a gate oxide layer on the sidewalls of the trench 31, which is the first gate oxide layer 41. The thickness of the first gate oxide layer 41 is essentially the same as the thickness of the second gate oxide layer 43. When applied to the sidewalls of the trench 31, the disposed first gate oxide layer 41 can be used to insulate the first gate 51 from the first channel 21.

Polycrystalline silicon is deposited on the fill layer remaining after etching, and an etching process is used to form the first gate 51. The fill layer is continuously deposited in the trench by chemical vapor deposition and etching.

The fill layer above the ohmic contact region in the trench is removed by etching, and a separate P-type highly doped region 23 and a separate P-type highly doped region 24 are formed by ion implantation on the surface of the epitaxial layer 12 and in the ohmic contact region at the bottom of the trench 31. Finally, metal is deposited to form the first source 61 and the second source 62.

The P-type highly doped region 23 is formed in the ohmic contact region on the surface of the epitaxial layer 12 by ion implantation, and finally metal is deposited to form the first source 61.

Figure 10 is a schematic diagram of another power semiconductor device structure according to an embodiment of this application. The structure of the power semiconductor device shown in Figure 10 is similar to the structure of the power semiconductor device shown in Figure 3, and differs only in the arrangement of the internal structure of the device.

For some reference numbers in FIG. 10, please refer to the same reference numbers in FIG. 3. Details will not be described again here. The trench shown in FIG. 10 is a T-shaped trench, which includes a first trench 32 and a second trench 33. The second gate 52 is disposed at the bottom of the T-shaped trench (the bottom of the second trench 33), and the first gate 51 is disposed at the step surface of the T-shaped trench (the bottom of the first trench 32).

As can be seen from FIG. 10, the first gate 51 and the second gate 52 are staggered along the depth direction of the trench. Compared to the power semiconductor device shown in FIG. 3, the first gate 51 can be placed directly at the bottom of the first trench 32, which makes it easier to position the first gate 51 during placement and improves the accuracy of placing the first gate 51. In addition, when the trench shown in FIG. 10 is used, the first gate 51 and the second gate 52 can be formed simultaneously by a single polycrystalline silicon etching process when the gate oxide layer is manufactured, which can simplify the manufacturing process.

11 is a top view of a power semiconductor device. Referring to FIG. 10 and FIG. 11, it can be seen that the components of the power semiconductor device are arranged in a lateral direction, and the first field effect transistor 100 and the second field effect transistor 101 adjacent to each other are mirror symmetric (along the center line of the trench). The first source 61, the heavily doped region 13 of the first doping type, the first gate oxide layer 41, the filling layer 42, and the second source 62 extend in sequence on the surface of the epitaxial layer 12 along the lateral direction. Two adjacent field effect transistors are mirror symmetric to form a cell. When there are multiple cells, the multiple cells can be arranged periodically and repeatedly along the lateral direction.

12 is a schematic diagram of a current in a power semiconductor device according to an embodiment of this application. The first gate 51 and the second gate 52 are the control ports of the power semiconductor device. The first source 61 is the input port of the power semiconductor device, and the second source 62 is the output port of the power semiconductor device. When a voltage is applied to the first gate 51 and the second gate 52, the levels of the first gate 51 and the second gate 52 become high relative to the levels of the first source 61 and the second source 62, and both the first channel 21 and the second channel 22 are opened. As shown by the dashed arrow in FIG. 5, a current can flow along a first path, which refers to a path that passes through the first source 61, the first channel 21, the drift region between the first channel 21 and the second channel 22, the second channel 22, and the second source 62 in order. Alternatively, as shown by the solid arrow in FIG. 5, the current flows along the second path, which refers to a path that passes through the second source 62, the second channel 22, the drift region between the first channel 21 and the second channel 22, the first channel 21, and the first source 61 in this order. When no positive voltage is applied to the first gate 51, the level of the first gate 51 is low relative to the first source 61, and the first channel 21 is closed, or when no positive voltage is applied to the second gate 52, the level of the second gate 52 is low relative to the first source 61, and the second channel 22 is closed.

In order to verify the technical effect of the present invention, the structural parameters and performance parameters of the device in this embodiment of this application are simulated by using semiconductor TCAD. The structural parameters of the field effect transistor are shown in Table 2 and Figure 13. An N-type epitaxial layer with a doping concentration of 1.3e17cm ^-3 and a thickness of 3μm is disposed on an N-type substrate with a doping concentration of 1.8e19cm ^-3 to form a device body. A first trench with a depth of 0.6μm and a width of 0.55μm is formed on the surface of the device body. The bottom of the first trench is further etched to form a second trench with a depth of 0.3μm and a width of 0.35μm. At the surface of the device body, a first P-type channel (first channel) is formed by P-type ion implantation with ^a potential well depth of 0.28 μm and a channel length of 14 μm, a heavily doped region of a first doping type with a depth of 0.15 μm and a width of 0.1 μm is formed by N-type ion implantation, and a heavily doped region of a second doping type with a depth of 0.15 μm and a width of 0.1 μm is formed by P-type ion implantation. At the bottom of the second trench, a second P-type channel (second channel) is formed by P-type ion implantation with a potential well depth of 0.55 μm and a channel length of 0.21 μm. A gate oxide layer having a thickness of 250 Å is disposed in the first trench and the second trench. Polysilicon with a depth of 0.4 μm and a width of 0.18 μm and polysilicon with a depth of 0.2 μm and a width of 0.18 μm are filled to form a first gate (gate G1) and a second gate (gate G2), respectively. The threshold voltage of the power semiconductor device depends on the thickness of the gate oxide layer and the concentration of the P-type well region. The breakdown voltage and on-resistance of the device are determined by factors such as the concentration, depth, and length of the N-type drift region, the concentration and length of the P-type channel region, the thickness of the oxide layer, and the trench depth.

A simulation was performed for the power semiconductor device in Table 2, and the simulation results are shown in Figures 14a and 14b. Figures 14a and 14b are simulation curves of the breakdown voltage of the power semiconductor device. When the potentials of the first gate and the first source (source S1) are at a low level, the voltages of the second source and the second gate gradually increase from 0V, and the current of the second source (source S2) is gradually read out. When the current of the second source suddenly changes to 1 μA/mm, the corresponding voltage of the second source is the breakdown voltage of the second MOS structure, that is, the breakdown voltage from the second source to the first source. It can be seen from Figure 14a that the breakdown voltage of the second MOS structure is 15V. Similarly, the breakdown voltage of the first MOS structure is the breakdown voltage from the first source to the second source. It can be seen from Figure 14b that the breakdown voltage of the first MOS structure is 15V.

15a and 15b are simulation curves of the changeover switch characteristics of the power semiconductor device. When the potential of the first source is at a low level and the second source is connected to a fixed voltage of 0.1V, the current of the first gate and the current of the second gate gradually increase from 0V and 0.1V, respectively, and the current of the second source is gradually read out. The corresponding voltage of the first gate when the current of the second source suddenly increases to 1μA/mm is the threshold voltage of the first MOS structure. As shown in FIG. 15a, the simulation result of the threshold voltage of the first MOS structure is 0.9V. The corresponding voltage of the second gate when the second source current suddenly increases to 1μA/mm is the threshold voltage of the second MOS structure. As shown in FIG. 15b, the simulation result of the threshold voltage of the second MOS structure is 0.9V.

Also, when the breakdown voltage of the power semiconductor device is 15V and its gate-source bias voltage is 3.1V, the specific on-resistance of both the first MOS structure and the second MOS structure in this embodiment of this application is only about 7mΩ· ^mm2 .

It can be seen from the above experimental verification that in the power semiconductor device provided in this embodiment of the application, when two MOS structures share a vertical drift region, the first gate and the second gate are staggered and distributed, and a lateral trench is used, the on-resistance per unit area is 7 mΩ·mm ^2. Meanwhile, in a power semiconductor device currently used in the industry in which two MOS structures are connected in series in a back-to-back common drain mode, when the breakdown voltage is 12 V, the specific on-resistance per unit area of the power semiconductor device is 10.6 mΩ·mm ² (data source: Panasonic product data FCAB21490L - Gate resistor installed Dual N-channel MOSFET For lithium-ion secondary battery protection circuits, 2016). Therefore, compared with the existing power semiconductor devices in the industry, the on-resistance per unit area of the power semiconductor device provided in the embodiment of the application can be reduced by 33%, and the breakdown voltage can be increased to 15 V or higher. Also, the first gate and the second gate are arranged in a staggered manner. This can simplify the manufacturing process and improve production efficiency.

An embodiment of this application further provides an electronic device, such as a notebook computer, a mobile phone, a wearable device, or a tablet computer. The electronic device includes a battery and an output circuit connected to the battery, and the output circuit includes any one of the power semiconductor devices described above. In the above technical solution, the first gate and the second gate are arranged one above the other along the depth direction of the trench to reduce the size occupied by each common drain metal oxide semiconductor field effect transistor in the horizontal direction. In addition, the first metal oxide semiconductor structure and the second metal oxide semiconductor structure share a drift region, thereby reducing the resistance of the drift region. Furthermore, two identical common drain metal oxide semiconductor field effect transistors are symmetrically connected back to back in parallel, so that the resistance of the power semiconductor device is half that of when the power semiconductor device uses a single common drain metal oxide semiconductor, thereby reducing the specific on-resistance per unit area of the power semiconductor device.

Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application, and this application intends to cover those modifications and variations to this application as long as they fall within the scope of protection defined by the following claims of this application and their equivalent technologies.

Claims (12)

A power semiconductor device, the power semiconductor device comprising: an epitaxial layer of a first doping type; and two common drain metal oxide semiconductor field effect transistors, the epitaxial layer of the first doping type having a trench disposed therein;
Each common drain metal oxide semiconductor field effect transistor has a first metal oxide semiconductor structure and a second metal oxide semiconductor structure disposed along a depth direction of the trench;
the first metal oxide semiconductor structure having a first channel disposed in the epitaxial layer of the first doping type and a first source connected to the first channel, the first source and the first channel being located on the same side of the trench, the first source being connected to the first channel, the first channel being a region of a second doping type disposed in the epitaxial layer of the first doping type;
the first metal oxide semiconductor structure further comprising a first gate disposed in the trench and configured to control conduction of the first channel;
the second metal oxide semiconductor structure has a second source and a second channel, the second source extending within the trench along the depth direction and located at a bottom of the trench, the second channel located in the epitaxial layer of the first doping type and connected to the second source , the second channel being a region of the second doping type disposed in the epitaxial layer of the first doping type;
the second metal oxide semiconductor structure further comprising a second gate disposed in the trench and configured to control conduction of the second channel;
the first channel and the second channel are spaced apart along the depth direction of the trench, and the second gate and the first gate are spaced apart along the depth direction of the trench;
When the first gate and the second gate are controlled to turn on the first channel and the second channel, respectively, a current flows along or in a direction opposite to the direction in which the first source, the first channel, the portion of the epitaxial layer of the first doping type between the first channel and the second channel, the second channel, and the second source are arranged;
The two common drain metal oxide semiconductor field effect transistors share a second source, two first channels of the two common drain metal oxide semiconductor field effect transistors are disposed on both sides of the trench, and two of the first sources are disposed on both sides of the trench.
Power semiconductor devices. Each common drain metal oxide semiconductor field effect transistor further comprises:
a first gate oxide layer insulating the first channel from the first gate;
a second gate oxide layer insulating the second channel from the second gate;
The power semiconductor device of claim 1 , The power semiconductor device of claim 2, wherein the first gate oxide layer and the second gate oxide layer are disposed on sidewalls of the trench. The power semiconductor device of claim 3, wherein the trench is filled with a fill layer that encases the first gate, the second gate, and the second source. The power semiconductor device according to any one of claims 1 to 4, wherein a first source contact region is disposed in the epitaxial layer of the first doping type, and the first channel is connected to the first source via the first source contact region. The power semiconductor device of claim 5, wherein the first source contact region has a highly doped region of a first doping type and a highly doped region of a second doping type. The power semiconductor device according to any one of claims 1 to 6, wherein a second source contact region is disposed in the epitaxial layer of the first doping type, and the second channel is connected to the second source via the second source contact region. The power semiconductor device of claim 7, wherein the second source contact region has a heavily doped region of a first doping type and a heavily doped region of a second doping type. The power semiconductor device according to any one of claims 1 to 8, wherein the trench is a linear trench, and the first gate and the second gate are disposed one above the other along the depth direction of the trench. The power semiconductor device according to any one of claims 1 to 8, wherein the first gate and the second gate are staggered along the depth direction of the trench. The power semiconductor device according to claim 10, wherein the trench is a T-shaped trench, the second gate is disposed at the bottom of the T-shaped trench, and the first gate is disposed at a step surface of the T-shaped trench. An electronic device having a battery and an output circuit connected to the battery, the output circuit having a power semiconductor device according to any one of claims 1 to 11.

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