JP7619216B2 - Semiconductor package and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor package in which a semiconductor chip is sealed with a sealing material, and a method for manufacturing the same.

Conventionally, semiconductor packages in which a semiconductor chip is sealed with a sealing member have been proposed (see, for example, Patent Document 1). Specifically, the sealing member of this semiconductor package is configured to have a resin part made of liquid crystal polymer that covers the semiconductor chip, and a wiring part that is electrically connected to the semiconductor chip. The wiring part has multiple wiring layers that extend along the surface direction of the semiconductor chip, and multiple connection vias that are connected to each wiring layer. The multiple wiring layers are arranged at different heights within the sealing member, and the multiple connection vias are arranged to connect the wiring layers to each other.

Such a semiconductor package is manufactured as follows. First, a sheet-like base member made of liquid crystal polymer is prepared. A wiring layer is then formed on one side of the base member, and conductive paste is filled into through holes formed to reach the wiring layer to prepare a wiring sheet. The wiring layer of the wiring sheet is formed by disposing a metal film on one side of the base member by plating, vapor deposition, sputtering, etc., and then placing a mask on the metal film and patterning it into a predetermined shape. Multiple wiring sheets are prepared according to the thickness of the sealing member to be constructed.

Next, multiple wiring sheets are stacked in order with the semiconductor chip placed inside. After that, the conductive paste is sintered by heating and pressurizing to form connection vias, and a semiconductor package is produced in which the semiconductor chip is sealed in the sealing material.

Patent No. 4568718

However, in the semiconductor package described above, when forming the wiring layer of the wiring sheet, a new mask such as a photoresist required for patterning the metal film must be placed each time a wiring layer is formed. This tends to increase the number of manufacturing steps.

In view of the above, the present invention aims to provide a semiconductor package and a method for manufacturing the same that can prevent an increase in the number of manufacturing processes.

To achieve the above object, claim 1 provides a semiconductor package in which a semiconductor chip (20) is sealed with a sealing member (30), comprising a semiconductor chip on which a semiconductor element is formed, an insulating heat dissipation member (10) on which the semiconductor chip is mounted, and a sealing member that seals the semiconductor chip, the sealing member having a resin portion (31) made of a liquid crystal polymer and a wiring portion (32) electrically connected to the semiconductor chip, the wiring portion having a plurality of wiring layers (322) extending along the surface direction of the semiconductor chip and connection vias (321) extending along the stacking direction of the semiconductor chip and the insulating heat dissipation member and connecting adjacent wiring layers along the stacking direction, the wiring layers and connection vias being made of sintered bodies.

According to this, the wiring layer and the connection vias are made of a sintered body. When the wiring layer is made of a sintered body, it is formed by sintering a conductive paste for the wiring layer. In this case, since the conductive paste for the wiring layer is placed by a printing method or the like, the mask used when placing the paste can be shared. Therefore, the manufacturing process can be simplified compared to when the wiring layer is formed by etching.

Claim 5 is a manufacturing method related to claim 1, which includes the steps of preparing a plurality of sheet-shaped base members (310) made of liquid crystal polymer and having one surface (310a) and the other surface (310b) opposite to the one surface, forming through holes (311) in the base members, filling the through holes with conductive paste for vias (341), arranging conductive paste for wiring layers (342) on one surface side of the base members so as to contact the conductive paste for vias, and forming a plurality of wiring sheets (400), stacking the plurality of wiring sheets in order on an insulating heat dissipation member and arranging a semiconductor chip, and forming a sealing member by sintering the conductive paste for vias and forming a wiring layer composed of a sintered body by applying heat and pressure.

According to this method, the wiring layer is formed by sintering the conductive paste for the wiring layer. In this case, since the conductive paste for the wiring layer is placed by a printing method or the like, it is possible to share the mask used for placement. Therefore, the manufacturing process can be simplified compared to the case where the wiring layer is formed by etching.

The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

1 is a cross-sectional view of a semiconductor package according to a first embodiment. 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor package shown in FIG. 2B is a cross-sectional view showing a manufacturing process of the semiconductor package subsequent to FIG. 2A. 2C is a cross-sectional view showing a manufacturing process of the semiconductor package subsequent to FIG. 2B. 2C is a cross-sectional view showing a manufacturing process of the semiconductor package following FIG. 2C. 2D; FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor package subsequent to FIG. 2D; 2E is a cross-sectional view showing a manufacturing process of the semiconductor package subsequent to FIG. 2E. 13 is a cross-sectional view showing a through hole formed in a base member in a second embodiment. FIG. 4 is a cross-sectional view of the vicinity of a connection via when a semiconductor package is constructed using the base member of FIG. 3. FIG. 11 is a cross-sectional view of the vicinity of a connection via in a modified example of the second embodiment. FIG. 11 is a cross-sectional view of the vicinity of a connection via in a modified example of the second embodiment.

The following describes embodiments of the present invention with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals.

First Embodiment
A first embodiment will be described with reference to the drawings. The semiconductor package of the present embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle.

As shown in FIG. 1, the semiconductor package is configured to include an insulating heat dissipation member 10, a semiconductor chip 20, a sealing member 30, etc.

The insulating heat dissipation member 10 is made of silicon nitride (SiN), aluminum nitride (ALN), or the like, and is in the form of a plate having one surface 10a and another surface 10b opposite to the first surface 10a. The insulating heat dissipation member 10 has a connection wiring 11 made of copper or the like formed on the first surface 10a. The connection wiring 11 has a thickness of about 10 to 100 μm.

In this embodiment, the semiconductor chip 20 is configured using a semiconductor substrate 23 in which a semiconductor layer 22 containing gallium nitride is laminated on a support substrate 21 made of silicon. In other words, the semiconductor chip 20 is configured using a semiconductor substrate 23 made of so-called GaN-on-Si. The front surface 20a of the semiconductor chip 20 is configured as the semiconductor layer 22, and the back surface 20b is configured as the support substrate 21.

In this embodiment, the semiconductor layer 22 containing gallium nitride is formed by stacking epitaxial layers such as a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer. In this embodiment, a two-dimensional electron gas (i.e., 2DEG) is formed at the interface between the gallium nitride layer and the aluminum gallium nitride layer.

Although details are omitted, the semiconductor chip 20 has a drain electrode, a source electrode, and a gate electrode formed on the surface 20a side, and a high electron mobility transistor is formed as a semiconductor element that uses two-dimensional electron gas to pass current between the drain electrode and the source electrode. In other words, the semiconductor chip 20 of this embodiment has a horizontal transistor formed that passes current in the surface direction of the semiconductor substrate 23.

The semiconductor chip 20 also has a back electrode 24 formed on the back surface 20b. The back electrode 24 is electrically connected to the source electrode through a connection via 321 and a wiring layer 322 formed in the sealing member 30, as will be described in detail later. This suppresses current collapse in the semiconductor chip 20 of this embodiment.

Such a semiconductor chip 20 is placed on the connection wiring 11 formed on the insulating heat dissipation member 10 with the back electrode 24 facing the insulating heat dissipation member 10.

The sealing member 30 is disposed on the insulating heat dissipation member 10 so as to seal the semiconductor chip 20 and one surface 10a of the insulating heat dissipation member 10. The sealing member 30 is also disposed between the semiconductor chip 20 and the insulating heat dissipation member 10. However, the sealing member 30 is disposed on the insulating heat dissipation member 10 so as to expose the other surface 10b of the insulating heat dissipation member 10.

The sealing member 30 of this embodiment has a resin part 31 made of liquid crystal polymer (hereinafter simply referred to as LCP) and a wiring part 32 electrically connected to the semiconductor chip 20. Specifically, the wiring part 32 has a plurality of wiring layers 322 extending along the surface direction of the semiconductor chip 20, and a plurality of connection vias 321 electrically connected to the wiring layers 322 and extending along the stacking direction (hereinafter simply referred to as the stacking direction) of the insulating heat dissipation member 10 and the semiconductor chip 20. More specifically, the plurality of wiring layers 322 are arranged at different positions along the stacking direction. The plurality of connection vias 321 are arranged so as to electrically connect each wiring layer 322.

The outermost wiring layer 322a formed on the outermost layer of the wiring layer 322 on the side opposite the insulating heat dissipation member 10 side is arranged so as to be electrically connected to the source electrode and the like formed on the semiconductor chip 20 through the connection via 321. An opening 33 is formed in the sealing member 30 to expose a part of the outermost wiring layer 322a. This exposes a part of the outermost wiring layer 322a, and the exposed part forms a pad part 322b for connecting to an external circuit.

In the semiconductor chip 20 of this embodiment, a source electrode, a drain electrode, a gate electrode, etc. are formed on the surface 20a side. Therefore, a plurality of outermost wiring layers 322a are formed so as to be connected to the source electrode, the drain electrode, the gate electrode, etc., respectively. Also, the sealing member 30 is formed with an opening 33 that exposes a part of the outermost wiring layer 322a connected to each electrode. Therefore, at least three pad portions 322b are formed in the semiconductor package of this embodiment.

The back-side connection via 321a, which is formed closest to the insulating heat dissipation member 10 among the multiple connection vias 321, is formed to connect the back-side electrode 24 of the semiconductor chip 20 to the connection wiring 11, and is also formed to connect the connection wiring 11 to the wiring layer 322.

Each wiring layer 322 and each connection via 321 is made of a sintered body of conductive paste. In this embodiment, the conductive paste used is made by adding a viscosity adjusting agent, an organic solvent, etc. to AgSn powder.

In this embodiment, adjacent connection vias 321 in the stacking direction are arranged at offset positions in the stacking direction. In other words, adjacent connection vias 321 in the stacking direction are arranged so as not to overlap in the stacking direction. This makes it possible to prevent the stress along the stacking direction from becoming too high, compared to when adjacent connection vias 321 in the stacking direction are arranged so as to overlap.

The above is the configuration of the semiconductor package in this embodiment. Next, the manufacturing method of the semiconductor package will be explained with reference to Figures 2A to 2F.

First, as shown in FIG. 2A, a sheet-like base member 310 is prepared, which constitutes the resin portion 31 of the sealing member 30 and has one surface 310a and the other surface 310b. The base member 310 is made of a sheet-like LCP. Also, although FIG. 2A shows only one base member 310, in reality, multiple base members 310 are prepared as required for carrying out the process of FIG. 2E described below.

Next, as shown in FIG. 2B, through holes 311 are formed in each base member 310. In this embodiment, the through holes 311 are formed by punching. As a result, compared to, for example, forming the through holes 311 in the base member 310 by laser processing, foreign matter such as debris originating from the base member 310 is less likely to scatter when forming the through holes 311, and adhesion of foreign matter to the base member 310 can be suppressed.

Next, as shown in FIG. 2C, a protective sheet 330 is placed on the other surface 310b of the base member 310. The protective sheet 330 is made of a material that is breathable and can prevent the conductive via paste 341 described later from flowing out. For example, a paper sheet having minute voids is used as the protective sheet 330. Then, the conductive via paste 341 is filled into the through holes 311 by a printing method or the like. The conductive via paste 341 is made by adding a viscosity adjusting agent, an organic solvent, etc. to AgSn powder to form a paste, and the viscosity is adjusted so that it is difficult to flow out of the protective sheet 330.

In this case, the protective sheet 330 is made of a material having breathability. Therefore, when filling the via conductive paste 341, the via conductive paste 341 can be filled while discharging air bubbles. Therefore, it is possible to prevent air bubbles from remaining in the via conductive paste 341.

Then, as shown in FIG. 2D, the protective sheet 330 is peeled off from the base member 310. Then, the conductive paste for wiring layer 342 is placed on one surface 310a of the base member 310 so as to contact the conductive paste for vias 341. This results in a wiring sheet 400 in which the conductive paste for vias 341 and the conductive paste for wiring layer 342 are placed on the base member 310. Note that the conductive paste for wiring layer 342 in this embodiment is made of the same material as the conductive paste for vias 341.

In addition, the conductive paste 342 for the wiring layer in this embodiment is placed by a printing method or the like. In this case, when forming the same wiring sheet 400, a common mask can be used. Therefore, there is no need to prepare a new mask each time the conductive paste 342 for the wiring layer is placed, and the manufacturing process can be simplified.

After the steps of FIG. 2C and FIG. 2D are completed, the conductive paste for vias 341 and the conductive paste for wiring layers 342 are not yet sintered, but they may be pre-sintered as necessary to make them less likely to flow. In addition, in the steps of FIG. 2B to FIG. 2D, the placement locations of the conductive paste for vias 341 and the conductive paste for wiring layers 342 are adjusted according to the position of the wiring sheet 400 that is placed in the step of FIG. 2E, which will be described later.

Then, in a separate process from those shown in Figures 2A to 2D, an insulating heat dissipation member 10 with connection wiring 11 formed thereon and a semiconductor chip 20 are prepared. After that, as shown in Figure 2E, a wiring sheet 400 and a semiconductor chip 20 are stacked and arranged on the insulating heat dissipation member 10. In this embodiment, each wiring sheet 400 is stacked so that the other surface 310b of the base member 310 faces one surface 10a of the insulating heat dissipation member 10. Also, in this embodiment, a base member 310 with an opening 33 formed therein is arranged on the outermost layer on the side opposite the insulating heat dissipation member 10 side in the stacking direction.

In addition, among the multiple wiring sheets 400 (i.e., the base member 310), the wiring sheet 400 on which the semiconductor chip 20 is arranged also has a placement hole 401 for placing the semiconductor chip 20 formed therein before stacking. Then, the semiconductor chip 20 is placed so as to be accommodated in the placement hole 401.

Next, as shown in FIG. 2F, the wiring sheets 400 are heated and pressed in the stacking direction to form the sealing member 30. At this time, the LCP that forms the base member 310 flows, and the conductive paste for vias 341 and the conductive paste for wiring layer 342 are pressurized from the surroundings. As a result, the conductive paste for vias 341 is sintered to form the connection vias 321, and the conductive paste for wiring layer 342 is sintered to form the wiring layer 322.

According to the embodiment described above, the connection via 321 is composed of a sintered body obtained by sintering the conductive paste 341 for the via, and the wiring layer 322 is composed of a sintered body obtained by sintering the conductive paste 342 for the wiring layer. The conductive paste 342 for the wiring layer is arranged by a printing method, and the mask used for the printing method can be shared. For this reason, the manufacturing process can be simplified compared to the case where, for example, a metal film such as copper foil is arranged on the base member 310, a new mask is prepared for each metal film, and the wiring layer is formed by etching. Furthermore, the mask used for etching, etc. requires waste liquid treatment when removed, which raises concerns about the impact on the environment. However, the mask used by the printing method can be shared, so the impact on the environment can also be reduced.

(1) In this embodiment, the connection vias 321 and the wiring layer 322 are made of the same sintered material. This makes it easy to prepare the materials and simplifies the manufacturing process.

(2) In this embodiment, when forming the wiring sheet 400, the through holes 311 are formed in the base member 310 by punching. This makes it possible to prevent foreign matter from adhering to the base member 310, compared to, for example, a case in which the through holes 311 are formed by irradiating the base member 310 with a laser beam.

(3) In this embodiment, when filling the via conductive paste 341, a breathable protective sheet 330 is placed. Therefore, when filling the via conductive paste 341, the via conductive paste 341 can be filled while discharging air bubbles. This makes it possible to prevent air bubbles from remaining in the via conductive paste 341. As a result, when the connection via 321 and the wiring layer 322 are made of a sintered body, it is possible to prevent the portion of the wiring layer 322 connected to the connection via 321 from being recessed toward the connection via 321, and it is possible to prevent the wiring layer 322 from being disconnected and causing a connection failure.

Second Embodiment
A second embodiment will be described. In this embodiment, the shape of the through hole 311 formed in the base member 310 is changed from that of the first embodiment. As the rest is similar to the first embodiment, a description thereof will be omitted here.

In this embodiment, when the process of FIG. 2B is performed to form the through hole 311, the opening on the side of the first surface 310a is made wider than the central portion between the first surface 310a and the other surface 310b, forming a through hole 311 having a tapered portion 311a. In this embodiment, the tapered portion 311a is tapered so that the width gradually narrows from the side of the first surface 310a toward the central portion. Such a through hole 311 is formed, for example, by adjusting conditions such as the shape of the punch used during punching and the punching speed.

When a semiconductor package is manufactured by filling such through holes 311 with conductive paste for vias 341, the connection vias 321 and the wiring layer 322 are connected as shown in FIG. 4. Specifically, because the through holes 311 are formed as described above, the width of the connection vias 321 on the wiring layer 322 side is wider than the width of the central portion of the connection vias 321. Note that the width refers to the length in the direction intersecting the extension direction of the connection vias 321, and in FIG. 4, it refers to the length in the left-right direction of the paper.

According to the present embodiment described above, since the wiring layer 322 is composed of a sintered body obtained by sintering the conductive paste 342 for the wiring layer, the same effects as those of the first embodiment can be obtained.

(1) In this embodiment, the width of the connection via 321 on the wiring layer 322 side is wider than the width of the central portion. This makes it easier to ensure adhesion to the wiring layer 322. In addition, such a connection via 321 is formed by filling a through hole 311, the opening of which is wider on the side of the first surface 310a than the central portion, with a conductive via paste 341. In this case, since the opening of the through hole 311 on the side of the first surface 310a is wider, it is easier to fill the conductive via paste 341.

(2) Modification of the Second Embodiment A modification of the second embodiment will be described. In the second embodiment, the tapered portion 311a (i.e., the portion of the connection via 321 on the wiring layer 322 side) may be rounded as shown in FIG. 5. By providing the rounded portion in this manner, stress concentration can be suppressed. In addition, the tapered portion 311a may be formed on both sides connected to the wiring layer 322 with respect to the central portion as shown in FIG. 6. In other words, the connection via 321 may be shaped so that the width of both end portions connected to each wiring layer 322 is wider than the width of the central portion. This can improve the bondability with the wiring layers 322 on both sides of the connection via 321.

Other Embodiments
Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

For example, in each of the above embodiments, the resin portion 31 of the sealing member 30 (i.e., the base member 310) may be made of an LCP material having an isotropic thermal expansion coefficient. The thermal expansion coefficient is adjusted by adjusting the amount of the added material. This allows the thermal stress to be evenly released to the surroundings, preventing localized concentration of thermal stress and preventing resin peeling, etc.

In addition, in each of the above embodiments, the connection via 321 and the wiring layer 322 may be made of sintered bodies of different materials. For example, the wiring layer 322 may be made of a sintered body containing CuSn to adjust the wiring resistance.

In each of the above embodiments, the through hole 311 may be formed by laser processing or the like.

Furthermore, in each of the above embodiments, when placing the conductive paste 342 for the wiring layer, a transfer method or the like may be used. Even if the conductive paste 342 for the wiring layer is placed using this method, it is not necessary to prepare a new mask each time the conductive paste 342 for the wiring layer is placed, and therefore the manufacturing process can be simplified.

Furthermore, in each of the above embodiments, the semiconductor chip 20 may be configured with a superjunction MOSFET or an IGBT formed thereon. Also, the semiconductor chip 20 may be configured using a support substrate 21 made of gallium oxide, gallium nitride, or the like, instead of a support substrate 21 made of silicon or SiC.

REFERENCE SIGNS LIST 10: insulating heat dissipation member 20: semiconductor chip 30: sealing member 31: resin portion 321: connection via 322: wiring layer

Claims (7)

A semiconductor package in which a semiconductor chip (20) is sealed with a sealing member (30),
The semiconductor chip on which a semiconductor element is formed;
An insulating heat dissipation member (10) on which the semiconductor chip is mounted;
the sealing member that seals the semiconductor chip,
The sealing member has a resin portion (31) made of a liquid crystal polymer and a wiring portion (32) electrically connected to the semiconductor chip,
the wiring portion includes a plurality of wiring layers (322) extending along a surface direction of the semiconductor chip, and connection vias (321) extending along a stacking direction of the semiconductor chip and the insulating heat dissipation member and connecting adjacent wiring layers along the stacking direction;
The wiring layer and the connection vias are made of a sintered body. The semiconductor package of claim 1, wherein the wiring layer and the connection vias are made of a sintered body of the same material. The semiconductor package according to claim 1 or 2, wherein the width of the connection via at the portion connected to the wiring layer is wider than the width of the portion located at the center of the stacking direction. The semiconductor package according to any one of claims 1 to 3, wherein the resin portion is made of a liquid crystal polymer having an isotropic thermal expansion coefficient. A semiconductor chip (20) on which a semiconductor element is formed;
An insulating heat dissipation member (10) on which the semiconductor chip is mounted;
and a sealing member (30) for sealing the semiconductor chip,
The sealing member has a resin portion (31) made of a liquid crystal polymer and a wiring portion (32) electrically connected to the semiconductor chip,
the wiring portion includes a plurality of wiring layers (322) extending along a surface direction of the semiconductor chip, and connection vias (321) extending along a stacking direction of the semiconductor chip and the insulating heat dissipation member and connecting adjacent wiring layers along the stacking direction;
A method for manufacturing a semiconductor package, wherein the wiring layer and the connection via are made of a sintered body,
Preparing a plurality of sheet-like base members (310) made of a liquid crystal polymer and having one surface (310a) and another surface (310b) opposite to the one surface;
forming a through hole (311) in the base member;
Filling the through holes with a via conductive paste (341);
A conductive paste for wiring layers (342) is arranged on one side of the base member so as to contact the conductive paste for vias, thereby forming a plurality of wiring sheets (400);
laminating the plurality of wiring sheets in order on the insulating heat dissipation member and disposing the semiconductor chip;
a conductive paste for a via is sintered by applying heat and pressure to form the connection via composed of the sintered body, and a conductive paste for a wiring layer is sintered to form the wiring layer composed of the sintered body, thereby forming the sealing member. The method for manufacturing a semiconductor package according to claim 5, wherein the through holes are formed by punching. Before filling the via-hole conductive paste, a breathable protective sheet (330) is placed on the other side of the base member;
7. The method for manufacturing a semiconductor package according to claim 5, wherein the step of filling the vias with the conductive paste comprises filling the vias with the conductive paste from one surface side of the base member.

Images