JP7620021B2 - Sidewall Notch Reduction for High Aspect Ratio 3D NAND Etch - Google Patents

Description

INCORPORATION BY REFERENCE A PCT application form is being filed contemporaneously herewith as part of this application. Each application to which this application claims the benefit of, or priority to, as set forth in the contemporaneously filed PCT application form is hereby incorporated by reference in its entirety for all purposes.

Embodiments herein relate to methods and apparatus for manufacturing semiconductor devices, and more particularly, to methods and apparatus for etching high aspect ratio features in dielectric-containing materials with reduced sidewall notches and no profile tradeoffs.

One process frequently used in the manufacture of semiconductor devices is the formation of etched cylinders or other recessed features in a stack of dielectric-containing materials. For example, such processes are widely used in memory applications such as the fabrication of 3D NAND (also known as vertical NAND or V-NAND) structures. As the semiconductor industry advances and device dimensions shrink, it becomes increasingly difficult to uniformly etch such features, especially for high aspect ratio cylinders with narrow widths and/or deep depths.

The background discussion provided herein is intended to provide an overall picture of the context of the present disclosure. To the extent described in this background section, aspects of the inventors' work as currently set forth, and of the discussion that may not have qualified as prior art at the time of filing, are not admitted, expressly or impliedly, to be prior art against the present disclosure.

Certain embodiments herein relate to methods and apparatus for etching features in a stack including a dielectric material. Typically, features are etched in the stack during fabrication of 3D NAND structures on a substrate.

In one aspect of an embodiment herein, there is provided a method of etching features in a stack including a dielectric material in fabricating a 3D NAND structure, the method comprising: receiving a substrate on a substrate support in a reaction chamber, the substrate including a stack and a mask layer patterned on top of the stack, the stack including either (a) alternating layers of silicon oxide and silicon nitride or (b) alternating layers of silicon oxide and polysilicon; exposing the substrate to a plasma in the reaction chamber, thereby etching features in the stack on the substrate, the plasma being generated from a plasma generating gas including WF ₆ , one or more fluorocarbons and/or hydrofluorocarbons, and one or more oxidants, the flow rate of WF ₆ being about 0.1-10 sccm, the plasma being a capacitively coupled plasma, the substrate being biased at a frequency between about 20 kHz and 1.5 MHz, at an RF power level between about 500 W and 20 kW per substrate, and the WF ₆ and the fluorocarbon and/or hydrofluorocarbon form a tungsten-based polymer film on the sidewalls of the feature during the etching process, which promotes a uniform etch rate between alternating layers of silicon oxide and silicon nitride or between alternating layers of silicon oxide and polysilicon to prevent the sidewalls of the feature from being notched during the etching process.

In certain embodiments, during the etching process, _WF6 may dissociate into tungsten-containing and fluorine-containing fragments, with the tungsten-containing fragments remaining relatively concentrated near the top of the feature compared to the fluorine-containing fragments, and the fluorine-containing fragments penetrating deeper into the feature compared to the tungsten-containing fragments. In some such embodiments, the tungsten-based polymer film is compositionally non-uniform along the sidewall of the feature such that the tungsten-based polymer film near the top of the feature has a higher percentage of tungsten compared to the tungsten-based polymer film near the bottom of the feature.

In some cases, certain process conditions may be used. For example, the plasma may be generated at an excitation frequency of about 20 MHz to 100 MHz and an RF power of about 6.3 kW or less. In these or other cases, the oxidant may be _O2 and the _O2 flow rate may be about 20-150 sccm. In these or other cases, the plasma generating gas may further include _SF6 and the _SF6 flow rate may be about 1-20 sccm. In these or other cases, the plasma generating gas may further include Kr and the Kr flow rate may be about 30-120 sccm. In these or other cases, the plasma generating gas may further include _NF3 and the _NF3 flow rate may be about 30 sccm or less. In these or other cases, the fluorocarbon or hydrofluorocarbon may include one or more of _{C4F8 , C3F8 , C4F6} , and _CH2F2 , and the total flow rate of the fluorocarbon and hydrofluorocarbon may be about 30-240 _{sccm .} In these or other cases, the substrate support may be maintained at a temperature of about 20-80°C during etching of the substrate. In these or other cases, the pressure in the reaction chamber may be maintained at about 10-80 mTorr during etching of the substrate. In these or other cases, the features may be etched into alternating layers of silicon oxide and silicon nitride. In these or other cases, the flow rate of _WF6 may be about 0.02%-10% of the total flow rate of the plasma generating gas. In these or other cases, the flow rate of _WF6 may be about 0.02%-1% of the total flow rate of the plasma generating gas. In these or other cases, the flow rate of _WF6 may be about 0.02%-0.5% of the total flow rate of the plasma generating gas. In these or other cases, the substrate may be biased at an RF frequency of about 300 kHz-600 kHz. For example, the substrate may be biased at an RF frequency of about 400 kHz. In these or other cases, the tungsten-based polymer film may be formed at a first thickness on a layer of silicon oxide and at a second thickness on a layer of silicon nitride or polysilicon, the first thickness and the second thickness being different.

In another aspect of the disclosed embodiments, an apparatus is provided for etching features in a stack including a dielectric material in fabricating a 3D NAND structure on a substrate, the apparatus including a reaction chamber having a substrate support therein, a capacitively coupled plasma generator; an inlet for introducing material into the reaction chamber, and an outlet for removing material from the reaction chamber; and a controller configured to perform any of the methods described herein.

For example, certain aspects of the disclosed embodiments provide an apparatus for etching features in a stack including a dielectric material in fabricating a 3D NAND structure on a substrate, the apparatus comprising a reaction chamber having a substrate support therein, a capacitively coupled plasma generator, an inlet for introducing material into the reaction chamber, an outlet for removing material from the reaction chamber, and a controller, the apparatus receiving a substrate on the substrate support in the reaction chamber, the substrate including a stack and a mask layer patterned on top of the stack, the stack including either (a) alternating layers of silicon oxide and silicon nitride or (b) alternating layers of silicon oxide and polysilicon, generating a plasma from a plasma generating gas including WF ₆ , one or more fluorocarbons and/or hydrofluorocarbons, and one or more oxidants, the flow rate of WF ₆ being about 0.1-10 sccm, biasing the substrate at an RF power level of about 500 W-20 kW at a frequency of about 20 kHz-1.5 MHz, exposing the substrate to the plasma in the reaction chamber, thereby etching features in the stack on the substrate, and ₆ and the fluorocarbon and/or hydrofluorocarbon form a tungsten-based polymer film on sidewalls of the feature during the etching process, the tungsten-based polymer film being configured to promote a uniform etch rate between alternating layers of silicon oxide and silicon nitride or between alternating layers of silicon oxide and polysilicon to prevent the sidewalls of the feature from being notched during the etching process.

These and other features are described below with reference to the associated drawings.

FIG. 1 shows a stack of alternating materials.

FIG. 2 shows the substrate of FIG. 1 after etching to reveal a noticeable notch in the sidewall.

2 is a view of the substrate of FIG. 1 after an etching process according to embodiments herein.

1 is a flow chart illustrating an etching method according to various embodiments herein.

FIG. 1 is a diagram of a reaction chamber that may be used to perform the etching processes described herein in accordance with certain embodiments. FIG. 1 is a diagram of a reaction chamber that may be used to perform the etching processes described herein in accordance with certain embodiments. FIG. 1 is a diagram of a reaction chamber that may be used to perform the etching processes described herein in accordance with certain embodiments.

1 and 2 show a substrate 101 including a 3D NAND structure fabricated in part by etching high aspect ratio features 102 in a stack 103 including alternating layers of a first material 104 and a second material 105. FIG. 1 shows the structure before etching, and FIG. 2 shows the structure after etching the high aspect ratio features 102. In one example, the first material is silicon oxide and the second material is silicon nitride. In another example, the first material is silicon oxide and the second material is polysilicon. The alternating layers form material pairs. For clarity, FIGS. 1 and 2 show the etched features with only a few material pairs. However, it is understood that an etching operation typically etches many more material pairs. In some cases, the number of material pairs may be at least about 20, at least about 30, at least about 40, at least about 60, or at least about 75. Each layer of the stack 103 may have a thickness of about 20-50 nm, such as about 30-40 nm. Overlying the stack 103 is a mask layer 106. The mask layer 106 is patterned with openings where the high aspect ratio features 102 are to be etched. Examples of mask materials include, but are not limited to, amorphous carbon, polysilicon, and other common mask materials. The thickness of the mask layer before etching may be about 1-2.5 μm. The depth of the high aspect ratio features 102 etched into the stack 103 may be about 3-10 μm, such as about 5-10 μm. The width/diameter of the high aspect ratio features 102 may be about 50-150 nm, such as about 60-110 nm. In some cases, the width of the features may be about 100 nm or less. The pitch between adjacent features may be about 100-200 nm, such as about 120-170 nm.

1, a substrate 101 is prepared in a semiconductor processing apparatus for etching. A suitable apparatus is described below. After the substrate 101 is introduced into the processing apparatus, a plasma is generated in the processing apparatus and the substrate 101 is exposed to the plasma. After a period of time, this exposure to the plasma etches the areas of the substrate 101 that are not protected by the mask layer 106, thereby forming the high aspect ratio feature 102 as shown in FIG. 2. Although the mask layer 106 is resistant to the etching chemistry, it typically undergoes some erosion during the etching process. Therefore, the mask layer 106 shown in FIG. 2 is thinner than the mask layer 106 shown in FIG. 1. When the stack 103 is etched, a passivation layer 107 is formed on the sidewalls of the high aspect ratio feature 102. The passivation layer 107 is a mixed layer formed from a combination of the material of the stack 103 and one or more materials resulting from the etching chemistry. Therefore, the composition of the passivation layer 107 depends on the composition of the layer being formed. For example, the portion of the passivation layer 107 forming the sidewall of a silicon oxide layer typically has a composition that includes at least silicon, oxygen, and carbon, while the portion of the passivation layer 107 forming the sidewall of a silicon nitride layer typically has a composition that includes at least silicon, nitrogen, and carbon. Similarly, the portion of the passivation layer 107 forming the sidewall of a polysilicon layer typically has a composition that includes at least silicon and carbon. Often the passivation layer is a fluorocarbon film, which may be a polymer.

2 shows that the passivation layer 107 is deposited uniformly with a relatively uniform shape, but this may not be the case. In some cases, the passivation layer 107 may be concentrated near the top of the high aspect ratio feature 102, with little or no passivation layer 107 near the bottom of the feature. In some cases, the passivation layer 107 may be formed non-uniformly between the layer of the first material 104 and the layer of the second material 105, as discussed further below.

One problem that can arise when etching a stack of alternating layers, as shown in FIG. 2, is non-uniform etch rates between the two different layers. Often, silicon oxide materials are etched faster in the vertical direction than silicon nitride or polysilicon materials. This high vertical etch rate of the oxide material results in relatively little horizontal etching of the oxide layer. In contrast, the nitride layer is etched slowly in the vertical direction and widely in the horizontal direction. This mismatch in etch rates can result in over-etched areas on the sidewalls of the silicon nitride material (or polysilicon material), resulting in a notched sidewall. In the example of FIG. 2, the layer of the first material 104 (e.g., silicon oxide) is etched less horizontally than the layer of the second material 105 (e.g., silicon nitride or polysilicon). Over time, this non-uniform etching results in a notched sidewall, as shown in FIG. 2. This notch is undesirable. Although not shown in FIG. 2, the notch can cause significant ion scattering, which can lead to the formation of significant bowing (e.g., if the center portion of the feature is over-etched relative to the top of the feature). The notch can also adversely affect the dielectric properties of the stack material.

2 shows each layer of stack 103 as having vertical sidewalls, this is not necessarily the case. In various implementations, a layer of material that is horizontally over-etched (e.g., silicon nitride in an oxide-nitride stack, or polysilicon in an oxide-polysilicon stack) is most over-etched near the top of the layer, resulting in an undercut beneath the other layer of material. The bottom of the over-etched layer may be less over-etched or may not be over-etched at all. Thus, the sidewalls of the over-etched layer may be sloping, curved, or non-vertical.

Without wishing to be bound by theory or mechanism of action, it is believed that the sidewall notches may be caused by non-uniform application of the passivation layer 107 to the different materials of the stack 103. For example, the passivation layer 107 may be applied with a greater thickness on the sidewalls of the layer of the first material 104 (e.g., silicon oxide) compared to the sidewalls of the layer of the second material 105 (e.g., silicon nitride or polysilicon). The thicker the passivation layer 107, the greater the protection against lateral etching. Thus, the layer of the first material is less lateral etched than the layer of the second material with the thinner passivation layer 107 on top.

Alternatively, or in addition, sidewall notches may be caused by non-uniform etch rates of two different materials. In some cases, this can result in corners being formed, particularly at the intersection between an upper layer that is etched at a first rate and an underlying layer that is etched at a different rate. Such corners are exposed to ion bombardment, which can cause undercut formation, particularly in the upper regions of the over-etched layer.

Sidewall notches can also be caused by stress differences between two different layers. Regardless of the cause or causes, it is clear that sidewall notches occur.

Certain techniques have been developed to reduce sidewall notching. These techniques often involve adjusting the composition of the etch chemistry. More specifically, the etch chemistry has been adjusted by controlling the ratio of nitrogen-containing, oxygen-containing, carbon-containing, and fluorine-containing species in the plasma that etches the substrate. However, these techniques typically result in tradeoffs related to the profile of the etched feature. For example, such techniques may result in bowing (e.g., when the center of the feature is overetched compared to the top of the feature), reduced selectivity, increased capping, or reduced etch rate. None of these outcomes are desirable.

It has been found that the inclusion of tungsten hexafluoride ( _WF6 ) in the etch chemistry eliminates or substantially reduces sidewall notching without tradeoffs in bowing, selectivity, capping, or etch rate, resulting in much smoother sidewalls for etched features, which is a highly desirable result.

Without wishing to be bound by theory or mechanism of action, it is believed that WF ₆ may make the vertical and/or horizontal etch rates of a first material (e.g., silicon oxide) and a second material (e.g., silicon nitride or polysilicon) more equal. For example, WF ₆ may reduce the vertical etch rate of the first material (e.g., increasing the horizontal etch rate of the first material) and/or increase the vertical etch rate of the second material (e.g., decreasing the horizontal etch rate of the second material). Alternatively or in addition, WF ₆ may reduce the formation rate of a passivation layer on the sidewalls of the first material (e.g., silicon oxide) and/or increase the formation rate of a passivation layer on the sidewalls of the second material (e.g., silicon nitride or polysilicon). Alternatively or in addition, WF ₆ may counteract differences in film stress or other properties between two different types of layers.

_WF6 may provide a more uniform etch rate between the first and second materials as a result of the excess of F* in the plasma. Alternatively or in addition, _WF6 may produce a tungsten-based (e.g., possibly tungsten oxide-based) sidewall polymer film, similar to the passivation layer 107 of FIG. 2. The tungsten-based sidewall polymer film may deposit smoothly on the sidewalls of the various layers, thereby preventing the formation of notches.

_WF6 is widely used to deposit tungsten-based films. However, _WF6 is not commonly used as part of the etch chemistry. The observed improvement in sidewall notching with the addition of _WF6 to the etch chemistry was unexpected.

FIG. 3 illustrates the substrate 101 of FIG. 1 after an etching process according to one embodiment herein. In this case, the etching chemistry includes WF _6. As a result, the first material 104 and the second material 105 are etched at a uniform rate, resulting in smooth sidewalls. The passivation layer 107 is shown in FIG. 3 as being uniform in shape. However, this is not necessarily the case. The passivation layer 107 may not be uniform in thickness and/or composition. For example, it may be relatively thick near the top of the feature and relatively thin or absent near the bottom of the feature (or vice versa). In one case, the passivation layer 107 may be relatively tungsten-rich near the top of the feature and relatively tungsten-poor near the bottom of the feature (or vice versa). In these or other cases, the passivation layer 107 may be relatively carbon-poor near the top of the feature and relatively carbon-rich near the bottom of the feature (or vice versa). In certain embodiments, the passivation layer 107 may include two passivation layers, one of which is tungsten-based and the other of which is carbon-based. The two passivation layers may overlap each other (e.g., as separate layers or intermixed layers) and/or may be formed at different vertical locations within the feature (e.g., the tungsten-based passivation layer may be closer to the top of the feature or closer to the bottom of the feature compared to the carbon-based passivation layer). As discussed above with respect to FIG. 2, the composition of the passivation layer 107 may also depend on the composition of the layers formed adjacent to it.

In one particular embodiment, the tungsten in the passivation layer may be concentrated toward the top of the feature compared to the bottom of the feature. In other words, much of the tungsten from the _WF6 remains near the top of the feature. This may help retain the mask layer in some cases. The concentration of tungsten near the top of the feature may be a result of the high sticking coefficient of tungsten and tungsten-containing species. When such high sticking species contact the sidewall, they are much more likely to "stick" rather than bounce back and penetrate deeper into the feature. The fluorine from _WF6 has a much lower sticking coefficient and can more easily penetrate the bottom of the feature, thereby contributing to the increased etch rate. Both of these factors (e.g., tungsten-containing species remaining near the top of the feature and fluorine-containing species migrating to the bottom of the feature to further etch the stack) allow the etch selectivity to remain desirably high.

FIG. 4 is a flow chart describing a method of etching a feature of a stack including a dielectric material according to various embodiments of the present invention. The method begins with operation 401, where a substrate is provided in a reaction chamber. The substrate may be, for example, the substrate described with respect to FIG. 1. Then, in operation 403, a plasma is generated from a plasma generating gas. The plasma generating gas includes at least _WF6 . The plasma generating gas also includes an etching chemistry suitable for etching the stack material. In _various examples, the etching chemistry includes, for example _, one or more oxygen-containing species, one or more carbon-containing species, _and one or more fluorine-containing species. Examples of materials commonly used in etching chemistries include, but are _not limited to, fluorocarbons and hydrofluorocarbons such as _C3F8 , _{C4F8 , C4F6} , _CH2F2 , _CH3F , _CHF3 , _C5F8 , _{C6F6 ,} oxidants such as _O2 , _O3 , CO, _CO2 , COS, and _NF3 . Inert species may also be provided in the plasma generating gas.

The flow rate of WF ₆ in the plasma generating gas may be at least about 0.1 sccm, or at least about 0.2 sccm, or at least about 0.5 sccm, or at least about 1 sccm. In these or other cases, the flow rate of WF ₆ may be about 20 sccm or less, such as about 10 sccm or less, or about 5 sccm or less, or about 2 sccm or less, or about 1 sccm or less, or about 0.5 sccm or less. In certain embodiments, the flow rate of WF ₆ may be about 0.1-10 sccm. The total flow rate of the plasma generating gas may be at least about 1 sccm, at least about 10 sccm, at least about 50 sccm, or at least about 80 sccm. In these or other cases, the total flow rate of the plasma generating gases may be about 600 sccm or less, or about 500 sccm or less, or about 300 sccm or less, or about 200 sccm or less, or about 100 sccm or less, or about 50 sccm or less. In some cases, one or more fluorocarbon sources may be mixed (before or after delivery to the reaction chamber) to provide, for example, a desired ratio of carbon and fluorine. In some examples, the flow rate of C ₄ F ₈ and/or C ₃ F ₈ and/or C ₄ F ₆ may be about 20-120 sccm. In these or other examples, the flow rate of CH ₂ F ₂ may be about 10-120 sccm. In various embodiments, the total flow rate of the fluorocarbons and hydrofluorocarbons may be about 30-240 sccm. In these or other examples, the flow rate of NF ₃ may be about 0-30 sccm. In these or other examples, the O ₂ flow rate may be about 20-150 sccm. In these or other examples, the SF ₆ flow rate may be about 1-20 sccm. In these or other examples, the Kr flow rate may be about 30-120 sccm. In various cases, WF ₆ may comprise at least about 0.02%, or at least about 0.05%, or at least about 0.1%, or at least about 0.5%, or at least about 1%, or at least about 3% of the volumetric flow rate of the plasma generating gas. In these or other cases, WF ₆ may comprise about 10% or less, or about 5% or less, or about 1% or less, or about 0.5% or less of the volumetric flow rate of the plasma generating gas.

In various cases, the following conditions may be used to generate the plasma: The plasma may be a capacitively coupled plasma. The plasma may be generated at an excitation frequency of about 13-169 MHz, such as about 20-100 MHz (e.g., in certain cases, about 60 MHz), and at a power level of about 0 watts to 6.3 kW per 300 mm substrate. In various cases, the power level used to generate the plasma may be particularly high, such as about 5 kW or more, or about 6 kW or more per 300 mm substrate. For example, to promote a high vertical etch rate, a relatively high bias may be applied to the substrate. The bias may be applied to the substrate at a frequency of about 20 kHz to 1.5 MHz, or about 200 kHz to 1.5 MHz, or about 300 kHz to 600 kHz (e.g., in certain cases, about 400 kHz), and at a power level of about 500 W to 20 kW per 300 mm substrate, or about 2-10 kW per 300 mm substrate. In certain embodiments, the substrate is biased at 400 kHz at a power level of about 500 W to 20 kW. The pressure in the reaction chamber may be at least about 10 mTorr or at least about 30 mTorr. In these or other cases, the pressure in the reaction chamber may be about 500 mTorr or less, such as 100 mTorr or less, or about 80 mTorr or less, or about 30 mTorr or less. In some cases, the pressure may remain relatively low during etching (e.g., 10-80 mTorr) but may be increased to a higher pressure (e.g., 100-500 mTorr, or 300-500 mTorr, or 400-500 mTorr) in a cleaning operation to clean the interior walls of the reaction chamber. A substrate support underlying the provided substrate may be maintained (e.g., by heating and/or cooling) at a temperature of about -80°C to 130°C. In some cases, the substrate support is maintained at a temperature of at least about -80°C, or at least about -50°C, or at least about -20°C, or at least about 0°C, or at least about 20°C, or at least about 50°C, or at least about 70°C. In these or other cases, the substrate support may be maintained at a temperature of about 130°C or less, or about 120°C or less, or about 100°C or less, or about 80°C or less, or about 50°C or less, or about 20°C or less, or about 0°C or less, or about -20°C or less, or about -50°C or less. In certain cases, the substrate support may be maintained at a temperature of about 20-80°C. These temperatures may be in reference to the temperature of the substrate support being controlled while the substrate is exposed to the plasma.

After a period of time, features begin to form in the stack. As shown in FIG. 3, after the features reach their final etch depth, the substrate is removed from the reaction chamber in operation 405. Compared to conventional approaches, the method described with respect to FIG. 4 allows for the formation of deep features with relatively little or no notching. The inclusion of WF ₆ in the plasma generating gas substantially reduces or eliminates sidewall notching when delivered at an appropriate flow rate and under appropriate plasma conditions. Advantageously, this reduction in sidewall notching does not result in a tradeoff in feature bowing, selectivity, capping, or etch rate.

Apparatus The methods described herein may be implemented in any suitable apparatus. A suitable apparatus includes hardware for implementing processing operations and a system controller including instructions for controlling processing operations according to the present embodiments. For example, in some embodiments, the hardware may include one or more processing stations included in a processing tool.

5A-5C show an embodiment of an adjustable gap capacitively coupled confined RF plasma reactor 500 that may be used to perform the etching operations described herein. As shown, a vacuum chamber 502 has a chamber housing 504 that encloses an interior space that houses a lower electrode 506. At the top of the chamber 502, an upper electrode 508 is vertically spaced apart from the lower electrode 506. The planar surfaces of the upper and lower electrodes 508, 506 are substantially parallel and perpendicular to the vertical direction between the electrodes. The upper and lower electrodes 508, 506 are preferably circular and coaxial with respect to a vertical axis. The lower surface of the upper electrode 508 faces the upper surface of the lower electrode 506. The spaced apart opposing electrode surfaces define an adjustable gap 510 between them. In operation, the lower electrode 506 is supplied with RF power by an RF power source (matched) 520. RF power is supplied to the lower electrode 506 through an RF supply tube 522, an RF strap 524, and an RF power member 526. A ground shield 536 may surround the RF power member 526 to achieve a more uniform RF field at the lower electrode 506. As described in commonly owned U.S. Patent Application No. 7,732,728, which is incorporated herein by reference in its entirety, a wafer is inserted through a wafer port 582 and supported in a gap 510 above the lower electrode 506 for processing, and a process gas is supplied to the gap 510 and excited into a plasma state by RF power. The upper electrode 508 can be powered or grounded.

In the embodiment shown in Figures 5A-5C, the lower electrode 506 is supported on a lower electrode support plate 516. An insulating ring 514 interposed between the lower electrode 506 and the lower electrode support plate 516 insulates the lower electrode 506 from the support plate 516.

An RF bias housing 530 supports the lower electrode 506 on an RF bias housing bowl 532. The bowl 532 is coupled by an arm 534 of the RF bias housing 530 to a conduit support plate 538 through an opening in the chamber wall plate 518. In a preferred embodiment, the RF bias housing bowl 532 and the RF bias housing arm 534 are integrally formed as one component, although the arm 534 and bowl 532 could be two separate components bolted or joined together.

The RF bias housing arm 534 has one or more hollow passages for passing RF power and equipment (gas coolant, liquid coolant, RF energy, cables for lift pin control, electrical monitoring and actuation signals, etc.) from outside the vacuum chamber 502 to inside the vacuum chamber 502 in the space behind the lower electrode 506. The RF supply tube 522 is insulated from the RF bias housing arm 534, which provides a return path for RF power back to the RF power source 520. Equipment conduit 540 provides a passage for the equipment elements. Further details of the equipment elements are described in U.S. Pat. Nos. 5,948,704 and 7,732,728 and are not presented here for brevity. The gap 510 is preferably surrounded by a confinement ring assembly or shroud (not shown), details of which can be found in commonly owned U.S. Pat. No. 7,740,736, which is incorporated herein by reference. The interior of the vacuum chamber 502 is maintained at low pressure by connecting it to a vacuum pump through a vacuum inlet 580.

The conduit support plate 538 is mounted to an actuating mechanism 542, the details of which are described in commonly owned U.S. Patent No. 7,732,728, which is hereby incorporated by reference. The actuating mechanism 542, such as a servomechanical motor, stepper motor, or the like, is mounted to a vertical linear bearing 544 by a screw gear 546, such as a ball screw and a motor that rotates the ball screw. In an operation to adjust the size of the gap 510, the actuating mechanism 542 moves along the vertical linear bearing 544. FIG. 5A shows the configuration when the actuating mechanism 542 is in a high position on the linear bearing 544, thereby creating a small gap 510a. FIG. 5B shows the configuration when the actuating mechanism 542 is in an intermediate position on the linear bearing 544. As shown, the lower electrode 506, RF bias housing 530, conduit support plate 538, and RF power supply 520 have all been moved downward relative to the chamber housing 504 and upper electrode 508, resulting in an intermediate size gap 510b.

Figure 5C shows a large gap 510c when the actuation mechanism 542 is in a low position on the linear bearing. Preferably, the upper and lower electrodes 508, 506 remain coaxial while adjusting the gap, and the facing surfaces of the upper and lower electrodes remain parallel throughout the gap.

In this embodiment, the gap 510 between the lower electrode 506 and the information electrode 508 in the CCP chamber 502 can be adjusted during a multi-step process recipe (such as BARC, HARC, and STRIP) to maintain uniform etching across large diameter substrates, such as 300 mm wafers and flat panel displays. In particular, the chamber is associated with a mechanical arrangement that allows the linear motion required to achieve an adjustable gap between the lower electrode 506 and the upper electrode 508.

FIG. 5A shows a laterally deflected bellows 550 sealed at its proximal end to a conduit support plate 538 and at its distal end to a stepped flange 528 of a chamber wall plate 518. The inner diameter of the stepped flange defines an opening 512 in the chamber wall plate 518 through which an RF bias housing arm 534 passes. The distal end of the bellows 550 is clamped with a clamp ring 552.

The laterally deflected bellows 550 provides a vacuum seal and allows the RF bias housing 530, the conduit support plate 538, and the actuation mechanism 542 to move vertically. The RF bias housing 530, the conduit support plate 538, and the actuation mechanism 542 can be referred to as a cantilever assembly. Preferably, the RF power supply 520 moves with the cantilever assembly and can be attached to the conduit support plate 538. FIG. 5B shows the bellows 550 in a neutral position when the cantilever assembly is in the intermediate position. FIG. 5C shows the bellows 550 deflected laterally when the cantilever assembly is in the low position.

A labyrinth seal 548 provides a particle barrier between the bellows 550 and the interior of the plasma processing chamber housing 504. A fixed shield 556 is fixedly mounted inside the inner wall of the chamber housing 504 at the chamber wall plate 518 to provide a labyrinth groove 560 (slot) in which a movable shield plate 558 moves vertically to accommodate the vertical movement of the cantilever assembly. An outer portion of the movable shield plate 558 remains in the slot at all vertical positions of the lower electrode 506.

In the illustrated embodiment, the labyrinth seal 548 has a fixed shield 556 attached to the inner surface of the chamber wall plate 518 around the opening 512 in the chamber wall plate 518 that defines the labyrinth groove 560. The movable shield plate 558 is attached to the RF bias housing arm 534 and extends radially therefrom where the arm 534 passes through the opening 512 in the chamber wall plate 518. The movable shield plate 558 extends into the labyrinth groove 560 but is separated from the fixed shield 556 by a first gap and from the inner surface of the chamber wall plate 518 by a second gap to allow vertical movement of the cantilever assembly. The labyrinth seal 548 prevents particles that are dislodged from the bellows 550 from migrating into the interior 505 of the vacuum chamber and prevents radicals from the process gas plasma from migrating to the bellows 550 where the radicals can form deposits that are subsequently dislodged.

5A shows the movable shield plate 558 in a high position in the labyrinth groove 560 over the RF bias housing arm 534 when the cantilever assembly is in a high position (small gap 510a). FIG. 5C shows the movable shield plate 558 in a low position in the labyrinth groove 560 over the RF bias housing arm 534 when the cantilever assembly is in a low position (large gap 510c). FIG. 5B shows the movable shield plate 558 in a neutral or intermediate position in the labyrinth groove 560 when the cantilever assembly is in a middle position (medium gap 510b). Although the labyrinth seal 548 is shown as symmetric about the RF bias housing arm 534, in other embodiments the labyrinth seal 548 may be asymmetric about the RF bias arm 534.

FIG. 6 illustrates a semiconductor process cluster architecture with various modules interfaced with a vacuum transfer module 638 (VTM). The configuration of transfer modules to "transport" substrates among multiple containment facilities and processing modules may be referred to as a "cluster tool architecture" system. An airlock 630, also known as a loadlock or transfer module, is shown in the VTM 638 with four processing modules 620a-620d, which may be individually optimized to perform various manufacturing processes. By way of example, the processing modules 620a-620d may be implemented to perform substrate etching, deposition, ion implantation, substrate cleaning, sputtering, and/or other semiconductor processes, as well as laser metrology and other defect detection and defect identification methods. One or more processing modules (any of 620a-620d) may be implemented as disclosed herein, i.e., to etch recessed features in a substrate. The airlock 630 and processing modules 620a-620d may be referred to as "stations." Each station has a facet 636 that interfaces the station to a VTM 638. Inside the facets, sensors 1-18 are used to detect the passage of the substrate 626 as it moves between the respective stations.

A robot 622 transports substrates between stations. In one implementation, the robot may have one arm, and in another implementation, the robot may have two arms, where each arm has an end effector 624 to pick up and transport the substrate. A front-end robot 632 in an atmospheric transfer module (ATM) 640 may be used to transport substrates from cassettes or front opening unified pods (FOUPs) 634 in a load port module (LPM) 642 to the airlock 630. A module center 628 inside the process modules 620a-620d may be one location for placing substrates. An aligner 644 in the ATM 640 may be used to align the substrates.

In one exemplary processing method, a substrate is placed in one of the FOUPs 634 in the LPM 642. The front-end robot 632 transfers the substrate from the FOUP 634 to the aligner 644, which allows the substrate 626 to be properly centered before etching, deposited on, or otherwise processed. After alignment, the substrate is moved by the front-end robot 632 to the airlock 630. The airlock module has the ability to match the environment between the ATM and the VTM, allowing the substrate to be moved between the two pressure environments without damage. From the airlock module 630, the substrate is moved by the robot 622 through the VTM 638 to one of the processing modules 620a-620d, for example, processing module 620a. To accomplish this substrate movement, the robot 622 uses an end effector 624 on each arm. In processing module 620a, the substrate undergoes etching as described. The robot 622 then moves the substrate from the processing module 620a to the next desired location.

Note that the computer controlling the movement of the substrate can be local to the cluster architecture, located outside the cluster architecture at the manufacturing site, or remotely located and connected to the cluster architecture via a network.

In some implementations, the controller is part of a system, which may be part of the examples above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for processing, and/or specific processing components (such as wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics that control the operation of the system before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as a "controller" and may control various components or subparts of the system or systems. The controller may be programmed to control any of the processes disclosed herein, such as supply of process gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, settings of radio frequency (RF) generating tools, settings of RF matching circuits, frequency settings, flow settings, settings of fluid supplies, settings of potentials and operations, wafer transfers into or out of tools and other transfer tools and/or load locks connected to or bounding a particular system, depending on the processing requirements and/or type of the system.

In general, a controller may be defined as an electronic device having various integrated circuits, logic circuits, memory, and/or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include chips in firmware form that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors or microcontrollers that execute the program instructions (e.g., software). The program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define the operating parameters to perform a particular process on or for a semiconductor wafer or for a system. The operating parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more process steps in the course of manufacturing one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of the wafer.

The controller may be part of or connected to a computer that is integral to, networked with, or a combination of the system in some embodiments. For example, the controller may be in the "cloud" or may be all or part of a fab host computer system that may enable remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance metrics from multiple manufacturing operations, modify parameters of a current process, set processing steps to follow a current process, or begin a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for input or programming of parameters and/or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each process step that is performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool with which the controller is configured to interface or control. Thus, as previously discussed, the controller may be distributed, such as by having one or more separate controllers networked together and functioning toward a common purpose, such as the processing and control described herein. An example of a distributed controller for this purpose would be one or more integrated circuits on a chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and in combination control processing on the chamber.

Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the manufacturing and/or production of semiconductor wafers.

As noted above, depending on the processing step or steps being performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and/or load ports within a semiconductor manufacturing factory.

ADDITIONAL EMBODIMENTS The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, but not necessarily, such tools/processes are used or performed together in a common manufacturing facility.

Lithographic patterning of a film typically involves some or all of the following steps, each of which can be accomplished with many possible tools: (1) applying a photoresist to a workpiece, e.g., a substrate with a silicon nitride film formed thereon, using a spin-on or spray-on tool; (2) curing the photoresist using a hotplate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or UV or X-ray light using a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist, thereby patterning the resist, using a tool such as a wet bench or spray developer; (5) transferring the resist pattern to the underlying film or workpiece using a dry etch or plasma-assisted etch tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hardmask layer (e.g., an amorphous carbon layer) and another suitable hardmask (e.g., an antireflective layer) may be deposited before applying the photoresist.

It is to be understood that the configurations and/or techniques described herein are exemplary in nature and that many variations are possible, and therefore the specific embodiments or examples should not be construed in a limiting sense. The specific procedures or methods described herein may represent one or more of any number of processing strategies. As such, the various acts depicted may be performed in the order depicted, in other orders, in parallel, or even omitted. Similarly, the order of the above processing may be changed. Certain references are incorporated herein by reference. It is understood that any negation or disclaimer contained in such references does not necessarily apply to the embodiments described herein. Similarly, features described as necessary in such references may be omitted in the embodiments described herein.

As used herein, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" may be used interchangeably. Those skilled in the art will appreciate that the term "partially fabricated integrated circuit" may refer to a silicon wafer at any of the many stages of integrated circuit manufacturing. Wafers or substrates used in the semiconductor device industry are typically 200 mm, or 300 mm, or 450 mm in diameter. The detailed description above assumes that the embodiments are realized on a wafer. However, the embodiments are not so limited. The shape, size, and material of the workpiece may vary. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, etc. Unless otherwise specified for a particular parameter, the terms "about" and "approximately" as used herein are intended to mean ±10% relative to the associated value.

In the above description, numerous specific details are set forth in order to provide a thorough understanding of the present embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments have been described in conjunction with specific embodiments, it will be understood that no limitation of the disclosed embodiments is intended. The subject matter of the present disclosure includes all novel and non-obvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts and/or properties disclosed herein, and any and all equivalents thereof.
[Application Example 1] A method for etching features in a stack including a dielectric material in fabricating a 3D NAND structure, comprising:
receiving a substrate on a substrate support in a reaction chamber, the substrate including the stack and a mask layer patterned on top of the stack, the stack including either (a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon;
exposing the substrate to a plasma in the reaction chamber, thereby etching the feature in the stack on the substrate;
the plasma is generated from a plasma generating gas comprising WF ₆ , one or more fluorocarbons and/or hydrofluorocarbons, and one or more oxidants, the flow rate of WF ₆ being about 0.1-10 sccm;
the plasma is a capacitively coupled plasma;
the substrate is biased at a frequency between about 20 kHz and 1.5 MHz and at an RF power level between about 500 W and 20 kW per substrate;
the WF6 _and the fluorocarbons and/or hydrofluorocarbons form a tungsten-based polymer film on the sidewalls of the feature during etching, the tungsten-based polymer film promoting a uniform etch rate between the alternating layers of silicon oxide and silicon nitride or between the alternating layers of silicon oxide and polysilicon to prevent the sidewalls of the feature from being notched during etching;
method.
[Application Example 2] The method according to Application Example 1, wherein during the etching process, the WF ₆ dissociates into a tungsten-containing fragment and a fluorine-containing fragment, the tungsten-containing fragment remains relatively concentrated near the top of the feature compared to the fluorine-containing fragment, and the fluorine-containing fragment penetrates deeper into the feature compared to the tungsten-containing fragment.
[Application Example 3] The method described in Application Example 2, wherein the tungsten-based polymer film has a non-uniform composition along the sidewall of the feature such that the tungsten content of the tungsten-based polymer film near the top of the feature is higher than the tungsten content of the tungsten-based polymer film near the bottom of the feature.
[Application Example 4] The method according to Application Example 1, wherein the plasma is generated at an excitation frequency of about 20 MHz to 100 MHz and an RF power of about 6.3 kW or less.
[Application Example 5] The method according to Application Example 4, wherein the oxidant is O ₂ and the flow rate of the O ₂ is about 20 to 150 sccm.
[Application Example 6] The method according to Application Example 5, wherein the plasma generating gas further contains SF ₆ , and the flow rate of the SF ₆ is about 1 to 20 sccm.
[Application Example 7] The method according to Application Example 6, wherein the plasma generating gas further contains Kr, and the flow rate of the Kr is about 30 to 120 sccm.
[Application Example 8] The method according to Application Example 7, wherein the plasma generating gas further contains NF ₃ and the flow rate of the NF ₃ is about 30 sccm or less.
[Application Example 9] The method according to Application Example 8, wherein the fluorocarbon or hydrofluorocarbon _{includes one} or more of _C4F8 , _{C3F8 ,} C4F6 , and _CH2F2 , and the total flow rate of the fluorocarbon and _{hydrofluorocarbon} is about 30 to 240 _sccm .
[Application Example 10] The method according to Application Example 9, wherein the substrate support is maintained at a temperature of about 20 to 80° C. while etching the substrate.
[Application Example 11] The method according to Application Example 10, wherein the pressure in the reaction chamber is maintained at about 10 to 80 mTorr while etching the substrate.
Application Example 12. The method of application example 11, wherein the features are etched into the alternating layers of silicon oxide and silicon nitride.
[Application Example 13] The method according to Application Example 11, wherein the flow rate of WF ₆ is about 0.02% to 10% of the total flow rate of the plasma generating gas.
[Application Example 14] The method according to Application Example 13, wherein the flow rate of WF ₆ is about 0.02% to 1% of the total flow rate of the plasma generating gas.
[Application Example 15] The method according to Application Example 14, wherein the flow rate of WF ₆ is about 0.02% to 0.5% of the total flow rate of the plasma generating gas.
[Application Example 16] The method according to Application Example 1, wherein the substrate is biased at an RF frequency of about 300 kHz to 600 kHz.
[Application Example 17] The method according to Application Example 16, wherein the substrate is biased at an RF frequency of about 400 kHz.
[Application Example 18] A method according to any one of Application Examples 1 to 17, wherein the tungsten-based polymer film is formed on the layer of silicon oxide to a first thickness and on the layer of silicon nitride or polysilicon to a second thickness, the first thickness and the second thickness being different.
[Application Example 19] An apparatus for etching features into a stack including a dielectric material in fabricating a 3D NAND structure on a substrate, comprising:
a reaction chamber having a substrate support therein;
a capacitively coupled plasma generator;
an inlet for introducing material into the reaction chamber;
an outlet for removing material from the reaction chamber;
and a controller, the controller comprising:
receiving the substrate on the substrate support in the reaction chamber, the substrate including the stack and a mask layer patterned on top of the stack, the stack including either a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon;
A plasma is generated from a plasma generating gas including WF ₆ , one or more fluorocarbons and/or hydrofluorocarbons, and one or more oxidants, the flow rate of WF ₆ being about 0.1-10 sccm;
biasing the substrate at an RF power level of about 500 W to 20 kW at a frequency of about 20 kHz to 1.5 MHz;
exposing the substrate to the plasma in the reaction chamber, thereby etching the feature in the stack on the substrate;
The WF6 _and the fluorocarbons and/or hydrofluorocarbons form a tungsten-based polymer film on the sidewalls of the feature during the etching process, and the tungsten-based polymer film promotes a uniform etch rate between the alternating layers of silicon oxide and silicon nitride or between the alternating layers of silicon oxide and polysilicon, preventing the sidewalls of the feature from being notched during the etching process.
The apparatus is configured to:

Claims (18)

1. A method of etching features in a stack including a dielectric material in fabricating a 3D NAND structure, comprising:
receiving a substrate on a substrate support in a reaction chamber, the substrate including the stack and a mask layer patterned on top of the stack, the stack including either (a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon;
exposing the substrate to a plasma in the reaction chamber, thereby etching the feature in the stack on the substrate;
The plasma is generated from a plasma generating gas including WF ₆ , one or more fluorocarbons and/or hydrofluorocarbons, and one or more oxidants, the flow rate of WF ₆ being 0.1-10 sccm, the plasma generating gas further including Kr, the flow rate of Kr being 30-120 sccm;
the plasma is a capacitively coupled plasma;
the substrate is biased at a frequency between 20 kHz and 1.5 MHz and at an RF power level between 500 W and 20 kW per substrate;
the _WF6 and the fluorocarbons and/or hydrofluorocarbons form a tungsten-based polymer film on the sidewalls of the feature during etching, the tungsten-based polymer film promoting a uniform etch rate between the alternating layers of silicon oxide and silicon nitride or between the alternating layers of silicon oxide and polysilicon to prevent the sidewalls of the feature from being notched during etching;
method. 2. The method of claim 1, wherein during an etching process, the _WF6 dissociates into a tungsten-containing fragment and a fluorine-containing fragment, the tungsten-containing fragment remaining relatively concentrated near a top of the feature compared to the fluorine-containing fragment, and the fluorine-containing fragment penetrating deeper into the feature compared to the tungsten-containing fragment. The method of claim 2, wherein the tungsten-based polymer film is compositionally non-uniform along the sidewall of the feature such that the tungsten-based polymer film near the top of the feature has a higher percentage of tungsten compared to the tungsten-based polymer film near the bottom of the feature. 2. The method of claim 1, wherein the plasma is generated at an excitation frequency between 20 MHz and 100 MHz and an RF power of 6.3 kW or less. 5. The method of claim 4, wherein the oxidant is O ₂ and the flow rate of the O ₂ is between 20 and 150 sccm. 2. The method of claim 1 , wherein the plasma generating gas further comprises _SF6 , and the flow rate of the _SF6 is between 1 and 20 sccm. 2. The method of claim 1 , wherein the plasma generating gas further comprises _NF3 , and the flow rate of the _NF3 is less than or equal to 30 sccm. 2. The method of claim 1 , wherein the fluorocarbon or hydrofluorocarbon comprises one or more of _{C4F8 , C3F8 , C4F6} , and _CH2F2 , and the total flow rate of the fluorocarbon and _{hydrofluorocarbon} is between 30 and 240 _sccm . 10. The method of claim 1 , wherein the substrate support is maintained at a temperature of 20-80 ° C. while etching the substrate. 10. The method of claim 1 , wherein a pressure in the reaction chamber is maintained between 10 and 80 mTorr while etching the substrate. 2. The method of claim 1 , wherein the features are etched into the alternating layers of silicon oxide and silicon nitride. 2. The method of claim 1 , wherein the flow rate of _WF6 is 0.02% to 10% of the total flow rate of the plasma generating gas. 13. The method of claim 12 , wherein the flow rate of _WF6 is between 0.02% and 1% of the total flow rate of the plasma generating gas. 14. The method of claim 13 , wherein the flow rate of _WF6 is between 0.02% and 0.5% of the total flow rate of the plasma generating gas. 10. The method of claim 1, wherein the substrate is biased at an RF frequency between 300 kHz and 600 kHz. 16. The method of claim 15 , wherein the substrate is biased at an RF frequency of 400 kHz. 17. The method of claim 1, wherein the tungsten-based polymer film is formed on the layer of silicon oxide at a first thickness and on the layer of silicon nitride or polysilicon at a second thickness, the first thickness and the second thickness being different. 1. An apparatus for etching features into a stack including a dielectric material in fabricating a 3D NAND structure on a substrate, comprising:
a reaction chamber having a substrate support therein;
a capacitively coupled plasma generator;
an inlet for introducing material into the reaction chamber;
an outlet for removing material from the reaction chamber;
and a controller, the controller comprising:
receiving the substrate on the substrate support in the reaction chamber, the substrate including the stack and a mask layer patterned on top of the stack, the stack including either a) alternating layers of silicon oxide and silicon nitride, or (b) alternating layers of silicon oxide and polysilicon;
A plasma is generated from a plasma generating gas including _WF6 , one or more fluorocarbons and/or hydrofluorocarbons, and one or more oxidants, the flow rate of _WF6 being 0.1-10 sccm, the plasma generating gas further including Kr, the flow rate of Kr being 30-120 sccm;
biasing the substrate at an RF power level between 500 W and 20 kW at a frequency between 20 kHz and 1.5 MHz;
exposing the substrate to the plasma in the reaction chamber, thereby etching the feature in the stack on the substrate;
wherein the _WF6 and the fluorocarbons and/or hydrofluorocarbons form a tungsten-based polymer film on sidewalls of the feature during an etching process, the tungsten-based polymer film configured to promote a uniform etch rate between the alternating layers of silicon oxide and silicon nitride or between the alternating layers of silicon oxide and polysilicon to prevent the sidewalls of the feature from being notched during the etching process.

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