JP7621099B2 - Printed Wiring Boards - Google Patents

Description

This disclosure relates to a printed wiring board in which insulating layers and conductor layers are laminated alternately.

In small electronic devices such as smartphones, mobile phones, and other portable communication devices, many electronic components are attached to printed wiring boards. For this reason, in order to enable high-density arrangement of electronic components in the limited space of a printed wiring board, the number of semiconductor integrated circuits (ICs) mounted on printed wiring boards that have an array terminal structure, such as BGA (Ball Grid Array), is increasing.

A printed wiring board used in such small electronic devices is shown in Japanese Patent Application Laid-Open No. 2003-233696.
The printed wiring board shown in Patent Document 1 is composed of a plurality of layers, and from the surface, transmission lines and signal layers are provided on the L1 layer, a ground pattern on the L2 layer, a ground pattern and transmission lines on the L3 layer, a power supply pattern on the L4 layer, a ground pattern on the L5 layer, and transmission lines and signal layers on the L6 layer. Power supply connection vias are provided which electrically connect the L1 layer, L4 layer, and L6 layer, and ground connection vias are provided which electrically connect the L1 layer, L2 layer, L3 layer, L5 layer, and L6 layer, and a bypass capacitor is disposed on the L6 layer.

JP 2008-218444 A

In recent years, the semiconductor integrated circuit devices used in the above-mentioned small electronic devices have become faster in reading and writing data, while the operating voltage is decreasing due to the demand for lower power consumption.
As data reading and writing speeds increase and operating voltages drop, there is a demand for printed wiring boards that maintain low impedance between the power supply terminals and ground terminals of semiconductor integrated circuit devices, even at higher frequencies, in order to prevent malfunctions caused by fluctuations in power supply voltage due to the adverse effects of switching noise and the like.

The present disclosure has been made in consideration of the above points, and aims to obtain a printed wiring board that can keep the impedance between the power supply terminal and the ground terminal of a semiconductor integrated circuit device low up to the high frequency range.

The printed wiring board according to the present disclosure has a plurality of insulating layers and conductor layers laminated alternately, the conductor layer on the front side has a power supply pad to which a power supply terminal of a semiconductor integrated circuit device is connected and a ground pad to which a ground terminal of the semiconductor integrated circuit device is connected, the conductor layer on the back side has a power supply side pad and a ground side pad to which a terminal of a bypass capacitor electrically connected between the power supply terminal and the ground terminal of the semiconductor integrated circuit device is connected, the conductor layer on the back side has a ground pattern on the second or subsequent conductor layer from the front side, the power supply pattern is on the back side of the conductor layer having the ground pattern and is located on the front side of the conductor layer on the center of the thickness from the conductor layer on the front side to the conductor layer on the back side , the power supply pad to which the power supply terminal of the semiconductor integrated circuit device is connected, the power supply pattern, and a power through hole electrically connected to the power supply side pad to which one terminal of the bypass capacitor is connected, the ground pad to which the ground terminal of the semiconductor integrated circuit device is connected, the ground pattern, and the ground through hole electrically connected to the ground side pad to which the other end of the bypass capacitor is connected, and the power supply through hole and the ground through hole are arranged adjacent to each other in the conductor layer on the front side .

According to the present disclosure, in a printed wiring board in which insulating layers and conductor layers are alternately laminated, the impedance between the power supply terminal and the ground terminal of the printed wiring board for a semiconductor integrated circuit device can be kept low up to the high frequency range.

1 is an enlarged cross-sectional view showing a main portion of a printed wiring board according to a first embodiment; 1 is an enlarged schematic view of a main portion of a surface of a printed wiring board according to a first embodiment of the present invention; 1 is an enlarged rear view (see-through view from the front) of a main portion of a printed wiring board according to a first embodiment; FIG. 11 is a diagram showing the relationship of impedance of a bypass capacitor to frequency. 4 is an enlarged cross-sectional view of a main portion for explaining a current path of a power supply system in the printed wiring board according to the first embodiment; FIG. 3 is an equivalent circuit diagram showing a current path of a power supply system in the printed wiring board according to the first embodiment; 5A and 5B are diagrams illustrating mutual inductance between a power through hole and a ground through hole in the printed wiring board according to the first embodiment. FIG. 11 is an enlarged surface view of a main portion showing a printed wiring board according to a second embodiment. FIG. 11 is an enlarged rear view (see-through view from the front) of a main portion of a printed wiring board according to a second embodiment.

Embodiment 1.
A printed wiring board according to a first embodiment will be described with reference to FIGS. 1 to 3. FIG.
The printed wiring board according to the first embodiment is intended for a printed wiring board in which insulating layers and conductor layers are alternately laminated, and for a printed wiring board on which a semiconductor integrated circuit device (IC) having an array terminal structure, such as a BGA (Ball Grid Array), is mounted on the surface.

The semiconductor integrated circuit device 40 has a plurality of solder balls as external terminals on its bottom surface, and the plurality of solder balls are arranged in a lattice pattern with a pitch of 0.65 mm vertically and horizontally. A portion of the plurality of solder balls constitutes a plurality of power supply terminals 40a, a plurality of ground terminals 40b, and a plurality of signal terminals 40c. The plurality of power supply terminals 40a and the plurality of ground terminals 40b are grouped together and arranged in a lattice pattern .

1 to 3 are diagrams showing the main parts for mainly explaining the characteristic parts of the printed wiring board of embodiment 1, that is, the part where a plurality of power supply pads 11a and a plurality of ground pads 11b are arranged in a cluster, as well as the conductor layer having a power supply pattern and the conductor layer having a ground pattern.
For the sake of simplicity, the semiconductor integrated circuit device 40 is shown to have one power supply terminal 40a, one ground terminal 40b, and two signal terminals 40c.
The relationships in other parts of the printed wiring board are similar to those in commonly known multi-layer printed wiring boards, and therefore a description thereof will be omitted.

The printed wiring board according to the first embodiment has eight conductor layers. However, the number of conductor layers is not limited to eight, and it is sufficient that the number of conductor layers is at least six or more.
As shown in FIG. 1, the multiple conductor layers are stacked in the following order from the front surface: front surface conductor layer 11, second conductor layer 12, third conductor layer 13, fourth conductor layer 14, fifth conductor layer 15, sixth conductor layer 16, seventh conductor layer 17, and back surface conductor layer 18.

The insulating layers are interposed between the conductor layers.
That is, rear insulating layer 27 has rear conductor layer 18 formed on the rear surface by copper plating or vapor deposition, and seventh conductor layer 17 formed on the front surface by copper plating or vapor deposition.
The sixth insulating layer 26 is formed by coating the surface of the back insulating layer 27 with a resin such as epoxy resin or polyimide so as to cover the surface of the seventh conductor layer 17 and then solidifying it, and the sixth conductor layer 16 is formed on the surface by copper plating or vapor deposition.

The fifth to second insulating layers 25-22 are formed in the same manner, by coating and solidifying a resin such as epoxy resin or polyimide so as to cover the surfaces of the conductor layers 16-13 formed in each layer on the surface of the insulating layers 26-23 immediately below, and the conductor layers 15-12 are formed on the surfaces by copper plating or vapor deposition.
The surface insulating layer 21 is formed by coating the surface of the second insulating layer 22 with a resin such as epoxy resin or polyimide so as to cover the second conductor layer 12 and then solidifying it, and the surface conductor layer 11 is formed on the surface by copper plating or vapor deposition.

The front conductor layer 11 and front insulating layer 21, the second conductor layer 12 and second insulating layer 22, the third conductor layer 13 and third insulating layer 23, the fourth conductor layer 14 and fourth insulating layer 24, the fifth conductor layer 15 and fifth insulating layer 25, the sixth conductor layer 16 and sixth insulating layer 26, the seventh conductor layer 17 and back insulating layer 27 and back conductor layer 18 may each be an insulating sheet with copper foil, and may be a laminate of insulating sheets with copper foil.

The conductor layer 11 on the surface has a power supply wiring pattern 11A, a ground wiring pattern 11B, and a signal wiring pattern 11C, and also has a plurality of power supply pads 11a, a plurality of ground pads 11b, and a plurality of signal pads 11c. The plurality of power supply pads 11a and the plurality of ground pads 11b are arranged to correspond to the plurality of power supply terminals 40a and the plurality of ground terminals 40b in the semiconductor integrated circuit device 40, respectively.

When mounted on a printed wiring board, the multiple power supply terminals 40a and the multiple ground terminals 40b of the semiconductor integrated circuit device 40 are electrically and mechanically connected to the multiple power supply pads 11a and the multiple ground pads 1b, respectively, by soldering.
FIG. 2 shows a diagram in which a plurality of power supply pads 11a and a plurality of ground pads 11b are concentratedly arranged.

As shown in FIG. 2, the multiple power supply pads 11a and the multiple ground pads 11b are composed of pads arranged in a grid pattern in multiple rows and columns, and the multiple power supply pads 11a and the multiple ground pads 11b are arranged in columns, with the power supply pads 11a arranged in the first, fourth, and fifth columns, and the ground pads 11b arranged in the second, third, and sixth columns.
That is, the power supply pads 11a and the ground pads 11b are arranged alternately every two rows.

The pads are arranged in a grid pattern of multiple rows and columns, with the pitch (the distance between the centers of the circles) in both the row and column directions being 0.65 mm.
Each of the plurality of power supply pads 11a and the plurality of ground pads 11b has a substantially circular planar shape with a diameter of 0.30 mm.

The second conductor layer 12 has a ground pattern. The ground pattern is a conductor layer pattern that is applied to the entire surface of the second insulating layer 22 via a clearance 41 between it and the power supply through hole 31 described below and a clearance (not shown) between it and the signal wiring through hole (not shown), and is electrically connected to the side wall of the ground through hole 32.

The third conductor layer 13 has a power supply pattern. The power supply pattern is a conductor layer pattern provided on the surface of the third insulating layer 23 with a clearance 42 between it and the ground through hole 32 and a clearance (not shown) between it and the signal wiring through hole, and is electrically connected to the side wall of the power supply through hole 31.
Since only the thin second insulating layer 22 is interposed between the third conductor layer 13 and the second conductor layer 12, a parasitic capacitance for high frequencies exists between the ground pattern in the second conductor layer 12 and the power supply pattern in the third conductor layer 13.

The fourth conductor layer 14 has a ground pattern. The ground pattern is a conductor layer pattern that is applied to the entire surface of the fourth insulating layer 24 with a clearance 41 between it and the power supply through hole 31 and a clearance (not shown) between it and the signal wiring through hole, and is electrically connected to the sidewall of the ground through hole 32.

The fifth conductor layer 15 and the sixth conductor layer 16 each have a signal wiring pattern in which multiple wirings are formed. Each of the multiple wirings in the signal wiring pattern is electrically connected to the sidewall of the corresponding signal wiring through hole, and the signal wiring through holes other than the corresponding signal wiring through hole are formed separately from the power supply through hole 31 and the ground through hole 32.

The seventh conductor layer 17 has a ground pattern. The ground pattern is a conductor layer pattern that is applied to the entire surface of the insulating layer 27 on the back side with a clearance 41 between it and the power supply through hole 31 and a clearance (not shown) between it and the signal wiring through hole, and is electrically connected to the side wall of the ground through hole 32.

The conductor layer 18 on the back surface has a power supply wiring pattern 18A, a ground wiring pattern 18B and a signal wiring pattern 18C, as well as a plurality of power supply pads 18a, a plurality of ground pads 18b and a plurality of signal pads (not shown).
FIG. 3 is a perspective view from the front side, and all overlapping portions are shown by solid lines.

The multiple power supply side pads 18a and multiple ground side pads 18b are arranged in a grid pattern with multiple rows and columns as shown in FIG. 3. In the columns, the power supply side pads 18a and the ground side pads 18b are arranged alternately, and in the rows, the ground side pads 18b are arranged in the first, fourth, and fifth columns, and the power supply side pads 18a are arranged in the second, third, and sixth columns.

That is, the power supply pads 18a and the ground pads 18b are arranged alternately in columns and alternately every two columns in rows.
In addition, in each row, adjacent power supply side pads 18a and ground side pads 18b are arranged so that the line segment connecting the power supply side pads 18a and ground side pads 18b is inclined at 30 degrees with respect to the row, and the midpoint of the line segment is located on the line connecting the adjacent power supply side pads 18a and ground side pads 18b.
The power supply side pads 18a in adjacent rows in adjacent columns are connected by power supply wiring in the power supply wiring side pattern 18A, and the ground side pads 18b in adjacent rows in adjacent columns are connected by ground wiring in the ground wiring side pattern 18B.

The power supply pads 18a and ground pads 18b are arranged in a lattice pattern of rows and columns, with the pitches (center-to-center distances of circles) in both the row and column directions being 0.65 mm.
Each of the plurality of power supply side pads 18a and ground side pads 18b has a substantially circular planar shape with a diameter of 0.30 mm.

In each row, a bypass capacitor 50 is connected between adjacent power supply side pads 18a and ground side pads 18b.
The bypass capacitor 50 is a surface-mount type laminated ceramic capacitor of 0603 square chip structure, and is a roughly rectangular parallelepiped of dimensions 0.3 mm in height, 0.3 mm in width and 0.6 mm in length, with terminals 50a, 50b at both ends.

When mounted on a printed wiring board, one terminal 50a and the other terminal 50b of the bypass capacitor 50 are electrically and mechanically connected to the multiple power supply pads 18a and the multiple ground pads 18b, respectively, by soldering.
The bypass capacitor 50 has its midpoint in the length direction positioned on a line connecting the adjacent power supply side pad 18a and ground side pad 18b, and is mounted on the back surface of the printed wiring board at an angle of 30 degrees to the row.

The thickness t of the printed wiring board having eight conductor layers configured in this way is 1.0 mm to 1.6 mm. The thickness is measured from the front surface of the front conductor layer 11 to the back surface of the back conductor layer 18, as shown in Figure 1.

Next, the power supply through hole 31 and the ground through hole 32 will be described.
In the printed wiring board according to the first embodiment, the through hole has a front land formed on the front surface of the insulating layer located on the front surface, a back land formed on the back surface of the insulating layer located on the back surface, an intermediate layer land formed on the front surface of the insulating layer of an inner layer having a conductor layer formed on its front surface and connected to the conductor layer of the inner layer, and a penetrating conductor layer (via) provided on the inner wall of the through hole reaching from the insulating layer located on the front surface to the insulating layer located on the back surface and electrically connecting the front surface land, the back surface land, and the intermediate layer land.
The through conductor layer is formed by conductor plating from the surface of the conductor layer located on the front surface to the back surface of the conductor layer located on the back surface along the inner wall of a through hole formed by drilling from the surface of the insulating layer located on the front surface to the back surface of the insulating layer located on the back surface.

As shown in FIG. 1, each of the power supply through holes 31 has a front land 31a formed on the front insulating layer 21 and connected to the power supply pad 11a formed on the front insulating layer 21 via the power supply wiring layer in the power supply wiring pattern 11A, a back land 31b formed on the back surface of the back insulating layer 21 and connected to the power supply pad 18a formed on the back surface of the back insulating layer 27 via the power supply side wiring layer in the power supply wiring side pattern 18A, and a through conductor layer (via) 31c on the inner wall of the through hole that reaches from the front insulating layer 21 to the back surface of the back insulating layer 27 and electrically connects the front land 31a and the back land 31b.

As shown in FIG. 1, each of the multiple ground through holes 32 has a front land 32a formed on the front insulating layer 21 and connected to the ground pad 11b formed on the front insulating layer 21 via the ground wiring layer in the ground wiring pattern 11B, a back land 32b formed on the back surface of the back insulating layer 27 and connected to the ground side pad 18b formed on the back surface of the back insulating layer 27 via the ground side wiring layer in the ground wiring pattern 18B, and a through conductor layer (via) 32c on the inner wall of the through hole that reaches from the front insulating layer 21 to the back surface of the back insulating layer 27 and electrically connects the front land 32a and the back land 32b.

As shown in FIG. 2, the multiple power supply through holes 31 and the multiple ground through holes 32 have one less row than the power supply pads 11a and ground pads 11b arranged in a lattice pattern, and are arranged in odd-numbered columns.
That is, the power supply through holes 31 and the ground through holes 32 are arranged alternately in the column direction between a plurality of power supply pads 11a arranged in a column direction and a plurality of ground pads 11b arranged in the adjacent column direction.

The power supply through holes 31 and the ground through holes 32 arranged alternately in the column direction are located between adjacent rows, in other words, between the power supply pads 11a arranged adjacently in the column direction, and between the ground pads 11b arranged adjacently in the column direction.
That is, the power supply through hole 31 or the ground through hole 32 is disposed at the center of a square formed by two adjacent power supply pads 11a and two adjacent ground pads 11b.

The multiple power supply through holes 31 and the multiple ground through holes 32 are alternately arranged in the column direction at a pitch of 0.65 mm (the distance between the centers of the circles) and in the row direction at a pitch of 1.30 mm (the distance between the centers of the circles), which is twice the pitch in the column direction.
Each of the plurality of power supply through holes 31 and the plurality of ground through holes 32 has a through hole diameter of 0.20 mm, in which the through conductor layer 31c and the through conductor layer 32c are formed.

In each of the power supply through holes 31, the front surface lands 31a are connected to power supply pads 11a located in two adjacent rows of adjacent columns via the power supply wiring layer in the power supply wiring pattern 11A as shown in FIG. 2, and the back surface lands 31b are connected to power supply side pads 18a located in adjacent rows of adjacent columns via the power supply side wiring layer in the power supply wiring pattern 18A as shown in FIG. 3.
In other words, the front surface lands 31a of each power supply through hole 31 are electrically connected to the two closest power supply pads 11a, and the back surface lands 31b are electrically connected to the two closest power supply pads 18a.

As shown in FIG. 2, the front surface land 32a of each of the ground through holes 32 is connected to ground pads 11b located in two adjacent rows of adjacent columns via the ground wiring layer in the ground wiring pattern 11B, and the back surface land 32b is connected to ground side pads 18b located in adjacent rows of adjacent columns via the ground side wiring layer in the ground wiring pattern 18B, as shown in FIG. 3.
That is, in each of the ground through holes 32, the front surface land 32a is electrically connected to the nearest ground pad 11b, and the back surface land 32b is electrically connected to the nearest ground pad 18b.

By configuring in this manner, the power supply pad 11a is connected to the power supply through hole 31 arranged in an adjacent row of an adjacent column via the power supply wiring in the power supply wiring pattern 11A, and is connected to the power supply side pad 18a arranged in an adjacent row of an adjacent column via the power supply wiring in the power supply wiring side pattern 18A.
In addition, the ground pad 11b is connected to a ground through hole 32 arranged in an adjacent row of an adjacent column via a ground wiring in the ground wiring pattern 11B, and is connected to a ground side pad 18b arranged in an adjacent row of an adjacent column via a ground wiring in the ground wiring side pattern 18B.

When the semiconductor integrated circuit device 40 and the bypass capacitor 50 are mounted on a printed wiring board, a high frequency current path is formed from each of the power supply terminals 40a of the semiconductor integrated circuit device 40 through the corresponding power supply pad 11a-power supply wiring in the power supply wiring pattern 11A-power supply through hole 31 arranged in an adjacent row of an adjacent column-power supply wiring in the power supply wiring side pattern 18A-power supply side pad 18a arranged in an adjacent row of an adjacent column-bypass capacitor 50-ground side pad 18b arranged in an adjacent row of an adjacent column-ground wiring in the ground wiring side pattern 18B-ground through hole 32-ground wiring in the ground wiring pattern 11B-ground pad 11b to each of the ground terminals 40b of the semiconductor integrated circuit device 40.

Next, we will explain how the printed wiring board according to embodiment 1 can keep the impedance between the power supply pad 11a and the ground pad 11b low up to the high frequency range when the semiconductor integrated circuit device 40 and the bypass capacitor 50 are mounted on the printed wiring board and the semiconductor integrated circuit device 40 is operating.

When a bypass capacitor 50 is connected between the power supply terminal 40a and the ground terminal 40b of the semiconductor integrated circuit device 40 to suppress power supply voltage fluctuations due to high frequencies such as switching noise, it is necessary to lower the impedance of the entire system between the power supply pad 11a to which the power supply terminal 40a is connected and the ground pad 11b to which the ground terminal 40b is connected. To lower the impedance, it is necessary to increase the capacitance and decrease the inductance.

First, the ability to maintain low impedance up to high frequency ranges will be explained with reference to Fig. 4, which shows the frequency characteristics of a capacitor. In Fig. 4, the horizontal axis represents the logarithm of frequency, and the vertical axis represents the logarithm of impedance.
A capacitor exhibits characteristics close to ideal capacitance C for frequencies below its self-resonant frequency, and impedance Z can be expressed by the following equation (1) and is inversely proportional to frequency (ω).
Z=1/jωC (1)
In FIG. 4, line C1 indicates the characteristic line based on equation (1) when capacitance C is large, and line C2 indicates the characteristic line based on equation (1) when capacitance C is small.
From the lines C1 and C2, it can be seen that the impedance Z is lower as the capacitance C is larger.

On the other hand, for frequencies equal to or higher than the self-resonant frequency, the inductance L in the system to which the capacitor is connected becomes dominant, and the impedance Z can be expressed by the following equation (2) and is proportional to the frequency (ω).
Z = jωL (2)
In FIG. 4, line L1 indicates the characteristic line based on equation (2) when the inductance L is small, and line L2 indicates the characteristic line based on equation (2) when the inductance L is large.
It can be seen from the straight lines L1 and L2 that the impedance Z is lower when the inductance L is smaller.

In recent years, the data read/write speed of semiconductor integrated circuit device 40 has been increasing, and the high frequency waves caused by switching noise and the like generated by high-speed data read/write in semiconductor integrated circuit device 40 are equal to or higher than the self-resonant frequency of bypass capacitor 50, and in many cases, bypass capacitor 50 is used in a region dominated by inductance L.
Therefore, the printed wiring board according to the first embodiment exhibits a characteristic due to the bypass capacitor that is a combination of the capacitance characteristic below the self-resonant frequency of the bypass capacitor and the inductance characteristic above the self-resonant frequency, and is configured such that the capacitance C has a large value C1 and the inductance L has a small value L1, as shown by the thick line R in FIG. 4 .

In light of the above, a current path that flows between the power supply terminal 40a and the ground terminal 40b of the semiconductor integrated circuit device 40 in the printed wiring board according to the first embodiment will be described.
That is, the current path from the power supply source to the semiconductor integrated circuit device 40 and the current path for high frequency waves due to switching noise etc. generated by high speed data reading and writing in the semiconductor integrated circuit device 40 will be described with reference to FIGS.

The current path from the power supply source to the semiconductor integrated circuit device 40 is a path from the power supply source (not shown) to the multiple power supply terminals 40a of the semiconductor integrated circuit device 40, via the power supply pattern in the third conductor layer 13--the multiple power supply through holes 31--the multiple power supply wires in the power supply wiring pattern 11A--the multiple power supply pads 11a, as shown by arrow i1 in FIG. 5.
The current path i 1 is the most important path for a DC-like current for supplying DC power to the semiconductor integrated circuit device 40 .

There are two current paths for high frequency, as shown by arrows i2 and i3 in FIG.
Current path i2 is a path from the ground terminal 40b of the semiconductor integrated circuit device 40 to the power supply terminal 40a of the semiconductor integrated circuit device 40, passing through the ground pad 11b to which the ground terminal 40b corresponds, the ground wiring in the ground wiring pattern 11B, the ground through hole 32, the ground wiring in the ground wiring side pattern 18B, the ground side pad 18b, the bypass capacitor 50, the power supply side pad 18a, the power supply wiring in the power supply wiring side pattern 18A, the power supply through hole 31, the power supply wiring in the power supply wiring pattern 11A, and the power supply pad 11a.

Similar current paths i2 are formed between the plurality of ground terminals 40b and the plurality of power supply terminals 40a of the semiconductor integrated circuit device 40, respectively.
Since the bypass capacitor 50 is connected between the power supply terminal 40a and the ground terminal 40b of the semiconductor integrated circuit device 40, the semiconductor integrated circuit device 40 responds quickly to high frequency power supply voltage fluctuations caused by switching noise, etc., generated by high speed data reading and writing in the semiconductor integrated circuit device 40.

As shown in FIG. 6, the current path i2 is an equivalent circuit that extends from the ground terminal 40b of the semiconductor integrated circuit device 40 to the power supply terminal 40a of the semiconductor integrated circuit device 40 via the inductance component L321 from the front land 32a of the ground through hole 32 to the connection point of the ground through hole 32 with the ground pattern on the second conductor layer 12, the inductance component L322 from the connection point of the ground through hole 32 with the ground pattern on the second conductor layer 12 to the back land 32b, the capacitance component C50 of the bypass capacitor 50, the inductance component L312 from the back land 31b of the power supply through hole 31 to the connection point of the power supply pattern on the third conductor layer 13, and the inductance component L311 from the connection point of the power supply through hole 31 with the power supply pattern on the third conductor layer 13 to the front land 31a.

The bypass capacitors 50 arranged in the current path i2 are arranged between adjacent power supply pads 18a and ground pads 18b in each row of the multiple power supply pads 18a and multiple ground pads 18b arranged alternately in columns and alternately every two columns in rows, as shown in FIG. 3. This allows a large number of bypass capacitors 50 to be densely arranged, and the capacitance C between the power supply pad 11a and the ground pad 11b is large.

On the other hand, similar current paths i2 are formed between the multiple ground terminals 40b and the multiple power supply terminals 40a of the semiconductor integrated circuit device 40, so the inductance components L321, L322, L312, and L311 of the multiple current paths i2 as a whole decrease.

Moreover, since the multiple power supply through holes 31 and the multiple ground through holes 32 are arranged close to each other in the column and row directions, as shown in FIG. 7, mutual induction by the high-frequency currents I1 and I2 flowing through the adjacent power supply through holes 31 and ground through holes 32 is strong, and since the directions of the high-frequency currents are opposite, the magnetic fluxes Φ1 and Φ2 generated by the respective high-frequency currents cancel each other out, so mutual inductances M1 and M2 come into play, and the inductance components L321, L322, L312, and L311 are further reduced.

Since the thickness of the second insulating layer 22 is thin, a parasitic capacitance for high frequencies exists between the ground pattern in the second conductor layer 12 and the power supply pattern in the third conductor layer 13. As a result, a current path i3 for high frequencies exists.
Current path i3 is a path from ground terminal 40b of semiconductor integrated circuit device 40, via ground pad 11b to which the multiple ground terminals 40b correspond, ground wiring in ground wiring pattern 11B, ground through hole 32, ground pattern in second conductor layer 12, parasitic capacitance between the ground pattern in the second conductor layer 12 and the power supply pattern in the third conductor layer 13, power supply pattern in the third conductor layer 13, power supply through hole 31, power supply wiring in power supply wiring pattern 11A, and power supply pad 11a, to multiple power supply terminals 40a of semiconductor integrated circuit device 40.
Similar current paths i3 are formed between the plurality of ground terminals 40b and the plurality of power supply terminals 40a of the semiconductor integrated circuit device 40, respectively.

In terms of an equivalent circuit, as shown in Figure 6, the current path i3 is a path from the multiple ground terminals 40b of the semiconductor integrated circuit device 40 to the multiple power supply terminals 40a of the semiconductor integrated circuit device 40, via an inductance component L321 from the surface land 32a of the multiple ground through holes 32 to the connection point of the multiple ground through holes 32 with the ground pattern on the second conductor layer 12, a capacitance component C22 between the ground pattern on the second conductor layer 12 and the power supply pattern on the third conductor layer 13, and an inductance component L311 from the connection point of the multiple power supply through holes 31 with the power supply pattern on the third conductor layer 13 to the surface land 31a.
The current path i3 is short, and the inductance component L321 and the inductance component L311 are small, so that the inductance component of the current path as a whole for high frequencies is small.

Therefore, in the printed wiring board according to the first embodiment, a large number of bypass capacitors 50 can be arranged, the capacitance C can be set large, and the inductance L of the current paths i2 and i3 as a whole for high frequencies can be set small, so that the impedance Z between the power supply pad 11a and the ground pad 11b can be reduced, and fluctuations in the power supply voltage due to adverse effects of high frequencies such as switching noise and the like, which causes malfunctions, can be suppressed.

As described above, in the printed wiring board according to embodiment 1, firstly, in a printed wiring board in which insulating layers and conductor layers are alternately laminated multiple times, a ground pattern is provided in the second conductor layer from the front surface, and a power supply pattern is provided in a conductor layer that is third or later from the front surface and is located on the front side of the center of the thickness from the conductor layer on the front surface to the conductor layer on the back surface. Therefore, a current path i3 for high frequencies is formed between the power supply pad and ground pad formed on the conductor layer on the front surface, and the inductance component of the overall current path for high frequencies can be reduced.
As a result, it is possible to suppress malfunctions caused by fluctuations in the power supply voltage due to adverse effects of high frequencies such as switching noise.

Secondly, the multiple power supply through holes and the multiple ground through holes are arranged alternately in the column direction between the multiple power supply pads arranged in the column direction and the multiple ground pads arranged in the adjacent column direction, so that mutual induction due to high-frequency current works strongly between the power supply through holes and the ground through holes, resulting in an effect of mutual inductance, and the inductance in the current paths i2 and i3 for high frequencies can be reduced.
As a result, it is possible to suppress malfunctions caused by fluctuations in the power supply voltage due to adverse effects of high frequencies such as switching noise.

Thirdly, the multiple power supply through holes and the multiple ground through holes are arranged alternately in the column direction between the multiple power supply pads arranged in the column direction and the multiple ground pads arranged in the adjacent column direction, and are also arranged alternately in the row direction. This allows a large number of bypass capacitors to be arranged closely together, thereby increasing the capacitance in the current path i2.
As a result, it is possible to suppress malfunctions caused by fluctuations in the power supply voltage due to adverse effects of high frequencies such as switching noise.

Fourth, since the power supply side pads and ground side pads are arranged such that the bypass capacitors are inclined with respect to the row direction, a large number of bypass capacitors can be arranged closely together, and the capacitance in the current path i2 can be increased.
As a result, it is possible to suppress malfunctions caused by fluctuations in the power supply voltage due to adverse effects of high frequencies such as switching noise.

Fifth, the power through hole and the ground through hole each have a front land on the insulating layer located on the front side, which is connected to the power pad to which the power terminal of the semiconductor integrated circuit device is connected, and a back land on the insulating layer located on the back side, which is connected to the power pad to which one terminal of the bypass capacitor is connected, on the inner wall of the through hole that reaches from the front surface of the insulating layer located on the front side to the back surface of the insulating layer located on the back side, electrically connecting the front land and the back pad, and having a through conductor layer on the side wall that is electrically connected to the power pattern or the ground pattern, making it possible to produce a printed wiring board at low cost.

Embodiment 2.
Second Embodiment A printed wiring board according to a second embodiment will be described with reference to FIGS.
The printed wiring board of the second embodiment differs from the printed wiring board of the first embodiment in that the printed wiring board is composed of pads arranged in a lattice pattern with multiple power supply pads 11a and multiple ground pads 11b in multiple rows and multiple columns, with the row pitch being the same as the column pitch, and with the multiple power supply pads 11a and multiple ground pads 11b and the multiple power supply through holes 31 and ground through holes 32 arranged in a manner corresponding to the arrangement of the multiple power supply pads 11a and multiple ground pads 11b, in that the power supply pads 11a and ground pads 11b are arranged in a lattice pattern with the row pitch being longer than the column pitch, and with the power supply pads 11a and ground pads 11b and the power supply through holes 31 and ground through holes 32 arranged in a manner corresponding to the arrangement of the multiple power supply pads 11a and ground pads 11b, but is otherwise the same.
In addition, in each figure, the same symbols indicate the same or corresponding parts.

The printed wiring board according to the second embodiment is a printed wiring board for mounting a high-speed memory, LPDDR4-SDRAM (Low Power Double Data Rate Synchronous Dynamic Random Access Memory), as a semiconductor integrated circuit device 40.
The LPDDR4-SDRAM has a number of solder balls as external terminals on the bottom surface, and the solder balls are arranged in a grid pattern with a vertical pitch of 0.65 mm and a horizontal pitch of 0.80 mm, forming a BGA package. Some of the solder balls form a power supply terminal 40a, a ground terminal 40b, and a number of signal terminals 40c. The power supply terminals 40a and the ground terminals 40b are arranged in a group.

FIG. 8 shows two power supply pads 11 a , one ground pad 11 b , one power supply through hole 31 , and one ground through hole 32 .
When mounted on a printed wiring board, the two power supply terminals 40a and the ground terminal 40b of the semiconductor integrated circuit device 40 are electrically and mechanically connected to the two power supply pads 11a and the one ground pad 1b by soldering, respectively.
The two power supply pads 11a are arranged in adjacent columns and adjacent rows, with a spacing of 0.80 mm between the two power supply pads 11a in the row direction and 0.65 mm between the two power supply pads 11a in the column direction.

The ground pad 11b is disposed adjacent to one of the two power supply pads 11a in the row direction, and adjacent to the other of the two power supply pads 11a in the column direction.
The row distance between ground pad 11b and one of the power supply pads adjacent thereto in the row direction is 0.80 mm, and the column distance between ground pad 11b and the other power supply pad adjacent thereto in the column direction is 0.65 mm.
Each of the power supply pad 11a and the ground pad 11b has a substantially circular planar shape with a diameter of 0.30 mm.

The power supply through hole 31 is disposed at the midpoint of the line segment connecting the two power supply pads 11a.
The power through hole 31 has a front surface land 31a connected to two power pads 11a via a power wiring layer in the power wiring pattern 11A.
The power supply through hole 31 has a surface land 31a electrically connected to the two power supply pads 11a located closest to each other.

The ground through-holes 32 are arranged adjacent to the power through-holes 31 in the row direction on the ground pad 11b side.
The surface land 32a of the ground through hole 32 is connected to the ground pad 11b via the ground wiring layer of the ground wiring pattern 11B.
The ground through hole 32 is electrically connected to the ground pad 11b to which the front surface land 32a is closest.

The power supply through holes 31 and the ground through holes 32 are spaced 0.80 mm apart in the row direction and are close to each other, so as shown in Figure 7, mutual induction due to the high-frequency currents flowing through the adjacent power supply through holes 31 and ground through holes 32 is strong. Furthermore, because the directions of the high-frequency currents are opposite, the magnetic fluxes generated by each high-frequency current cancel each other out, so the inductance of the power supply through holes 31 and ground through holes 32 is small.

FIG. 9 is a perspective view from the front, with all overlapping portions shown in solid lines, and shows power supply pad 18 a, ground side pad 18 b, power supply through hole 31, ground through hole 32, and bypass capacitor 50.
The power supply through hole 31 and the ground through hole 32 shown in FIG. 9 are the same as the power supply through hole 31 and the ground through hole 32 shown in FIG.

The power supply side pad 18a and the ground side pad 18b are arranged adjacent to each other in a straight line in the row direction, are close to the power supply through hole 31 and the ground through hole 32 in the column direction, and are located between the power supply through hole 31 and the ground through hole 32.
The distance between the power supply pads 18a and the ground pads 18b in the row direction is the same as the length of the bypass capacitor 50, 0.6 mm.

The back surface land 31b of the power through hole 31 is connected to the power supply side pad 18a via the power supply wiring layer in the power supply wiring side pattern 18A.
The power supply through hole 31 is electrically connected to the power supply side pad 18a in the position closest to the rear surface land 31b.

The back surface land 32b of the ground through hole 32 is connected to the ground side pad 18b via the ground wiring layer of the ground wiring side pattern 18B.
The ground through hole 32 has a rear land 32b electrically connected to the nearest ground pad 18b.

When the bypass capacitor 50 is mounted on the printed wiring board, the power supply side pad 18a is electrically and mechanically connected to one terminal 50a of the bypass capacitor 50, and the ground side pad 18b is electrically and mechanically connected to the other terminal 50b of the bypass capacitor 50 by soldering.

Even in the printed wiring board according to the second embodiment configured in this way, when the semiconductor integrated circuit device 40 and the bypass capacitor 50 are mounted on the printed wiring board, a high frequency current path is formed from the two power supply terminals 40a of the semiconductor integrated circuit device 40 through the two power supply pads 11a-two power supply wires in the power supply wire pattern 11A-power supply through hole 31-power supply wires in the power supply wire side pattern 18A-power supply side pad 18a-bypass capacitor 50-ground side pad 18b-ground wires in the ground wire side pattern 18B-ground through hole 32-ground wires in the ground wire pattern 11B-ground pad 11b to the ground terminal 40b of the semiconductor integrated circuit device 40.

As described above, the printed wiring board according to the second embodiment achieves the same effects as the first and fifth effects described for the printed wiring board according to the first embodiment, and since the power supply through hole 31 and the ground through hole 32 are arranged close to each other, mutual induction due to high-frequency currents acts between the power supply through hole 31 and the ground through hole 32, resulting in the effect of mutual inductance, and the inductance in the current paths i2 and i3 for high frequencies can be reduced.
As a result, it is possible to suppress malfunctions caused by fluctuations in the power supply voltage due to adverse effects of high frequencies such as switching noise.

The pitch values and pad shapes and dimensions shown in the first and second embodiments are merely examples and are not intended to be limiting.

The embodiments may be freely combined, any of the components of each embodiment may be modified, or any of the components of each embodiment may be omitted.

It is particularly suitable for printed wiring boards in which insulating layers and conductor layers are alternately stacked in multiple layers, on which semiconductor integrated circuit devices with an array terminal structure, such as ball grid arrays, are mounted.

11-18 Conductor layers, 11a Power supply pad, 11b Ground pad, 18a Power supply side pad, 18b Ground side pad, 21-27 Insulation layers, 31 Power supply through hole, 31a Surface land, 31b Backside land, 31c Penetrating conductor layer, 32 Ground through hole, 32a Surface land, 32b Backside land, 32c Penetrating conductor layer, 40 Semiconductor integrated circuit device, 40a Power supply terminal, 40b Ground terminal, 50 Bypass capacitor, 50a One terminal, 50b The other terminal.

Claims (13)

Multiple insulating and conductor layers are stacked alternately,
a power supply pad to which a power supply terminal of a semiconductor integrated circuit device is connected and a ground pad to which a ground terminal of the semiconductor integrated circuit device is connected, the power supply pad being provided on a conductor layer on the surface of the semiconductor integrated circuit device;
a power supply side pad and a ground side pad are provided on a conductor layer on a rear surface thereof to which terminals of a bypass capacitor electrically connected between a power supply terminal and a ground terminal of the semiconductor integrated circuit device are connected;
A ground pattern is provided on the second or subsequent conductor layer from the front surface,
a power supply pattern is provided on a conductor layer located on the back side of the conductor layer having the ground pattern and on the front side of the conductor layer from the center of a thickness from the front conductor layer to the rear conductor layer ;
a power supply pad to which a power supply terminal of the semiconductor integrated circuit device is connected, and a power supply through hole electrically connected to the power supply pattern and a power supply side pad to which one terminal of the bypass capacitor is connected;
a ground pad to which a ground terminal of the semiconductor integrated circuit device is connected, and a ground through hole electrically connected to the ground pattern and a ground side pad to which the other end of the bypass capacitor is connected;
a printed wiring board, in which the power supply through hole and the ground through hole are disposed adjacent to each other in the conductor layer on the surface . Multiple insulating and conductor layers are stacked alternately,
a plurality of power supply pads to which a plurality of power supply terminals of a semiconductor integrated circuit device are respectively connected, and a plurality of ground pads to which a plurality of ground terminals of the semiconductor integrated circuit device are respectively connected, on a conductor layer on a surface of the semiconductor integrated circuit device;
a conductive layer on a back surface of the semiconductor integrated circuit device has a plurality of power supply side pads and ground side pads to which terminals of bypass capacitors, each of which is electrically connected between a power supply terminal and a ground terminal of the semiconductor integrated circuit device, are connected;
A ground pattern is provided on the second or subsequent conductor layer from the front surface,
a power supply pattern is provided on a conductor layer located on the back side of the conductor layer having the ground pattern and on the front side of the conductor layer from the center of a thickness from the front conductor layer to the rear conductor layer ;
a power supply pad to which a power supply terminal of the semiconductor integrated circuit device is connected, and a plurality of power supply through holes electrically connected to the power supply pattern and a power supply side pad to which one terminal of the bypass capacitor is connected;
a ground pad to which a ground terminal of the semiconductor integrated circuit device is connected, and a plurality of ground through holes electrically connected to the ground pattern and a ground side pad to which the other end of the bypass capacitor is connected;
A printed wiring board, in which the power supply through holes and the ground through holes are alternately arranged adjacent to each other in the conductor layer on the surface . the plurality of power supply pads and the plurality of ground pads are configured with pads arranged in a lattice pattern in a plurality of rows and a plurality of columns, the plurality of power supply pads and the plurality of ground pads are arranged in columns,
3. The printed wiring board according to claim 2, wherein the power supply through holes and the ground through holes are arranged alternately in the column direction between a plurality of power supply pads arranged in a column direction and a plurality of ground pads arranged in an adjacent column direction. The printed wiring board according to claim 3, wherein the power supply through holes and the ground through holes arranged alternately in the column direction are located between power supply pads arranged adjacently in the column direction. The printed wiring board according to claim 3 or claim 4, wherein the power through holes and the ground through holes arranged in the row direction are arranged alternately in the row direction. The printed wiring board according to claim 5, wherein the power supply through holes and the ground through holes arranged alternately in the row direction are located between the power supply pads and the ground pads arranged adjacent to each other in the row direction. The printed wiring board according to any one of claims 3 to 6, wherein the pitch between the pads in at least one of the row and column directions of the plurality of power supply pads and the plurality of ground pads is 0.65 mm. The printed wiring board according to any one of claims 3 to 6, wherein the pitch between the row-direction pads of the plurality of power supply pads and the plurality of ground pads is different from the pitch between the column-direction pads of the plurality of power supply pads and the plurality of ground pads. The printed wiring board according to any one of claims 1 to 8, wherein the bypass capacitors, one end of which is connected to the power supply through hole and the other end of which is connected to the ground through hole, are arranged at an angle with respect to the row direction. The printed wiring board according to claim 9, wherein the inclination angle of the bypass capacitors with respect to the row direction is 30°. the conductor layer having the ground pattern is the second conductor layer from the front surface,
11. The printed wiring board according to claim 1, wherein the conductor layer having the power supply pattern is a third conductor layer from the front surface. The printed wiring board according to claim 11, which has a ground pattern on the fourth conductor layer from the surface. the power supply through hole has a front surface land, connected to a power supply pad to which a power supply terminal of the semiconductor integrated circuit device is connected, on the front surface of a front insulating layer, and a back surface land, connected to a power supply pad to which one terminal of the bypass capacitor is connected, on the back surface of a back insulating layer, on an inner wall of a through hole extending from the front surface of the front insulating layer to the back surface of the back insulating layer, electrically connecting the front surface land and the back surface land , and has a through conductor layer electrically connected to the power supply pattern at a side wall;
The ground through hole has a surface land, on the surface of the front insulating layer, which is connected to a ground pad to which a ground terminal of the semiconductor integrated circuit device is connected, and a back land, on the back insulating layer, which is connected to a ground side pad to which the other terminal of the bypass capacitor is connected, and a through conductor layer, which is provided on an inner wall of a through hole reaching from the surface of the front insulating layer to the back surface of the back insulating layer, electrically connects the front surface land and the back surface land , and is electrically connected to the ground pattern at a side wall.
The printed wiring board according to claim 1 .

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