JP7622063B2 - Comparator and Analog-to-Digital Converter - Google Patents

Description

The present disclosure relates to a comparator and an analog-to-digital converter.

There is known a successive approximation type analog-to-digital converter (hereinafter, successive approximation type ADC) that includes a sampling switch, a comparator to which two differential input signal pairs are input, and a digital-to-analog converter (hereinafter, DAC) (see Non-Patent Document 1). This type of comparator holds a signal that corresponds to the difference signal between one differential input signal pair and the difference signal between the other differential input signal pair. The DAC is controlled by the signal held by the comparator, and two differential input signal pairs are generated based on the output signal of the DAC.

“An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS” (IEEE Journal of Solid-State Circuit, 2016)

The comparator includes a comparator that generates a difference signal between one differential input signal pair and a comparator that generates a difference signal between the other differential input signal pair, but gain mismatch occurs due to manufacturing variations in the transistors that make up each comparator. Gain mismatch also occurs when the common voltage of one differential input signal pair is not aligned with the common voltage of the other differential input signal pair. When gain mismatch occurs, the signal-to-noise ratio of the ADC decreases and stability deteriorates.
Therefore, the present disclosure provides a comparator and an analog-to-digital converter capable of detecting gain mismatch.

In order to solve the above problems, the present disclosure provides a first comparison circuit for comparing a first differential input signal pair;
a second comparison circuit for comparing a second pair of differential input signals;
There is provided a comparator comprising: a switching circuit that switches between comparing the first differential input signal pair in the first comparison circuit and comparing the second differential input signal pair in the second comparison circuit, or comparing a gain difference between the first comparison circuit and the second comparison circuit.

A correction circuit may be provided to correct the gain of the first comparison circuit and the gain of the second comparison circuit.

The correction circuit may correct the gain of the first comparison circuit and the gain of the second comparison circuit so that the gain difference becomes smaller.

a comparison output node pair for transmitting the differential signal switched by the switching circuit,
The correction circuit may adjust a discharge rate of a discharge path from one node of the comparison output node pair through the switching circuit and the first comparison circuit to a reference potential node, and a discharge rate of a discharge path from the other node of the comparison output node pair through the switching circuit and the second comparison circuit to the reference potential node, so that the gain difference is smaller.

a first variable capacitance connected between the first comparison circuit and the reference potential node;
a second variable capacitance connected between the second comparison circuit and the reference potential node;
The correction circuit may adjust the discharge rate by adjusting a capacitance value of at least one of the first variable capacitance and the second variable capacitance.

The first comparison circuit is
a first transistor pair for generating a difference signal of the first differential input signal pair;
a first switching circuit that switches whether or not the first transistor pair and the reference potential node are connected,
The second comparison circuit is
a second transistor pair for generating a difference signal of the second differential input signal pair;
a second switching circuit that switches whether or not the second transistor pair and the reference potential node are connected,
The correction circuit may adjust the discharge rate by adjusting a timing for switching at least one of the first switching circuit and the second switching circuit.

the first comparison circuit has a first current source capable of adjusting a current flowing into the reference potential node in response to a difference signal of the first differential input signal pair;
the second comparison circuit has a second current source capable of adjusting a current flowing to the reference potential node in response to a difference signal of the second differential input signal pair;
The correction circuit may adjust the discharge rate by adjusting a current flowing from at least one of the first current source and the second current source to the reference potential node.

the first comparison circuit includes a first transistor pair that generates a first differential output signal pair in response to a difference signal of the first differential input signal pair;
the second comparison circuit has a second transistor pair that generates a second differential output signal pair according to a difference signal of the second differential input signal pair;
The correction circuit may adjust the discharge rate by adjusting a gate width of at least one of the first transistor pair and the second transistor pair.

the first comparison circuit includes a first transistor pair that generates a first differential output signal pair in response to a difference signal of the first differential input signal pair;
the second comparison circuit has a second transistor pair that generates a second differential output signal pair according to a difference signal of the second differential input signal pair;
The gain difference may be the difference between the product of a transconductance of the first transistor pair and a common voltage of the first differential input signal pair and the product of a transconductance of the second transistor pair and a common voltage of the second differential input signal pair.

a comparison output node pair for transmitting the differential signal switched by the switching circuit;
and a latch circuit for holding the differential signal of the comparison output node pair.

a first waveform shaping circuit and a second waveform shaping circuit, which are respectively arranged on the comparison output node pair and perform waveform shaping of the differential signal;
The latch circuit may hold the differential signals whose waveforms have been shaped by the first waveform shaping circuit and the second waveform shaping circuit.

Each of the first waveform shaping circuit and the second waveform shaping circuit may be an inverter.

The latch circuit includes:
a first latch section that holds the differential signals on the comparison output node pair when the first comparison circuit compares the first differential input signal pair and the second comparison circuit compares the second differential input signal pair;
The input/output amplifier may further include a second latch section that holds the differential signal on the comparison output node pair when comparing a gain difference between the first comparison circuit and the second comparison circuit.

The latch circuit may be connected between a power supply voltage node having a higher voltage level than the comparison output node pair and the comparison output node pair.

The switching circuit may alternate between a first operating mode in which the first comparison circuit compares the first differential input signal pair and the second comparison circuit compares the second differential input signal pair, and a second operating mode in which the gain difference between the first comparison circuit and the second comparison circuit is compared.

The switching circuit may perform the first operating mode at the start of operation, and then repeat the switching operation between the second operating mode and the first operating mode in that order.

The switching circuit may perform the second operating mode at the start of operation, and then repeat the switching operation between the first operating mode and the second operating mode in that order.

the first comparison circuit includes a first transistor pair that generates a first differential output signal pair in response to a difference signal of the first differential input signal pair;
the second comparison circuit has a second transistor pair that generates a second differential output signal pair according to a difference signal of the second differential input signal pair;
The switching circuit may short-circuit the gates of the first transistor pair and short-circuit the gates of the second transistor pair when comparing a gain difference between the first comparison circuit and the second comparison circuit.

a comparison output node pair for transmitting the differential signal switched by the switching circuit,
the first comparison circuit has a first output node and a second output node;
the second comparison circuit has a third output node and a fourth output node;
When the first comparison circuit compares the first differential input signal pair and the second comparison circuit compares the second differential input signal pair, the switching circuit may connect the first output node and the third output node to one node of the comparison output node pair and connect the second output node and the fourth output node to the other node of the comparison output node pair, and when comparing a gain difference between the first comparison circuit and the second comparison circuit, the switching circuit may connect the first output node and the second output node to one node of the comparison output node pair and connect the third output node and the fourth output node to the other node of the comparison output node pair.

According to one aspect of the present disclosure, a first sampling switch that switches whether or not one of a pair of differential input signals is sampled;
a first digital-to-analog converter that converts the sampled one of the signals into a digital signal consisting of a plurality of bits one bit at a time, and outputs a signal having a voltage level corresponding to the unconverted bits;
a second sampling switch that switches whether or not the other signal of the differential input signal pair is sampled;
a second digital-to-analog converter that converts the sampled other signal into a digital signal consisting of a plurality of bits one bit at a time and outputs a signal having a voltage level corresponding to the unconverted bits;
a filter circuit that samples and outputs an output signal of the first digital-to-analog converter and an output signal of the second digital-to-analog converter;
a comparator that outputs a signal according to a difference signal of a first differential input signal pair, which is a pair of an output signal of the first digital-analog converter and an output signal of the second digital-analog converter, and a difference signal of a second differential input signal pair output from the filter circuit;
a control circuit for controlling the first digital-to-analog converter and the second digital-to-analog converter based on an output signal of the comparator,
a first comparison circuit for comparing the first pair of differential input signals;
a second comparison circuit for comparing the second pair of differential input signals;
An analog-to-digital converter is provided having a switching circuit that switches between comparing the first differential input signal pair in the first comparison circuit and comparing the second differential input signal pair in the second comparison circuit, or comparing a gain difference between the first comparison circuit and the second comparison circuit.

Sampling of the differential input signal pair by the first sampling switch and the second sampling switch, conversion to the digital signal by the first digital-to-analog converter and the second digital-to-analog converter, comparison of the gain difference, and correction of the gain difference may be repeated in sequence.

1 is a circuit diagram of a comparator according to a first embodiment. FIG. 11 is a circuit diagram of a comparator according to a comparative example. 4 is a waveform diagram of a comparison output signal pair during a comparison operation of the comparator. 4 is a waveform diagram of a comparison output signal pair during a comparison operation of the comparator. 6 is a diagram comparing the gain of a first comparison circuit and the gain of a second comparison circuit; FIG. 1 is a circuit diagram of a successive approximation type ADC equipped with a comparator. 6 is a voltage waveform diagram of the output node voltage of the first DAC and the output node voltage of the second DAC in FIG. 5 . FIG. 7 is a timing diagram showing the operation timing of the ADC in FIG. 6 . 6 is a flowchart showing a processing procedure of the ADC in FIG. 5 . 6 is a flowchart showing a modified example of the processing procedure of the ADC in FIG. 5 . FIG. 11 is a circuit diagram of a comparator according to a second embodiment. FIG. 11 is a circuit diagram of a comparator according to a third embodiment. FIG. 13 is a circuit diagram of a comparator according to a fourth embodiment. FIG. 13 is a circuit diagram of a comparator according to a fifth embodiment. FIG. 13 is a circuit diagram of a comparator according to a sixth embodiment. FIG. 13 is a circuit diagram of a comparator according to a seventh embodiment. FIG. 13 is a circuit diagram of a comparator according to an eighth embodiment. FIG. 13 is a circuit diagram of a comparator according to a ninth embodiment.

Below, an embodiment of a comparator and an analog-to-digital converter will be described with reference to the drawings. The following description will focus on the main components of the comparator and the analog-to-digital converter, but the comparator and the analog-to-digital converter may have components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

(First embodiment)
FIG. 1 is a circuit diagram of a comparator 1 according to a first embodiment. FIG. 2 is a circuit diagram of a comparator 101 according to a comparative example. The comparators 1 and 101 in FIG. 1 and FIG. 2 are used in, for example, a successive approximation type ADC, as described later, but the use of the comparators 1 and 101 in FIG. 1 and FIG. 2 is not necessarily limited to ADCs. Two differential input signal pairs (hereinafter, referred to as a first differential input signal pair Vin_p, Vin_n and a second differential input signal pair Vns_p, Vns_n) are input to the comparators 1 and 101 in FIG. 1 and FIG. 2. The comparators 1 and 101 output a differential output signal pair Vout_p, Vout_n according to a difference signal between the first differential input signal pair Vin_p, Vin_n and a difference signal between the second differential input signal pair Vns_p, Vns_n. In this manner, the comparators 1 and 101 in FIGS. 1 and 2 are dynamic comparators that perform a comparison operation between two differential input signal pairs (Vin_p, Vin_n) and (Vns_p, Vns_n).

Before explaining the configuration and operation of the comparator 1 in Fig. 1, the configuration and operation of the comparator 101 in Fig. 2 will be explained. The comparator 101 in Fig. 2 includes a first comparison circuit 2 and a second comparison circuit 3.

The first comparison circuit 2 outputs a first differential output signal pair according to the difference signal of the first differential input signal pair Vin_p, Vin_n. The first comparison circuit 2 has a first transistor pair Q11, Q12, whose gates receive the first differential input signal pair Vin_p, Vin_n, and a transistor Q13 that functions as a switch. A clock signal Clk is input to the gate of the transistor Q13, and when the clock signal Clk is at a high potential, the transistor Q13 turns on and the first comparison circuit 2 performs a comparison operation.

The second comparison circuit 3 outputs a second differential output signal pair according to the difference signal of the second differential input signal pair Vns_p, Vns_n. The second comparison circuit 3 has a second transistor pair Q21, Q22, whose gates receive the second differential input signal pair Vns_p, Vns_n, and a transistor Q23 that functions as a switch. When the clock signal Clk input to the gate of the transistor Q23 is at a high potential, the second comparison circuit 3 performs a comparison operation.

The drains of the first transistor pair Q11, Q12 are connected to the comparison output node pair n1, n2. Similarly, the drains of the second transistor pair Q21, Q22 are connected to the same comparison output node pair n1, n2. In this specification, the voltage signals on the comparison output node pair n1, n2 are called the comparison output signal pair Vgm_p, Vgm_n. A pull-up circuit 4 and a latch circuit 5 are connected to the comparison output node pair n1, n2.

The pull-up circuit 4 has a transistor pair Q1, Q2, and pulls up the comparison output node pair n1, n2 to a high potential when the clock signal Clk is at a low level. In this way, the pull-up circuit 4 pulls up the comparison output node pair n1, n2 to a high potential when the first comparison circuit 2 and the second comparison circuit 3 are not performing a comparison operation.

Latch circuit 5 has transistors Q31 to Q40. Latch circuit 5 determines the logic of the latch output according to the difference in discharge speed between comparison output node pair n1, n2. More specifically, of the comparison output node pair n1, n2, the node with the faster discharge speed becomes high potential, and the node with the slower discharge speed becomes low potential.

Next, the operation of the comparator 101 in FIG. 2 will be described. When the clock signal Clk transitions from low level to high level, the comparator 101 in FIG. 2 starts a comparison operation. While the clock signal Clk is at low level, the comparison output node pair n1, n2 is pulled up to a high potential. When the clock signal Clk transitions to a high level, the potentials Vgm_p, Vgm_n on the comparison output node pair n1, n2 decrease due to discharging as one of the first transistor pair Q11, Q12 and one of the second transistor pair Q21, Q22 turn on.

If the transconductance of each transistor of the first transistor pair Q11, Q12 is gm_in and the transconductance of each transistor of the second transistor pair Q21, Q22 is gm_ns, then when (Vin_p x gm_in + Vns_p x gm_ns) > (Vin_n x gm_in + Vns_n x gm_ns), the discharge speed of Vgm_p is greater than the discharge speed of Vgm_n. Conversely, when (Vin_p x gm_in + Vns_p x gm_ns) < (Vin_n x gm_in + Vns_n x gm_ns), the discharge speed of Vgm_p is less than the discharge speed of Vgm_n.

Thus, the discharge speed of the comparison output signal pair Vgm_p, Vgm_n depends on the potentials of the first differential input signal pair Vin_p, Vin_n and the second differential input signal pair Vns_p, Vns_n, and the transconductance of the first transistor pair Q11, Q12 and the second transistor pair Q21, Q22.

3A and 3B are waveform diagrams of the comparison output signal pair Vgm_p and Vgm_n during the comparison operation of the comparator 101. Fig. 3A is a waveform diagram when (Vin_p×gm_in + Vns_p×gm_ns)>(Vin_n×gm_in + Vns_n×gm_ns), and Fig. 3B is a waveform diagram when (Vin_p×gm_in + Vns_p×gm_ns)<(Vin_n×gm_in + Vns_n×gm_ns).

Comparison output signal pair Vgm_p, Vgm_n The difference between the discharge rates of Vgm_p and Vgm_n determines the logic of the latch output of the latch circuit 5 downstream of the comparator 101. If the discharge rate of Vgm_p is greater than the discharge rate of Vgm_n, then Vout_p = High / Vout_n = Low. If the discharge rate of Vgm_p is less than the discharge rate of Vgm_n, then Vout_p = Low / Vout_n = High.

1 and 2 can be used inside a successive approximation ADC, as described later. In a successive approximation ADC, a differential analog input signal to be A/D converted is sampled, and the voltages converted into digital form starting from the most significant bit are used as a first differential input signal pair Vin_p, Vin_n, and the differential signal obtained by filtering the voltage remaining in a capacitive DAC, described later, is used as a second differential input signal pair Vns_p, Vns_n, and a comparison operation is performed by the comparators 1, 101.

However, in the comparator 101 of Figure 2, a gain mismatch can occur, in which the gain of the first comparison circuit 2 that compares the first differential input signal pair Vin_p, Vin_n differs from the gain of the second comparison circuit 3 that compares the second differential input signal pair Vns_p, Vns_n.

Figure 4 is a diagram comparing the gain of the first comparison circuit 2 and the gain of the second comparison circuit 3 in the comparator 101 of Figure 2. The horizontal axis of Figure 4 is the potential difference between the second differential input signal pair Vns_p, Vns_n, and the vertical axis is the potential difference between the first differential input signal pair Vin_p, Vin_n. The dashed line w1 in Figure 4 indicates the case where the absolute value of the potential difference between the first differential input signal pair Vin_p, Vin_n is equal to the absolute value of the potential difference between the second differential input signal pair Vns_p, Vns_n.

4 is a case where the absolute value of the potential difference between the first differential input signal pair Vin_p, Vin_n is greater than the absolute value of the potential difference between the second differential input signal pair Vns_p, Vns_n, in which case the output potential Vout_p of the latch circuit 5 is a high potential and Vout_n is a low potential. On the other hand, the area below the dashed line w1 in FIG. 4 is a case where the absolute value of the potential difference between the first differential input signal pair Vin_p, Vin_n is smaller than the absolute value of the potential difference between the second differential input signal pair Vns_p, Vns_n, in which case the output potential Vout_p of the latch circuit 5 is a low potential and Vout_n is a high potential.

In Figure 4, if the product gm_in × Vin_cm of the transconductance gm_in of the first transistor pair Q11, Q12 in the first comparison circuit 2 and the common voltage Vin_cm of the first differential input signal pair Vin_p, Vin_n is equal to the product gm_ns × Vns_cm of the transconductance gm_ns of the second transistor pair Q21, Q22 in the second comparison circuit 3 and the common voltage Vns_cm of the second differential input signal pair Vns_p, Vns_n, then the characteristics shown by the dashed line w1 in Figure 4 will be obtained, but in reality gm_in × Vin_cm is not the same as gm_ns × Vns_cm, and the characteristics will be, for example, like the solid line w2 in Figure 4.

In the case of solid line w2 in Figure 4, when the potential difference between the second differential input signal pair Vns_p, Vns_n is Vns_p-Vns_n=1mV, if Vin_p-Vin_n>-1.1mV, the output voltage Vout_p of the comparator 101 will be at high potential and Vout_n will be at low potential. If Vin_p-Vin_n<1.1mV, Vout_p will be at low potential and Vout_n will be at high potential.

The characteristics shown by the solid line w2 in Figure 4 arise because there is a gain difference, or gain mismatch, between the first comparison circuit 2 and the second comparison circuit 3 in the comparator 101. More precisely, the gain difference refers to the difference between gm_in x Vin_cm and gm_ns x Vns_cm. The comparator 101 having characteristics shown by the solid line w2 in Figure 4 is a non-ideal comparator. A comparator with a gain difference may have reduced performance, such as S/N, and may become less stable. For this reason, a comparator that minimizes gain mismatch is desirable.

The main reason for the gain difference is that, as mentioned above, gm_in×Vin_cm and gm_ns×Vns_cm do not match. There are several possible reasons why gm_in×Vin_cm and gm_ns×Vns_cm do not match. One of these reasons is the variation in the manufacturing process when forming the comparator 101 on a semiconductor substrate. The variation in the manufacturing process causes a discrepancy between the transconductance gm_in of the first transistor pair Q11, Q12 and the transconductance gm_ns of the second transistor pair Q21, Q22.

Another factor is the misalignment of the common voltage Vin_cm of the first differential input signal pair Vin_p, Vin_n and the common voltage Vns_cm of the second differential input signal pair Vns_p, Vns_n. The common voltage Vin_cm of the first differential input signal pair Vin_p, Vin_n depends on the common voltage of the differential input signal pair input to the ADC, and the common voltage Vns_cm of the second differential input signal pair Vns_p, Vns_n depends on the characteristics of the filter circuit in the ADC, so there is no guarantee that the two common voltages will match.

The transconductance gm_in and gm_ns of the first transistor pair Q11, Q12 in the first comparison circuit 2 and the second transistor pair Q21, Q22 in the second comparison circuit 3 are expressed by the formula μCox × (W/L) × (Vgs - Vth). μ is the mobility, Cox is the gate oxide thickness, W is the gate width, L is the gate length, Vgs is the gate-source voltage, and Vth is the threshold voltage. Of these, the mobility μ, oxide thickness Cox, gate width W, gate length L, and threshold voltage Vth are parameters that change due to manufacturing variations. The gate-source voltage Vgs is a parameter that depends on the common voltage of the first differential input signal pair Vin_p, Vin_n and the second differential input signal pair Vns_p, Vns_n.

In this way, manufacturing variations and fluctuations in common voltage can cause a gain difference, i.e., a gain mismatch, in comparator 101, which can lead to a decrease in the S/N ratio and deterioration of stability of comparator 1.

The comparator 1 in Fig. 1 is characterized by the implementation of measures against manufacturing variations and fluctuations in the common voltage. The configuration and operation of the comparator 1 in Fig. 1 will be explained below. The comparator 1 in Fig. 1 includes a first comparison circuit 2, a second comparison circuit 3, and a switching circuit 6.

The first comparison circuit 2 compares the first differential input signal pair Vin_p, Vin_n. The first comparison circuit 2 has a first transistor pair Q11, Q12 that generates a first differential output signal pair according to the difference signal of the first differential input signal pair Vin_p, Vin_n. The second comparison circuit 3 compares the second differential input signal pair Vns_p, Vns_n. The second comparison circuit 3 has a second transistor pair Q21, Q22 that generates a second differential output signal pair according to the difference signal of the second differential input signal pair Vns_p, Vns_n.

The switching circuit 6 switches between comparing the first differential input signal pair Vin_p, Vin_n in the first comparison circuit 2 and comparing the second differential input signal pair Vns_p, Vns_n in the second comparison circuit 3, or comparing the gain difference between the first comparison circuit 2 and the second comparison circuit 3.

The comparator 1 according to this embodiment includes a correction circuit 7. The correction circuit 7 corrects the gain of the first comparison circuit 2 and the gain of the second comparison circuit 3. The correction circuit 7 corrects the gain of the first comparison circuit 2 and the gain of the second comparison circuit 3 so that the gain difference becomes smaller. The correction circuit 7 can be built into a control circuit in the ADC, as described later.

The comparator 1 according to this embodiment includes a comparison output node pair n1, n2 that transmits a differential signal switched by the switching circuit 6. The correction circuit 7 adjusts the discharge speed when the voltage of one node n1 of the comparison output node pair n1, n2 is discharged to the reference potential node through the switching circuit 6 and the first comparison circuit 2, and the discharge speed when the voltage of the other node n2 of the comparison output node pair n1, n2 is discharged to the reference potential node through the switching circuit 6 and the second comparison circuit 3, so that the gain difference is smaller.

1 has a first transistor pair Q11, Q12 that generates a differential output signal pair according to the difference signal of the first differential input signal pair Vin_p, Vin_n. The first transistor pair Q11, Q12 is, for example, a pair of NMOS transistors. In this specification, it is assumed that the transconductances gm_in of the pair of NMOS transistors that constitute the first transistor pair Q11, Q12 are equal to each other.

An NMOS transistor that functions as a switch is connected between the sources of the first transistor pair Q11 and Q12 and a reference potential node (e.g., a ground node). The clock signal Clk is input to the gate of this transistor.

1 has a second transistor pair Q21, Q22 that generates a differential output signal pair according to the difference signal of the second differential input signal pair Vns_p, Vns_n. The second transistor pair Q21, Q22 is, for example, a pair of NMOS transistors. In this specification, it is assumed that the transconductances gm_ns of the pair of NMOS transistors constituting the second transistor pair Q21, Q22 are equal to each other.

An NMOS transistor that functions as a switch is connected between the sources of the second transistor pair Q21, Q22 and a reference potential node (e.g., a ground node). The clock signal Clk is input to the gate of this transistor.

While the clock signal Clk is at a low potential, the first comparison circuit 2 and the second comparison circuit 3 do not perform a comparison operation, and when the clock signal Clk transitions from a low potential to a high potential, the first comparison circuit 2 and the second comparison circuit 3 start their comparison operation.

1, the output node pair of the first comparison circuit 2 and the output node pair of the second comparison circuit 3 are connected to a comparison output node pair n1, n2 via a switching circuit 6. A first differential output signal pair is output from the output node pair of the first comparison circuit 2, and a second differential output signal pair is output from the output node pair of the second comparison circuit 3.

The switching circuit 6 in FIG. 1 switches between a first operating mode (hereinafter also referred to as a normal comparison mode) in which the first comparison circuit 2 compares the first differential input signal pair Vin_p, Vin_n and the second comparison circuit 3 compares the second differential input signal pair Vns_p, Vns_n, and a second operating mode (hereinafter also referred to as a gain comparison mode) in which the gain difference between the first comparison circuit 2 and the second comparison circuit 3 is compared.

The switching circuit 6 has first to fourth switch pairs 6a, 6b, 6c, and 6d. The two switches SW1 and SW2 constituting the first switch pair 6a and the two switches SW3 and SW4 constituting the second switch pair 6b are turned on in the normal comparison mode. One end of the switch SW1 is connected to the drain of the transistor Q11, and the other end is connected to the comparison output node n1. One end of the switch SW2 is connected to the drain of the transistor Q12, and the other end is connected to the comparison output node n2. One end of the switch SW3 is connected to the drain of the transistor Q21, and the other end is connected to the comparison output node n1. One end of the switch SW4 is connected to the drain of the transistor Q22, and the other end is connected to the comparison output node n2.

The two switches SW5 and SW6 constituting the third switch pair 6c and the two switches SW7 and SW8 constituting the fourth switch pair 6d are turned on in the gain comparison mode. One end of the switch SW5 is connected to the drain of the transistor Q11, and the other end is connected to the comparison output node n1. One end of the switch SW6 is connected to the drain of the transistor Q12, and the other end is connected to the comparison output node n1. One end of the switch SW7 is connected to the drain of the transistor Q21, and the other end is connected to the comparison output node n2. One end of the switch SW8 is connected to the drain of the transistor Q22, and the other end is connected to the comparison output node n2.

In the normal comparison mode, the first differential output signal pair output from the first comparison circuit 2 is supplied to the comparison output node pair n1, n2 via the switching circuit 6, and the second differential output signal pair output from the second comparison circuit 3 is supplied to the comparison output node pair n1, n2 via the switching circuit 6.

On the other hand, in the gain comparison mode, the first differential output signal pair output from the first comparison circuit 2 is supplied to the comparison output node n1 via the switching circuit 6, and the second differential output signal pair output from the second comparison circuit 3 is supplied to the comparison output node n2 via the switching circuit 6.

1 includes a first variable capacitance C1 connected between the sources of the first transistor pair Q11, Q12 in the first comparison circuit 2 and a reference potential node (e.g., a ground node), and a second variable capacitance C2 connected between the sources of the second transistor pair Q21, Q22 in the second comparison circuit 3 and a reference potential node (e.g., a ground node). The capacitance values of the first variable capacitance C1 and the second variable capacitance C2 can be adjusted by a correction circuit 7. The correction circuit 7 adjusts the capacitance values of the first variable capacitance C1 and the second variable capacitance C2 so that the gain difference between the first comparison circuit 2 and the second comparison circuit 3 becomes smaller. Here, the gain difference is the difference between the product gm_in × Vin_cm of the transconductance gm_in of the first transistor pair Q11, Q12 and the common voltage Vin_cm of the first differential input signal pair Vin_p, Vin_n, and the product gm_ns × Vns_cm of the transconductance gm_ns of the second transistor pair Q21, Q22 and the common voltage Vns_cm of the second differential input signal pair Vns_p, Vns_n.

The correction circuit 7 can individually control the capacitance value of the first variable capacitance C1 and the capacitance value of the second variable capacitance C2. The correction circuit 7 can be provided inside a control circuit in the ADC described later. As described above, the first comparison circuit 2 and the second comparison circuit 3 start a comparison operation when the clock signal Clk transitions from a low potential to a high potential, but by variably controlling the capacitance values of the first variable capacitance C1 and the second variable capacitance C2, the timing at which the first comparison circuit 2 and the second comparison circuit 3 start a comparison operation can be adjusted. That is, the correction circuit 7 individually controls the capacitance values of the first variable capacitance C1 and the second variable capacitance C2, so that the discharge speed of one node of the comparison output node pair n1, n2 and the discharge speed of the other node can be individually adjusted. The smaller the capacitance value of the first variable capacitance C1, the faster the discharge speed of the comparison output node n1 can be. Similarly, the smaller the capacitance value of the second variable capacitance C2, the faster the discharge speed of the comparison output node n2 can be.

The magnitude relationship of the latch output logic of the latch circuit 5 is determined by the difference in discharge rate between one node and the other node of the comparison output node pair n1, n2. When there is the gain difference between the first comparison circuit 2 and the second comparison circuit 3, the compensation circuit 7 individually controls the capacitance values of the first variable capacitance C1 and the second variable capacitance C2, so that the gain difference is smaller. The discharge rate of one node and the discharge rate of the other node of the comparison output node pair n1, n2 can be set so that the gain difference is smaller.

For example, when gm_ns×Vns_cm<gm_in×Vin_cm, the capacitance value of the second variable capacitance C2 connected to the second comparison circuit 3 is gradually decreased to gradually increase the discharge rate of the comparison output node n2. When the discharge rates of the comparison output node pair n1, n2 become approximately equal, the correction process by the correction circuit 7 in the gain comparison mode is terminated. In this state, the gain difference is eliminated, and by subsequently performing the normal comparison mode, the comparison process of the first differential input signal pair Vin_p, Vin_n and the second differential input signal pair Vns_p, Vns_n can be performed without being affected by the gain difference.

In the comparator 1 of Figure 1, the capacitance value of the first variable capacitance C1 and the capacitance value of the second variable capacitance C2 can be controlled by the correction circuit 7 to have characteristics such as the dashed line w1 in Figure 4.

Figure 5 is a circuit diagram of a successive approximation ADC 11 equipped with a comparator 1 according to this embodiment. The successive approximation ADC 11 in Figure 5 shows an example in which a differential input signal pair Vad_p, Vad_n is converted into a 5-bit digital signal. Note that the number of bits of the successive approximation ADC 11 is arbitrary. Also, the circuit configuration of the successive approximation ADC 11 is not limited to that shown in Figure 5.

5 includes a first sampling switch 12, a second sampling switch 13, a first digital-to-analog converter (hereinafter, first DAC) 14, a second digital-to-analog converter (second DAC) 15, a filter circuit 16, a comparator 1, and a control circuit (SAR logic) 17. In this specification, the first DAC 14 and the second DAC 15 are collectively referred to as a capacitive DAC 18.

The first sampling switch 12 switches whether or not to sample one signal Vad_p of the differential input signal pair Vad_p, Vad_n. The second sampling switch 13 switches whether or not to sample the other signal Vad_n of the differential input signal pair Vad_p, Vad_n.

The first DAC 14 converts one of the sampled signals Vad_p into a digital signal consisting of multiple bits, one bit at a time, and outputs a signal with a voltage level corresponding to the unconverted bits.

The first DAC 14 has five capacitors C1 to C5 whose capacitances differ by a power of two, and three switches (first to third switches) SW11 to SW13 connected to the capacitors C1 to C5. The first switch SW11 switches whether or not one end of the capacitors C1 to C5 is set to 0V. The second switch SW12 switches whether or not one end of the capacitors C1 to C5 is set to a common voltage Vcom. The third switch SW13 switches whether or not one end of the capacitors C1 to C5 is set to a reference voltage Vref. The common voltage Vcom is, for example, a voltage level that is 1/2 the reference voltage Vref.

The first to third switches SW11 to SW13 are switched on or off based on a control signal from the control circuit 17. The control circuit 17 turns on the second switch SW12 at the start of the comparison operation. Thereafter, the control circuit 17 turns on the first switch SW11 when it is desired to lower the output node voltage (one of the first differential input signal pair Vin_p, Vin_n) Vin_p of the first DAC 14, and turns on the third switch SW13 when it is desired to raise the output node voltage (one of the first differential input signal pair Vin_p, Vin_n) Vin_p of the first DAC 14.

The second DAC 15 converts the other sampled signal into a digital signal consisting of multiple bits one bit at a time, and outputs a signal with a voltage level corresponding to the unconverted bits. The second DAC 15 is configured similarly to the first DAC 14, and switches the first to third switches SW11 to SW13 based on a control signal from the control circuit 17, similar to the first DAC 14.

The filter circuit 16 samples and outputs the output signal of the first DAC 14 and the output signal of the second DAC 15. The differential output signal pair output from the filter circuit 16 is the second differential input signal pair Vns_p, Vns_n.

The comparator 1 has the configuration shown in Fig. 1. The comparator 1 receives a first differential input signal pair Vin_p, Vin_n, which is a pair of the output signal of the first DAC 14 and the output signal of the second DAC 15, and a second differential input signal pair Vns_p, Vns_n output from the filter circuit 16. The comparator 1 outputs a differential output signal pair Vout_p, Vout_n corresponding to the difference signal of the first differential input signal pair Vin_p, Vin_n and the difference signal of the second differential input signal pair Vns_p, Vns_n.

The control circuit 17 controls the switching of the first to third switches SW11 to SW13 in the first DAC 14 and the second DAC 15 based on the differential output signal pair of the comparator 1. The control circuit 17 can incorporate the correction circuit 7 shown in FIG. 1 and the like. An example in which the control circuit 17 incorporates the correction circuit 7 will be described below. The control circuit 17 generates the signals Sw_comp, Sw_gain, Comp_end, Gain_cal_in, and Gain_cal_ns based on the differential output signal pair of the comparator 1. The signal Sw_comp is a signal that becomes a high potential in the normal comparison mode. The signal Sw_gain is a signal that becomes a high potential in the gain comparison mode. The signal Comp_end is a signal that becomes a high potential when the gain difference disappears in the gain comparison mode. The signal Gain_cal_in is a signal that adjusts the capacitance value of the first variable capacitance C1 after adjustment in the gain comparison mode. The signal Gain_gain_ns is a signal that adjusts the capacitance value of the second variable capacitor C2 after adjustment in the gain comparison mode.

The timing of the clock signal Clk input to the comparator 1 is set by the switching signal Clk_smpl of the first sampling switch 12 and the second sampling switch 13, the differential output signal pair of the comparator 1, and the signal Comp_end. To set the timing of the clock signal Clk, the ADC 11 in FIG. 5 includes inverters 31 and 32, a NOR gate 33, and AND gates 34 and 35. These logic gates can be replaced with other logic circuit elements.

Figure 6 is a voltage waveform diagram of the output node voltage Vin_p (one of the first differential input signal pair Vin_p, Vin_n) of the first DAC 14 in Figure 5 and the output node voltage Vin_n (the other of the first differential input signal pair Vin_p, Vin_n) of the second DAC 15. First, the first sampling switch 12 and the second sampling switch 13 are both turned on to sample the differential input signal pair Vad_p, Vad_n. At this time, one end of each of the capacitors C1 to C5 is set to the common voltage Vcom of the first differential input signal pair Vin_p, Vin_n via the second switch SW12. As a result, a charge corresponding to the difference signal of the differential input signal pair Vad_p, Vad_n is accumulated in the capacitive DAC 18. The output signal of the first DAC 14 and the output signal of the second DAC 15 that constitute the capacitive DAC 18 are the first differential input signal pair Vin_p, Vin_n input to the comparator 1. Moreover, the differential output signals of the filter circuit 16 are a second differential input signal pair Vns_p, Vns_n input to the comparator 1 .

Then, the first sampling switch 12 and the second sampling switch 13 are both turned off, and the comparison operation by the comparator 1 is started. The output of the capacitive DAC 18 is controlled in accordance with the difference signal of the sampled differential input signal pair Vad_p, Vad_n so that the potential difference of the first differential input signal decreases from the above bits in order as shown in FIG. 6, and the potential difference of the first differential input signal gradually approaches zero.

When the control is completed, the voltage remaining in the capacitive DAC 18 is sampled by the filter circuit 16, causing the output voltage (second differential input signal) of the filter circuit 16 to change. Normally, the residual voltage when the control of the capacitive DAC 18 is completed is at a very small voltage level, and the filter circuit 16 continues to output a signal at a small voltage level. In other words, the difference signal (Vns_p-Vns_n) of the second differential input signal pair Vns_p, Vns_n is maintained at ≒0.

Figure 7 is a timing diagram showing the operation timing of the ADC 11 in Figure 6. From time t1 to t2, the signal Clk_smpl goes high, and the first sampling switch 12 and the second sampling switch 13 are turned on. As a result, the first DAC 14 and the second DAC 15 sample the differential input signals Vad_p and Vad_n. At time t2, the first sampling switch 12 and the second sampling switch 13 are turned off, and the sampling of the differential input signals Vad_p and Vad_n ends. Also, at time t2, the signal Sw_comp transitions to a high potential, and the switching circuit 6 in the comparator 1 connects the first differential output signal pair output from the first comparison circuit 2 to the comparison output node pair n1, n2, and connects the second differential output signal pair output from the second comparison circuit 3 to the comparison output node pair n1, n2.

When the clock signal Clk transitions from low potential to high potential at time t3, the comparator 1 in FIG. 5 starts a comparison operation. The first comparison circuit 2 and the second comparison circuit 3 in the comparator 1 perform a comparison operation only while the clock signal Clk is at high potential. After time t3, each time the clock signal Clk transitions from low potential to high potential, the first DAC 14 and the second DAC 15 convert the sampled differential input voltage into a digital value bit by bit, starting from the most significant bit. More specifically, the first comparison circuit 2 determines whether the difference signal Vin_p-Vin_n between the output voltages of the first DAC 14 and the second DAC 15 (first differential input signal pair Vin_p, Vin_n) is positive or negative, and outputs a differential output signal pair indicating the determination result. The control circuit 17 controls the value of each bit of the first DAC 14 and the second DAC 15, starting from the most significant bit, so that the difference signal Vin_p-Vin_n of the output voltages of the first DAC 14 and the second DAC 15 (second differential input signal pair Vns_p, Vns_n) approaches zero. As a result, as shown in FIG. 6, the difference signal of the first differential input signal pair Vin_p, Vin_n gradually approaches zero.

At time t4, when the D/A conversion process by the first DAC 14 and the second DAC 15 is completed, the signal Sw_comp transitions to a low potential and the signal Sw_gain goes to a high potential for a predetermined period. When the signal Sw_gain goes to a high potential, the gain comparison mode is entered and the switching circuit 6 connects the first differential output signal pair output from the first comparison circuit 2 to one of the comparison output node pair n1, n2 and connects the second differential output signal pair output from the second comparison circuit 3 to the other of the comparison output node pair n1, n2.

At time t5, the signal Comp_end becomes high potential, and from then on, the clock signal Clk is no longer supplied to the first comparison circuit 2 and the second comparison circuit 3.

At time t6, based on the comparison result in the gain comparison mode, the correction circuit 7 controls the capacitance value of the first variable capacitance C1 and the capacitance value of the second variable capacitance C2 so that the difference between gm_in×Vin_cm and gm_ns×Vns_cm becomes small. The gain adjustment signal Gain_cal_in is a signal that specifies the capacitance value of the first variable capacitance C1, and the gain adjustment signal Gain_cal_ns is a signal that specifies the capacitance value of the second variable capacitance C2. Around time t6, the gain adjustment signal Gain_cal_in switches the capacitance value setting of the first variable capacitance C1, and the gain adjustment signal Gain_cal_ns switches the capacitance value setting of the second variable capacitance C2. After that, from time t7 onwards, the same operations as those from time t1 to t6 are repeated.

Figure 8 is a flow chart showing the processing procedure of the ADC 11 in Figure 5, which conforms to the timing diagram in Figure 6. When a power supply voltage is supplied to the ADC 11, first, the differential input signal pair Vad_p, Vad_n input from the outside is sampled (step S1). Next, a normal comparison mode is set, and the capacitances of the first DAC 14 and the second DAC 15 are controlled based on the sampled voltage, and the most significant bit is converted into a digital value one bit at a time (step S2). Next, a gain comparison mode is set, and the gain of the first comparison circuit 2 and the gain of the second comparison circuit 3 are compared (step S3), and the capacitance values of the first variable capacitance C1 and the second variable capacitance C2 are controlled so that the gain difference is eliminated (step S4). When the gain difference is eliminated, the processing from step S2 onwards is repeated.

The processing order of FIG. 8 may be partially interchanged. FIG. 9 is a flowchart showing a modified example of the processing procedure of the ADC 11 of FIG. 5. After supplying a power supply voltage to the ADC 11, first, the gain comparison mode is set, the gain of the first comparison circuit 2 is compared with the gain of the second comparison circuit 3 (step S11), and the capacitance values of the first variable capacitance C1 and the second variable capacitance C2 are controlled so that the gain difference is eliminated (step S12). When the gain difference is eliminated, the differential input signal pair Vad_p, Vad_n input from the outside is sampled (step S13). Next, the normal comparison mode is set, and the capacitances of the first DAC 14 and the second DAC 15 are controlled based on the sampled voltage, and the most significant bit is converted into a digital value one bit at a time (step S14). When the least significant bit is converted into a digital value, the processing from step S11 onwards is repeated.

Thus, in Figure 8, when power supply voltage is supplied to ADC 11, first sampling of the differential input signal pair and A/D conversion are performed, followed by gain comparison and gain correction, whereas in Figure 9, gain comparison and gain correction are performed first, followed by sampling and A/D conversion. However, Figures 8 and 9 are the same in that they perform gain comparison and gain correction each time sampling and A/D conversion are performed, except for the operation immediately after power supply voltage is supplied to ADC 11.

As described above, in the first embodiment, the capacitance value of the first variable capacitance C1 and the capacitance value of the second variable capacitance C2 are controlled so that the gain difference between the first comparison circuit 2 and the second comparison circuit 3 in the comparator 1 is eliminated. Therefore, even if there is a difference between the transconductance of the first transistor pair Q11, Q12 in the first comparison circuit 2 and the transconductance of the second transistor pair Q21, Q22 in the second comparison circuit 3 due to manufacturing variations, and even if there is a difference between the common voltage of the first differential input signal pair Vin_p, Vin_n input to the first comparison circuit 2 and the common voltage of the second differential input signal pair Vns_p, Vns_n input to the second comparison circuit 3, it is possible to control so that gm_in×Vin_cm and gm_ns×Vns_cm are equal, thereby improving the S/N ratio of the ADC 11 and the comparator 1 and increasing stability.

Second Embodiment
1 may not output a correct comparison result when the voltage level of the first differential input signal pair Vin_p, Vin_n input to the first comparison circuit 2 is high, or when the voltage level of the second differential input signal pair Vns_p, Vns_n input to the second comparison circuit 3 is high. Therefore, the second embodiment is intended to prevent such a problem from occurring.

Figure 10 is a circuit diagram of a comparator 1a according to the second embodiment. The comparator 1a in Figure 10 can be used in place of the comparator 1 in Figure 5, thereby forming an ADC 11 that operates in the same manner as in Figure 5.

The comparator 1a in FIG. 10 has a switching circuit 6 with a configuration that is partially different from that of the comparator 1 in FIG. 1. In addition to the switch configuration of the switching circuit 6 in FIG. 1, the switching circuit 6 in FIG. 10 has a switch SW9 that switches whether or not the gates of the first transistor pair Q11, Q12 are shorted together, and a switch SW10 that switches whether or not the gates of the second transistor pair Q21, Q22 are shorted together. These switches SW9 and SW10 are off in the normal comparison mode, and on in the gain comparison mode. When these switches SW9 and SW10 are on, the gates of the first transistor pair Q11, Q12 are shorted together, and similarly, the gates of the second transistors are shorted together. Therefore, the gates of the first transistor pair Q11, Q12 are at the same potential, and the gates of the second transistor pair Q21, Q22 are also at the same potential.

In the gain comparison mode, the difference in transconductance between the first transistor pair Q11, Q12 and the second transistor pair Q21, Q22 and the difference in common voltage between the first differential input signal pair Vin_p, Vin_n and the second differential input signal pair Vns_p, Vns_n are corrected, and the correction process can be performed even if the gates of the first transistor pair Q11, Q12 are shorted together and the gates of the second transistor pair Q21, Q22 are shorted together. Rather, by performing gain comparison and gain correction in a state in which the first differential input signal pair Vin_p, Vin_n are shorted together and the second differential input signals are shorted together, a large voltage is not applied between the gates of the first transistor pair Q11, Q12 or between the gates of the second transistor pair Q21, Q22, and there is no risk of the first comparison circuit 2 and the second comparison circuit 3 outputting an incorrect comparison result.

Third Embodiment
The comparator 1b according to the third embodiment has transistors of the opposite conductivity type to the comparators 1 according to the first and second embodiments.

Figure 11 is a circuit diagram of a comparator 1b according to the third embodiment. The comparator 1b in Figure 11 can be used in place of the comparator 1 in Figure 5, thereby forming an ADC 11 that operates in the same way as in Figure 5.

The comparator 1b in FIG. 11 has a configuration in which the conductivity type of each transistor in the comparator 1 in FIG. 1 is reversed. The first comparison circuit 2 in the comparator 1b in FIG. 11 has a first transistor pair Q11a, Q12a consisting of two PMOS transistors. A switch consisting of a PMOS transistor Q13a and a first variable capacitance C1 are connected between the power supply voltage node and the sources of the first transistor pair Q11a, Q12a. The second comparison circuit 3 in the comparator 1b in FIG. 11 has a second transistor pair Q21a, Q22a consisting of two PMOS transistors. A switch consisting of a PMOS transistor Q23a and a second variable capacitance C2 are connected between the power supply voltage node and the sources of the second transistor pair Q21a, Q22a.

A switching circuit 6 is connected between the drains of the first transistor pair Q11a, Q12a and the drains of the second transistor pair Q21a, Q22a and the comparison output node pair n1, n2. A pull-down circuit 8 is connected between the switching circuit 6 and a reference voltage node (e.g., a ground node). The latch circuit 5 in FIG. 11 has transistors of a different conductivity type than the latch circuit 5 in FIG. 1.

The comparator 1b in Fig. 11 has the opposite transistor conductivity type to the comparator 1 in Fig. 1, but the circuit operation is the same. The capacitance value of the first variable capacitance C1 and the capacitance value of the second variable capacitance C2 are controlled so that the gain difference becomes zero in the gain comparison mode. Therefore, even if there is a difference in the transconductance of the first transistor pair Q11a, Q12a and the second transistor pair Q21a, Q22a due to manufacturing variations, and even if there is a deviation in the common voltage of the first differential input signal pair Vin_p, Vin_n and the common voltage of the second differential input signal pair Vns_p, Vns_n, it is possible to control so that gm_in x Vin_cm and gm_ns x Vns_cm are equal, thereby improving the S/N ratio of the ADC 11 and improving stability.

As with comparator 1b in Figure 11, the conductivity type of each transistor in comparator 1a in Figure 10 may be reversed.

(Fourth embodiment)
In the fourth embodiment, the latch circuit 5 is connected at a location different from the comparator 1 in FIG.

Figure 12 is a circuit diagram of a comparator 1c according to the fourth embodiment. The comparator 1c in Figure 12 includes a latch circuit 5 connected between a power supply voltage node and a comparison output node pair n1, n2. The conductivity type of the transistors in the latch circuit 5 is opposite to that of the transistors in the latch circuit 5 in Figure 1. The comparator 1c in Figure 12 can be used in place of the comparator 1 in Figure 5, thereby forming an ADC 11 that operates in the same manner as in Figure 5.

The comparator 1c of Figure 12 is equipped with a switching circuit 6, a first variable capacitance C1, a second variable capacitance C2 and a correction circuit 7 similar to the comparator 1 of Figure 1, and therefore, similar to the comparator 1 of Figure 1, in the gain comparison mode, it can be controlled so that gm_in x Vin_cm and gm_ns x Vns_cm are equal, thereby improving the S/N ratio of the ADC 11 and also improving stability.

Fifth Embodiment
In the fifth embodiment, the drive capability of the signals transmitted through the comparison output node pair n1, n2 is increased, thereby speeding up the latch operation of the latch circuit 5.

Figure 13 is a circuit diagram of a comparator 1d according to the fifth embodiment. The comparator 1d in Figure 13 has inverters IV1 and IV2 connected to a comparison output node pair n1 and n2. These inverters IV1 and IV2 invert the logic of the signal and output it, and at that time, perform waveform shaping to make the output signal waveform steeper. In this way, these inverters IV1 and IV2 function as a waveform shaping circuit. Various logic operation elements (e.g., NAND elements, NOR elements, etc.) may be used instead of the inverters IV1 and IV2. The comparator 1d in Figure 13 can be used instead of the comparator 1 in Figure 5, and this makes it possible to configure an ADC 11 that operates in the same way as in Figure 5.

When inverters IV1 and IV2 are provided at the comparison output node pair n1 and n2 as in Figure 13, the signal logic is inverted, so the internal configuration of the latch circuit 5 must be different from that in Figure 1. The latch circuit 5 in Figure 13 has two NMOS transistors Q41 and Q42 having gates connected to the comparison output node pair n1 and n2, two NMOS transistors Q43 and Q44 connected between the sources of these NMOS transistors Q41 and Q42 and a reference voltage node (e.g., a ground node), and PMOS transistors Q45 to Q48 connected between the drains of these NMOS transistors Q43 and Q44 and a power supply voltage node.

In this way, the comparator 1d in Figure 13 connects inverters IV1 and IV2 to the comparison output node pair n1 and n2, thereby enabling waveform shaping of the signals at the comparison output node pair n1 and n2 and speeding up the latch operation of the latch circuit 5.

Sixth Embodiment
The sixth embodiment is provided with alternatives to the first variable capacitance C1 and the second variable capacitance C2.

Figure 14 is a circuit diagram of a comparator 1e according to the sixth embodiment. The comparator 1e in Figure 14 can be used in place of the comparator 1 in Figure 5, thereby forming an ADC 11 that operates in the same manner as in Figure 5. The comparator 1e in Figure 14 includes a first variable delay buffer 21 that controls the timing at which the transistor Q13, which is a switch in the first comparison circuit 2, turns on, and a second variable delay buffer 22 that controls the timing at which the transistor Q23, which is a switch in the second comparison circuit 3, turns on, instead of the first variable capacitance C1 and the second variable capacitance C2 in Figure 1.

The first variable delay buffer 21 variably controls the delay time until the input clock signal Clk is output by the signal Gain_cal_in. Similarly, the second variable delay buffer 22 variably controls the delay time until the input clock signal Clk is output by the signal Gain_cal_ns. In the gain comparison mode, the discharge speed of the discharge path from the comparison output node n1 to the ground node through the transistor Q11 or Q12 and the transistor Q13 in the first comparison circuit 2 changes depending on the timing when the output of the first variable delay buffer 21 becomes high potential. Similarly, in the gain comparison mode, the discharge speed of the discharge path from the comparison output node n2 to the ground node through the transistor Q21 or Q22 and the transistor Q23 in the second comparison circuit 3 changes depending on the timing when the output of the second variable delay buffer 22 becomes high potential.

Therefore, by individually controlling the delay time of the first variable delay buffer 21 and the second variable delay buffer 22, the gain difference between the first comparison circuit 2 and the second comparison circuit 3 can be adjusted to zero.

The delay times of the first variable delay buffer 21 and the second variable delay buffer 22 are adjusted by the correction circuit 7. By adjusting the delay times of the first variable delay buffer 21 and the second variable delay buffer 22, the correction circuit 7 adjusts the timing at which the transistors Q13 and Q23, which are switches, are shorted to a reference potential node (e.g., a ground node), thereby adjusting the discharge speed of the comparison output nodes n1 and n2.

In the comparator 1e of Figure 14, instead of the first variable capacitance C1 and the second variable capacitance C2, the gain difference is made zero by adjusting the delay time of the first variable delay buffer 21 and the second variable delay buffer 22, so that the circuit area of the comparator 1e can be reduced more than that of the comparator 1 of Figure 1.

Seventh Embodiment
The seventh embodiment is provided with alternatives to the first variable capacitance C1 and the second variable capacitance C2.

Figure 15 is a circuit diagram of a comparator 1f according to the seventh embodiment. The comparator 1f in Figure 15 can be used in place of the comparator 1 in Figure 5, thereby forming an ADC 11 that operates in the same manner as in Figure 5. The comparator 1f in Figure 15 has a first variable current source 23 in the first comparison circuit 2 and a second variable current source 24 in the second comparison circuit 3, instead of the first variable capacitance C1 and second variable capacitance C2 in Figure 1.

The first variable current source 23 is connected between the source of transistor Q13 in the first comparison circuit 2 and a reference voltage node (e.g., a ground node). The second variable current source 24 is connected between the source of transistor Q23 in the second comparison circuit 3 and a reference voltage node. The current value of the first variable current source 23 is controlled by the signal Gain_cal_in. The current value of the second variable current source 24 is controlled by the signal Gain_cal_ns.

In the comparator 1f in Fig. 15, the discharge speed of the comparison output node pair n1, n2 can be adjusted by individually controlling the current values flowing through the first variable current source 23 and the second variable current source 24. Therefore, like the comparator 1f in Fig. 1, gm_in x Vin_cm and gm_ns x Vns_cm can be controlled to be equal in the gain comparison mode, improving the S/N ratio of the ADC 11 and improving stability.

Eighth embodiment
The eighth embodiment is provided with alternatives to the first variable capacitance C1 and the second variable capacitance C2.

Figure 16 is a circuit diagram of a comparator 1g according to the eighth embodiment. The comparator 1g in Figure 16 can be used in place of the comparator 1 in Figure 5, thereby forming an ADC 11 that operates in the same manner as in Figure 5. The comparator 1g in Figure 16 can variably control the size of the first transistor pair Q11s, Q12s in the first comparison circuit 2, and can variably control the size of the second transistor pair Q21s, Q22s in the second comparison circuit 3, instead of the first variable capacitance C1 and the second variable capacitance C2 in Figure 1.

The size is, for example, the gate width. By providing a switch that can select any number of transistors from among a number of transistors, and by switching the switch, a circuit in which any number of transistors are connected in series or parallel can be treated as a single transistor, which effectively makes it possible to variably adjust the gate width of the transistor.

In the comparator 1g of Figure 16, like the comparator 1g of Figure 1, it is possible to control gm_in x Vin_cm and gm_ns x Vns_cm to be equal in gain comparison mode, thereby improving the S/N ratio of the ADC 11 and also improving its stability.

Ninth embodiment
In the ninth embodiment, a latch circuit 5 for the normal comparison mode and a latch circuit 5 for the gain comparison mode are provided separately.

Figure 17 is a circuit diagram of a comparator 1h according to the ninth embodiment. The comparator 1h in Figure 17 is configured similarly to the comparator 1h in Figure 1, except that the latch circuit 5 has a different configuration. The comparator 1h in Figure 17 can be used in place of the comparator 1 in Figure 5, thereby forming an ADC 11 that operates in the same manner as in Figure 5.

The comparator 1h in Fig. 17 has two latch circuits 5 (hereinafter referred to as the first latch circuit 5a and the second latch circuit 5b) connected to the comparison output node pair n1, n2. The internal configuration of the first latch circuit 5a and the second latch circuit 5b is basically the same as that of the latch circuit 5 in Fig. 1, but has NAND gates 36, 37 for switching operation.

When the signal Sw_gain is at a high potential, the NAND gate 36 in the first latch circuit 5a inverts and outputs the clock signal Clk and supplies it to the first latch circuit 5a. The first latch circuit 5a performs a latch operation when the signal Sw_gain is at a high potential.

When the signal Sw_comp is at a high potential, the NAND gate 37 in the second latch circuit 5b inverts and outputs the clock signal Clk and supplies it to the second latch circuit 5b. The second latch circuit 5b performs a latch operation when the signal Sw_comp is at a high potential.

As shown in FIG. 17, by providing a first latch circuit 5a for normal comparison mode and a second latch circuit 5b for gain comparison, after the normal comparison mode is terminated, latch operation can be performed by the second latch circuit 5b for gain comparison without initializing the first latch circuit 5a, so that switching between the normal comparison mode and the gain comparison mode can be performed quickly.

The alternative means for the first variable capacitance C1 and the second variable capacitance C2 in Figures 15 to 17 described above are applicable not only to the comparator 1 in Figure 1, but also to the comparators 1a, 1b, 1c, 1d, and 1e in Figures 10 to 14.

The present technology can be configured as follows.
(1) a first comparison circuit for comparing a first pair of differential input signals;
a second comparison circuit for comparing a second pair of differential input signals;
a switching circuit that switches between comparing the first differential input signal pair in the first comparison circuit and comparing the second differential input signal pair in the second comparison circuit, or comparing a gain difference between the first comparison circuit and the second comparison circuit.
(2) The comparator according to (1), further comprising a correction circuit that corrects a gain of the first comparison circuit and a gain of the second comparison circuit.
(3) The comparator according to (2), wherein the correction circuit corrects the gain of the first comparison circuit and the gain of the second comparison circuit so that the gain difference becomes smaller.
(4) A comparison output node pair is provided for transmitting the differential signal switched by the switching circuit,
The comparator according to claim 3, wherein the correction circuit adjusts a discharge rate of a discharge path from one node of the comparison output node pair through the switching circuit and the first comparison circuit to a reference potential node, and a discharge rate of a discharge path from the other node of the comparison output node pair through the switching circuit and the second comparison circuit to the reference potential node, so that the gain difference is smaller.
(5) a first variable capacitance connected between the first comparison circuit and the reference potential node;
a second variable capacitance connected between the second comparison circuit and the reference potential node;
The comparator according to (4), wherein the correction circuit adjusts the discharge rate by adjusting a capacitance value of at least one of the first variable capacitance and the second variable capacitance.
(6) The first comparison circuit
a first transistor pair for generating a difference signal of the first differential input signal pair;
a first switching circuit that switches whether or not the first transistor pair and the reference potential node are connected,
The second comparison circuit is
a second transistor pair for generating a difference signal of the second differential input signal pair;
a second switching circuit that switches whether or not the second transistor pair and the reference potential node are connected,
The comparator according to (4), wherein the correction circuit adjusts the discharge rate by adjusting a timing for switching at least one of the first switching circuit and the second switching circuit.
(7) The first comparison circuit includes a first current source capable of adjusting a current flowing to the reference potential node in response to a difference signal of the first differential input signal pair,
the second comparison circuit has a second current source capable of adjusting a current flowing to the reference potential node in response to a difference signal of the second differential input signal pair;
The comparator according to (4), wherein the correction circuit adjusts the discharge rate by adjusting a current flowing from at least one of the first current source and the second current source to the reference potential node.
(8) The first comparison circuit includes a first transistor pair that generates a first differential output signal pair according to a difference signal of the first differential input signal pair,
the second comparison circuit has a second transistor pair that generates a second differential output signal pair according to a difference signal of the second differential input signal pair;
The comparator according to claim 4, wherein the correction circuit adjusts the discharge speed by adjusting a gate width of at least one of the first transistor pair and the second transistor pair.
(9) The first comparison circuit includes a first transistor pair that generates a first differential output signal pair according to a difference signal of the first differential input signal pair,
the second comparison circuit has a second transistor pair that generates a second differential output signal pair according to a difference signal of the second differential input signal pair;
A comparator as described in any one of (1) to (7), wherein the gain difference is a difference between the product of the transconductance of the first transistor pair and the common voltage of the first differential input signal pair and the product of the transconductance of the second transistor pair and the common voltage of the second differential input signal pair.
(10) a comparison output node pair transmitting a differential signal switched by the switching circuit;
and a latch circuit for holding the differential signal of the comparison output node pair.
(11) A first waveform shaping circuit and a second waveform shaping circuit are provided in the comparison output node pair, respectively, and perform waveform shaping of the differential signal,
The comparator according to (9), wherein the latch circuit holds the differential signals whose waveforms have been shaped by the first waveform shaping circuit and the second waveform shaping circuit.
(12) The comparator according to (11), wherein each of the first waveform shaping circuit and the second waveform shaping circuit is an inverter.
(13) The latch circuit comprises:
a first latch section that holds the differential signals on the comparison output node pair when the first comparison circuit compares the first differential input signal pair and the second comparison circuit compares the second differential input signal pair;
and a second latch unit that holds the differential signal on the comparison output node pair when comparing a gain difference between the first comparison circuit and the second comparison circuit.
(14) The comparator according to (13), wherein the latch circuit is connected between the comparison output node pair and a power supply voltage node having a voltage level higher than that of the comparison output node pair.
(15) The comparator according to any one of (1) to (14), wherein the switching circuit alternates between a first operating mode in which the first comparison circuit compares the first differential input signal pair and the second comparison circuit compares the second differential input signal pair, and a second operating mode in which a gain difference between the first comparison circuit and the second comparison circuit is compared.
(16) The comparator according to (15), wherein the switching circuit performs the first operation mode at the start of operation, and then repeats the switching operation between the second operation mode and the first operation mode in that order.
(17) The comparator according to (15), wherein the switching circuit performs the second operation mode at the start of operation, and then repeats the switching operation between the first operation mode and the second operation mode in that order.
(18) The first comparison circuit includes a first transistor pair that generates a first differential output signal pair according to a difference signal of the first differential input signal pair,
the second comparison circuit has a second transistor pair that generates a second differential output signal pair according to a difference signal of the second differential input signal pair;
The comparator according to any one of (1) to (17), wherein, when comparing a gain difference between the first comparison circuit and the second comparison circuit, the switching circuit shorts the gates of the first transistor pair together and shorts the gates of the second transistor pair together.
(19) A comparison output node pair is provided for transmitting the differential signal switched by the switching circuit,
the first comparison circuit has a first output node and a second output node;
the second comparison circuit has a third output node and a fourth output node;
The comparator according to any one of (1) to (3), wherein, when the first comparison circuit compares the first differential input signal pair and the second comparison circuit compares the second differential input signal pair, the switching circuit connects the first output node and the third output node to one node of the comparison output node pair and connects the second output node and the fourth output node to the other node of the comparison output node pair, and when comparing a gain difference between the first comparison circuit and the second comparison circuit, the switching circuit connects the first output node and the second output node to one node of the comparison output node pair and connects the third output node and the fourth output node to the other node of the comparison output node pair.
(20) A first sampling switch that switches whether or not one of a pair of differential input signals is sampled;
a first digital-to-analog converter that converts the sampled one of the signals into a digital signal consisting of a plurality of bits one bit at a time, and outputs a signal having a voltage level corresponding to the unconverted bits;
a second sampling switch that switches whether or not the other signal of the differential input signal pair is sampled;
a second digital-to-analog converter that converts the sampled other signal into a digital signal consisting of a plurality of bits one bit at a time and outputs a signal having a voltage level corresponding to the unconverted bits;
a filter circuit that samples and outputs an output signal of the first digital-to-analog converter and an output signal of the second digital-to-analog converter;
a comparator that outputs a signal according to a difference signal of a first differential input signal pair, which is a pair of an output signal of the first digital-analog converter and an output signal of the second digital-analog converter, and a difference signal of a second differential input signal pair output from the filter circuit;
a control circuit for controlling the first digital-to-analog converter and the second digital-to-analog converter based on an output signal of the comparator,
a first comparison circuit for comparing the first pair of differential input signals;
a second comparison circuit for comparing the second pair of differential input signals;
and a switching circuit that switches between comparing the first differential input signal pair in the first comparison circuit and comparing the second differential input signal pair in the second comparison circuit, or comparing a gain difference between the first comparison circuit and the second comparison circuit. (21) The analog-to-digital converter according to (20), wherein sampling of the differential input signal pair by the first sampling switch and the second sampling switch, conversion to the digital signal by the first digital-analog converter and the second digital-analog converter, comparison of the gain difference, and correction of the gain difference are performed in a repeated order.

The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by a person skilled in the art, and the effects of the present disclosure are not limited to the above. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure derived from the contents defined in the claims and their equivalents.

1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 101 Comparator, 2 First comparison circuit, 3 Second comparison circuit, 4 Pull-up circuit, 5 Latch circuit, 5a First latch circuit, 5b Second latch circuit, 6 Switching circuit, 6a First switch pair, 6b Second switch pair, 6c Third switch pair, 6d Fourth switch pair, 7 Correction circuit, 11 ADC, 12 First sampling switch, 13 Second sampling switch, 14 First DAC, 15 Second DAC, 16 Filter circuit, 17 Control circuit, 18 Capacitive DAC

Claims (21)

a first comparison circuit for comparing a first pair of differential input signals;
a second comparison circuit for comparing a second pair of differential input signals;
a switching circuit that switches between comparing the first differential input signal pair in the first comparison circuit and comparing the second differential input signal pair in the second comparison circuit, or comparing a gain difference between the first comparison circuit and the second comparison circuit. The comparator according to claim 1, further comprising a correction circuit that corrects the gain of the first comparison circuit and the gain of the second comparison circuit. The comparator of claim 2, wherein the correction circuit corrects the gain of the first comparison circuit and the gain of the second comparison circuit so that the gain difference becomes smaller. a comparison output node pair for transmitting the differential signal switched by the switching circuit,
4. The comparator according to claim 3, wherein the correction circuit adjusts a discharge rate of a discharge path from one node of the comparison output node pair through the switching circuit and the first comparison circuit to a reference potential node, and a discharge rate of a discharge path from the other node of the comparison output node pair through the switching circuit and the second comparison circuit to the reference potential node, so that the gain difference is smaller. a first variable capacitance connected between the first comparison circuit and the reference potential node;
a second variable capacitance connected between the second comparison circuit and the reference potential node;
5. The comparator according to claim 4, wherein the correction circuit adjusts the discharge rate by adjusting a capacitance value of at least one of the first variable capacitance and the second variable capacitance. The first comparison circuit is
a first transistor pair for generating a difference signal of the first differential input signal pair;
a first switching circuit that switches whether or not the first transistor pair and the reference potential node are connected,
The second comparison circuit is
a second transistor pair for generating a difference signal of the second differential input signal pair;
a second switching circuit that switches whether or not the second transistor pair and the reference potential node are connected,
The comparator according to claim 4 , wherein the correction circuit adjusts the discharge rate by adjusting a timing for switching at least one of the first switching circuit and the second switching circuit. the first comparison circuit has a first current source capable of adjusting a current flowing into the reference potential node in response to a difference signal of the first differential input signal pair;
the second comparison circuit has a second current source capable of adjusting a current flowing to the reference potential node in response to a difference signal of the second differential input signal pair;
5. The comparator according to claim 4, wherein the correction circuit adjusts the discharge rate by adjusting a current flowing from at least one of the first current source and the second current source to the reference potential node. the first comparison circuit includes a first transistor pair that generates a first differential output signal pair in response to a difference signal of the first differential input signal pair;
the second comparison circuit has a second transistor pair that generates a second differential output signal pair according to a difference signal of the second differential input signal pair;
5. The comparator according to claim 4, wherein the correction circuit adjusts the discharge rate by adjusting a gate width of at least one of the first transistor pair and the second transistor pair. the first comparison circuit includes a first transistor pair that generates a first differential output signal pair in response to a difference signal of the first differential input signal pair;
the second comparison circuit has a second transistor pair that generates a second differential output signal pair according to a difference signal of the second differential input signal pair;
2. The comparator of claim 1, wherein the gain difference is a difference between a product of a transconductance of the first transistor pair and a common voltage of the first differential input signal pair and a product of a transconductance of the second transistor pair and a common voltage of the second differential input signal pair. a comparison output node pair for transmitting the differential signal switched by the switching circuit;
2. The comparator according to claim 1, further comprising: a latch circuit that holds the differential signal of the comparison output node pair. a first waveform shaping circuit and a second waveform shaping circuit, which are respectively arranged on the comparison output node pair and perform waveform shaping of the differential signal;
11. The comparator according to claim 10, wherein the latch circuit holds the differential signals waveform-shaped by the first waveform shaping circuit and the second waveform shaping circuit. The comparator of claim 11, wherein each of the first waveform shaping circuit and the second waveform shaping circuit is an inverter. The latch circuit includes:
a first latch section that holds the differential signals of the comparison output node pair when the first comparison circuit compares the first differential input signal pair and the second comparison circuit compares the second differential input signal pair;
11. The comparator according to claim 10, further comprising: a second latch section that holds the differential signal of the comparison output node pair when comparing a gain difference between the first comparison circuit and the second comparison circuit. The comparator of claim 13, wherein the latch circuit is connected between a power supply voltage node having a higher voltage level than the comparison output node pair and the comparison output node pair. The comparator of claim 1, wherein the switching circuit alternates between a first operating mode in which the first comparison circuit compares the first differential input signal pair and the second comparison circuit compares the second differential input signal pair, and a second operating mode in which the gain difference between the first comparison circuit and the second comparison circuit is compared. The comparator of claim 15, wherein the switching circuit performs the first operating mode at the start of operation, and then repeats the switching operation between the second operating mode and the first operating mode in that order. The comparator of claim 15, wherein the switching circuit performs the second operating mode at the start of operation, and then repeats the switching operation between the first operating mode and the second operating mode in that order. the first comparison circuit includes a first transistor pair that generates a first differential output signal pair in response to a difference signal of the first differential input signal pair;
the second comparison circuit has a second transistor pair that generates a second differential output signal pair according to a difference signal of the second differential input signal pair;
2. The comparator according to claim 1, wherein the switching circuit shorts the gates of the first transistor pair together and shorts the gates of the second transistor pair together when comparing a gain difference between the first comparison circuit and the second comparison circuit. a comparison output node pair for transmitting the differential signal switched by the switching circuit,
the first comparison circuit has a first output node and a second output node;
the second comparison circuit has a third output node and a fourth output node;
2. The comparator according to claim 1, wherein, when the first comparison circuit compares the first differential input signal pair and the second comparison circuit compares the second differential input signal pair, the switching circuit connects the first output node and the third output node to one node of the comparison output node pair and connects the second output node and the fourth output node to the other node of the comparison output node pair, and when comparing a gain difference between the first comparison circuit and the second comparison circuit, the switching circuit connects the first output node and the second output node to one node of the comparison output node pair and connects the third output node and the fourth output node to the other node of the comparison output node pair. a first sampling switch that switches whether or not one of the differential input signal pair is sampled;
a first digital-to-analog converter that converts the sampled one of the signals into a digital signal consisting of a plurality of bits one bit at a time, and outputs a signal having a voltage level corresponding to the unconverted bits;
a second sampling switch that switches whether or not the other signal of the differential input signal pair is sampled;
a second digital-to-analog converter that converts the sampled other signal into a digital signal consisting of a plurality of bits one bit at a time and outputs a signal having a voltage level corresponding to the unconverted bits;
a filter circuit that samples and outputs an output signal of the first digital-to-analog converter and an output signal of the second digital-to-analog converter;
a comparator that outputs a signal according to a difference signal of a first differential input signal pair, which is a pair of an output signal of the first digital-analog converter and an output signal of the second digital-analog converter, and a difference signal of a second differential input signal pair output from the filter circuit;
a control circuit for controlling the first digital-to-analog converter and the second digital-to-analog converter based on an output signal of the comparator,
a first comparison circuit for comparing the first pair of differential input signals;
a second comparison circuit for comparing the second pair of differential input signals;
and a switching circuit that switches between comparing the first differential input signal pair in the first comparison circuit and comparing the second differential input signal pair in the second comparison circuit, or comparing a gain difference between the first comparison circuit and the second comparison circuit. An analog-to-digital converter as described in claim 20, wherein sampling of the differential input signal pair by the first sampling switch and the second sampling switch, conversion to the digital signal by the first digital-to-analog converter and the second digital-to-analog converter, comparison of the gain difference, and correction of the gain difference are performed in a repeated sequence.

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