JP7623154B2 - Amplification equipment - Google Patents

Description

The present invention relates to an amplification device.

Amplification devices are widely used to amplify sensor signals, etc., but some applications require that the offset components and low-frequency noise inside the amplification device be very small. As a method for reducing the offset components and low-frequency noise, the Ping-Pong auto-zero amplifier using two auto-zero amplifiers 200 shown in FIG. 22 is known (Patent Document 1, Non-Patent Document 1).

As shown in the figure, the Ping-Pong auto-zero amplifier includes two auto-zero amplifiers 200. The auto-zero amplifier 200 includes a transconductance amplifier A1 and a calibration circuit 201. The calibration circuit 201 includes a number of switches S1 and S2, a transconductance amplifier A2, and a sampling capacitor C. The auto-zero amplifier 200 alternates between two modes: a calibration mode and an amplification mode.

In the calibration mode, switch S2 is turned on and switch S1 is turned off to sample the offset component and low-frequency noise component of the transconductance amplifier A1 to the sampling capacitor C. In the amplification mode, switch S1 is turned on and switch S2 is turned off to connect the transconductance amplifier A1 to the output terminal and input terminal, and the calibration signal (voltage) sampled by the sampling capacitor C is applied to the output of the transconductance amplifier A1 to reduce the offset component and low-frequency noise component. In addition, when one of the two auto-zero amplifiers 200 is in the calibration mode, the other is in the amplification mode, and when one is in the amplification mode, the other is in the calibration mode. As a result, the Ping-Pong auto-zero amplifier always outputs an output Vout with reduced offset components and low-frequency noise components.

The input offset voltage V _io,in of the above-described auto-zero amplifier 200 is expressed by the following equation (1).

The variables in equation (1) represent the offset voltage _Vio1 and transconductance value _Gm1 of the transconductance amplifier A1, the offset voltage _Vio2 and transconductance value _Gm2 of the transconductance amplifier A2, and the output resistance R of each of the transconductance amplifiers A1 and A2. It can be seen from equation (1) that the offset voltage _Vio1 of the transconductance amplifier A1 is reduced by the transconductance amplifier A2, and the offset voltage _Vio2 of the transconductance amplifier A2 is reduced by the transconductance amplifier A1.

For example, if V _io1 =V _io2 =10 mV, Gm ₂ is a quarter of Gm ₁ , and Gm ₁ ·R is 4000 times, the input offset voltage V _{io,in will be +12.5 μV to −12.5 μV. In other words, the input offset voltage V io,in of} the conventional auto-zero amplifier 200 can be +12.5 μV to −12.5 μV, and further, for example, if one input offset voltage of the auto-zero amplifier 200 is +12.5 μV and the other input offset voltage is −12.5 μVμV, there is a risk of switching noise with an amplitude of ±12.5 μV occurring when switching modes.

U.S. Pat. No. 6,476,671

Ion E. Opris and Gregory T.A. Kovacs, “A Rail-to-Rail Ping-Pong Op-Amp”, IEEE J. Solid-State Circuits, vol. 31, no 9, pp. 1320-1324, Sep. 1996.

The present invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide an amplifier device that reduces the input offset voltage.

In order to achieve the above-mentioned object, an amplifier according to the present invention is characterized by the following features [1] to [5].
[1]
a transconductance amplifier;
a first calibration circuit including a first sampling capacitor and a first calibration transconductance amplifier;
a second calibration circuit including a second sampling capacitor and a second calibration transconductance amplifier;
a first calibration mode in which a first calibration signal that reduces offset components and low-frequency noise components of the transconductance amplifier and the second calibration transconductance amplifier is sampled into the first sampling capacitor;
a second calibration mode in which a second calibration signal that reduces an offset component and a low-frequency component of the transconductance amplifier calibrated by the first calibration signal is sampled into the second sampling capacitor;
an auto-zero amplifier switchable between an amplification mode in which an offset component and a low-frequency noise component of the transconductance amplifier are reduced by the first calibration signal and the second calibration signal;
a control circuit that switches the auto-zero amplifier between the first calibration mode, the second calibration mode, and the amplification mode in this order, and repeats the switching;
the first sampling capacitor has one end connected to ground and the other end connected to the output of the transconductance amplifier;
the first calibration transconductance amplifier has an input connected to the other end of the first sampling capacitor and an output connected to the output of the transconductance amplifier;
the second sampling capacitor has one end connected to ground and the other end connected to the output of the transconductance amplifier;
the second calibration transconductance amplifier has an input connected to the other end of the second sampling capacitor and an output connected to the output of the transconductance amplifier;
It is an amplification device.
[2]
In the amplification device according to [1],
the second calibration transconductance amplifier has an inverting input and a non-inverting input connected to the second sampling capacitor,
the second calibration circuit has a first switch that shorts the inverting input and the non-inverting input of the second calibration transconductance amplifier, and a second switch connected between either the inverting input or the non-inverting input of the second calibration transconductance amplifier and the second sampling capacitor.
It is an amplification device.
[3]
In the amplification device according to [2],
a third switch connected between the other of the inverting input and the non-inverting input of the second calibration transconductance amplifier and the second sampling capacitor;
It is an amplification device.
[4]
In the amplification device according to [2],
the second calibration transconductance amplifier, the first switch, and the second switch are each provided in two pieces;
one of the two second switches is connected between the inverting input of the second calibration transconductance amplifier and the second sampling capacitor;
the other of the two second switches is connected between the non-inverting input of the second calibration transconductance amplifier and the second sampling capacitor;
It is an amplification device.
[5]
[1] to [4] In the amplification device according to any one of the above,
the control circuit makes the time during which the second calibration mode is in effect longer than the time during which the first calibration mode is in effect;
It is an amplification device.

The present invention provides an amplifier device that reduces the input offset voltage.

The present invention has been briefly described above. The details of the present invention will become clearer by reading the following description of the embodiment of the invention (hereinafter referred to as "embodiment") with reference to the attached drawings.

FIG. 1 is a circuit diagram showing an auto-zero amplifier in a first calibration mode in the first embodiment. FIG. 2 is a circuit diagram showing the auto-zero amplifier in the second calibration mode in the first embodiment. FIG. 3 is a circuit diagram showing the auto-zero amplifier in the amplification mode in the first embodiment. FIG. 4 is a time chart of a clock that controls the on/off of the switches that constitute the auto-zero amplifier of the first embodiment. FIG. 5 is a circuit diagram showing an auto-zero amplifier in the first calibration mode in the second embodiment. FIG. 6 is a circuit diagram showing an auto-zero amplifier in the second calibration mode in the second embodiment. FIG. 7 is a circuit diagram showing an auto-zero amplifier in an amplification mode according to the second embodiment. FIG. 8 is a time chart of a clock that controls the on/off of the switches that constitute the auto-zero amplifier of the second embodiment. FIG. 9 is a circuit diagram showing an auto-zero amplifier according to the third embodiment. FIG. 10 is a circuit diagram showing an auto-zero amplifier in the first calibration mode according to the fourth embodiment. FIG. 11 is a circuit diagram showing the auto-zero amplifier in the second calibration mode according to the fourth embodiment. FIG. 12 is a circuit diagram showing an auto-zero amplifier in an amplification mode according to the fourth embodiment. FIG. 13 is a circuit diagram showing a Ping-Pong auto-zero amplifier including an auto-zero amplifier according to the fifth embodiment of the present invention. FIG. 14 is a circuit diagram showing a phase inversion auto-zero amplifier including an auto-zero amplifier according to the sixth embodiment of the present invention. FIG. 15 is a circuit diagram showing an amplifying device including the Ping-Pong auto-zero amplifier shown in FIG. 13 according to the seventh embodiment. FIG. 16 is a circuit diagram showing a chopper-stabilized amplifier including the Ping-Pong auto-zero amplifier shown in FIG. 13 according to the eighth embodiment. FIG. 17 is a circuit diagram showing a chopper-stabilized amplifier including the Ping-Pong auto-zero amplifier shown in FIG. 13 or the phase-inversion auto-zero amplifier shown in FIG. 14 in the ninth embodiment. FIG. 18 is a circuit diagram showing an example of the chopper output circuit shown in FIG. FIG. 19 is a circuit diagram showing an example of the chopper output circuit shown in FIG. FIG. 20 is a characteristic diagram showing an example of time waveforms and frequency characteristics of a signal component, a noise component, and an offset component by the amplifying device of the ninth embodiment. FIG. 21 is a circuit diagram showing a modification of the amplifier constituting the chopper stabilized amplifier shown in FIG. FIG. 22 is a circuit diagram showing a Ping-Pong auto-zero amplifier using a conventional auto-zero amplifier.

Specific embodiments of the present invention are described below with reference to the drawings.

First Embodiment
1 to 3 are diagrams showing the configuration of an auto-zero amplifier used in the amplifier device of the first embodiment. As shown in the figures, the auto-zero amplifier 1A is configured to include a transconductance amplifier A1 (amplifier), a first calibration circuit 2, and a second calibration circuit 3. The transconductance amplifier A1 inverts and amplifies a signal Vin supplied to an input terminal, and outputs the signal Vout from an output terminal.

The first calibration circuit 2 is a circuit that reduces the offset components and low-frequency noise components of the transconductance amplifier A1 and the transconductance amplifier A3 of the second calibration circuit 3, which are included in the signal Vout. The first calibration circuit 2 includes switches S11, S12, switches S21, S22, switches S31, S32, switches S41, S42, sampling capacitors C11, C12 (first sampling capacitors), and a transconductance amplifier A2 (first calibration amplifier).

The switches S11 and S12 are connected between the input of the transconductance amplifier A1 and the input terminal. The switches S21 and S22 are connected between the common mode voltage Vcm and the connection point between the input of the transconductance amplifier A1 and the switches S11 and S12. The switches S31 and S32 are connected between the output of the transconductance amplifier A1 and the output terminal. The switches S41 and S42 are connected between the connection point between the output of the transconductance amplifier A1 and the switches S31 and S32 and the sampling capacitors C11 and C12.

One end of the sampling capacitors C11 and C12 is connected to ground, and the other end is connected to the switches S41 and S42. The other ends of the switches S41 and S42 and the connection points of the sampling capacitors C11 and C12 are connected to the input of the transconductance amplifier A2.

The transconductance amplifier A2 inverts and amplifies the input and outputs it. The positive output of the transconductance amplifier A2 is connected to the positive output of the transconductance amplifier A1, and the negative output is connected to the negative output of the transconductance amplifier A1.

The second calibration circuit 3 is a circuit that reduces the offset components and low-frequency noise components of the transconductance amplifiers A1 and A2 contained in the signal Vout. The second calibration circuit 3 includes switches S51, S52, and S6, sampling capacitors C21 and C22 (second sampling capacitors), and a transconductance amplifier A3 (second calibration amplifier).

Switches S51 and S52 are connected between the connection point of the output of the transconductance amplifier A1 and the switches S31 and S32 and the sampling capacitors C21 and C22. One end of the sampling capacitors C21 and C22 is connected to ground, and the other end is connected to the switches S51 and S52. Switch S6 (first switch) is connected between the inverting input and the non-inverting input of the transconductance amplifier A3.

The transconductance amplifier A3 inverts and amplifies the input and outputs it. The positive output of the transconductance amplifier A3 is connected to the positive output of the transconductance amplifier A1, and the negative output is connected to the negative output of the transconductance amplifier A1.

The auto-zero amplifier 1A has a calibration mode and an amplification mode as its operating modes, and is configured to be able to alternate between the calibration mode and the amplification mode. The auto-zero amplifier 1A also has a first calibration mode and a second calibration mode as its calibration modes, and is configured to be able to switch between the first calibration mode and the second calibration mode in that order. In the first calibration mode, a first calibration signal (voltage) for reducing the offset components and low-frequency noise components of the transconductance amplifiers A1 and A3 is sampled in the sampling capacitors C11 and C12.

As shown in FIG. 1, in the first calibration mode, switches S11, S12, S31, and S32 are turned off, and switches S21 and S22 are turned on. This disconnects the input and output of transconductance amplifier A1 from the input terminal and output terminal. Also, the inverting input and non-inverting input of transconductance amplifier A1 are shorted, and offset components and low-frequency noise components are output from transconductance amplifier A1.

In the first calibration mode, switches S51 and S52 are turned off and switch S6 is turned on. This shorts the inverting input and non-inverting input of the transconductance amplifier A3, and the offset component and low-frequency noise component are output from the transconductance amplifier A3.

In the first calibration mode, switches S41 and S42 are turned on, and the outputs of the transconductance amplifiers A1 and A3 are connected to the sampling capacitors C11 and C12. This allows the offset components and low-frequency noise components output from the transconductance amplifiers A1 and A3 to be sampled as the first calibration signal in the sampling capacitors C11 and C12.

In the second calibration mode, a second calibration signal (voltage) is sampled to sampling capacitors C21 and C22 to reduce the offset components and low-frequency noise components of the transconductance amplifier A1, which is calibrated by the first calibration signal sampled to sampling capacitors C11 and C12.

As shown in FIG. 2, in the second calibration mode, as in the first calibration mode, switches S11, S12, S31, and S32 are turned off, and switches S21 and S22 are turned on. This disconnects the input and output of transconductance amplifier A1 from the input terminal and output terminal. In addition, the inverting input and non-inverting input of transconductance amplifier A1 are shorted, and offset components and low-frequency noise components are output from transconductance amplifier A1.

In the second calibration mode, switches S41 and S42 are turned off. This causes the first calibration signal sampled in sampling capacitors C11 and C12 to be applied to the output of transconductance amplifier A1 via transconductance amplifier A2, reducing the offset component and low-frequency noise component of transconductance amplifier A1.

In the second calibration mode, switches S51 and S52 are turned on, and the outputs of transconductance amplifiers A1 and A2 are connected to sampling capacitors C21 and C22. This allows the offset component and low-frequency noise component of transconductance amplifier A1, calibrated by the first calibration signal, to be sampled as the second calibration signal in sampling capacitors C21 and C22.

As shown in FIG. 3, in the amplification mode, switches S11, S12, S31, and S32 are turned on, and switches S21 and S22 are turned off. As a result, the input and output of the transconductance amplifier A1 are connected to the input and output terminals, and a signal Vout obtained by amplifying the signal Vin by the transconductance amplifier A1 is output from the output terminal. Also, in the amplification mode, switches S41, S42, S51, S52, and S6 are turned off. As a result, the first calibration signal and the second calibration signal are applied to the output of the transconductance amplifier A1 via the transconductance amplifiers A2 and A3, and the offset component and low-frequency noise component contained in the signal Vout are reduced.

Next, the operation of the auto-zero amplifier 1A having the above-mentioned configuration will be described with reference to the time chart shown in FIG. 4. A clock CLK1 is supplied to the switches S11, S12, S31, and S32 of the auto-zero amplifier 1A, and a clock CLK2 is supplied to the switches S21 and S22. A clock CLK3 is supplied to the switches S41, S42, and S6. A clock CLK4 is supplied to the switches S51 and S52. The clocks CLK1 to CLK4 cause the auto-zero amplifier 1A to switch between the first calibration mode (FIG. 1), the second calibration mode (FIG. 2), and the amplification mode (FIG. 3) in that order, and this switching is repeated. The circuit (not shown) that supplies the clocks CLK1 to CLK4 constitutes the control circuit of the auto-zero amplifier 1A. The auto-zero amplifier 1A and the control circuit (not shown) of the auto-zero amplifier 1A constitute the amplifier device of this embodiment.

As shown in FIG. 4, the control circuit of the auto-zero amplifier 1A supplies clocks CLK1 to CLK4 that make the time in the amplification mode the same as the time in the calibration mode. The control circuit of the auto-zero amplifier 1A also supplies clocks CLK1 to CLK4 that make the time in the second calibration mode longer than the time in the first calibration mode. This ensures that the time for sampling the second calibration signal is longer than the time for sampling the first calibration signal.

The input offset voltage V _io,in of the above-described auto-zero amplifier 1A can be expressed by the following equation (2).

The variables in equation (2) represent the offset voltage _Vio1 and transconductance value _Gm1 of the transconductance amplifier A1, the offset voltage _Vio2 and transconductance value _Gm2 of the transconductance amplifier A2, the offset voltage _Vio3 and transconductance value _Gm3 of the transconductance amplifier A3, and the output resistance R of each transconductance amplifier. From equation (2), it can be seen that the offset voltage _Vio1 of the transconductance amplifier A1 is reduced by the transconductance amplifiers A2 and A3, the offset voltage _Vio2 of the transconductance amplifier A2 is reduced by the transconductance amplifiers A1 and A3, and the offset voltage _Vio3 of the transconductance amplifier A3 is reduced by the transconductance amplifiers A1 and A2.

For example, if V _io1 = V _io2 = V _io3 = 10 mV, _Gm2 is set to 1/4 of _Gm1 , _Gm3 is set to 1/4 of _Gm2 , and _Gm1 ·R is set to 4000 times, then the input offset voltage V _io,in will be +0.0525 μV to −0.0525 μV, which is a much greater reduction in the input offset voltage than conventional auto-zero amplifiers.

Second Embodiment
Next, an auto-zero amplifier 1B according to a second embodiment will be described. Figures 5 to 7 are diagrams showing the configuration of the auto-zero amplifier 1B according to the second embodiment. In Figures 5 to 7, parts equivalent to those of the auto-zero amplifier 1A shown in Figures 1 to 3 already described in the first embodiment above are given the same reference numerals, and detailed description thereof will be omitted.

The major difference between the first and second embodiments is that the second calibration circuit 3 of the auto-zero amplifier 1B includes a switch S71 (second switch) that prevents the discharge of the charges accumulated in the sampling capacitors C21 and C22 during the first calibration mode. The switch S71 is connected between the sampling capacitor C21 and the inverting input of the transconductance amplifier A3.

The switch S71 is supplied with the clock CLK5 shown in FIG. 8, is turned off in the first calibration mode (see FIG. 5), and is turned on in the second calibration mode and the amplification mode (see FIG. 6 and FIG. 7). The on/off of the switches S11, S12, S21, S22, S31, S32, S41, S42, S51, S52, and S6 is the same as in the first embodiment described above, so a detailed description will be omitted here.

In the first embodiment, as shown in FIG. 1, when the first calibration mode is entered and switch S6 is turned on, a closed circuit is formed and the charges accumulated in the sampling capacitors C21 and C22 are discharged. In contrast, in the second embodiment, as shown in FIG. 5, even if the first calibration mode is entered and switch S6 is turned on, switch S71 is turned off, so a closed circuit is not formed and the charges accumulated in the sampling capacitors C21 and C22 are not discharged.

In the second embodiment, the switch S71 is connected between the sampling capacitor C21 and the inverting input of the transconductance amplifier A3, but this is not limited to this. The switch S71 may be connected between the sampling capacitor C22 and the non-inverting input of the transconductance amplifier A3.

Third Embodiment
Next, an auto-zero amplifier 1C according to a third embodiment will be described. Fig. 9 is a diagram showing the configuration of the auto-zero amplifier 1C according to the third embodiment. In Fig. 9, parts equivalent to those of the auto-zero amplifier 1B shown in Figs. 5 to 7 already described in the second embodiment above are given the same reference numerals, and detailed description thereof will be omitted.

The major difference between the second and third embodiments is that the auto-zero amplifier 1C includes a switch S72 (third switch). The switch S72 is connected between the sampling capacitor C22 and the non-inverting input of the transconductance amplifier A3.

The switch S72 is supplied with the clock CLK5 shown in FIG. 8, is turned off in the first calibration mode, and is turned on in the second calibration mode and the amplification mode. The on/off of the switches S11, S12, S21, S22, S31, S32, S41, S42, S51, S52, and S6 is the same as in the first embodiment described above, so a detailed description will be omitted here.

In the second embodiment, switch S71 is connected only to the inverting input of the two inputs of transconductance amplifier A3. This causes a bias in the differential impedance of transconductance amplifier A3. In the third embodiment, switches S71 and S72 are connected to the two inputs of transconductance amplifier A3, respectively, so that the bias in the differential impedance of transconductance amplifier A3 can be improved.

Fourth Embodiment
Next, an auto-zero amplifier 1D according to a fourth embodiment will be described. Figures 10 to 12 are diagrams showing the configuration of the auto-zero amplifier 1D according to the fourth embodiment. In Figures 10 to 12, parts equivalent to those of the auto-zero amplifier 1B shown in Figures 5 to 7 already described in the second embodiment above are given the same reference numerals, and detailed descriptions thereof will be omitted.

The major difference between the second and fourth embodiments is that the second calibration circuit 3 includes two transconductance amplifiers A3 connected in parallel. In addition, the second calibration circuit 3 includes switches S51, S52, and S6, and sampling capacitors C21 and C22 for each of the two transconductance amplifiers A3.

The second calibration circuit 3 is also provided with two switches S71 corresponding to the two transconductance amplifiers A3. One of the two switches S71 is connected between the inverting input of the transconductance amplifier A3 and the sampling capacitor C21. The other of the two switches S71 is connected between the non-inverting input of the transconductance amplifier A3 and the sampling capacitor C22. A clock CLK5 that is turned off only in the first calibration mode is supplied to the switch S71.

According to the above-described embodiment, a switch S71 is connected only to the inverting input of one of the two transconductance amplifiers A3. As a result, a differential impedance bias occurs in one of the two transconductance amplifiers A3. On the other hand, a switch S71 is connected only to the non-inverting input of the other of the two transconductance amplifiers A3. As a result, a differential impedance bias opposite to that of the other of the two transconductance amplifiers A3 occurs in the other of the two transconductance amplifiers A3. As a result, the impedance bias of the two transconductance amplifiers A3 is offset, and the impedance bias can be improved.

Fifth Embodiment
Next, the fifth embodiment will be described. As shown in FIG. 13, in the fifth embodiment, the Ping-Pong auto-zero amplifier 100 is configured using the auto-zero amplifiers 1A to 1D described in the first to fourth embodiments. The Ping-Pong auto-zero amplifier 100 includes two auto-zero amplifiers 1A to 1D connected in parallel. The two auto-zero amplifiers 1A to 1D are connected in parallel and invert and amplify the input. When one of the two auto-zero amplifiers 1A to 1D is switched to the first calibration mode or the second calibration mode, the other is switched to the amplification mode. When one of the two auto-zero amplifiers 1A to 1D is switched to the amplification mode, the other is switched to the first calibration mode or the second calibration mode. This allows the Ping-Pong auto-zero amplifier 100 to constantly output a signal Vout in which the offset component and the low-frequency component are reduced.

Sixth Embodiment
Next, the sixth embodiment will be described. As shown in FIG. 14, in the sixth embodiment, a phase inversion auto-zero amplifier 101 is configured using the auto-zero amplifiers 1A to 1D described in the first to fourth embodiments. The phase inversion auto-zero amplifier 101 includes two auto-zero amplifiers 1A to 1D connected in parallel. The fifth embodiment differs from the sixth embodiment in that the input terminals of the two auto-zero amplifiers 1A to 1D are inverted and connected. That is, the positive input terminal of one of the two auto-zero amplifiers 1A to 1d is connected to the negative input terminal of the other, and the negative input terminal of one is connected to the positive input terminal of the other.

In the phase-inverting auto-zero amplifier 101, similarly to the Ping-Pong auto-zero amplifier 100, when one of the two auto-zero amplifiers 1A-1D is switched to the first calibration mode or the second calibration mode, the other is switched to the amplification mode. When one of the two auto-zero amplifiers 1A-1D is switched to the amplification mode, the other is switched to the first calibration mode or the second calibration mode. As a result, the phase-inverting auto-zero amplifier 101 constantly outputs a signal Vout with reduced offset components and low-frequency components, and the signal Vout is inverted every time the amplifier is switched from the amplification mode to the calibration mode.

Seventh Embodiment
Next, the seventh embodiment will be described. As shown in FIG. 15, in the seventh embodiment, an amplifier device 103 having two or more stages of amplifiers is configured using the Ping-Pong auto-zero amplifier 100 described in the fifth embodiment. The amplifier device 103 includes the Ping-Pong auto-zero amplifier 100 as an input stage, and an amplifier 104 that amplifies the output of the Ping-Pong auto-zero amplifier 100. The signal Vin input to the Ping-Pong auto-zero amplifier 100 is amplified by the Ping-Pong auto-zero amplifier 100 and the amplifier 104, and is output as a signal Vout. This configuration allows the amplifier device 103 to have high accuracy.

Eighth embodiment
Next, an eighth embodiment will be described. As shown in Fig. 16, in the eighth embodiment, a chopper stabilized amplifier 105 is configured using the Ping-Pong auto-zero amplifier 100 described in the fifth embodiment. The chopper stabilized amplifier 105 includes a chopper modulator 106, the Ping-Pong auto-zero amplifier 100, a chopper modulator 107, and an amplifier 108.

The chopper modulator 106 modulates the signal Vin to a high frequency band. The Ping-Pong auto-zero amplifier 100 amplifies and outputs the signal modulated by the chopper modulator 106. The chopper modulator 107 demodulates the signal components of the output of the Ping-Pong auto-zero amplifier 100 to a low frequency band, and modulates the offset components and low frequency noise components to a high frequency band and outputs them. The amplifier 108 amplifies the output of the chopper modulator 107 and outputs it as a signal Vout. In this way, by using the Ping-Pong auto-zero amplifier 100 described in the fifth embodiment, it is possible to improve the accuracy of the chopper stabilized amplifier 105.

Ninth embodiment
Next, a ninth embodiment will be described. As shown in Fig. 17, in the ninth embodiment, a chopper stabilized amplifier 109 having three or more stages is configured using the Ping-Pong auto-zero amplifier 100 described in the fifth embodiment and the phase inversion auto-zero amplifier 101 described in the sixth embodiment. The chopper stabilized amplifier 109 includes a chopper modulator 110, a transconductance amplifier 111, a chopper output circuit 112, an amplifier 113, and a transconductance amplifier 114.

The chopper modulator 110 modulates the signal Vin to a high frequency band. The transconductance amplifier 111 amplifies and outputs the signal modulated by the chopper modulator 110. The chopper output circuit 112 is configured, for example, as shown in FIG. 18. As shown in the figure, the chopper output circuit 112 has a chopper modulator 115 and a noise reduction loop circuit 116. The chopper modulator 115 demodulates the signal components of the output of the transconductance amplifier 111 to a low frequency band, and modulates the offset components and low frequency noise components to a high frequency band and outputs them.

The noise reduction loop circuit 116 extracts the offset component of the transconductance amplifier 111 and negatively feeds back the extracted offset component to the output of the transconductance amplifier 111. This noise reduction loop circuit 116 reduces the offset component and low-frequency noise components generated in the transconductance amplifier 111, thereby reducing the ripple noise contained in the output of the chopper output circuit 112 (see Figures 20(B) and 20(C)).

In the example shown in FIG. 18, the noise reduction loop circuit 116 has a configuration including the Ping-Pong auto-zero amplifier 100 described in the fifth embodiment that amplifies the input of the noise reduction loop circuit 116, a filter circuit 117 that reduces high-frequency signal components in the output of the Ping-Pong auto-zero amplifier 100, and a transconductance amplifier 118 that amplifies the output of the filter circuit 117. The output of the transconductance amplifier 111 is input to the Ping-Pong auto-zero amplifier 100. The filter circuit 117 has the function of amplifying low-frequency signal components and reducing high-frequency signal components in the output of the Ping-Pong auto-zero amplifier 100. The filter circuit 117 can reduce high-frequency signal components and feed back the offset components of the amplifier.

The chopper output circuit 112 may also be configured, for example, as shown in FIG. 19. As shown in the figure, the chopper output circuit 112 has a chopper modulator 115 and a ripple calibration circuit 119. The chopper modulator 115 is similar to the chopper modulator 115 shown in FIG. 18.

The ripple calibration circuit 119 has an input connected to the output of the chopper modulator 115 and an output connected to the input of the chopper modulator 115. The ripple calibration circuit 119 is a circuit that extracts high-frequency noise components (ripple noise) from the output of the chopper modulator 115, modulates the extracted ripple noise to an offset component, and negatively feeds back the modulated offset component to the input of the chopper modulator 115. The ripple calibration circuit 119 reduces the offset component contained in the input of the chopper modulator 115, and can reduce the ripple noise contained in the output of the chopper modulator 115 (see Figures 20 (B) and (C)).

In this embodiment, the ripple calibration circuit 119 includes a high-pass filter 120 that reduces low-frequency noise components input to the ripple calibration circuit 119 and detects ripple noise, a phase-inverting auto-zero amplifier 101 that demodulates the ripple noise at the output of the high-pass filter 120 into low-frequency components and modulates it into an offset component, a filter circuit 121 that reduces high-frequency components at the output of the phase-inverting auto-zero amplifier 101, and a transconductance amplifier 122 that amplifies the output of the filter circuit 121.

As shown in FIG. 17, amplifier 113 amplifies the signal component output from chopper output circuit 112. In this embodiment, the output of amplifier 113 becomes the output terminal of chopper stabilized amplifier 109, and signal Vout is output. Amplifier 113 has transconductance amplifier 123, amplifier 124, and phase compensation circuit 125 that performs phase compensation for amplifiers 123 and 124. The input of amplifier 124 is connected to the output of transconductance amplifier 123, and the output of amplifier 124 becomes the output of amplifier 113, i.e., the output terminal of chopper stabilized amplifier 109.

The phase compensation circuit 125 is composed of capacitances Cc1 to Cc3. Capacitor Cc1 is connected between the input and output of amplifier 124. Capacitor Cc2 is connected between the inverting input of transconductance amplifier 123 and the output of amplifier 124. Capacitor Cc3 is connected between the non-inverting input of transconductance amplifier 123 and ground.

The transconductance amplifier 114 is connected between the input terminal and the input of the amplifier 124, and functions as a feed-forward amplifier. In this way, by using the Ping-Pong auto-zero amplifier 100 described in the fifth embodiment, it is possible to improve the accuracy of the three or more stage chopper stabilized amplifier 109.

The present invention is not limited to the above-described embodiment, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, location, etc. of each component in the above-described embodiment are arbitrary as long as they can achieve the present invention, and are not limited.

For example, the output stage amplifier 113 shown in the ninth embodiment described above is composed of a transconductance amplifier 123 and an amplifier 124, but is not limited to this. For example, as shown in FIG. 21, two transconductance amplifiers 126 and 127 may be provided instead of the transconductance amplifier 123. In the example shown in FIG. 21, the phase compensation circuit 125 is composed of two capacitances Cc4 and Cc5. The capacitance Cc4 is connected between the inverting input and the positive output of the transconductance amplifier 126. The capacitance Cc5 is connected between the non-inverting input and the negative output of the transconductance amplifier 126.

In addition, according to the first to third embodiments described above, two switches S11, S12 are provided to separate the input and input terminal of the transconductance amplifier A1, and two switches S21, S22 are provided to short-circuit the input of the transconductance amplifier A1, but this is not limited to this. As in the conventional example shown in FIG. 22, one switch S1 may be provided to separate the input and input terminal of the transconductance amplifier A1, and one switch S2 may be provided to short-circuit the input of the transconductance amplifier A1.

1A to 1D Auto-zero amplifier 2 First calibration circuit 3 Second calibration circuit A1 Transconductance amplifier (amplifier)
A2 Transconductance amplifier (first calibration amplifier)
A3 Transconductance amplifier (second calibration amplifier)
C11, C12 Sampling capacitance (first sampling capacitance)
C21, C22 Sampling capacitance (second sampling capacitance)
S6 Switch (first switch)
S71 switch (second switch)
S72 switch (third switch)

Claims (5)

a transconductance amplifier;
a first calibration circuit including a first sampling capacitor and a first calibration transconductance amplifier;
a second calibration circuit including a second sampling capacitor and a second calibration transconductance amplifier;
a first calibration mode in which a first calibration signal that reduces offset components and low-frequency noise components of the transconductance amplifier and the second calibration transconductance amplifier is sampled into the first sampling capacitor;
a second calibration mode in which a second calibration signal that reduces an offset component and a low-frequency component of the transconductance amplifier calibrated by the first calibration signal is sampled into the second sampling capacitor;
an auto-zero amplifier switchable between an amplification mode in which an offset component and a low-frequency noise component of the transconductance amplifier are reduced by the first calibration signal and the second calibration signal;
a control circuit that switches the auto-zero amplifier between the first calibration mode, the second calibration mode, and the amplification mode in this order, and repeats the switching;
the first sampling capacitor has one end connected to ground and the other end connected to the output of the transconductance amplifier;
the first calibration transconductance amplifier has an input connected to the other end of the first sampling capacitor and an output connected to the output of the transconductance amplifier;
the second sampling capacitor has one end connected to ground and the other end connected to the output of the transconductance amplifier;
the second calibration transconductance amplifier has an input connected to the other end of the second sampling capacitor and an output connected to the output of the transconductance amplifier;
Amplification device. 2. The amplifier according to claim 1,
the second calibration transconductance amplifier has an inverting input and a non-inverting input connected to the second sampling capacitor,
the second calibration circuit has a first switch that shorts the inverting input and the non-inverting input of the second calibration transconductance amplifier, and a second switch connected between either the inverting input or the non-inverting input of the second calibration transconductance amplifier and the second sampling capacitor.
Amplification device. 3. The amplifier according to claim 2,
a third switch connected between the other of the inverting input and the non-inverting input of the second calibration transconductance amplifier and the second sampling capacitor;
Amplification device. 3. The amplifier according to claim 2,
the second calibration transconductance amplifier, the first switch, and the second switch are each provided in two pieces;
one of the two second switches is connected between the inverting input of the second calibration transconductance amplifier and the second sampling capacitor;
the other of the two second switches is connected between the non-inverting input of the second calibration transconductance amplifier and the second sampling capacitor;
Amplification device. In the amplifier according to any one of claims 1 to 4,
the control circuit makes the time during which the second calibration mode is in effect longer than the time during which the first calibration mode is in effect;
Amplification device.

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