JP7623873B2 - Photodetection circuit and measuring device - Google Patents

Description

This disclosure relates to a photodetection circuit and a measurement device.

Patent document 1 discloses a multi-channel optical detection and ranging system. The system includes a plurality of active channels. Each active channel includes a photosensitive element arranged to be exposed to light and an analog front-end circuit that receives a signal from each photosensitive element. The system further includes at least one compensation channel and a processing unit. The compensation channel includes a compensation element that is substantially insensitive to light and an analog front-end circuit that receives a signal from the compensation element. The processing unit receives signals from the active channels and the compensation channel, derives a compensation signal from the signal received from the compensation channel, and compensates for crosstalk interference of the active channels and/or interference common to the analog front-end circuit using the compensation signal.

JP 2018-119954 A

As an example of a device that detects the incident position and timing of a light pulse using multiple photodiodes, there is LiDAR (Light Detection And Ranging). When multiple photodiodes are arranged in such a device, parasitic capacitance occurs at least between adjacent photodiodes and between adjacent output wirings. A part of the pulse current output from a certain photodiode may pass through this parasitic capacitance and be input to a circuit that detects the output current of other photodiodes. This phenomenon is called crosstalk. In such a case, when light is incident on a certain photodiode, it may be mistakenly recognized that a light pulse is also incident on other photodiodes at the same time. For example, in LiDAR, such a misrecognition can lead to the detection of an object that does not actually exist.

The present disclosure aims to provide a photodetection circuit capable of reducing crosstalk caused by at least one of the parasitic capacitance between photodiodes and the parasitic capacitance between output wiring, and a measurement device equipped with the photodetection circuit.

The light detection circuit according to one embodiment of the present disclosure includes a first photodiode and a second photodiode for detecting a light pulse, a first circuit element, a second circuit element, a first circuit, and a second circuit. The first circuit element has a capacitance between one end and the other end. One end of the first circuit element is electrically connected to the output end of the first photodiode. The second circuit element has a capacitance between one end and the other end. One end of the second circuit element is electrically connected to the output end of the second photodiode. The first circuit is electrically connected to the output end of the first photodiode via a first wiring and is electrically connected to the other end of the second circuit element. The first circuit generates a first signal according to the difference between the current received through the first wiring and the current received through the second circuit element. The second circuit is electrically connected to the output end of the second photodiode via a second wiring and is electrically connected to the other end of the first circuit element. The second circuit generates a second signal according to the difference between the current received through the second wiring and the current received through the first circuit element.

The photodetection circuit and measurement device disclosed herein can reduce crosstalk caused by at least one of the parasitic capacitance between photodiodes and the parasitic capacitance between output wiring.

FIG. 1 is a diagram illustrating a schematic configuration of a measurement apparatus according to an embodiment. FIG. 2 is a plan view of a photodetection circuit including a PD array and a TIA array. FIG. 3 is a diagram showing a schematic cross-sectional structure of the PD array. FIG. 4 is a circuit diagram showing the configuration of a photodetection circuit when the number of PDs in the PD array is two. 5A to 5G are diagrams each showing a schematic time waveform of each signal in the photodetector circuit according to an embodiment. FIG. 6 is a circuit diagram showing a configuration of a photodetection circuit of a comparative example. FIG. 7 is a diagram illustrating a schematic time waveform of each signal in the photodetection circuit of the comparative example. 8A and 8B are graphs showing simulation results regarding the operation of each photodetection circuit of the embodiment and the comparative example. FIG. 9 is a circuit diagram showing the configuration of a photodetection circuit when the number of PDs is three or more. FIG. 10 is a diagram for explaining the operation of the photodetection circuit. FIG. 11 is a circuit diagram showing a configuration of a photodetection circuit according to one modified example. FIG. 12 is a diagram for explaining the operation of the photodetection circuit. FIG. 13 is a circuit diagram showing the configuration of a photodetection circuit when the number of PDs is three or more. FIG. 14 is a diagram for explaining the operation of the photodetection circuit.

The light detection circuit according to one embodiment of the present disclosure includes a first photodiode and a second photodiode for detecting a light pulse, a first circuit element, a second circuit element, a first circuit, and a second circuit. The first circuit element has a capacitance between one end and the other end. One end of the first circuit element is electrically connected to the output end of the first photodiode. The second circuit element has a capacitance between one end and the other end. One end of the second circuit element is electrically connected to the output end of the second photodiode. The first circuit is electrically connected to the output end of the first photodiode via a first wiring and is electrically connected to the other end of the second circuit element. The first circuit generates a first signal according to the difference between the current received through the first wiring and the current received through the second circuit element. The second circuit is electrically connected to the output end of the second photodiode via a second wiring and is electrically connected to the other end of the first circuit element. The second circuit generates a second signal according to the difference between the current received through the second wiring and the current received through the first circuit element.

In this photodetection circuit, when a light pulse is incident on the first photodiode, the current output from the first photodiode is input to the first circuit through the first wiring, and a first signal corresponding to the light intensity of the light pulse is generated in the first circuit. At this time, the potential of the first wiring fluctuates slightly, so that a part of the current output from the first photodiode is input to the second circuit through the second wiring due to at least one of the parasitic capacitance between the first photodiode and the second photodiode and the parasitic capacitance between the first wiring and the second wiring. In a conventional photodetection circuit, this part of the current input to the second circuit is detected as crosstalk. However, in this photodetection circuit, another part of the current output from the first photodiode is input to the second circuit through the first circuit element. Then, a second signal corresponding to the difference between the current received as crosstalk through the second wiring and the current received through the second circuit element is generated in the second circuit. That is, at least a part of the component caused by the parasitic capacitance is offset in the second signal.

When an optical pulse is incident on the second photodiode, the current output from the second photodiode is input to the second circuit through the second wiring, and a second signal corresponding to the optical intensity of the optical pulse is generated in the second circuit. At this time, the potential of the second wiring fluctuates slightly, so that a part of the current output from the second photodiode is input to the first circuit through the first wiring due to at least one of the parasitic capacitance between the first photodiode and the second photodiode and the parasitic capacitance between the first wiring and the second wiring. In a conventional photodetection circuit, this part of the current input to the first circuit is detected as crosstalk. However, in this photodetection circuit, another part of the current output from the second photodiode is input to the first circuit through the second circuit element. Then, a first signal corresponding to the difference between the current received as crosstalk through the first wiring and the current received through the first circuit element is generated in the first circuit. That is, at least a part of the component caused by the parasitic capacitance is offset in the first signal.

In this way, this photodetection circuit can reduce crosstalk caused by at least one of the parasitic capacitance between the first photodiode and the second photodiode and the parasitic capacitance between the first wiring and the second wiring.

In the above-mentioned photodetection circuit, the first photodiode and the second photodiode may be monolithically formed on a common substrate. In this case, parasitic capacitance is likely to occur between the first photodiode and the second photodiode. Therefore, the above-mentioned configuration of the photodetection circuit is particularly effective.

In the above-mentioned photodetection circuit, the first wiring and the second wiring may have a portion disposed along each other. In this case, parasitic capacitance is likely to occur between the first wiring and the second wiring. Therefore, the above-mentioned configuration of the photodetection circuit is particularly effective.

In the above photodetection circuit, the capacitance of each of the first and second circuit elements may be equal to the sum of the parasitic capacitance between the first and second photodiodes and the parasitic capacitance between the first and second wirings. In this case, the magnitude of the current received through the first circuit element is approximately equal to the magnitude of the current received as crosstalk through the first wiring. Therefore, the crosstalk can be reduced to approximately zero.

In the above photodetection circuit, the capacitance of each of the first and second circuit elements may be smaller than twice the sum of the parasitic capacitance between the first and second photodiodes and the parasitic capacitance between the first and second wirings. In this case, crosstalk can be effectively reduced.

In the above photodetection circuit, the capacitance of each of the first and second circuit elements may be greater than 0.1 times the sum of the parasitic capacitance between the first and second photodiodes and the parasitic capacitance between the first and second wirings. In this case, crosstalk can be effectively reduced.

In each of the above cases, either the parasitic capacitance between the first photodiode and the second photodiode or the parasitic capacitance between the first wiring and the second wiring may be zero.

In the above-mentioned photodetection circuit, the capacitance of each of the first and second circuit elements may be set to a magnitude that generates a signal in the first circuit or the second circuit that is smaller than twice the sum of the crosstalk component caused by the parasitic capacitance between the first photodiode and the second photodiode and the crosstalk component caused by the parasitic capacitance between the first wiring and the second wiring. In this case, crosstalk can be effectively reduced.

In the above-mentioned photodetection circuit, the capacitance of each of the first and second circuit elements may be set to a magnitude that generates a signal in the first circuit or the second circuit that is greater than 0.1 times the sum of the crosstalk component caused by the parasitic capacitance between the first photodiode and the second photodiode and the crosstalk component caused by the parasitic capacitance between the first wiring and the second wiring. In this case, crosstalk can be effectively reduced.

In each of the above cases, either the crosstalk component caused by the parasitic capacitance between the first photodiode and the second photodiode or the crosstalk component caused by the parasitic capacitance between the first wiring and the second wiring may be zero.

In the above photodetection circuit, the first circuit may have a first transimpedance amplifier (TIA) that converts the current received through the first wiring into a first voltage signal, a second TIA that converts the current received through the second circuit element into a second voltage signal, and a circuit that generates a signal corresponding to the difference between the first and second voltage signals. The second circuit may have a third TIA that converts the current received through the second wiring into a third voltage signal, a fourth TIA that converts the current received through the first circuit element into a fourth voltage signal, and a circuit that generates a signal corresponding to the difference between the third and fourth voltage signals. For example, by having such a configuration in the first and second circuits, it is possible to generate a first signal corresponding to the difference between the current received through the first wiring and the current received through the second circuit element, and a second signal corresponding to the difference between the current received through the second wiring and the current received through the first circuit element.

The above-mentioned photodetection circuit may further include a third circuit element having a capacitance between one end and the other end. The first circuit may include a differential input type TIA, one input end of the TIA may be connected to the first photodiode via the first wiring, and the other input end may be connected to the other end of the second circuit element and one end of the third circuit element. The second circuit may include a differential input type TIA, one input end of the TIA may be connected to the second photodiode via the second wiring, and the other input end may be connected to the other end of the first circuit element and the other end of the third circuit element. For example, by having such a configuration in the first circuit and the second circuit, a first signal corresponding to the difference between the current received through the first wiring and the current received through the second circuit element, and a second signal corresponding to the difference between the current received through the second wiring and the current received through the first circuit element can be generated. In addition, the differential input type TIA has a property that the potential of the other input end also fluctuates under the influence of the potential fluctuation of one input end. For example, when a current is output from the first photodiode, the potential of one input terminal of the TIA of the first circuit fluctuates slightly, and as a result, the potential of the other input terminal of the TIA of the first circuit also fluctuates. As a result, the crosstalk current passes through the second circuit element and is input to one input terminal of the TIA of the second circuit. Even in such a case, at least a portion of the crosstalk current can be offset by connecting the other input terminals of the TIAs of the first and second circuits via the third circuit element.

A measurement device according to an embodiment of the present disclosure is a device that irradiates a measurement object with pulsed laser light, and measures the distance and direction to the measurement object based on the incident position of the reflected light from the measurement object and the time difference between the irradiation of the laser light and the incidence of the reflected light. This measurement device includes a light emitting unit that emits laser light, and a light detecting unit that detects the reflected light. The light detecting unit has any of the light detecting circuits described above. According to this measurement device, since the light detecting unit has any of the light detecting circuits described above, crosstalk caused by at least one of the parasitic capacitance between photodiodes and the parasitic capacitance between output wiring can be reduced. Therefore, it is possible to reduce erroneous detection of an object or shape that does not actually exist.

Below, an embodiment of a light detection circuit and a measurement device according to the present disclosure will be described in detail with reference to the attached drawings. Note that in the description of the drawings, the same elements are given the same reference numerals, and duplicate descriptions will be omitted.

FIG. 1 is a schematic diagram showing the configuration of a measurement device 1 according to an embodiment of the present disclosure. The measurement device 1 irradiates a measurement object A with a pulsed laser light PL1, and measures the distance and direction to the measurement object A based on the incident position of the reflected light PL2 from the measurement object A and the time difference between the irradiation of the laser light PL1 and the incidence of the reflected light PL2. As shown in FIG. 1, the measurement device 1 of this embodiment includes a light emitting unit 10 that emits the laser light PL1, a light detecting unit 20 that detects the reflected light PL2, and a controller 8.

The light emitting unit 10 has a driver 11, a pulsed laser 12, and an emission optical system 13. The driver 11 is electrically connected to the controller 8, and periodically generates a pulsed driving current to the pulsed laser 12 based on an instruction signal from the controller 8. The driver 11 is configured by an electronic circuit including, for example, a transistor. The pulsed laser 12 is electrically connected to the current output terminal of the driver 11, and receives the driving current output from the driver 11. The pulsed laser 12 periodically outputs a pulsed laser light PL1 according to this driving current. The wavelength of the laser light PL1 is, for example, 300 nm or more and 1700 nm or less, and the pulse half-width of the laser light PL1 is, for example, 0.1 nsec or more and 100 nsec or less. The pulsed laser 12 is, for example, a laser diode. The emission optical system 13 is optically coupled to the pulsed laser 12. The light emission optical system 13 scans the laser light PL1 output from the pulsed laser 12, irradiating the laser light PL1 over a wide range.

The light detection unit 20 detects the reflected light PL2 from the measurement object A. The light detection unit 20 has a light receiving optical system 21, a photodiode (PD) array 22, a transimpedance amplifier (TIA) array 23, and an A/D converter array 24. The light receiving optical system 21 receives the reflected light PL2, and introduces the reflected light PL2 into one of N (N is an integer equal to or greater than 2; FIG. 1 illustrates the case where N=4) optical paths depending on the incident position of the reflected light PL2.

The PD array 22 includes N PDs 22a. Each PD 22a is, for example, a PN-type photodiode or an avalanche photodiode (APD). Each PD 22a is optically coupled to a corresponding optical path of the light receiving optical system 21. Each PD 22a generates a current signal according to the optical intensity of the reflected light PL2 input from the corresponding optical path, and outputs this current signal from an output end. The N PDs 22a are arranged in one or two rows along a predetermined direction (for example, the scanning direction of the laser light PL1).

The TIA array 23, together with the PD array 22, constitutes the photodetection circuit 2. The TIA array 23 includes N TIAs 23a. The input terminal of each TIA 23a is electrically connected to the output terminal of the corresponding PD 22a, and receives a current signal from the corresponding PD 22a. Each TIA 23a converts the current signal received from the corresponding PD 22a into a voltage signal, and outputs the voltage signal from its output terminal. The A/D converter array 24 includes N A/D converters 24a. The input terminal of each A/D converter 24a is electrically connected to the output terminal of the corresponding TIA 23a. Each A/D converter 24a converts the voltage signal received from the corresponding TIA 23a into a digital signal, and outputs the digital signal from its output terminal.

The controller 8 is, for example, a computer including a CPU and memory, and realizes various functions by the CPU reading and executing programs stored in the memory. The controller 8 is electrically connected to the driver 11 and provides instruction signals to the driver 11. The controller 8 is also electrically connected to the output terminals of the N A/D converters 24a and receives digital signals output from each A/D converter 24a. The controller 8 detects the incident position of the reflected light PL2 in the light receiving optical system 21 based on which A/D converter 24a the controller 8 has received a digital signal from, and measures the direction in which the measurement object A exists from this incident position. The controller 8 also calculates the distance from the measurement device 1 to the measurement object A based on the time from when the controller 8 provides an instruction signal to the driver 11 to when it receives the digital signal.

Figure 2 is a plan view of the photodetection circuit 2 including the PD array 22 and the TIA array 23. As described above, the PD array 22 has N PDs 22a (FIG. 2 illustrates an example in which N=4). In the illustrated example, the N PDs 22a are arranged in a row. The TIA array 23 is arranged in a row with a gap between them in a direction intersecting the arrangement direction of the PDs 22a relative to the PD array 22. The input terminals of the TIAs 23a of the TIA array 23 are electrically connected to the output terminals of the corresponding PDs 22a via wires 25. The N wires 25 are arranged in a row in the arrangement direction of the PDs 22a and extend along a direction intersecting the arrangement direction of the PDs 22a. In other words, the N wires 25 are arranged along each other.

Figure 3 is a diagram showing a schematic cross-sectional structure of the PD array 22 when the PD 22a is an APD. As shown in Figure 3, the N PDs 22a are monolithically formed on a common substrate 221. Specifically, the PD array 22 has a common substrate 221, a semiconductor layer 222 of a first conductivity type formed on the common substrate 221, N semiconductor regions 223 of the first conductivity type formed in the semiconductor layer 222, N semiconductor regions 224 of a second conductivity type formed in the semiconductor layer 222, an electrode 225, and N electrodes 226. Each semiconductor region 224 is disposed on each semiconductor region 223 and contacts each semiconductor region 223 to form a pn junction. In one example, the common substrate 221 is a high concentration p type, the semiconductor layer 222 is a low concentration p type, the semiconductor region 223 is a high concentration p type, and the semiconductor region 224 is a high concentration n type. Each pair of one semiconductor region 223 and one semiconductor region 224 constitutes PD 22a. Electrode 225 is provided on the rear surface of common substrate 221 and forms an ohmic junction with the rear surface of common substrate 221. Each electrode 226 is provided on each semiconductor region 224 and forms an ohmic junction with each semiconductor region 224.

Figure 4 is a circuit diagram showing the configuration of a photodetection circuit 2A when the number of PDs 22a in the PD array 22 is two (i.e., N=2), as an example of the photodetection circuit 2. As shown in Figure 4, the photodetection circuit 2A includes two PDs 22a(1) and PD22a(2), wires 25(1) and 25(2), a parasitic capacitance 26, circuit elements 27(1) and 27(2), two signal generating circuits 28(1) and 28(2), and a bias power supply 41. PD22a(1) and PD22a(2) are the first photodiode and the second photodiode, respectively, in this embodiment. Wire 25(1) and wire 25(2) are the first wiring and the second wiring, respectively, in this embodiment. Circuit element 27(1) and circuit element 27(2) are the first circuit element and the second circuit element, respectively, in this embodiment.

The signal generating circuit 28(1) is the first circuit in this embodiment, and the signal generating circuit 28(2) is the second circuit in this embodiment. The signal generating circuit 28(1) has single-ended input type TIAs 23a(1) and 23b(1) and a differential amplifier circuit 28a(1). The signal generating circuit 28(2) has single-ended input type TIAs 23a(2) and 23b(2) and a differential amplifier circuit 28a(2). The TIAs 23a(1) and TIA 23b(1) are the first and second TIAs, respectively, in this embodiment. The TIAs 23a(2) and TIA 23b(2) are the third and fourth TIAs, respectively, in this embodiment.

The negative electrode of the bias power supply 41 is connected to each anode of PD22a(1) and PD22a(2) (or each cathode if PD22a(1) and PD22a(2) are PIN type). The positive electrode of the bias power supply 41 is connected to the ground potential line (reference potential line). The bias power supply 41 supplies a negative bias voltage to PD22a(1) and PD22a(2). The anodes of PD22a(1) and PD22a(2) are connected to each other via wiring with substantially zero resistance for connection to the bias power supply 41. The output end of PD22a(1) is connected to the input end of TIA23a(1) via wire 25(1). The output end of PD22a(2) is connected to the input end of TIA23a(2) via wire 25(2).

Parasitic capacitance 26 is a parasitic capacitance that occurs between the input terminal of TIA 23a(1) and the input terminal of TIA 23a(2). The magnitude of parasitic capacitance 26 is approximately equal to the sum (C1+C2) of parasitic capacitance C1 between PD22a(1) and PD22a(2) and parasitic capacitance C2 between wire 25(1) and wire 25(2). Parasitic capacitance C1 between PD22a(1) and PD22a(2) occurs mainly due to capacitive coupling between adjacent PD22a(1) and PD22a(2) via common substrate 221 and semiconductor layer 222 shown in FIG. 3. Parasitic capacitance C2 between wire 25(1) and wire 25(2) occurs mainly due to adjacent wire 25(1) and wire 25(2) being arranged along (parallel to) each other as shown in FIG. 2.

The circuit elements 27(1) and 27(2) are capacitive circuit elements. The capacitance of the circuit elements 27(1) and 27(2) is very small, for example, in the range of 10 fF to 200 fF. The circuit elements 27(1) and 27(2) may be capacitive elements such as capacitors having very small capacitance, silicon capacitors formed on a silicon substrate, two conductive films arranged on a wiring substrate with an insulating film between them, or two conductive lines adjacent to each other with a small gap between them. There are no limitations on the configuration of the circuit elements 27(1) and 27(2) as long as the configuration can realize a very small capacitance. The circuit elements 27(1) and 27(2) are formed on the circuit substrate of the TIA array 23, for example.

It is preferable that each capacitance of the circuit element 27(1) and the circuit element 27(2) is smaller than twice the sum of the parasitic capacitance between PD22a(1) and PD22a(2) and the parasitic capacitance between wire 25(1) and wire 25(2). It is also preferable that each capacitance of the circuit element 27(1) and the circuit element 27(2) is larger than 0.1 times the sum of the parasitic capacitance between PD22a(1) and PD22a(2) and the parasitic capacitance between wire 25(1) and wire 25(2). In one example, each capacitance of the circuit element 27(1) and the circuit element 27(2) is equal to the sum of the parasitic capacitance between PD22a(1) and PD22a(2) and the parasitic capacitance between wire 25(1) and wire 25(2). In one example, the capacitance values of the circuit element 27(1) and the circuit element 27(2) are equal to each other.

The sum of the parasitic capacitance between PD22a(1) and PD22a(2) and the parasitic capacitance between wire 25(1) and wire 25(2) can be obtained, for example, by measurement. In this case, the parasitic capacitance may be measured for each individual measurement device 1 manufactured, or the parasitic capacitance of several representative measurement devices 1 may be measured and the average value may be applied to the other measurement devices 1.

One end of the circuit element 27(1) is electrically connected to the output end of the PD22a(1). In the illustrated example, one end of the circuit element 27(1) is connected to the output end of the PD22a(1) via the wire 25(1), but one end of the circuit element 27(1) may be connected to the output end of the PD22a(1) without via the wire 25(1). The other end of the circuit element 27(1) is electrically connected to the input end of the TIA23b(2).

One end of the circuit element 27(2) is electrically connected to the output end of the PD22a(2). In the illustrated example, one end of the circuit element 27(2) is connected to the output end of the PD22a(2) via the wire 25(2), but one end of the circuit element 27(2) may be connected to the output end of the PD22a(2) without via the wire 25(2). The other end of the circuit element 27(2) is electrically connected to the input end of the TIA23b(1).

The signal generating circuit 28(1) is electrically connected to the output end of the PD 22a(1) via the wire 25(1) and is also electrically connected to the other end of the circuit element 27(2). The signal generating circuit 28(1) generates an output signal Vout1 (first signal), which is a voltage signal corresponding to the difference between the current received through the wire 25(1) and the current received through the circuit element 27(2).

TIA 23a(1) is one of the N TIAs 23a described above. TIA 23a(1) converts the current received through wire 25(1) into a voltage signal Vtp1 (first voltage signal). The output terminal of TIA 23a(1) is connected to the positive input terminal of differential amplifier circuit 28a(1). TIA 23b(1) is a TIA provided separately from the N TIAs 23a described above. TIA 23b(1) converts the current received through circuit element 27(2) into a voltage signal Vtn1 (second voltage signal). The output terminal of TIA 23b(1) is connected to the negative input terminal of differential amplifier circuit 28a(1). The differential amplifier circuit 28a(1) outputs an output signal Vout1 that corresponds to (for example, is proportional to) the difference between the voltage signal Vtp1 output from the TIA 23a(1) and the voltage signal Vtn1 output from the TIA 23b(1). Note that the TIA 23b(1) and the differential amplifier circuit 28a(1) may be built into the TIA array 23, or may be provided separately from the TIA array 23.

The signal generating circuit 28(2) is electrically connected to the output end of the PD 22a(2) via the wire 25(2) and is also electrically connected to the other end of the circuit element 27(1). The signal generating circuit 28(2) generates an output signal Vout2 (second signal), which is a voltage signal corresponding to the difference between the current received through the wire 25(2) and the current received through the circuit element 27(1).

TIA23a(2) is another of the N TIAs 23a described above. TIA23a(2) converts the current received through wire 25(2) into a voltage signal Vtp2 (third voltage signal). The output terminal of TIA23a(2) is connected to the positive input terminal of differential amplifier circuit 28a(2). TIA23b(2) is a TIA provided separately from the N TIAs 23a described above. TIA23b(2) converts the current received through circuit element 27(1) into a voltage signal Vtn2 (fourth voltage signal). The output terminal of TIA23b(2) is connected to the negative input terminal of differential amplifier circuit 28a(2). The differential amplifier circuit 28a(2) outputs an output signal Vout2 that corresponds to (for example, is proportional to) the difference between the voltage signal Vtp2 output from the TIA 23a(2) and the voltage signal Vtn2 output from the TIA 23b(2). Note that the TIA 23b(2) and the differential amplifier circuit 28a(2) may be built into the TIA array 23, or may be provided separately from the TIA array 23.

The effect of the photodetection circuit 2A shown in FIG. 4 will be described together with the problems of the photodetection circuit of the comparative example. FIG. 6 is a circuit diagram showing the configuration of the photodetection circuit 100 of the comparative example. The photodetection circuit 100 has PD22a(1) and PD22a(2), TIA23a(1) and TIA23a(2), wires 25(1) and 25(2), parasitic capacitance 26, and bias power supply 41, but does not have circuit elements 27(1), 27(2), TIA23b(1), TIA23b(2), differential amplifier circuit 28a(1), and differential amplifier circuit 28a(2) shown in FIG. 4. The connection relationship of PD22a(1), PD22a(2), TIA23a(1), TIA23a(2), wires 25(1), wires 25(2), parasitic capacitance 26, and bias power supply 41 is the same as in this embodiment.

Figure 7 is a diagram showing the time waveforms of (a) current Jin1 output from PD22a(1), (b) output signal Vout1 output from TIA23a(1), and (c) output signal Vout2 output from TIA23a(2) in the photodetector circuit 100. When an optical pulse is incident on PD22a(1), pulse P1 contained in current Jin1 output from PD22a(1) is input to TIA23a(1) through wire 25(1), and output signal Vout1 containing pulse P3 corresponding to the optical intensity of the optical pulse is generated in TIA23a(1). At this time, the potential of wire 25(1) fluctuates slightly. Therefore, a portion of the current Jin1 output from PD 22a(1) passes through parasitic capacitance 26 and wire 25(2) and is input to TIA 23a(2), which generates output signal Vout2 including crosstalk waveform P6. Crosstalk waveform P6 is, for example, a differentiated waveform of pulse P1.

Figure 5 is a diagram showing schematic time waveforms of (a) current Jin1 output from PD22a(1), (b) output voltage Vtp1 output from TIA23a(1), (c) output voltage Vtn1 output from TIA23b(1), (d) output signal Vout1 output from differential amplifier circuit 28a(1), (e) output voltage Vtp2 output from TIA23a(2), (f) output voltage Vtn2 output from TIA23b(2), and (g) output signal Vout2 output from differential amplifier circuit 28a(2) in the photodetector circuit 2A of this embodiment.

In the photodetection circuit 2A of this embodiment, when an optical pulse is incident on the PD 22a(1), the PD 22a(1) outputs a current Jin1 including a pulse P1 (FIG. 5(a)). This current Jin1 including the pulse P1 is input to the TIA 23a(1) of the signal generation circuit 28(1) through the wire 25(1). Then, the TIA 23a(1) generates a voltage signal Vtp1 including a pulse P2 corresponding to the optical intensity of the optical pulse (FIG. 5(b)). On the other hand, since no current including a pulse is input to the TIA 23b(1) of the signal generation circuit 28(1), the voltage signal Vtn1 output from the TIA 23b(1) does not include a pulse (FIG. 5(c)). As a result, the differential amplifier circuit 28a(1) outputs an output signal Vout1 including a pulse P3 corresponding to the optical intensity of the optical pulse (FIG. 5(d)).

At this time, the potential of the wire 25(1) fluctuates slightly. Therefore, a part of the current Jin1 output from the PD 22a(1) is input to the TIA 23a(2) of the signal generating circuit 28(2) through the parasitic capacitance 26 and the wire 25(2). Then, in the TIA 23a(2), a voltage signal Vtp2 including a crosstalk waveform P4 is generated ((e) of FIG. 5). Meanwhile, another part of the current output from the PD 22a(1) is input to the TIA 23b(2) of the signal generating circuit 28(2) through the circuit element 27(1). Then, in the TIA 23b(2), a voltage signal Vtn2 including a pseudo crosstalk waveform P5 is generated ((f) of FIG. 5). From the differential amplifier circuit 28a(2), an output signal Vout2 corresponding to the difference between these voltage signals Vtp2 and Vtn2 is output ((g) of FIG. 5). At this time, the crosstalk waveform P4 is offset or reduced by the pseudo crosstalk waveform P5, and no crosstalk waveform occurs or is small in the output signal Vout2.

The same is true when an optical pulse is incident on PD22a(2). That is, when an optical pulse is incident on PD22a(2), a current containing a pulse is output from PD22a(2). This current is input to TIA23a(2) of signal generating circuit 28(2) through wire 25(2). Then, in TIA23a(2), a voltage signal Vtp2 containing a pulse corresponding to the optical intensity of the optical pulse is generated. On the other hand, since a current containing a pulse is not input to TIA23b(2) of signal generating circuit 28(2), the voltage signal Vtn2 output from TIA23b(2) does not contain a pulse. As a result, an output signal Vout2 containing a pulse corresponding to the optical intensity of the optical pulse is output from differential amplifier circuit 28a(2).

At this time, the potential of the wire 25(2) fluctuates slightly. Therefore, a part of the current output from the PD 22a(2) is input to the TIA 23a(1) of the signal generating circuit 28(1) through the parasitic capacitance 26 and the wire 25(1). Then, in the TIA 23a(1), a voltage signal Vtp1 including a crosstalk waveform is generated. Meanwhile, another part of the current output from the PD 22a(2) is input to the TIA 23b(1) of the signal generating circuit 28(1) through the circuit element 27(2). Then, in the TIA 23b(1), a voltage signal Vtn1 including a pseudo crosstalk waveform is generated. From the differential amplifier circuit 28a(1), an output signal Vout1 according to the difference between these voltage signals Vtp1 and Vtn1 is output. At this time, the crosstalk waveform is offset or reduced by the pseudo crosstalk waveform, and the crosstalk waveform does not occur or is small in the output signal Vout1.

In this way, the photodetection circuit 2A of this embodiment can reduce crosstalk caused by the parasitic capacitance 26. In this embodiment, the parasitic capacitance 26 is the sum (C1+C2) of the parasitic capacitance C1 between PD22a(1) and PD22a(2) and the parasitic capacitance C2 between wire 25(1) and wire 25(2). However, for example, when PD22a(1) and PD22a(2) are not monolithically integrated but are separate elements, the parasitic capacitance 26 may be composed only of the parasitic capacitance C2 between wire 25(1) and wire 25(2). In that case, the capacitance of each of the circuit elements 27(1) and 27(2) is preferably smaller than twice the parasitic capacitance C2, preferably larger than 0.1 times the parasitic capacitance C2, and in one example, equal to the parasitic capacitance C2. Alternatively, for example, when wire 25(1) and wire 25(2) are not adjacent to each other or have no portions along each other, parasitic capacitance 26 may consist only of parasitic capacitance C1 between PD22a(1) and PD22a(2). In that case, the capacitance of each of circuit elements 27(1) and 27(2) is preferably smaller than twice the parasitic capacitance C1, preferably larger than 0.1 times the parasitic capacitance C1, and in one example, equal to the parasitic capacitance C1.

Figure 8 is a graph showing the results of a simulation of the operation of the photodetection circuit 2A of this embodiment and the photodetection circuit 100 of the comparative example when an optical pulse is input to PD22a(1). Figure 8(a) shows the time waveform of the output signal Vout1 including the pulse P3 corresponding to the optical pulse. Graph G1 of Figure 8(b) shows the time waveform of the output signal Vout2 in the photodetection circuit 2A of this embodiment. Graph G2 of Figure 8(b) shows the time waveform of the output signal Vout2 in the photodetection circuit 100 of the comparative example. Referring to graph G2 of Figure 8(b), it can be seen that a crosstalk waveform occurs in the output signal Vout2 in the photodetection circuit 100 of the comparative example. In contrast, referring to graph G1 of Figure 8(b), it can be seen that no crosstalk waveform occurs in the output signal Vout2 in the photodetection circuit 2A of this embodiment.

In this simulation, it is assumed that the capacitance of each of circuit elements 27(1) and 27(2) is equal to the parasitic capacitance. In reality, however, it is difficult to know the exact magnitude of the parasitic capacitance, and the magnitude of the parasitic capacitance differs slightly for each individual measuring device 1. However, even if the capacitance of each of circuit elements 27(1) and 27(2) differs from the parasitic capacitance, the crosstalk waveform can be reduced by canceling out at least a portion of the crosstalk waveform with the pseudo crosstalk waveform.

As in this embodiment, PD22a(1) and PD22a(2) may be monolithically formed on a common substrate 221. In this case, parasitic capacitance is likely to occur between PD22a(1) and PD22a(2). Therefore, the configuration of the photodetection circuit 2A in this embodiment is particularly effective.

As in this embodiment, wire 25(1) and wire 25(2) may have portions that are arranged along each other. In this case, parasitic capacitance is likely to occur between wire 25(1) and wire 25(2). Therefore, the configuration of the photodetection circuit 2A in this embodiment is particularly effective.

As in this embodiment, the capacitance of each of circuit elements 27(1) and 27(2) may be equal to the sum of the parasitic capacitance between PD22a(1) and PD22a(2) and the parasitic capacitance between wires 25(1) and 25(2). In this case, the magnitude of the current received through circuit element 27(1) is approximately equal to the magnitude of the current received as crosstalk through wire 25(1). Therefore, the crosstalk can be reduced to approximately zero.

As in this embodiment, the capacitance of each of the circuit elements 27(1) and 27(2) may be smaller than twice the sum of the parasitic capacitance between PD22a(1) and PD22a(2) and the parasitic capacitance between wire 25(1) and wire 25(2). In this case, crosstalk can be effectively reduced. Also, as in this embodiment, the capacitance of each of the circuit elements 27(1) and 27(2) may be larger than 0.1 times the sum of the parasitic capacitance between PD22a(1) and PD22a(2) and the parasitic capacitance between wire 25(1) and wire 25(2). In this case, crosstalk can be effectively reduced. Note that in each of these cases, either the parasitic capacitance between PD22a(1) and PD22a(2) or the parasitic capacitance between wire 25(1) and wire 25(2) may be zero.

In addition, the capacitance of each of the circuit elements 27(1) and 27(2) may be set to a magnitude that generates a signal (pseudo crosstalk waveform P5) in the differential amplifier circuit 28a(1) or 28a(2) that is smaller than twice the sum of the crosstalk components caused by the parasitic capacitance between PD22a(1) and PD22a(2) and the crosstalk components caused by the parasitic capacitance between wires 25(1) and 25(2) (i.e., the crosstalk waveform P4 shown in FIG. 5(e)). In this case, crosstalk can be effectively reduced. In addition, the capacitance of each of the circuit elements 27(1) and 27(2) may be set to a magnitude that generates a signal (pseudo crosstalk waveform P5) in the differential amplifier circuit 28a(1) or 28a(2) that is larger than 0.1 times the sum of the crosstalk components (crosstalk waveform P4). In this case, crosstalk can be effectively reduced. In each of these cases, either the crosstalk component caused by the parasitic capacitance between PD22a(1) and PD22a(2) or the crosstalk component caused by the parasitic capacitance between wire 25(1) and wire 25(2) may be zero.

As in this embodiment, the signal generating circuit 28(1) may have a TIA 23a(1) that converts the current received through the wire 25(1) into a voltage signal Vtp1, a TIA 23b(1) that converts the current received through the circuit element 27(2) into a voltage signal Vtn1, and a differential amplifier circuit 28a(1) that generates an output signal Vout1 according to the difference between the voltage signals Vtp1 and Vtn1. Also, the signal generating circuit 28(2) may have a TIA 23a(2) that converts the current received through the wire 25(2) into a voltage signal Vtp2, a TIA 23b(2) that converts the current received through the circuit element 27(1) into a voltage signal Vtn2, and a differential amplifier circuit 28a(2) that generates an output signal Vout2 according to the difference between the voltage signals Vtp2 and Vtn2. For example, by having such a configuration in signal generating circuits 28(1) and 28(2), it is possible to generate an output signal Vout1 corresponding to the difference between the current received through wire 25(1) and the current received through circuit element 27(2), and an output signal Vout2 corresponding to the difference between the current received through wire 25(2) and the current received through circuit element 27(1).

Figure 9 is a circuit diagram showing the configuration of the photodetection circuit 2B when the number N of PD22a is 3 or more (N=4 in the illustrated example). Even if the number of PD22a increases, the configuration related to each PD22a is the same as that of the photodetection circuit 2A shown in Figure 4. That is, this photodetection circuit 2B includes PD22a(1) to PD22a(N), wires 25(1) to 25(N), parasitic capacitances 26(1) to 26(N-1), circuit elements 27(1) to 27(N), signal generation circuits 28(1) to 28(N), and a bias power supply 41. However, there are two of each of the circuit elements 27(2) to 27(N-1).

If any of PD22a(1) to PD22a(N) is defined as the first photodiode in this embodiment, the PD adjacent to that PD corresponds to the second photodiode. In the following, the nth PD22a(n) will be described as the first photodiode. In this case, PD22a(n+1) and PD22a(n-1) (only PD22a(n+1) when n is 1, and only PD22a(n-1) when n is N) are the second photodiodes in this embodiment. Wire 25(n) is the first wiring in this embodiment, and wires 25(n+1) and 25(n-1) (only wire 25(n+1) when n is 1, and only wire 25(n-1) when n is N) are the second wiring in this embodiment. Circuit element 27(n) is the first circuit element in this embodiment, and circuit elements 27(n+1) and 27(n-1) (only circuit element 27(n+1) when n is 1, and only circuit element 27(n-1) when n is N) are the second circuit elements in this embodiment.

Signal generating circuit 28(n) is the first circuit in this embodiment, and signal generating circuits 28(n+1) and 28(n-1) (when n is 1, only signal generating circuit 28(n+1) and when n is N, only signal generating circuit 28(n-1)) are the second circuit in this embodiment. Signal generating circuit 28(n) has single-ended input type TIAs 23a(n) and 23b(n) and differential amplifier circuit 28a(n). TIA 23a(n) and TIA 23b(n) are the first TIA and second TIA, respectively, in this embodiment.

The negative electrode of the bias power supply 41 is connected to each anode of the PDs 22a(1) to 22a(N). The positive electrode of the bias power supply 41 is connected to the ground potential line (reference potential line). The bias power supply 41 supplies a negative bias voltage to the PDs 22a(1) to 22a(N). The anodes of the PDs 22a(1) to 22a(N) are connected to each other via wiring with substantially zero resistance for connection to the bias power supply 41. The output terminal of the PD 22a(n) is connected to the input terminal of the TIA 23a(n) via the wire 25(n).

Parasitic capacitance 26(n) is a parasitic capacitance that occurs between the input terminal of TIA 23a(n) and the input terminal of TIA 23a(n+1). The magnitude of parasitic capacitance 26(n) is approximately equal to the sum (C1+C2) of the parasitic capacitance C1 between PD22a(n) and PD22a(n+1) and the parasitic capacitance C2 between wire 25(n) and wire 25(n+1). The parasitic capacitance C1 between PD22a(n) and PD22a(n+1) occurs mainly due to the capacitive coupling of adjacent PD22a(n) and PD22a(n+1) via the common substrate 221 and semiconductor layer 222 shown in FIG. 3. The parasitic capacitance C2 between wire 25(n) and wire 25(n+1) occurs mainly because adjacent wires 25(n) and 25(n+1) are arranged along (parallel to) each other as shown in FIG. 2.

The circuit element 27(n) is a capacitive circuit element. The capacitance value and specific configuration of the circuit element 27(n) are the same as those of the circuit element 27(1) and the circuit element 27(2) shown in FIG. 4. One end of the circuit element 27(n) is electrically connected to the output end of the PD22a(n). In the illustrated example, one end of the circuit element 27(n) is connected to the output end of the PD22a(n) via the wire 25(n), but one end of the circuit element 27(n) may be connected to the output end of the PD22a(n) without the wire 25(n). When n is neither 1 nor N, the other end of one circuit element 27(n) is electrically connected to the input end of the TIA23b(n-1), and the other end of the other circuit element 27(n) is electrically connected to the input end of the TIA23b(n+1). The other end of the circuit element 27(1) is electrically connected to the input end of the TIA23b(2). The other end of circuit element 27(N) is electrically connected to the input end of TIA 23b(N-1).

The signal generating circuit 28(n) is electrically connected to the output end of the PD 22a(n) via the wire 25(n), and is also electrically connected to the other end of each of the circuit elements 27(n-1) and 27(n+1). The signal generating circuit 28(n) generates an output signal Vout(n) that corresponds to the difference between the current received through the wire 25(n) and the current received through the circuit element 27(n-1) or the current received through the circuit element 27(n+1).

TIA 23a(n) is one of the N TIAs 23a described above. TIA 23a(n) converts the current received through wire 25(n) into a voltage signal Vtp(n). The output terminal of TIA 23a(n) is connected to the positive input terminal of differential amplifier circuit 28a(n). TIA 23b(n) is a TIA provided separately from the N TIAs 23a described above. TIA 23b(n) converts the current received through circuit element 27(n-1) and the current received through circuit element 27(n+1) into a voltage signal Vtn(n). The output terminal of TIA 23b(n) is connected to the negative input terminal of differential amplifier circuit 28a(n). The differential amplifier circuit 28a(n) outputs an output signal Vout(n) that corresponds to (for example, is proportional to) the difference between the voltage signal Vtp(n) output from the TIA 23a(n) and the voltage signal Vtn(n) output from the TIA 23b(n). Note that the TIA 23b(n) and the differential amplifier circuit 28a(n) may be built into the TIA array 23 or may be provided separately from the TIA array 23.

The operation of the photodetection circuit 2B will be described with reference to FIG. 10. In the photodetection circuit 2B, when an optical pulse PL is incident on the PD 22a(n), a current Jin(n) containing a pulse is output from the PD 22a(n) (current Jin(2) is shown by a dashed line in FIG. 10 as a representative). This current Jin(n) is input to the TIA 23a(n) of the signal generation circuit 28(n) through the wire 25(n). Then, in the TIA 23a(n), a voltage signal Vtp(n) containing a pulse corresponding to the optical intensity of the optical pulse PL is generated (FIG. 5(b)). On the other hand, since a current containing a pulse is not input to the TIA 23b(n) of the signal generation circuit 28(n), the voltage signal Vtn(n) output from the TIA 23b(n) does not contain a pulse (FIG. 5(c)). As a result, the differential amplifier circuit 28a(n) outputs an output signal Vout(n) that includes a pulse corresponding to the light intensity of the light pulse PL (Figure 5(d)).

At this time, the potential of wire 25(n) fluctuates slightly. Therefore, when n is neither 1 nor N, a portion Ja(n) of the current Jin(n) output from PD 22a(n) passes through parasitic capacitance 26(n-1) and wire 25(n-1) and is input to TIA 23a(n-1) of signal generating circuit 28(n-1), and another portion Jb(n) of the current Jin(n) passes through parasitic capacitance 26(n) and wire 25(n+1) and is input to TIA 23a(n+1) of signal generating circuit 28(n+1) (representative portions Ja(2) and Jb(2) are shown by dashed lines in Figure 10). Then, in the TIA 23a(n-1), a voltage signal Vtp(n-1) including a crosstalk waveform is generated, and in the TIA 23a(n+1), a voltage signal Vtp(n+1) including a crosstalk waveform is generated (FIG. 5(e)). In addition, another part Jc(n) of the current Jin(n) output from the PD 22a(n) is input to the TIA 23b(n-1) of the signal generating circuit 28(n-1) through one of the two circuit elements 27(n), and another part Jd(n) of the current Jin(n) is input to the TIA 23b(n+1) of the signal generating circuit 28(n+1) through the other of the two circuit elements 27(n) (representatively, parts Jc(2) and Jd(2) are shown by dashed lines in FIG. 10). Then, in the TIA 23b(n-1), a voltage signal Vtn(n-1) including a pseudo crosstalk waveform is generated, and in the TIA 23b(n+1), a voltage signal Vtn(n+1) including a pseudo crosstalk waveform is generated (FIG. 5(f)). Then, the differential amplifier circuit 28a(n-1) outputs an output signal Vout(n-1) corresponding to the difference between the voltage signal Vtp(n-1) and the voltage signal Vtn(n-1), and the differential amplifier circuit 28a(n+1) outputs an output signal Vout(n+1) corresponding to the difference between the voltage signal Vtp(n+1) and the voltage signal Vtn(n+1) (FIG. 5(g)). At this time, the crosstalk waveform is offset or reduced by the pseudo crosstalk waveform, and the crosstalk waveform does not occur or is small in the output signals Vout(n-1) and Vout(n+1). When n=1, only the operations related to the signal generating circuit 28(n+1) are performed, and when n=N, only the operations related to the signal generating circuit 28(n-1) are performed. In this way, the photodetection circuit 2B can reduce crosstalk caused by the parasitic capacitances 26(1) to 26(N-1).

As shown in FIG. 10, the parasitic capacitance 26(2) is connected in series with the parasitic capacitance 26(3), so that a part of the current Jin(2) Jb(2) passes through the parasitic capacitance 26(2), and then a part of it Je(2) passes through the parasitic capacitance 26(3) and the wire 25(4) and is input to the TIA 23a(4). Also, since the circuit element 27(2) is connected in series with the circuit element 27(4), a part of the current Jin(2) Jd(2) passes through the circuit element 27(2), and then a part of it Jf(2) passes through the circuit element 27(4) and is input to the TIA 23a(4). However, since the impedance of the parasitic capacitance 26(2) and the circuit element 27(2) is much larger than the input impedance of the TIA 23a(4), the parts Je(2) and Jf(2) are small and can be ignored. The same is true for other parasitic capacitances connected in series, and other circuit elements connected in series.

In the photodetection circuit 2B shown in FIG. 9, the PDs 22a(1)-22a(N) may also be monolithically formed on a common substrate 221. In this case, parasitic capacitance is likely to occur between adjacent PDs. Therefore, the configuration of the photodetection circuit 2B is particularly effective. Furthermore, the wires 25(1)-25(N) may have portions that are arranged parallel to one another. In this case, parasitic capacitance is likely to occur between adjacent wires. Therefore, the configuration of the photodetection circuit 2B is particularly effective.
(Modification)

Figure 11 is a circuit diagram showing the configuration of a photodetection circuit 2C according to one variation of the above embodiment. This photodetection circuit 2C includes signal generation circuits 29(1) and 29(2) instead of the signal generation circuits 28(1) and 28(2) of the above embodiment. This photodetection circuit 2C also includes a circuit element 30 in addition to the other configurations of the above embodiment. The other configurations are the same as those of Figure 4 of the above embodiment, so detailed explanations will be omitted.

Signal generating circuits 29(1) and 29(2) are the first circuit and the second circuit, respectively, in this embodiment. Signal generating circuit 29(1) is electrically connected to the output end of PD22a(1) via wire 25(1) and is electrically connected to one end of circuit element 27(1). Signal generating circuit 29(1) is also electrically connected to the other end of circuit element 27(2) and is electrically connected to one end of circuit element 30. Signal generating circuit 29(1) generates an output signal Vout1 (first signal) according to the difference between the sum of the current flowing through wire 25(1) and the current flowing through circuit element 27(1) and the sum of the current flowing through circuit element 27(2) and the current flowing through circuit element 30.

In this modified example, the signal generating circuit 29(1) includes a TIA 23c(1), and the signal generating circuit 29(2) includes a TIA 23c(2). The TIAs 23c(1) and 23c(2) are differential input type TIAs. The TIAs 23c(1) and 23c(2) constitute the TIA array 23 in place of the TIAs 23a(1) and 23a(2) shown in FIG. 4. The positive input terminal of the TIA 23c(1) is connected to the PD 22a(1) via the wire 25(1). The negative input terminal of the TIA 23c(1) is connected to the other end of the circuit element 27(2). The positive input terminal of the TIA 23c(2) is connected to the PD 22a(2) via the wire 25(2). The inverted input terminal of TIA23c(2) is connected to the other terminal of circuit element 27(1).

The circuit element 30 is a third circuit element in this modified example. The circuit element 30 is a capacitive circuit element. The capacitance of the circuit element 30 is minute, like the capacitance of the circuit elements 27(1) and 27(2), and is, for example, in the range of 10 fF to 200 fF. The circuit element 30 may be a capacitive element such as a capacitor having a minute capacitance, a silicon capacitor formed on a silicon substrate, or may be composed of two conductive films arranged on a wiring substrate with an insulating film between them, or may be composed of two conductive lines adjacent to each other with a small gap between them. There are no other limitations on the configuration of the circuit element 30 as long as it is a configuration that can realize a minute capacitance. The circuit element 30 is formed, for example, on the circuit substrate of the TIA array 23.

The capacitance of the circuit element 30 is preferably less than twice the capacitance of the circuit elements 27(1) and 27(2). The capacitance of the circuit element 30 is preferably greater than 0.1 times the capacitance of the circuit elements 27(1) and 27(2). In one example, the capacitance of the circuit element 30 is equal to the capacitance of one or both of the circuit elements 27(1) and 27(2). One end of the circuit element 30, together with the other end of the circuit element 27(2), is electrically connected to the negative phase input terminal of the TIA 23c(1). The other end of the circuit element 30, together with the other end of the circuit element 27(1), is electrically connected to the negative phase input terminal of the TIA 23c(2).

The operation of the photodetection circuit 2C will be described with reference to FIG. 12. In the photodetection circuit 2C, when an optical pulse is incident on PD22a(1), a current Jin1 containing a pulse is output from PD22a(1). This current Jin1 passes through wire 25(1) and is input to the positive-phase input terminal of TIA23c(1). On the other hand, no current containing a pulse is input to the negative-phase input terminal of TIA23c(1). Therefore, an output signal Vout1 containing a pulse corresponding to the optical intensity of the optical pulse is output from TIA23c(1).

At this time, the potential of wire 25(1) fluctuates slightly. Therefore, a part Ja1 of the current Jin1 output from PD22a(1) is input to the positive-phase input terminal of TIA23c(2) through parasitic capacitance 26 and wire 25(2). Also, another part Jc1 of the current output from PD22a(1) is input to the negative-phase input terminal of TIA23c(2) through circuit element 27(1). An output signal Vout2 corresponding to the difference between the parts Ja1 and Jc1 is output from TIA23c(2). At this time, the crosstalk waveform contained in the part Ja1 is offset or reduced by the pseudo crosstalk waveform contained in the part Jc1. Therefore, no crosstalk waveform occurs or is small in the output signal Vout2.

The same is true when an optical pulse is incident on PD22a(2). That is, when an optical pulse is incident on PD22a(2), a current containing a pulse is output from PD22a(2). This current passes through wire 25(2) and is input to the positive-phase input terminal of TIA23c(2). On the other hand, no current containing a pulse is input to the negative-phase input terminal of TIA23c(2). Therefore, an output signal Vout2 containing a pulse corresponding to the optical intensity of the optical pulse is output from TIA23c(2).

At this time, the potential of wire 25(2) fluctuates slightly. Therefore, a part of the current output from PD22a(2) is input to the positive-phase input terminal of TIA23c(1) through parasitic capacitance 26 and wire 25(1). Another part of the current output from PD22a(2) is input to the negative-phase input terminal of TIA23c(1) through circuit element 27(2). An output signal Vout1 corresponding to the difference between these currents is output from TIA23c(1). At this time, the crosstalk waveform contained in the current input to the positive-phase input terminal of TIA23c(1) is offset or reduced by the pseudo crosstalk waveform contained in the current input to the negative-phase input terminal of TIA23c(1). Therefore, no crosstalk waveform occurs or is small in the output signal Vout1.

In this way, the photodetection circuit 2C of this modified example can reduce crosstalk caused by the parasitic capacitance 26.

Here, the differential input type TIA has a property that when a current is input to the positive-phase input terminal, the potential of the positive-phase input terminal fluctuates, but in addition, the potential of the negative-phase input terminal also fluctuates. That is, when a current is output from PD22a(1), the potential of the positive-phase input terminal of TIA23c(1) fluctuates slightly, but in addition, the potential of the negative-phase input terminal of TIA23c(1) also fluctuates. As a result, the crosstalk current Jg1 is input to the positive-phase input terminal of TIA23c(2) through circuit element 27(2). However, in this modified example, a circuit element 30 is connected between the negative-phase input terminal of TIA23c(1) and the negative-phase input terminal of TIA23c(2). Through this circuit element 30, the pseudo crosstalk current Ji1 is input to the negative-phase input terminal of TIA23c(2). Therefore, in TIA23c(2), the crosstalk current Jg1 is offset or reduced by the pseudo crosstalk current Ji1, so that the crosstalk waveform does not occur or is small in the output signal Vout2. The same is true when a current is output from PD22a(2). In this way, by connecting circuit element 30 between the negative phase input terminal of TIA23c(1) and the negative phase input terminal of TIA23c(2), at least a portion of the crosstalk current caused by circuit elements 27(1) and 27(2) can be offset.

Figure 13 is a circuit diagram showing the configuration of the photodetection circuit 2D when the number N of PD22a is 3 or more (N=4 in the illustrated example). Even if the number of PD22a increases, the configuration related to each PD22a is the same as that of the photodetection circuit 2C shown in Figure 11. That is, this photodetection circuit 2D includes PD22a(1) to PD22a(N), wires 25(1) to 25(N), parasitic capacitances 26(1) to 26(N-1), circuit elements 27(1) to 27(N), circuit elements 30(1) to 30(N-1), signal generation circuits 29(1) to 29(N), and a bias power supply 41. However, there are two of each of the circuit elements 27(2) to 27(N-1). Below, the differences from the photodetection circuit 2B (Figure 9) described above will be mainly explained.

If the nth PD 22a(n) is defined as the first photodiode, then the signal generating circuit 29(n) is the first circuit in this modified example, and the signal generating circuits 29(n-1) and 29(n+1) are the second circuit in this modified example. The signal generating circuit 29(n) is electrically connected to the output end of the PD 22a(n) via the wire 25(n), and is also electrically connected to the other ends of the circuit elements 27(n-1) and 27(n+1). The signal generating circuit 29(n) generates an output signal Vout(n) that corresponds to the difference between the current received through the wire 25(n) and the current received through the circuit element 27(n-1) or 27(n+1).

The signal generating circuits 29(1) to 29(N) each include a TIA 23c(1) to 23c(N). The TIAs 23c(1) to 23c(N) are differential input type TIAs. The TIAs 23c(1) to 23c(N) constitute the TIA array 23 in place of the TIAs 23a(1) to 23a(N) shown in FIG. 9. The positive input terminal of the TIA 23c(n) is connected to the PD 22a(n) via the wire 25(n). When n is neither 1 nor N, the negative input terminal of the TIA 23c(n) is connected to the other terminals of the circuit elements 27(n-1) and 27(n+1). The negative input terminal of the TIA 23c(1) is connected to the other terminal of the circuit element 27(2). The negative input terminal of TIA23c(N) is connected to the other terminal of circuit element 27(N-1).

Circuit elements 30(1) to 30(N) are the third circuit elements in this modified example. The capacitance values and specific configurations of circuit elements 30(1) to 30(N) are the same as those of circuit element 30 described above. One end of circuit element 30(n) is electrically connected to the negative phase input terminal of TIA 23c(n). The other end of circuit element 30(n) is electrically connected to the negative phase input terminal of TIA 23c(n+1).

The operation of the photodetection circuit 2D will be described with reference to FIG. 14. When an optical pulse is incident on PD22a(n), a current Jin(n) containing a pulse is output from PD22a(n) (current Jin(2) is shown by a dashed line in FIG. 14 as a representative). This current Jin(n) passes through wire 25(n) and is input to the positive-phase input terminal of TIA23c(n). On the other hand, no current containing a pulse is input to the negative-phase input terminal of TIA23c(n). Therefore, an output signal Vout(n) containing a pulse corresponding to the optical intensity of the optical pulse is output from TIA23c(n).

At this time, the potential of wire 25(n) fluctuates slightly. Therefore, a portion Ja(n) of the current Jin(n) output from PD22a(n) passes through parasitic capacitance 26(n-1) and wire 25(n-1) and is input to the positive phase input terminal of TIA23c(n-1). Also, another portion Jb(n) of the current Jin(n) output from PD22a(n) passes through parasitic capacitance 26(n) and wire 25(n+1) and is input to the positive phase input terminal of TIA23c(n+1). Note that in FIG. 14, the portions Ja(2) and Jb(2) are shown by dashed lines as representatives.

In addition, when n is neither 1 nor N, another part Jc(n) of the current Jin(n) output from PD22a(n) is input to the inverting input terminal of TIA23c(n-1) through one of the two circuit elements 27(n), and another part Jd(n) of the current Jin(n) is input to the inverting input terminal of TIA23c(n+1) through the other of the two circuit elements 27(n) (parts Jc(2) and Jd(2) are shown by dashed lines in FIG. 14 as representatives). An output signal Vout(n-1) corresponding to the difference between part Ja(n) and part Jc(n) is output from TIA23c(n-1). An output signal Vout(n+1) corresponding to the difference between part Jb(n) and part Jd(n) is output from TIA23c(n+1). At this time, the crosstalk waveforms contained in Ja(n) and Jb(n) are offset or reduced by the pseudo crosstalk waveforms contained in Jc(n) and Jd(n). Therefore, the crosstalk waveforms do not occur or are small in the output signals Vout(n-1) and Vout(n+1). When n=1, only the operation related to TIA23c(n+1) is performed among the above operations, and when n=N, only the operation related to TIA23c(n-1) is performed among the above operations. In this way, the photodetection circuit 2D can reduce crosstalk caused by the parasitic capacitances 26(1) to 26(N-1).

As mentioned above, the differential input type TIA has the property that the potential of one input terminal fluctuates in response to the influence of the potential fluctuation of the other input terminal. That is, when the current Jin(n) is output from PD22a(n), the potential of the positive phase input terminal of TIA23c(n) fluctuates slightly, but the potential of the negative phase input terminal of TIA23c(n) also fluctuates due to the influence. As a result, the crosstalk current Jg(n) is input to the positive phase input terminal of TIA23c(n-1) through circuit element 27(n-1), and the crosstalk current Jh(n) is input to the positive phase input terminal of TIA23c(n+1) through circuit element 27(n+1). However, in this modification, a circuit element 30(n-1) is connected between the negative phase input terminal of TIA 23c(n-1) and the negative phase input terminal of TIA 23c(n), and a circuit element 30(n) is connected between the negative phase input terminal of TIA 23c(n) and the negative phase input terminal of TIA 23c(n+1). Therefore, the pseudo crosstalk current Ji(n) passes through the circuit element 30(n-1) and is input to the negative phase input terminal of TIA 23c(n-1), and the pseudo crosstalk current Jj(n) passes through the circuit element 30(n) and is input to the negative phase input terminal of TIA 23c(n+1). Therefore, in the TIA 23c(n-1), the crosstalk current Jg(n) is offset or reduced by the pseudo crosstalk current Ji(n), and in the TIA 23c(n+1), the crosstalk current Jh(n) is offset or reduced by the pseudo crosstalk current Jj(n). Therefore, in the output signals Vout(n-1) and Vout(n+1), the crosstalk waveforms caused by the circuit elements 30(n-1) and 30(n) are not generated or are small. Note that, when n=1, only the operation related to the TIA 23c(n+1) is performed among the above operations, and when n=N, only the operation related to the TIA 23c(n-1) is performed among the above operations. In this way, by connecting circuit elements 30(n-1) and 30(n) between the negative phase input terminal of TIA 23c(n) and the negative phase input terminals of TIAs 23c(n-1) and 23c(n+1), respectively, it is possible to cancel at least a portion of the crosstalk current caused by circuit elements 27(n-1) and 27(n+1).

The photodetection circuit and measurement device according to the present disclosure are not limited to the above-described embodiments, and various other modifications are possible. For example, the signal generation circuit is not limited to the configurations described in the above embodiments and modifications, and various other configurations can be adopted as long as they can generate an output signal corresponding to the difference between one current and another current.

In addition, in the above embodiment, the voltage signal indicating the difference between the voltage signal Vtp(n) and the voltage signal Vtn(n) is generated by the differential amplifier circuit 28a(n), but the voltage signals Vtp(n) and Vtn(n) may be A/D converted and digitized, and the difference may then be calculated in the controller 8 or another digital device.

1...Measuring device, 2...Photodetection circuit, 2A to 2D...Photodetection circuits, 8...Controller, 10...Light emitting section, 11...Driver, 12...Pulse laser, 13...Light emitting optical system, 20...Photodetection section, 21...Light receiving optical system, 22...PD array, 23...TIA array, 23a, 23a(1) to 23a(N)...TIA, 23b(1) to 23b(N)...TIA, 23c(1) to 23c(N)...TIA, 24...A/D converter array, 24a...A/D converter, 25, 25(1) to 25(N)...Wires, 26, 26(1) to 26(N-1)...Parasitic capacitance, 27(1) to 27(N)...Circuit element, 28(1) 28(N), 29(1) to 29(N)...signal generation circuit, 28a(1) to 28a(N)...differential amplifier circuit, 30, 30(1) to 30(N)...circuit element, 41...bias power supply, 100...photodetection circuit, 221...common substrate, 222...semiconductor layer, 223, 224...semiconductor region, 225, 226...electrode, A...measurement object, PL...light pulse, PL1...laser light, PL2...reflected light, Vout1, Vout2, Vout(1) to Vout(N)...output signal, Vtp1, Vtn1, Vtp2, Vtn2, Vtp(1) to Vtp(N), Vtn(1) to Vtn(N)...voltage signal.

Claims (11)

a first photodiode and a second photodiode for detecting a light pulse;
a first circuit element having a capacitance between one end and the other end, the one end being electrically connected to an output end of the first photodiode;
a second circuit element having a capacitance between one end and the other end, the one end being electrically connected to the output end of the second photodiode;
a first circuit electrically connected to an output end of the first photodiode via a first wiring and electrically connected to the other end of the second circuit element, the first circuit generating a first signal according to a difference between a current received through the first wiring and a current received through the second circuit element;
a second circuit electrically connected to an output end of the second photodiode via a second wiring and electrically connected to the other end of the first circuit element, the second circuit generating a second signal corresponding to a difference between a current received through the second wiring and a current received through the first circuit element;
A photodetection circuit comprising: The photodetection circuit of claim 1, wherein the first photodiode and the second photodiode are monolithically formed on a common substrate. The photodetection circuit according to claim 1 or 2, wherein the first wiring and the second wiring have portions arranged along each other. The photodetection circuit according to any one of claims 1 to 3, wherein the capacitance of each of the first circuit element and the second circuit element is equal to the sum of the parasitic capacitance between the first photodiode and the second photodiode and the parasitic capacitance between the first wiring and the second wiring. The photodetection circuit according to any one of claims 1 to 3, wherein the capacitance of each of the first circuit element and the second circuit element is smaller than twice the sum of the parasitic capacitance between the first photodiode and the second photodiode and the parasitic capacitance between the first wiring and the second wiring. The photodetection circuit according to any one of claims 1 to 3 and 5, wherein the capacitance of each of the first circuit element and the second circuit element is greater than 0.1 times the sum of the parasitic capacitance between the first photodiode and the second photodiode and the parasitic capacitance between the first wiring and the second wiring. The photodetection circuit according to any one of claims 1 to 3, wherein the capacitance of each of the first circuit element and the second circuit element is set to a magnitude that generates in the first circuit or the second circuit a signal that is smaller than twice the sum of the crosstalk component caused by the parasitic capacitance between the first photodiode and the second photodiode and the crosstalk component caused by the parasitic capacitance between the first wiring and the second wiring. The photodetection circuit according to any one of claims 1 to 3 and 7, wherein the capacitance of each of the first circuit element and the second circuit element is set to a magnitude that generates in the first circuit or the second circuit a signal that is greater than 0.1 times the sum of a crosstalk component caused by a parasitic capacitance between the first photodiode and the second photodiode and a crosstalk component caused by a parasitic capacitance between the first wiring and the second wiring. The first circuit is
a first transimpedance amplifier that converts the current received through the first wiring into a first voltage signal;
a second transimpedance amplifier that converts the current received through the second circuit element into a second voltage signal;
a circuit for generating a signal corresponding to a difference between the first voltage signal and the second voltage signal;
having
The second circuit is
a third transimpedance amplifier that converts the current received through the second wiring into a third voltage signal;
a fourth transimpedance amplifier that converts the current received through the first circuit element into a fourth voltage signal;
a circuit for generating a signal corresponding to a difference between the third voltage signal and the fourth voltage signal;
The photodetection circuit according to claim 1 , further comprising: a third circuit element having a capacitance between one end and the other end;
the first circuit includes a differential input type transimpedance amplifier, one input end of the transimpedance amplifier is connected to the first photodiode via the first wiring, and the other input end is connected to the other end of the second circuit element and the one end of the third circuit element,
9. The photodetection circuit according to claim 1, wherein the second circuit includes a differential input type transimpedance amplifier, one input end of the transimpedance amplifier is connected to the second photodiode via the second wiring, and the other input end of the transimpedance amplifier is connected to the other end of the first circuit element and the other end of the third circuit element. 1. An apparatus for measuring a distance and a direction to a measurement object based on a position of incidence of reflected light from the measurement object and a time difference between the irradiation of the laser light and the incidence of the reflected light, comprising:
a light emitting unit that emits the laser light;
A light detection unit that detects the reflected light;
Equipped with
A measuring device, wherein the light detection section has the light detection circuit according to any one of claims 1 to 10.

Images