JP7623913B2 - Video Transmission Equipment - Google Patents

Description

The present invention relates to a video transmission device that receives a video signal composed of multiple split images obtained by splitting the video to be transmitted in the horizontal and vertical directions.

In recent years, video transmission using 4K video signals in the form of serial signals in SDI (Serial Digital Interface) format has come into practical use. FIG. 18 shows an example of the processing flow of a video transmission device according to the prior art. In a 4K video signal in the form of a serial signal in SDI format, the Square Division method (hereinafter, "SQD method") is a signal configuration in which 4K video is divided into four 2K videos of 3G-SDI at a speed of 3 Gbps. In the following, the SQD signals divided into four 2K videos are referred to as sub-images SDI(a) to SDI(d), respectively.

In the video transmission device, the signal level of each of the input sub-images SDI(a) to SDI(d) is corrected by the receiver (RCV) 100a of the SDI receiving circuit 100, and then the SDI decoding unit 100b converts (decodes) the serial signal into a parallel signal. In general, the four input signals of the video transmission device have non-uniform path lengths due to differences in wiring length inside and outside the device, resulting in a phase difference between the signals. Therefore, the TRS detection unit 101 detects a characteristic signal (TRS: Timing Reference Signal) that indicates the beginning reference of the horizontal line of the video signal from the decoded signal, and the subsequent phase correction unit 103 matches the phase between the four input signals under the control of the phase control unit 102. This makes it possible to treat the four divided signals as a single 4K signal within the device. In the following, the parallel signals that have undergone phase correction are referred to as sub-images (a) to (d), respectively. Each sub-image consists of 10-bit parallel signals, which are the luma and chroma streams.

In video processing within the video transmission device, the signal is first extracted to a video buffer, the video is processed in various ways, and then re-multiplexed onto the stream. At this time, the re-multiplexing process is timed based on the TRS, so that the signal is multiplexed into the correct position on the SDI. To verify that the re-multiplexing process is normal, it is usually necessary to input a test signal with a simple pattern from outside, observe the signal output from the video transmission device with a measuring instrument, and determine whether the signal code written is correct.

Here, the following are examples of prior art in the technical field related to the present invention. For example, Patent Document 1 discloses an invention in which a relay device receives video information transmitted from a source device and superimposes information related to the reception state on the black screen area of an SDTV signal during a relay operation in which the relay device receives the video information transmitted from a source device and transmits it to a destination device. Patent Document 2 discloses an invention in which first and second active video signals are extracted from first and second video signals with horizontal and vertical blanking areas removed, and a predetermined video signal of the second active video signal is inserted into a block having an empty space area among a plurality of blocks obtained by dividing the first active video signal.

JP 2008-193518 A JP 2008-244667 A

As described above, when transmitting an SDI signal in which 4K video has been converted into serial data, the video transmission device divides the video into 2K videos, processes the images, then combines the 2K videos and outputs them as an SDI signal for 4K video. However, as a result of dividing and combining the video signal and undergoing image processing, the display position of each divided video cannot be accurately restored, and there is a possibility that a shift in the display may occur. Furthermore, when the signal output from the video transmission device is restored to 4K video and checked, it is difficult to recognize the shift in the video at first glance, and it is not easy to determine whether or not there was a shift when combining based on the restored video alone.

The present invention was made in consideration of the above-mentioned conventional circumstances, and aims to make it possible to easily determine whether there is a misalignment during synthesis when restoring a signal output from a video transmission device to 4K video and checking it.

In order to achieve the above object, a video transmission device according to one aspect of the present invention is configured as follows.
That is, in a video transmission device to which a video signal composed of a plurality of divided videos obtained by dividing a video to be transmitted in the horizontal and vertical directions is input, a test signal of a predetermined color is drawn along the side corresponding to the boundary line dividing the video to be transmitted for each of the plurality of divided videos constituting the input video signal, and the video signal composed of the plurality of divided videos on which the test signal is drawn is output.

Here, in the video transmission device according to the present invention, the test signal drawn on each of the multiple split images may be multiple lines and the same number of lines.

In addition, in the video transmission device according to the present invention, test signals of different colors can be drawn on two opposing sides of two adjacent split images.

The video transmission device according to the present invention may also be configured to generate an enlarged test signal that enlarges the intersection of the horizontal and vertical composite boundaries based on the multiple split images on which the test signal is drawn, and further draw the enlarged test signal on one of the multiple split images.

According to the present invention, when a signal output from a video transmission device is restored to 4K video and checked, it becomes easy to determine whether there is a misalignment during synthesis.

FIG. 2 is a diagram illustrating an example of a processing flow of a video transmission device according to an embodiment of the present invention. FIG. 13 is a diagram showing an image of a test signal relative to a video signal. 5 is a diagram showing the relationship between parameters related to the test signal writing circuit and test signals; FIG. FIG. 2 is a diagram illustrating a configuration example of a horizontal test signal drawing circuit. FIG. 2 is a diagram illustrating a configuration example of a vertical test signal drawing circuit. FIG. 13 is a diagram for explaining a method of drawing a test signal for each sub-image. FIG. 11 is a diagram showing an example of parameters of each sub-image used in the horizontal and vertical test signal drawing circuit. FIG. 13 is a diagram illustrating an example of a timing chart of the horizontal/vertical test signal drawing circuit. FIG. 2 is a diagram illustrating a configuration example of an enlargement display circuit. FIG. 13 is a diagram showing the line width of the crossing portion of the test signal expanded four times; 11A and 11B are diagrams for explaining RAM input/output control when enlarging a crossing portion of a test signal; 13 is a diagram showing an example of the configuration of a write enable generation circuit and a write address generation circuit in a RAM write control unit of the enlargement display circuit. FIG. 13 is a diagram showing an example of the configuration of a read enable generation circuit in a RAM read control unit of the enlargement display circuit; FIG. 13 is a diagram showing an example of the configuration of a read address generation circuit in a RAM read control unit of the enlargement display circuit; FIG. FIG. 13 is a diagram illustrating an example of a timing chart of a read enable generation circuit. FIG. 13 is a diagram illustrating an example of a timing chart of a read address generation circuit. 11 is a diagram illustrating an example of the configuration of an enlarged signal generating unit and an enlarged test signal drawing unit. FIG. FIG. 1 is a diagram illustrating an example of a processing flow of a video transmission device according to a conventional technique. FIG. 13 is a diagram illustrating a screen configuration when dividing/combining 4K video in the SQD format. FIG. 2 is a diagram illustrating the mapping structure and data stream structure of each sub-image. 13 is a diagram for explaining bit assignments of XYZ and LN words and the frame structure of each sub-image. FIG.

A video transmission device according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an example of a processing flow of a video transmission device according to one embodiment of the present invention. An input/output circuit for a 4-split 2K video signal is implemented in each of the transmitter and receiver of the video transmission device, and generally, the drawing of a test signal is often processed on the transmitter side, and the display of the test signal is often processed on the receiver side. The video processing shown in FIG. 1 implements a common input/output interface for the transmitter and receiver, and is a common module that can be applied to either device.

The video transmission device of this example has a test signal drawing circuit A for drawing a line-shaped test signal (i.e., a test line) on the outline (i.e., side) of the composite boundary of each sub-image, and an enlarged display circuit B for partially enlarging and displaying the test signal, so that the presence or absence of display misalignment in the 4K video restored by combining four 2K videos (sub-images) can be easily determined. Note that the process up to the stage where the phase of the SQD type 4K video signal input from the outside to the video transmission device is corrected inside the device (processing indicated by symbols 100 to 103) is the same as the conventional technology.

The test signal drawing circuit A has a line number detection unit 1, a pixel detection unit 2, a horizontal/vertical test signal drawing unit 3, and a delay adjustment unit 4. In general, the test signal drawing circuit A detects the line number and pixel sample (position) number from each of the sub-images (a) to (d) after phase correction, and performs a process of replacing the data of the outline portion that becomes the synthesis boundary when synthesizing each sub-image with fixed test data, thereby realizing drawing of the test signal. The operation of the test signal drawing circuit A will be described in detail below.

First, the test signal drawing circuit A detects the video line number decoded value LNDEC from each of the phase-corrected sub-images (a) to (d) in the line number detection unit 1. Specifically, the line number detection unit 1 references the TRS timing signal EAV1W, which indicates the beginning of the video line and is output from the phase control unit 102 in the previous stage, to determine the signal position on the stream. Note that since each sub-image has already been phase-adjusted, the TRS timing signal EAV1W is common regardless of the sub-image.

After reading the line number decoded value LNDEC written at the position specified by the TRS reference, the pixel detection unit 2 generates a counter CNTR to identify the position (sample) of each pixel in the video. Through line number detection and pixel detection, the position of each pixel in the video signal becomes clear, making it possible to determine the position at which to draw the test signal.

The horizontal/vertical test signal drawing unit 3 performs drawing processing of a test signal for each sub-image signal at a position determined by line number detection and pixel detection. There are horizontal test signals, which are horizontal test signals, and vertical test signals, which are vertical test signals. Since the test signals are displayed at different positions for each sub-image, drawing processing is performed for each sub-image. The delay adjustment unit 4 is a correction circuit for a fixed delay amount that takes into account the processing delay in generating the test signal. The processing delay is constant depending on the circuit, and the delay adjustment unit 4 corrects the fixed delay amount. This completes the operation of the test signal drawing processing circuit A.

The enlarged display circuit B has a RAM write control unit 5, a video buffer 6, a RAM read control unit 7, an enlarged signal creation unit 8, and an enlarged test signal drawing unit 9. In general, the enlarged display circuit B stores each sub-image signal on which a test signal has been drawn in a video buffer, and when reading out the sub-image signal from the video buffer in the target enlarged display area, it performs processing to repeatedly read out the control signal for the read process in the horizontal and vertical directions according to the enlargement magnification, thereby realizing a partial enlarged display of the test signal. The operation of the enlarged display circuit B is described in detail below.

The enlarged display circuit B first temporarily stores each sub-image signal (i.e., each sub-image signal in which a test signal is drawn) output from the horizontal/vertical test signal drawing section 3 of the test signal drawing circuit A in the image buffer 6, which is a RAM (Random Access Memory). At that time, the RAM write control 5 controls writing to the image buffer 6 based on the line number decoded value LNDEC detected from the sub-image signal and the counter CNTR indicating the pixel position.

The enlarged display process is performed by a read process from the video buffer 6 by the RAM read control 7. As an example, the test signal is enlarged by continuously reading out the signal of the same line across multiple lines and continuously reading out the signal of the same pixel position across multiple pixels, based on the position of the target enlarged display area on the 4K video. The enlarged display area is, for example, an area of a predetermined size centered on the intersection of the horizontal test signal and the vertical test signal. The signals of each sub-image read from the video buffer 6 are synthesized into a single enlarged test signal by the enlargement signal creation unit 8.

The enlarged test signal drawing unit 9 creates a video signal in which the enlarged test signal is drawn by overwriting an arbitrary sub-image signal with the enlarged test signal output from the enlarged signal creation unit 8. A signal specifying the sub-image into which the enlarged image is to be drawn is given to the enlarged test signal drawing unit 9 as a display area selection SIN. It is possible to select whether or not to perform the drawing process of the test signal and the enlarged test signal. A signal specifying whether or not to perform the drawing process is given to the horizontal/vertical test signal drawing unit 3 and the enlarged test signal drawing unit 9 as display control ON/OFF. This completes the operation of the enlarged display circuit B.

Figure 2 shows a drawing image of a test signal for a video signal input to a video transmission device. Figure 2(a) shows a drawing image of a test signal by test signal drawing circuit A. The upper part of Figure 2(a) shows a drawing image of a test signal in a 4K video, in which test signals of two different colors (e.g. red and blue) are drawn side by side with the vertical and horizontal centers of the video as the boundaries. In other words, test signals of different colors are drawn on two opposing sides of two sub-images that are adjacent to each other.

The lower part of FIG. 2(a) shows the image of the test signal drawn for each subimage. In each subimage, a horizontal test signal is drawn along either the upper or lower edge, which corresponds to the outline of the image, and a vertical test signal is drawn along either the left or right edge. Whether the test signal is drawn on the upper or lower edge, and whether the test signal is drawn on the left or right edge is determined for each subimage. Specifically, the test signal is drawn on the lower and right edges of the subimage (a) that constitutes the upper left part of the 4K image. The test signal is drawn on the lower and left edges of the subimage (b) that constitutes the upper right part of the 4K image. The test signal is drawn on the upper and left edges of the subimage (c) that constitutes the lower left part of the 4K image. The test signal is drawn on the upper and right edges of the subimage (d) that constitutes the lower right part of the 4K image.

Figure 2(b) shows the portion shown by the dashed line in Figure 2(a), that is, the enlarged test signal in which the intersection of the test signal is enlarged by the enlargement display circuit B. The upper part of Figure 2(b) shows an enlarged view in a normal state, and it can be seen that the lines drawn with the same width on either side of the composite boundary of the screen are displayed with the same width even in the composited 4K image. In other words, all test signals are multiple lines and the same number of lines. The lower part of Figure 2(b) shows an enlarged view of a state in which a display shift has occurred in some sub-images. In the illustrated example, the horizontal test signal is displayed thinly because the sub-image (c) is shifted vertically to the negative side (upper side), and the vertical test signal is displayed thinly because the sub-image (d) is further shifted horizontally to the negative side (left side). In this way, it is possible to easily grasp the presence or absence of a shift during composition and the direction of the shift by simply checking the state of the composite boundary.

Figure 2(c) shows an example of an enlarged test signal drawn on any sub-image. In the example shown, the enlarged test signal is drawn on sub-image (d). By enlarging the display in this way, it is possible to clearly check the state of the composite boundary even in the composite image.

Here, as a premise for the test signal drawing circuit A and the enlarged display circuit B of this example, the screen configuration when dividing/combining in the 4K video SQD method will be described with reference to FIG. 19. A 4K video with an effective display area of 3840 pixels x 2160 lines is divided into 2K size sub-image images of 1920 pixels x 1080 lines along the center lines in the vertical and horizontal directions. The sub-image is the effective display area of the 2K video, and constitutes a video frame to which timing signals such as EAV (End of Active Video) and SAV (Start of Active Video), horizontal auxiliary areas (H Blanking), vertical auxiliary areas (V Blanking), etc. are added. The signal that serializes this frame becomes the SDI signal.

Similarly, among the SMPTE standards for constructing SDI video signals, the SDI technology related to the test signal drawing circuit A and the enlarged display circuit B in this example will be described with reference to Figures 20 and 21. As explained in the section on prior art, the sub-image is constructed from 10-bit parallel signals (data streams) of luminance and color difference.

Figure 20(a) shows a mapping structure (Mapping Structure 1) in which the color difference signals Cb and Cr are arranged in a 4:2:2 ratio relative to the luminance signal Y. Inside the device, the entire 4K video is treated as a parallel signal with a width of 80 bits. Figure 20(b) shows the arrangement of header signals in the luminance signal and color difference signal. The values in the figure are the values for the domestic standard frame frequency of 60/1.001 Hz. For both luminance and color difference, one line is 2200 samples. Of this, the period of 280 samples excluding the video signal width of 1920 samples becomes the horizontal blanking period in which header information and auxiliary data can be inserted.

For both the luminance signal and the color difference signal, the start of the blanking period other than the effective image is the four words EAV indicating the end of the image. The first three words of EAV are fixed value prefix information (3FF,000,000), and the next word is identification information XYZ. At the end of the blanking period, there is SAV indicating the start of the effective image, which is the same four words as EAV. EAV is followed by two words (LN0, LN1) describing the line number. The line number is 11-bit data and is inserted at the bit position shown in Figure 21 (a). In addition, among the breakdown of XYZ, the F, V, and H signals (hereinafter referred to as "FVH") related to the test signal drawing circuit A and the enlarged display circuit B in this example are inserted at the bit position shown in Figure 21 (a). FVH indicates the position of EAV or SAV in the image frame, and by reading its value, it is possible to determine the insertion position of EAV or SAV. Figure 21(b) shows the relationship between the FVH value and the position on the frame. Reading the EAV, line number, and FVH as described above is the prerequisite for creating the test signal and drawing processing.

Next, we will explain the drawing of the test signal using the parameters of sub-image (a). Similar processing is applied to both the luma and chroma streams. Figure 3 shows the relationship between the parameters of test signal drawing circuit A and the test signal. The left diagram in Figure 3 shows the state where only the horizontal test signal is drawn from 280 to 1919 horizontal samples of the effective image, at a height of n to 1121 vertical lines. The right diagram in Figure 3 shows the state where only the vertical test signal is drawn from 42 to 1121 vertical lines, at a height of p to 1919 horizontal samples of the effective image.

Figure 4 shows an example of the configuration of the horizontal test signal drawing circuit A1, which is part of the test signal drawing circuit A. The line detection unit 1 in the figure has a counter 11, a comparator 12, a flip-flop 13, a latch 14, and an LN decode unit 15. The pixel detection unit 2 has a comparator 21, a comparator 22, an RS flip-flop 23, a logical product calculator 24, and a flip-flop 25. The horizontal test signal drawing unit 3a, which constitutes part of the horizontal/vertical test signal drawing unit 3, has a flip-flop 31 and a switch 32.

The horizontal test signal drawing circuit A1 operates with a clock CLK at a speed for processing one word of data, as do the other circuits described below. The counter 11 is initialized by the TRS timing signal EAV1W input from the phase control unit 102 in FIG. 1. Based on the counter value CNTR output from the counter 11, the comparator 12 generates a timing signal LNEn with a count value of "4" or "5", which is the superimposition position of the line number data. This timing signal LNEn is given to the latch 14 as an enable signal.

The sub-image signal input to the horizontal test signal drawing circuit A1 is delayed and adjusted by the flip-flop 13 before being input to the latch 14, which outputs two words LN describing the line number in the EAV. Next, the LN decoding unit 15 detects the line number decoded value LNDEC from LN and inputs it to the comparator 21. The comparator 21 outputs H-TstEn as the judgment result when the line number is between n and 1121, which is the horizontal test signal period, and outputs V-TstEn as the judgment result when the line number is between 42 and 1121, which is the vertical test signal period.

At the same time, the comparator 22 sets the set (S)/reset (R) of the RS flip-flop 23 so that the counter value CNTR is positive logic when it is in the range of 280 to 1919, which is the horizontal test signal period. The logical product calculator 24 calculates the logical product H-TstVar of the output of the RS flip-flop 23 and the judgment result H-TstEn of the horizontal test signal period output from the comparator 21. H-TstVar is delayed and adjusted by the flip-flop 25, and then provided to the switch 32 as a switching control signal.

The sub-image signal that has been delay-adjusted by the flip-flop 31 is input to the switch 32. The switch 32 switches the input sub-image signal to a constant C1 according to H-TstVar, thereby obtaining a horizontal test signal H-TstDt that draws the horizontal test signal. Here, the constant C1 is a set value according to the drawing color of the horizontal test signal.

Figure 5 shows an example of the configuration of the vertical test signal drawing circuit A2, which is part of the test signal drawing circuit A. The pixel detection unit 2 in the figure has a comparator 21, a comparator 26, an RS flip-flop 27, and a logical product calculator 28. The vertical test signal drawing unit 3b, which constitutes part of the horizontal/vertical test signal drawing unit 3, has a flip-flop 33, a flip-flop 34, and a switch 35.

In the vertical test signal drawing circuit A2, the comparator 26 sets the set (S)/reset (R) of the RS flip-flop 27 so that the counter value CNTR is positive logic when it is in the range p to 1919, which is the vertical test signal period. The logical product calculator 28 calculates the logical product V-TstVar of the output of the RS flip-flop 27 and the judgment result V-TstEn of the vertical test signal period output from the comparator 21. After being delayed and adjusted by the flip-flop 34, V-TstVar is given to the switch 35 as a switching control signal.

The horizontal test signal H-TstDt, which has been delay-adjusted by the flip-flop 33, is input to the switch 35. The switch 35 switches the horizontal test signal H-TstDt to a constant C2 according to V-TstVar, thereby obtaining a horizontal and vertical test signal HV-TstDt that draws the horizontal test signal and the vertical test signal. Here, the constant C2 is a set value according to the drawing color of the vertical test signal.

Here, in the horizontal/vertical test signal drawing circuits A1 and A2 in FIG. 4 and FIG. 5, the vertical test signal is drawn after the horizontal test signal, but in identifying the state of the composite boundary, it is effective to change the drawing order according to the display image. This point will be explained with reference to FIG. 6. For example, the hatched and shaded parts in FIG. 6(a) are the test signals to be drawn, and indicate that the drawing positions are different for each subimage. For each subimage, the horizontal test signal and the vertical test signal are drawn in the order shown in FIG. 6(b) at the positions specified in FIG. 6(a). In other words, for subimages (a) and (b), the vertical test signal is drawn after the horizontal test signal, and for subimages (c) and (d), the horizontal test signal is drawn after the vertical test signal. By drawing in this order, it is possible to draw the crossing lines as shown in FIG. 6(c).

Figure 7 shows an example of parameters for each sub-image used in the horizontal and vertical test signal drawing circuits A1 and A2 in Figures 4 and 5. In Figure 7, the set values for drawing the horizontal test signal are set as follows for sub-images (a) and (b): V upper limit of comparator 21 = n1, V lower limit = 1121, set (S) of RS flip-flop 23 = 280, reset (R) = 1919, and for sub-images (c) and (d): V upper limit of comparator 21 = 42, V lower limit = n2, set (280) of RS flip-flop 23 = 1919. In addition, as the setting values for drawing the vertical test signal, for sub-images (a) and (c), the comparator 21 has a V upper limit of 42, a V lower limit of 1121, and the RS flip-flop 27 has a set of p1 and a reset of 1919. For sub-images (b) and (d), the comparator 21 has a V upper limit of 42, a V lower limit of 1121, and the RS flip-flop 27 has a set of 280 and a reset of p2.

The drawing colors of the horizontal test signal and vertical test signal are determined by the constants C1 and C2, as described above. As an example, the lower part of Figure 7 shows an example of constants when drawing in red. That is, when drawing in red with a brightness level of 75% using 10-bit Y/C data, Y = 0CC, and C is a repetition of Cb (= 1B3) and Cr (= 1E1).

Figure 8 shows an example of a timing chart for the horizontal and vertical test signal drawing circuits A1 and A2 of Figures 4 and 5. As can be seen from Figure 8, the horizontal test signal H-TstDt becomes the constant C1 at pixel positions of the video signal indicated by the word counter (CNTR) = 280 to 1919 samples, and the horizontal and vertical test signal HV-TstDt is overwritten with the vertical test signal constant C2 at pixel positions = p to 1919 samples.

Next, the enlarged display of the test signal by the enlargement display circuit B will be described. Figure 9 shows an example of the configuration of the enlargement display circuit B. The enlargement display circuit B is centered around the video buffer 6, which is a RAM that stores the signal under test. It has a RAM write control unit 5 that generates a write signal to the video buffer 6, a RAM read control unit 7 that performs enlargement processing when reading from the video buffer 6, an enlargement signal creation unit 8 that creates an enlarged signal to be displayed, and an enlargement test signal drawing unit 9 that multiplexes the enlargement signal into the input stream. The enlargement test signal output EXP-TstDt for each sub-image is read from the video buffer 6, integrated by the enlargement signal drawing unit 8, and then multiplexed into the input stream by the enlargement test signal drawing unit 9.

Figure 10 shows how the line width of the intersection of the test signal is enlarged by four times by controlling the input and output of the RAM (video buffer 6) implemented in the enlargement processing circuit B. As parameters indicating the area of the sub-image unit, the RAM input has a size of horizontal pixels = h1-h2, vertical lines = v1-v2, and the RAM output has a size of horizontal pixels = H1-H2, vertical lines = V1-V2.

With reference to Figure 11, the RAM input/output control when enlarging the intersection of the test signals will be described. The RAM write control unit 5 controls data writing to the RAM so as to obtain the memory configuration shown in the table of Figure 11. That is, the address ADR is set to pixels h1 to h2 for the write line v1, and the input signal DT is written. At the same time as the input signal, a LAST flag that identifies the last data of the line is also written. Then, after writing line v1, the signal of the next line v(+1) is written in the same way. This is repeated until the signals of all pixels corresponding to the area to be enlarged are written as data of consecutive addresses ADR.

The read order example on the right side of the table in Figure 11 shows the flow of the RAM data read operation when enlarging by 4 times. It shows that after the signal of the same line (v1) is read out four times repeatedly, the transition to reading the next line v (+1) is made. In this way, the vertical line width is enlarged by repeating the read out a number of times according to the enlargement ratio. Note that the horizontal line width is enlarged by the repeated read control of the same address, which will be described later.

Figure 12 shows an example of the configuration of the RAM write control unit 5. Figure 12(a) shows an example of the configuration of a write enable WE generation circuit in the RAM write control unit 5, and Figure 12(b) shows an example of the configuration of a write address WADR generation circuit in the RAM write control unit 5. The write enable WE generation circuit has a comparator 51, a comparator 52, and a logical AND operator 53. The write address WADR generation circuit has a comparator 54, a comparator 55, a logical AND operator 56, and an address counter 57.

First, referring to FIG. 12(a), a method for generating the write enable signal WE is described. Based on the counter value CNTR and the line number decoded value LNDEC generated by the circuit in FIG. 4, the horizontal and vertical sizes of the area to be enlarged are determined, and the write enable signal WE is generated. More specifically, window comparator type comparators 51 and 52 are used to decode each area in the horizontal and vertical directions. In the horizontal direction, comparator 52 detects the range h1≦CNTR≦h2. In the vertical direction, comparator 51 detects the range v1≦LNDEC≦v2. The logical product of the outputs of these comparators 51 and 52 is calculated by logical product calculator 53 to obtain the write enable signal WE.

Next, a method for generating the write address WADR will be described with reference to FIG. 12(b). WADR is generated as the output of the address counter 57. The address counter 57 is initialized when the input stream reaches the position of LNDEC=v2 and CNTR=h2, which is the final data of the area to be enlarged. The address counter 57 then increments the counter using the active period of WE as the count enable. The input stream reaching the position of LNDEC=v2 is detected by the comparator 54, and the input stream reaching the position of CNTR=h2 is detected by the comparator 55. The logical product of the outputs of these comparators 54 and 55 is calculated by the logical product calculator 56 and is given to the address counter 57 as an initialization signal. The timing of the arrival of the final data h2 of the horizontal line of the area to be enlarged is written to the RAM as LASTw together with the video signal for use in subsequent processing. Using the WE and WADR generated as described above, all data within the area to be enlarged is written to RAM while incrementing the RAM write address, as shown in the memory configuration example shown in Figure 11.

Figures 13 and 14 show examples of the configuration of the RAM read control unit 7. Figure 13 shows an example of the configuration of the read enable RE generation circuit, and Figure 14 shows an example of the configuration of the read address RADR generation circuit. The read enable RE generation circuit has a comparator 71a, a comparator 71b, a logical product operator 71c, a counter 72a, a comparator 72b, a logical sum operator 72c, a comparator 73a, and a logical product operator 73b. The read address RADR generation circuit has a comparator 74a, a comparator 74b, a logical product operator 74c, a logical sum operator 74d, a logical sum operator 74e, a line counter 75a, a comparator 75b, a pixel counter 76a, an adder 76b, a flip-flop 76c, an address counter 77a, a flip-flop 77b, and an adder 78.

First, a method for generating the read enable RE will be described with reference to FIG. 13. Counter 72a counts the number of pixels in the enlarged display area. Comparator 71a detects that the line number decoded value LNDEC of the video stream is within the V1 to V2 lines of the enlarged display area. Comparator 71b similarly detects that the counter value CNTR, which indicates the pixel position of the video stream, is within the H1 to H2 samples. The logical product of the outputs of these comparators 71a and 71b is calculated by logical product calculator 71c, which generates a signal DRWEN indicating the enlarged display area.

Counter 72a increments sequentially using DRWEN as count enable to obtain output HCTR. HCTR has its counter value decoded by comparators 73a and 72b. Note that comparator 72b is used to set parameter M (=X-1) according to the amount of enlargement X by which the pixels stored in RAM are stretched in the horizontal direction. For example, when enlarging by 4 times, M=3. Counter 72a is initialized by the output of comparator 72b or EAV1W indicating the beginning of each line, which is given through logical OR operator 72c. This makes counter 72a a cyclic counter that corresponds to the horizontal enlargement magnification.

Meanwhile, comparator 73a decodes HCTR value = 0 and generates timing to extend the RAM read timing to the set number of pixels. The logical product of the outputs COMP and DRWEN of comparator 73a is calculated by logical product calculator 73b to become read enable RE. Read enable RE extends the in-line data stored in RAM to the set period within the enlarged display area, and becomes a timing signal to read it discretely.

Next, a method for generating the read address RADR will be described with reference to FIG. 14. The line counter 75a is a counter that counts the number of times line data is repeatedly read from the RAM in order to expand the line width in the vertical direction. The line counter 75a is initialized at the beginning of the enlarged display area, where the line number decoded value LNDEC of the video stream is the V1 line (read-out first line setting value) and the pixel position CNTR is the H1 sample (read-out first pixel setting value). The line counter 75a then increments the counter value LCTR according to LASTr, which indicates the reading of the final value of each line data. Note that the comparator 74a detects that the line number decoded value LNDEC of the video stream is the V1 line, and the comparator 74b detects that the pixel position CNTR is the H1 sample. The logical product of the outputs of these comparators 74a and 74b is calculated by the logical product calculator 74c and is given to the line counter 75a as an initialization signal via the logical sum calculator 74d.

The comparator 75b detects that the number of reads of line data LCTR has reached N times, and outputs an enable signal ADDEN to the adder 76b in the subsequent stage. ADDEN, which indicates that the number of reads has reached N times, is provided as an initialization signal to the line counter 75a via the logical sum calculator 74d. This causes the line counter 75a to function as a cyclic counter according to the vertical enlargement magnification.

The pixel counter 76a counts the number of read pixels, and its output PCTR is used to update the address corresponding to the read line number. The logical sum calculator 74e calculates the logical sum CTRLD of the start position of each line in the enlarged display area where the counter value CNTR is H1 (the output of the comparator 74b) and the line data final value LASTr, and provides this as an initialization signal to the pixel counter 76a and the address counter 77a. In response to this initialization signal, the pixel counter 76a sets the counter value PCTR to its initial value (=1). The pixel counter 76a increments the counter value PCTR in accordance with the clock synchronized with the word data, using DRWEN, which indicates that the video stream is within the enlarged display area, as a count enable.

The adder 76b performs addition in units of the number of words in one line of the write area by enabling the addition process with ADDEN. The UADR output from the adder 76b is delayed and adjusted by the flip-flop 76c, and then input to the adder 78 as the line address for reading from the RAM.

The address counter 77a is a counter that generates a read address within one line. The address counter 77a counts with DRWEN, which indicates that the video stream is within the enlarged display area, and increments the counter value LADR after initializing it according to CTRLD. The output LADR of the address counter 77a is delayed and adjusted by the flip-flop 77b, and then input to the adder 78 as a pixel address for RAM readout.

The adder 78 sequentially adds the input UADR (upper address) and LADR (lower address) to obtain the read address RADR of the RAM. This causes the data in one line stored in the RAM to be repeatedly read out the number of times set by the parameter N, and after the set number of times has elapsed, a read address is generated that transitions the line data to be read out to the next line.

Figure 15 shows an example of a timing chart for the read enable RE generation circuit shown in Figure 13. Figure 15 shows an example where M=3, i.e., the setting is to stretch by 4 pixels in the horizontal direction, and it can be seen that the read data DT from the RAM is stretched as set by the RE generation process.

Figure 16 shows an example of a timing chart of the read address RADR generation circuit shown in Figure 14. Figure 16 shows an example where N=4, i.e., where four lines are set for extension, and it can be seen that the RADR generation process sets addresses for the same line data for four consecutive lines.

FIG. 17 shows an example of the configuration of the enlarged signal creation unit 8 and the enlarged test signal drawing unit 9. The enlarged signal creation unit 8 has a switch 80. The enlarged test signal drawing unit 9 has a switch 91a, a flip-flop 91b, a logical sum calculator 92a, a switch 92b, a switch 92c, and a logical product calculator 93.

The enlarged test signals EXP-TstDt(a)-(d) obtained by reading out each sub-image from the RAM shown in FIG. 9 are input to the switch 80. The switch 80 switches between the EXP-TstDt(a)-(d) using the enlarged display area DRWEN(a)-(d) as a switching signal. In other words, the switch 80 selects and outputs the video signal corresponding to the active switching signal. Here, the signal selected by the switching has a data structure of luminance EXP-TstDt(Y) and color difference EXP-TstDt(C). The luminance signal EXP-TstDt(Y) is input to the switch 92b, and the color difference signal EXP-TstDt(C) is input to the switch 92c.

The video transmission device can arbitrarily select the area in which the enlarged test signal is displayed on a sub-image basis, and the switch 91a selects one of the horizontal and vertical test signals HV-TstDt(a)-(d) for each sub-image according to the selection signal SIN. Here, the selected horizontal and vertical test signal has a luminance and color difference data configuration, and after being delayed and adjusted by the flip-flop 91b, the luminance signal Stream (Y) is input to the switch 92b, and the color difference signal Stream (C) is input to the switch 92c.

The logical sum calculator 92a calculates the logical sum of the enlarged drawing areas DRWEN(a)-(d) of each sub-image. According to the output of the logical sum calculator 92a, the switch 92b switches between outputting Stream(Y) or EXP-TstDt(Y), and the switch 92c similarly switches between outputting Stream(C) or EXP-TstDt(C). This makes it possible to draw a test signal of the target color. Furthermore, the logical sum calculator 93 calculates the logical product of the display control ON/OFF selected arbitrarily by the video transmission device and DRWEN, and provides this as a switching signal to the switches 92b and 92c, making it possible to select whether or not to display the enlarged test signal.

As described above, the video transmission device of this example is configured to receive a video signal composed of four sub-images (2K images) obtained by dividing the 4K image to be transmitted horizontally and vertically, draw a test signal of a predetermined color along the edge corresponding to the boundary line dividing the 4K image for each of the four sub-images constituting the video signal, and output a video signal composed of the multiple divided images on which the test signal is drawn. As a result, the 4K image restored based on the video signal output from the video transmission device of this example will display horizontal and vertical composite boundaries. Therefore, simply by looking at the state of the horizontal and vertical composite boundaries, it becomes easy to know whether there is any misalignment during composition. As a result, it becomes possible to determine whether the divided image processing inside the device is appropriate.

In addition, in the video transmission device of this example, the test signal drawn on each of the multiple sub-images is multiple lines, and the number of lines is the same. Therefore, simply by checking the line width of the horizontal and vertical synthesis boundaries of the video output, it is possible to determine whether there is any misalignment during synthesis.

In addition, in the video transmission device of this example, the two opposing sides of two adjacent sub-images are configured to have test signals of different colors drawn on them. Therefore, if a shift occurs during composition, it is easy to determine which sub-image is shifted in which direction.

The video transmission device of this example is also configured to generate an enlarged test signal that enlarges the intersection of the horizontal and vertical composite boundaries based on the multiple sub-images on which the test video is drawn, and further draw the enlarged test signal on one of the multiple split videos. This makes it easier to check the state of the horizontal and vertical composite boundaries in the video output, and makes it easier to determine whether there is any misalignment during composition.

In the above explanation, an example was given of transmitting 4K video in the SQD format, but the present invention is not limited to this, and can be applied to the transmission of video in other formats. Also, in the above explanation, an example was given of the video to be transmitted being divided into four parts, but the present invention can be applied to the case where the video to be transmitted is divided into more parts.

Although the embodiments of the present invention have been described above, these embodiments are merely illustrative and do not limit the technical scope of the present invention. The present invention can take various other embodiments, and various modifications such as omissions and substitutions can be made without departing from the gist of the present invention. These embodiments and their modifications are included in the scope and gist of the invention described in this specification, etc., and are included in the scope of the invention described in the claims and their equivalents.

The present invention can be provided not only as the devices described above or as systems composed of these devices, but also as methods executed by these devices, programs for implementing the functions of these devices using a processor, and storage media for storing such programs in a computer-readable format.

The present invention can be used in a video transmission device that receives a video signal composed of multiple split images obtained by splitting the video to be transmitted in the horizontal and vertical directions.

1: Line number detection unit, 2: Pixel detection unit, 3: Horizontal/vertical test signal drawing unit, 3a: Horizontal test signal drawing unit, 3b: Vertical test signal drawing unit, 4: Delay adjustment unit, 5: RAM write control unit, 6: Video buffer, 7: RAM read control unit, 8: Enlarged signal creation unit, 9: Enlarged test signal drawing unit, 11, 72a: Counter, 12, 21, 22, 26, 51, 52, 54, 55, 71a, 71b, 72b, 73a, 74a, 74b, 75b: Comparator, 13, 25, 31, 33, 34, 76c, 77b, 91b: Flip-flop, 14: Latch, 15: LN decoding unit, 23, 27: RS flip-flop, 24, 28, 53, 56, 71c, 73b, 74c, 93: logical product calculator, 32, 35, 80, 91a, 92b, 92c: switch, 57, 77a: address counter, 72c, 74d, 74e, 92a: logical sum calculator, 75a: line counter, 76a: pixel counter, 76b, 78: adder, 100: SDI receiving circuit, 100a: receiver, 100b: SDI decoding unit, 101: TRS detection unit, 102: phase control unit, 103: phase correction unit,

Claims (3)

In a video transmission device to which a video signal composed of a plurality of divided videos obtained by dividing a video to be transmitted in the horizontal and vertical directions is input,
For each of a plurality of divided images constituting the input video signal, a test signal of a predetermined color is drawn along a side corresponding to a boundary line dividing the video to be transmitted, and a video signal composed of the plurality of divided images on which the test signal is drawn is output ;
In this case, the video transmission device generates an enlarged test signal that enlarges the portion where the horizontal composite boundary and the vertical composite boundary intersect based on the multiple divided images on which the test signal is drawn, and draws the enlarged test signal on one of the multiple divided images . 2. The video transmission device according to claim 1,
A video transmission device, characterized in that the test signal drawn on each of the plurality of divided videos is a plurality of lines, the number of lines being the same. 3. The video transmission device according to claim 1,
A video transmission device, characterized in that test signals of different colors are drawn on two opposing sides of two adjacent divided videos.

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