JP7625868B2 - Integrated circuit device and oscillator - Google Patents

Description

The present invention relates to integrated circuit devices and oscillators, etc.

Integrated circuit devices having an oscillator circuit that oscillates an oscillator such as a quartz crystal oscillator have been known for some time. Patent Document 1 discloses a layout arrangement for an integrated circuit device having a temperature-compensated oscillator circuit. For example, Patent Document 1 discloses an integrated circuit device that suppresses the propagation of power supply noise by providing a discontinuous portion between the clock signal output circuit area and the temperature compensation circuit area in the power supply lines provided along the outer periphery of the integrated circuit device for an oscillator equipped with a temperature compensation circuit.

JP 2018-98428 A

However, even if noise propagation is suppressed by isolating the power supply lines as in Patent Document 1, there is a risk that radiation noise will be superimposed on the DC voltage generated by the circuitry provided around the output buffer circuit that outputs the clock signal, degrading the noise performance of the oscillator.

One aspect of the present disclosure relates to an integrated circuit device including an oscillation circuit that generates an oscillation signal using an oscillator, an output buffer circuit that outputs a clock signal based on the oscillation signal, a DC voltage generation circuit that generates a DC voltage used to generate the oscillation signal or the clock signal, a power supply pad to which a power supply voltage is supplied, a ground pad to which a ground voltage is supplied, and a clock pad to which the clock signal is output, the ground pad and the DC voltage generation circuit being arranged to overlap in a planar view.

Another aspect of the present disclosure relates to an oscillator including the integrated circuit device described above and the resonator.

2 shows an example of the configuration of an integrated circuit device according to the present embodiment. 2 shows a detailed configuration example of the integrated circuit device of the present embodiment. 2 shows a detailed configuration example of a PLL circuit. FIG. 4 is a cross-sectional view showing the positional relationship between a ground pad and a DC voltage generating circuit. FIG. 11 is a cross-sectional view showing another example of the structure of the ground pad. 2 shows an example of the configuration of a reference voltage generation circuit. 13 shows another example of the configuration of the reference voltage generating circuit. An example of regulator configuration. Other examples of regulator configurations. An example of a temperature sensor circuit. An example of a temperature compensation circuit. 3 shows an example of a layout of the integrated circuit device according to the present embodiment. 13 shows another example of the layout arrangement of the integrated circuit device of the present embodiment. FIG. 1 is a diagram illustrating phase noise. An example of oscillator structure.

The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the contents of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential components.

1. Integrated Circuit Device FIG. 1 shows a configuration example of an integrated circuit device 20 of this embodiment. The integrated circuit device 20 of this embodiment includes an oscillation circuit 30, an output buffer circuit 50, a power supply pad PVDD, a ground pad PGND, and a clock pad PCK. The integrated circuit device 20 can also include a power supply circuit 60 and pads PX1 and PX2 for connecting an oscillator. For example, the integrated circuit device 20 includes a reference voltage generation circuit 62 and a regulator 64 as a DC voltage generation circuit 61 in FIG. 4 and FIG. 5 described later. In FIG. 1, the reference voltage generation circuit 62 and the regulator 64, which are the DC voltage generation circuit 61, are provided in the power supply circuit 60. The oscillator 4 of this embodiment also includes an oscillator 10 and an integrated circuit device 20. The oscillator 10 is electrically connected to the integrated circuit device 20. For example, the oscillator 10 and the integrated circuit device 20 are electrically connected to each other using internal wiring, bonding wires, metal bumps, or the like of a package that houses the oscillator 10 and the integrated circuit device 20.

The vibrator 10 is an element that generates mechanical vibrations by an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 can be realized by a quartz crystal vibrating piece that vibrates in a thickness shear manner, such as an AT cut or SC cut cut angle, a tuning fork type quartz crystal vibrating piece, or a double tuning fork type quartz crystal vibrating piece. For example, the vibrator 10 may be a vibrator built into a temperature compensated quartz crystal oscillator (TCXO) that does not have a thermostatic oven, or a vibrator built into an oven-controlled quartz crystal oscillator (OCXO) that has a thermostatic oven. Alternatively, the vibrator 10 may be a vibrator built into an oscillator of an SPXO (Simple Packaged Crystal Oscillator). The vibrator 10 of this embodiment can also be realized by various vibrating pieces, such as a vibrating piece other than a thickness shear vibration type, a tuning fork type, or a double tuning fork type, or a piezoelectric vibrating piece formed of a material other than quartz. For example, the vibrator 10 may be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) vibrator, which is a silicon vibrator formed using a silicon substrate.

The integrated circuit device 20 is, for example, an IC (Integrated Circuit) manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. In FIG. 1, the integrated circuit device 20 includes an oscillator circuit 30, an output buffer circuit 50, and a power supply circuit 60.

The oscillator circuit 30 is a circuit that oscillates the vibrator 10. For example, the oscillator circuit 30 is electrically connected to the pads PX1 and PX2, and generates an oscillation signal OSC by oscillating the vibrator 10. The pad PX1 is the first pad, and the pad PX2 is the second pad. For example, the oscillator circuit 30 can be realized by an oscillation drive circuit provided between the pads PX1 and PX2, and active elements such as a capacitor and a resistor. The drive circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillator circuit 30, and the drive circuit drives the vibrator 10 with voltage or current to oscillate the vibrator 10. As the oscillator circuit 30, various types of oscillator circuits such as an inverter type, a Pierce type, a Colpitts type, or a Hartley type can be used. In addition, a variable capacitance circuit is provided in the oscillator circuit 30, and the oscillation frequency can be adjusted by adjusting the capacitance of this variable capacitance circuit. The variable capacitance circuit can be realized by a variable capacitance element such as a varactor. For example, the variable capacitance circuit can be realized by a variable capacitance element whose capacitance is controlled based on a temperature compensation voltage. Alternatively, the variable capacitance circuit may be realized by a capacitor array and a switch array connected to the capacitor array. For example, the variable capacitance circuit may be configured by a capacitor array having a plurality of capacitors whose capacitance values are binary weighted, and a switch array having a plurality of switches, each of which turns on and off the connection between each capacitor of the capacitor array and the ground node. In addition, the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that allows information to be transmitted by an electrical signal. The electrical connection may be a connection via a passive element or the like.

The output buffer circuit 50 outputs a clock signal CKQ based on the oscillation signal OSC. For example, the output buffer circuit 50 buffers the oscillation signal OSC and outputs it to the clock pad PCK as a clock signal CKQ. This clock signal CKQ is then output to the outside via the external terminal TCK of the oscillator 4. For example, the output buffer circuit 50 outputs the clock signal CKQ in a single-ended CMOS signal format. Note that the output buffer circuit 50 may also output the clock signal CKQ in a signal format other than CMOS. For example, the output buffer circuit 50 may output a differential clock signal to the outside in a signal format such as LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed Current Steering Logic), or differential CMOS (Complementary MOS).

The power supply circuit 60 receives the power supply voltage VDD from the power supply pad PVDD and the ground voltage from the ground pad PGND, and supplies various power supply voltages for the internal circuits of the integrated circuit device 20 to the internal circuits. For example, the power supply circuit 60 supplies a regulated power supply voltage based on the power supply voltage VDD to the oscillator circuit 30, etc., as described later. The power supply circuit 60 includes a reference voltage generation circuit 62, which is the DC voltage generation circuit 61 in Figures 4 and 5, and a regulator 64. The reference voltage generation circuit 62 generates and outputs a reference voltage. The reference voltage generation circuit 62 generates a reference voltage that is constant even if the power supply voltage VDD or temperature changes, for example. For example, the reference voltage generation circuit 62 generates a reference voltage for generating at least one of a bias current, a bias voltage, or a regulated power supply voltage. For example, the integrated circuit device 20 has an analog circuit, and the reference voltage generation circuit 62 generates a reference voltage for generating a bias current or a bias voltage for this analog circuit. The regulator 64 receives the power supply voltage VDD and generates various regulated power supply voltages. For example, the regulator 64 generates a regulated power supply voltage that is a constant voltage obtained by stepping down the power supply voltage VDD based on the reference voltage generated by the reference voltage generation circuit 62, and supplies the generated regulated power supply voltage to each circuit block of the integrated circuit device 20. The reference voltage generation circuit 62 can be realized by, for example, a bandgap reference circuit, a circuit that uses the difference in gate work functions, or a circuit that uses the difference in threshold voltages caused by changing the channel impurity concentration.

The integrated circuit device 20 also includes a power supply pad PVDD, a ground pad PGND, a clock pad PCK, and pads PX1 and PX2 for connecting an oscillator. These pads are terminals of the integrated circuit device 20, which is, for example, a semiconductor chip. For example, in the pad region, a metal layer is exposed from a passivation film, which is an insulating layer, and the exposed metal layer constitutes the pads of the integrated circuit device 20. The power supply pad PVDD is a pad to which a power supply voltage VDD is input. For example, the power supply voltage VDD from an external power supply device is supplied to the power supply pad PVDD. The ground pad PGND is a terminal to which GND, which is a ground voltage, is supplied. GND can also be called VSS, and the ground voltage is, for example, a ground potential. In this embodiment, the ground is appropriately described as GND. The clock pad PCK is a pad to which a clock signal CKQ is output. For example, a clock signal CKQ based on an oscillation signal OSC in the oscillation circuit 30 is output to the outside from the clock pad PCK. The power supply pad PVDD, the ground pad PGND, and the clock pad PCK are electrically connected to the external terminals TVDD, TGND, and TCK for external connection of the oscillator 4, respectively. For example, they are electrically connected using internal wiring of the package, bonding wires, metal bumps, etc. The external terminals TVDD, TGND, and TCK of the oscillator 4 are electrically connected to an external device. The pads PX1 and PX2 are pads for connecting the vibrator 10. For example, the pad PX1 is electrically connected to one end of the vibrator 10, and the pad PX2 is electrically connected to the other end of the vibrator 10. For example, the pad PX1 is electrically connected to the pads PX1 and PX2 of the vibrator 10 and the integrated circuit device 20 using internal wiring, bonding wires, metal bumps, etc. of the package that houses the vibrator 10 and the integrated circuit device 20.

Figure 2 shows a detailed configuration example of the integrated circuit device 20 of this embodiment. In Figure 2, the integrated circuit device 20 further includes a PLL circuit 40, a logic circuit 70, a non-volatile memory 78, a temperature compensation circuit 80, a temperature sensor circuit 90, a test circuit 92, and an interface circuit 94 in addition to the circuit blocks shown in Figure 1. The integrated circuit device 20 also includes an output enable pad POE in addition to the pads shown in Figure 1.

The PLL circuit 40 performs a PLL operation to generate a clock signal CKQ that is phase-synchronized with the oscillation signal OSC. For example, the PLL circuit 40 receives the oscillation signal OSC, which is an oscillation clock signal from the oscillation circuit 30, and outputs a clock signal CK that is phase-synchronized with the oscillation signal OSC. Specifically, the PLL circuit 40 outputs a clock signal CK that is phase-synchronized with the oscillation signal OSC and has a frequency that is multiplied by the frequency of the oscillation signal OSC. The output buffer circuit 50 receives the clock signal CK from the PLL circuit 40 and outputs the clock signal CKQ. That is, the output buffer circuit 50 buffers the clock signal CK based on the oscillation signal OSC and outputs it as the clock signal CKQ. Details of the PLL circuit 40 will be described later.

The logic circuit 70 is a control circuit that performs various control processes. For example, the logic circuit 70 controls the entire integrated circuit device 20 and controls the operation sequence of the integrated circuit device 20. For example, the logic circuit 70 controls each circuit block of the integrated circuit device 20, such as the oscillation circuit 30, the output buffer circuit 50, the power supply circuit 60, or the temperature compensation circuit 80. The logic circuit 70 also performs write and read control of the non-volatile memory 78. The logic circuit 70 can be realized by an ASIC (Application Specific Integrated Circuit) circuit that is automatically placed and wired, such as a gate array.

The non-volatile memory 78 stores various information used in the integrated circuit device 20. The non-volatile memory 78 can be realized by an EEPROM such as a FAMOS (Floating gate Avalanche injection MOS) memory or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) memory, but is not limited thereto and may be an OTP (One Time Programmable) memory or a fuse-type ROM, etc.

The temperature compensation circuit 80 performs temperature compensation of the oscillation signal OSC of the oscillation circuit 30. The temperature compensation of the oscillation signal OSC is temperature compensation of the oscillation frequency of the oscillation circuit 30. Specifically, the temperature compensation circuit 80 performs temperature compensation based on temperature detection information from the temperature sensor circuit 90. For example, the temperature compensation circuit 80 generates a temperature compensation voltage VCP based on the temperature detection voltage VT from the temperature sensor circuit 90, and outputs the generated temperature compensation voltage VCP to the oscillation circuit 30 to perform temperature compensation of the oscillation signal OSC of the oscillation circuit 30. For example, the temperature compensation circuit 80 performs temperature compensation by outputting a temperature compensation voltage VCP, which is a capacitance control voltage of the variable capacitance circuit, to the variable capacitance circuit of the oscillation circuit 30. In this case, the variable capacitance circuit of the oscillation circuit 30 is realized by a variable capacitance element such as a varactor. Temperature compensation is a process that suppresses and compensates for fluctuations in the oscillation frequency due to temperature fluctuations. For example, the temperature compensation circuit 80 performs analog temperature compensation using polynomial approximation. For example, when the temperature compensation voltage for compensating the frequency-temperature characteristic of the vibrator 10 is approximated by a polynomial, the temperature compensation circuit 80 performs analog temperature compensation based on coefficient information of the polynomial. The analog temperature compensation is realized by, for example, adding current signals and voltage signals, which are analog signals. Specifically, the nonvolatile memory 78 stores coefficient information of a polynomial for temperature compensation, and the logic circuit 70 reads out the coefficient information from the nonvolatile memory 78 and sets it, for example, in a register of the temperature compensation circuit 80. The temperature compensation circuit 80 then performs analog temperature compensation based on the coefficient information set in the register. The temperature compensation circuit 80 may also perform digital temperature compensation. In this case, the temperature compensation circuit 80 is realized by, for example, a logic circuit. Specifically, the temperature compensation circuit 80 performs digital temperature compensation processing based on temperature detection data, which is temperature detection information of the temperature sensor circuit 90. For example, the temperature compensation circuit 80 obtains frequency adjustment data based on the temperature detection data. Then, the capacitance value of the variable capacitance circuit of the oscillation circuit 30 is adjusted based on the obtained frequency adjustment data, thereby realizing temperature compensation processing of the oscillation frequency of the oscillation circuit 30. In this case, the variable capacitance circuit of the oscillation circuit 30 is realized by a capacitor array having a plurality of binary-weighted capacitors and a switch array. In addition, the non-volatile memory 78 stores a lookup table that indicates the correspondence between the temperature detection data and the frequency adjustment data, and the temperature compensation circuit 80 performs temperature compensation processing to obtain the frequency adjustment data from the temperature data using the lookup table read from the non-volatile memory 78 by the logic circuit 70.

The temperature sensor circuit 90 is a sensor circuit that detects temperature. Specifically, the temperature sensor circuit 90 outputs a temperature-dependent voltage that changes according to the temperature of the environment as the temperature detection voltage VT. For example, the temperature sensor circuit 90 generates the temperature detection voltage VT using a circuit element having temperature dependency. Specifically, the temperature sensor circuit 90 outputs the temperature detection voltage VT whose voltage value changes depending on the temperature by using the temperature dependency of the forward voltage of the PN junction. For example, the forward voltage of the PN junction can be the base-emitter voltage of a bipolar transistor. When performing digital temperature compensation processing, the temperature sensor circuit 90 measures a temperature such as the environmental temperature and outputs the result as temperature detection data. The temperature detection data is, for example, data that monotonically increases or decreases with respect to the temperature. In this case, the temperature sensor circuit 90 can be a temperature sensor circuit that utilizes the fact that the oscillation frequency of a ring oscillator has temperature dependency. Specifically, the temperature sensor circuit 90 includes a ring oscillator and a counter circuit. The counter circuit counts the output pulse signal, which is the oscillation signal of the ring oscillator, during a count period defined by a clock signal based on the oscillation signal OSC from the oscillation circuit 30, and outputs the count value as temperature detection data.

The output enable pad POE is a pad for controlling the output enable of the clock signal CKQ. Specifically, the output enable of the clock signal CKQ is controlled based on the output enable signal OE input via the output enable pad POE. The output enable pad POE is electrically connected to the external terminal TOE for external connection of the oscillator 4. For example, the logic circuit 70 receives the output enable signal OE from the output enable pad POE and controls the output enable of the clock signal CKQ in the output buffer circuit 50. For example, when the output enable signal OE becomes active, the clock signal CKQ is output from the output buffer circuit 50. On the other hand, when the output enable signal OE becomes inactive, the clock signal CKQ is set to a fixed voltage level, such as a low level. Note that an active signal is, for example, a high level in the case of positive logic, and a low level in the case of negative logic. Also, an inactive signal is, for example, a low level in the case of positive logic, and a high level in the case of negative logic.

The test circuit 92 is a circuit for testing the integrated circuit device 20. For example, the test circuit 92 is used to test circuit blocks such as analog circuits of the integrated circuit device 20. The interface circuit 94 is a circuit for performing serial interface communication. For example, in a test mode, the clock pad PCK becomes an input terminal for a serial clock signal, and the output enable pad POE becomes an input/output terminal for serial data. The interface circuit 94 performs serial interface communication, taking in serial data and outputting serial data in synchronization with the serial clock signal. The interface circuit 94 can be realized by a serial interface circuit such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit). By using such an interface circuit 94, for example, information used for temperature compensation can be written to the non-volatile memory 78.

Figure 3 shows a detailed configuration example of the PLL circuit 40. In Figure 3, the PLL circuit 40 is a fractional-N type PLL circuit that can fractionally multiply the frequency of the oscillation signal OSC.

The PLL circuit 40 includes a phase comparator 41, a charge pump circuit 42, a loop filter 43, a voltage controlled oscillator circuit 44, a frequency divider circuit 45, and an output frequency divider circuit 46. The logic circuit 70 includes a delta-sigma modulation circuit 72.

The phase comparator 41 of the PLL circuit 40 compares the phase of the oscillation signal OSC, which is a reference clock signal, with the feedback clock signal FCK from the frequency divider circuit 45, and outputs a phase comparison result signal. The phase comparison result signal is a signal corresponding to the phase difference between the oscillation signal OSC and the feedback clock signal FCK. Specifically, the phase comparator 41 outputs an up signal or a down signal as a phase comparison result signal. The charge pump circuit 42 converts the phase comparison result signal, which is an up signal or a down signal from the phase comparator 41, into an output current. That is, the up signal and the down signal, which are rectangular voltage pulses, are converted into an output current, which is a rectangular current pulse. For example, the charge pump circuit 42 outputs a positive current pulse when an up signal is input, and outputs a negative current pulse when a down signal is input. The loop filter 43 smoothes the output signal of the charge pump circuit 42, generates a control voltage that controls the oscillation frequency of the voltage controlled oscillator circuit 44, and outputs it to the voltage controlled oscillator circuit 44. Specifically, the loop filter 43 performs current-voltage conversion of the output current of the charge pump circuit 42 and performs filtering. The control voltage, which is the output voltage of the loop filter 43, rises when an up signal is output, and falls when a down signal is output. The loop filter 43 can be realized, for example, by a third or fourth order RC filter. That is, it can be realized by a passive RC filter using resistors and capacitors. The loop filter 43 may be a passive filter using an inductor as a passive element. Then, the control voltage from the loop filter 43 is input to the voltage controlled oscillator circuit 44, which changes the capacitance of a variable capacitance element realized by a varactor or the like, thereby controlling the oscillation frequency of the voltage controlled oscillator circuit 44, which is a VCO. Then, a clock signal CKV with a frequency set by the control voltage is output to the frequency divider circuit 45. The voltage controlled oscillator circuit 44 generates the clock signal CKV by, for example, a resonant circuit using an inductor.

In this embodiment, the frequency divider circuit 45 and the delta sigma modulation circuit 72 constitute a fractional frequency divider. The fractional frequency divider divides the clock signal CKV using the inverse of the multiplication rate of the PLL circuit 40 as the division ratio, and outputs the divided clock signal to the phase comparator 41 as the feedback clock signal FCK. The delta sigma modulation circuit 72 performs delta sigma modulation of the decimal part of the frequency division ratio to generate a modulation value that is an integer. For example, the delta sigma modulation circuit 72 performs third or fourth order delta sigma modulation processing. The sum of the integer part of the frequency division ratio and the modulation value is set in the frequency divider circuit 45 as the setting value of the frequency division ratio. This realizes the fractional-N type PLL circuit 40. The PLL circuit 40 is provided with an output frequency divider circuit 46, which divides the clock signal CKV from the voltage controlled oscillator circuit 44 and outputs the divided signal to the output buffer circuit 50 as the clock signal CK. The output buffer circuit 50 then outputs the buffered signal of the clock signal CK as the clock signal CKQ. Note that a modification that does not include the output divider circuit 46 is also possible.

3, regulators 65, 66, 67, and 68 are provided as regulator 64 in FIGS. 1 and 2. Regulator 65 generates regulated power supply voltage VREG1 and supplies it to oscillation circuit 30, temperature compensation circuit 80, and temperature sensor circuit 90. Regulator 66 generates regulated power supply voltage VREG2 and supplies it to charge pump circuit 42 of PLL circuit 40. Regulator 67 generates regulated power supply voltage VREG3 and supplies it to loop filter 43, voltage controlled oscillation circuit 44, and output divider circuit 46 of PLL circuit 40. Regulator 68 generates regulated power supply voltage VREG4 and supplies it to logic circuit 70, phase comparator 41, and divider circuit 45 of PLL circuit 40. For example, in the voltage controlled oscillator circuit 44 and the output divider circuit 46, high frequency noise is generated by the clock signal, and in the logic circuit 70, high frequency noise is generated by logic operation. Therefore, these circuits are operated by the regulated power supply voltage VREG3 from the regulator 67 and the regulated power supply voltage VREG4 from the regulator 68, while the oscillator circuit 30, the charge pump circuit 42, etc. are operated by the regulated power supply voltage VREG1 from the regulator 65 and the regulated power supply voltage VREG2 from the regulator 66. This prevents high frequency noise caused by the clock signal and logic operation from being transmitted to the oscillator circuit 30, the charge pump circuit 42, the temperature compensation circuit 80, etc., and prevents the accuracy of the clock frequency from decreasing due to the high frequency noise.

As described above, the integrated circuit device 20 of this embodiment includes an oscillator circuit 30 that generates an oscillation signal OSC using an oscillator 10, an output buffer circuit 50 that outputs a clock signal CKQ based on the oscillation signal OSC, a power supply pad PVDD, a ground pad PGND, and a clock pad PCK. It also includes a reference voltage generation circuit 62 that generates a DC voltage used to generate the oscillation signal OSC or the clock signal CKQ, and a DC voltage generation circuit 61 such as a regulator 64. The regulator 64 is, for example, regulators 65, 66, 67, 68, etc. as shown in FIG. 3.

And, it was found that such an integrated circuit device 20 has a problem that high-frequency noise is transmitted to the DC voltage generating circuit 61 due to electromagnetic coupling or electrostatic coupling between the output buffer circuit 50 or the clock pad PCK and the DC voltage generating circuit 61 such as the reference voltage generating circuit 62 or the regulator 64, resulting in a decrease in the accuracy of the clock frequency. Specifically, in the integrated circuit device 20, the oscillation signal OSC and the clock signal CKQ are generated based on the DC voltage such as the reference voltage and the regulated power supply voltage output by the DC voltage generating circuit 61. Therefore, when high-frequency noise is superimposed on this DC voltage, the accuracy of the oscillation frequency in the oscillation circuit 30 decreases, thereby decreasing the accuracy of the clock frequency, or the accuracy of the clock frequency decreases when generating a clock signal in the PLL circuit 40, etc., etc., resulting in a problem.

On the other hand, in recent years, the proportion of the total area of the integrated circuit device 20 that is occupied by the pad area has been increasing. In the integrated circuit device 20 used in the oscillator 4, no active circuitry was placed below the pads, so the locations of the pads were dead space in the integrated circuit device 20. Therefore, if the proportion of the pad area that is occupied by the pads in the total area of the integrated circuit device 20 increases, the dead space caused by the pads increases, which hinders miniaturization of the integrated circuit device 20. On the other hand, if the area of the pads is reduced in order to reduce the dead space caused by the pads, it becomes difficult to perform flip mounting or mounting by bonding wire, which will be described later. Therefore, in order to achieve stable mounting, it is not possible to adopt a method of reducing the dead space by further reducing the area of the pads.

Furthermore, if the distance between the DC voltage generating circuit 61, such as the reference voltage generating circuit 62 or regulator 64, and the ground pad PGND is large, when the ground wiring is shared with other circuits, potential fluctuations occur in the DC voltage output by the DC voltage generating circuit 61 due to the finite impedance of the ground wiring. For example, potential fluctuations occur in the reference voltage and regulated power supply voltage output by the reference voltage generating circuit 62 and regulator 64, which are the DC voltage generating circuit 61. When potential fluctuations occur in DC voltages such as the reference voltage and regulated power supply voltage, the accuracy of the frequency of the clock signal generated based on this DC voltage decreases.

Therefore, in this embodiment, as shown in FIG. 4, the ground pad PGND and the DC voltage generating circuit 61 are arranged so as to overlap in a planar view. Specifically, the ground pad PGND and the DC voltage generating circuit 61 are arranged so as to overlap in a planar view in the direction DR in FIG. 4. For example, the DC voltage generating circuit 61 is arranged on the direction DR side below the ground pad PGND. The direction DR is, for example, a direction perpendicular to the substrate PSUB, which is the semiconductor substrate of the integrated circuit device 20. Note that it is not necessary for all circuit parts of the ground pad PGND and the DC voltage generating circuit 61 to overlap in a planar view, and for example, the layout may be such that a part of the DC voltage generating circuit 61 does not overlap the ground pad PGND.

Figure 4 is a cross-sectional view showing the layout relationship between the ground pad PGND and the DC voltage generating circuit 61. The integrated circuit device 20 has a five-layer wiring structure of metal layers ALA to ALE made of aluminum or the like, and the pad metal 6 is formed by the top metal layer ALE. Specifically, the pad metal 6 is exposed from the passivation film 5 at the opening of the pad region, allowing for flip mounting or bonding wire mounting, which will be described later. In addition, a P-type well PWL and an N-type well NWL are formed on the P-type substrate PSUB, and N-type transistors constituting the DC voltage generating circuit 61 are formed in the P-type well PWL, and P-type transistors are formed in the N-type well NWL. Note that Figure 4 is a schematic diagram showing the layout relationship between the ground pad PGND and the DC voltage generating circuit 61. In reality, the layout area of the transistors relative to the layout area of the ground pad PGND is sufficiently small, and the number of transistors required to configure the DC voltage generating circuit 61 are arranged below the ground pad PGND.

Figure 5 is a cross-sectional view showing another example of the structure of the ground pad PGND. In Figure 5, conductive layers 7, 8, and 9 are formed on the pad metal 6 by, for example, plating. The conductive layer 7 is formed of a material that has good adhesion to the pad metal 6 formed of aluminum or an aluminum alloy, for example, nickel or a nickel alloy. The conductive layer 7 has a thickness of, for example, 2 μm to 10 μm. By increasing the thickness of the conductive layer 7 in this way, even if a large load is applied when bonding a bump or a bonding wire to the ground pad PGND, this load is less likely to be transmitted below the ground pad PGND. Therefore, it is possible to prevent a situation in which a malfunction occurs in the DC voltage generating circuit 61 provided below the ground pad PGND due to the load when bonding the bump or the bonding wire. The conductive layer 8 is interposed between the conductive layer 7 and the conductive layer 9, and functions as a barrier layer that increases the adhesion between the conductive layers 7 and 9 and prevents the conductive layer 7 from diffusing into the conductive layer 9. The conductive layer 8 is formed of a material that has good adhesion to both the conductive layer 7 and the conductive layer 9, for example, palladium or a palladium alloy. The conductive layer 8 may be provided as necessary, and may be omitted, for example, when the adhesion between the conductive layer 7 and the conductive layer 9 is good. The conductive layer 9 functions as a connection layer with the bump or bonding wire. The conductive layer 9 is formed of a material that has low contact resistance with the bump or bonding wire, for example, gold or a gold alloy. By using the ground pad PGND having the structure shown in FIG. 5, it is possible to protect the DC voltage generating circuit 61 under the pad against the load applied during mounting when the bump or bonding wire is joined to the ground pad PGND, and it is possible to join the bump or bonding wire with low contact resistance, which makes it possible to facilitate mounting and improve reliability.

As described above, in this embodiment, in an integrated circuit device 20 having an oscillator circuit 30, an output buffer circuit 50, a DC voltage generating circuit 61, a power supply pad PVDD, a ground pad PGND, and a clock pad PCK, the ground pad PGND and the DC voltage generating circuit 61 are arranged so as to overlap in a planar view.

In this way, the ground pad PGND functions as a shielding member, making it possible to suppress the transmission of high-frequency noise to the DC voltage generating circuit 61. For example, the shielding effect of the ground pad PGND can reduce electromagnetic and electrostatic coupling between the output buffer circuit 50 or the clock pad PCK and the DC voltage generating circuit 61, preventing high-frequency noise from being superimposed on the DC voltage output by the DC voltage generating circuit 61. This makes it possible to prevent problems such as a decrease in the accuracy of the oscillation frequency, resulting in a decrease in the accuracy of the clock frequency, or a decrease in the accuracy of the clock frequency when a clock signal is generated, caused by high-frequency noise. As a result, it becomes possible to realize an integrated circuit device 20 that can generate a highly accurate clock signal CKQ.

In addition, by arranging the ground pad PGND and the DC voltage generating circuit 61 so that they overlap in a planar view, the area of the ground pad PGND can be effectively utilized to arrange the DC voltage generating circuit 61. This prevents the area of the ground pad PGND from becoming dead space. In this way, by arranging the DC voltage generating circuit 61 in the area of the ground pad PGND, which would otherwise be dead space, it is possible to reduce the layout area of the integrated circuit device 20 even if the proportion of the pad area in the total area of the integrated circuit device 20 becomes high, and the integrated circuit device 20 can be made smaller.

In addition, by arranging the ground pad PGND and the DC voltage generating circuit 61 so as to overlap in a plan view, the ground voltage from the ground pad PGND can be supplied to the DC voltage generating circuit 61 through the short-path ground wiring route from the ground pad PGND to the DC voltage generating circuit 61 arranged directly below it. That is, the ground voltage from the ground pad PGND can be supplied to the DC voltage generating circuit 61 through the short-path second ground wiring route separated from the first ground wiring that connects the ground pad PGND to other circuits located far from the ground pad PGND. For example, the ground voltage from the ground pad PGND can be supplied through the second ground wiring route with an extremely small impedance. Therefore, it is possible to prevent the potential fluctuation caused by the impedance of the first ground wiring that connects the ground pad PGND to other circuits located far from the ground pad PGND from adversely affecting the DC voltage output by the DC voltage generating circuit 61. As a result, it becomes possible to prevent the accuracy of the clock frequency from decreasing due to this potential fluctuation, and it becomes possible to realize an integrated circuit device 20 that can generate a highly accurate clock signal CKQ.

Here, the DC voltage generating circuit 61 arranged below the ground pad PGND is a circuit that generates a DC voltage used to generate the oscillation signal OSC or the clock signal CKQ. For example, the DC voltage generating circuit 61 is a circuit that generates a DC voltage such as a reference voltage or a frequency control voltage that is input to the oscillation circuit 30. Alternatively, the DC voltage generating circuit 61 is a circuit that generates a DC voltage such as a reference voltage or a frequency control voltage that is input to a frequency control voltage generating circuit such as a temperature compensation circuit 80 that controls the oscillation frequency of the oscillation circuit 30. Alternatively, the DC voltage generating circuit 61 is a circuit that generates a DC voltage used in the PLL circuit 40 that operates based on the oscillation signal OSC from the oscillation circuit 30.

Specifically, the DC voltage generating circuit 61 is, for example, a reference voltage generating circuit 62 that generates a reference voltage for generating at least one of a bias current, a bias voltage, or a regulated power supply voltage. That is, the ground pad PGND and the reference voltage generating circuit 62, which is the DC voltage generating circuit 61, are arranged so as to overlap in a plan view. In this way, the shielding effect of the ground pad PGND reduces electromagnetic coupling and electrostatic coupling between the output buffer circuit 50 and the clock pad PCK and the reference voltage generating circuit 62, thereby preventing high-frequency noise from being superimposed on the reference voltage output by the reference voltage generating circuit 62. Therefore, it is possible to prevent the accuracy of the clock frequency from decreasing due to high-frequency noise. In addition, since the reference voltage generating circuit 62 can be arranged by effectively utilizing the area of the ground pad PGND, it is possible to reduce the layout area of the integrated circuit device 20, and the integrated circuit device 20 can be made smaller. In addition, the ground voltage from the ground pad PGND can be supplied to the reference voltage generating circuit 62 via the second ground wiring route, which is a short path separated from the first ground wiring that connects the ground pad PGND to other circuits located far away from the ground pad PGND. Therefore, it is possible to suppress the potential fluctuation caused by the impedance of the first ground wiring that connects the ground pad PGND to other circuits, from being transmitted to the reference voltage of the reference voltage generating circuit 62, and it is possible to prevent the accuracy of the clock frequency from decreasing due to this potential fluctuation.

Alternatively, the DC voltage generating circuit 61 may be a regulator 64 that generates a regulated power supply voltage based on the power supply voltage VDD. That is, the ground pad PGND and the regulator 64, which is the DC voltage generating circuit 61, are arranged so as to overlap in a plan view. In this way, the shielding effect of the ground pad PGND can prevent high-frequency noise from being superimposed on the regulated power supply voltage output by the regulator 64, and it becomes possible to prevent the accuracy of the clock frequency from decreasing due to high-frequency noise. In addition, since the regulator 64 can be arranged by effectively utilizing the area of the ground pad PGND, it is possible to realize a miniaturization of the integrated circuit device 20. In addition, it is possible to suppress the transmission of potential fluctuations caused by the impedance of the ground wiring that connects other circuits to the ground pad PGND to the regulated power supply voltage of the regulator 64, and it becomes possible to prevent the accuracy of the clock frequency from decreasing due to this potential fluctuation.

3, the integrated circuit device 20 includes a PLL circuit 40 that generates a clock signal CK based on an oscillation signal OSC, and the PLL circuit 40 includes a phase comparator 41, a charge pump circuit 42, and a loop filter 43. In this case, the DC voltage generation circuit 61 arranged to overlap the ground pad PGND in a planar view may be the charge pump circuit 42, the loop filter 43, or a regulator 66 that supplies a regulated power supply voltage VREG2 to the charge pump circuit 42. That is, the ground pad PGND and the charge pump circuit 42, the loop filter 43, or the regulator 66 that are the DC voltage generation circuit 61 are arranged to overlap in a planar view. In this way, the shielding effect of the ground pad PGND can prevent high-frequency noise from being superimposed on the output voltage of the charge pump circuit 42, the loop filter 43, or the regulator 66, and it becomes possible to prevent the accuracy of the clock frequency from decreasing due to high-frequency noise. In addition, the area of the ground pad PGND can be effectively utilized to place the charge pump circuit 42, the loop filter 43, or the regulator 66, thereby realizing a smaller integrated circuit device 20. In addition, it is possible to suppress the transmission of potential fluctuations caused by the impedance of the ground wiring that connects other circuits to the ground pad PGND to the output voltage of the charge pump circuit 42, the loop filter 43, or the regulator 66, and it is possible to prevent the accuracy of the clock frequency from decreasing due to these potential fluctuations.

Figure 6 shows an example of the configuration of the reference voltage generating circuit 62. The reference voltage generating circuit 62 in Figure 6 includes an N-type transistor TD1, resistors RD1, RD2, RD3, and bipolar transistors BP1 and BP2 arranged between the VDD node and the GND node. The reference voltage generating circuit 62 also includes P-type transistors TD2 and TD3, the gate of which is input with a bias voltage VB, and a bipolar transistor BP3 arranged between the drain node of the transistor TD2 and the GND node. The reference voltage generating circuit 62 is a bandgap reference circuit, and generates and outputs a reference voltage VREF based on a bandgap voltage. For example, the base-emitter voltages of the PNP bipolar transistors BP1 and BP2 are VBE1 and VBE2, respectively, and ΔVBE = VBE1 - VBE2. The reference voltage generating circuit 62 outputs a reference voltage VREF, for example, VREF = K x ΔVBE + VBE2. K is set by the resistance values of resistors RD1 and RD2. For example, VBE2 has a negative temperature characteristic and ΔVBE has a positive temperature characteristic, so by adjusting the resistance values of resistors RD1 and RD2, it becomes possible to generate a constant reference voltage VREF that is not temperature dependent. The generated reference voltage VREF is then a constant voltage based on the ground voltage.

Figure 7 shows another example of the configuration of the reference voltage generating circuit 62. The reference voltage generating circuit 62 in Figure 7 is also a bandgap reference circuit, and includes N-type transistors TE1 and TE2, P-type transistors TE3, TE4, and TE5, resistors RE1 and RE2, and diodes DI1, DI2, and DI3 having PN junctions. The N-type transistors TE1 and TE2 form a current mirror circuit, and the P-type transistors TE3, TE4, and TE5 also form a current mirror circuit, so that the currents flowing through these transistors are almost equal. The source voltages of the N-type transistors TE1 and TE2 are also almost equal. The number of parallel connections of the PN junctions in the diode DI2 is formed to be M times the number of parallel connections of the PN junctions in the diode DI1. Therefore, when the saturation current of the diode DI1 is Is, the saturation current of the diode DI2 is M x Is. Here, if the current flowing through transistors TE3, TE4, and TE5 is I, the voltages across diodes DI1, DI2, and DI3 are Vd1, Vd2, and Vd3, respectively, and the resistances of resistors RE1 and RE2 are R1 and R2, then the reference voltage VREF generated by the reference voltage generation circuit 62 is expressed by the following equation (1).

VREF=I・R2+Vd3
=(R2/R1)・(kT/q)・In(M)+Vd3 (1)
Here, k is the Boltzmann constant, T is the absolute temperature, and q is the charge of an electron. Differentiating the above formula (1) with respect to the absolute temperature T gives the following formula (2).

dVREF/dT=(R2/R1)・(k/q)・In(M)+Vd3/dT (2)
In the above formula (2), the term Vd3/dT has a negative temperature characteristic, and the value of (R2/R1)·(k/q)·In(M) is adjusted to a positive value accordingly. By doing so, the value of the above formula (2) can be set to zero, and it becomes possible to generate a reference voltage VREF whose temperature dependency is cancelled. However, the reference voltage VREF is not limited to the above, and may be of various configurations, such as a circuit that generates the reference voltage VREF by using a work function difference voltage of a transistor.

Figure 8 shows an example of the configuration of the regulator 64. The regulator 64 includes an N-type driving transistor TA1 and resistors RA1 and RA2 arranged in series between the VDD node and the GND node, and an operational amplifier OPA. The regulator 64 may also include a resistor RA3 and a capacitor CA arranged on the output terminal side of the operational amplifier OPA. A reference voltage VREF is input to the non-inverting input terminal of the operational amplifier OPA, and a voltage VDA obtained by dividing the regulated power supply voltage VREG by resistors RA1 and RA2 is input to the inverting input terminal. The output terminal of the operational amplifier OPA is input to the gate of the transistor TA1 via resistor RA3, and the regulated power supply voltage VREG is output from the drain node of the transistor TA1. Figure 9 shows another example of the configuration of the regulator 64. In FIG. 9, unlike FIG. 8, the driving transistor is a P-type transistor TA2, a reference voltage VREF is input to the inverting input terminal of the operational amplifier OPA, and a voltage VDA is input to the non-inverting input terminal. Also, in FIG. 9, the connection configuration of the phase compensation capacitor CA is different from that in FIG. 8. The regulators 65, 66, 67, and 68 described in FIG. 3 can be realized by, for example, a regulator 64 configured as shown in FIG. 8 and FIG. 9.

As described above, the reference voltage generating circuit 62 and regulator 64 generate the reference voltage VREF and regulated power supply voltage VREG based on the ground voltage. Therefore, when high-frequency noise from the output buffer circuit 50, etc. is superimposed on the ground voltage, the potentials of the reference voltage VREF and regulated power supply voltage VREG also fluctuate. For this reason, it is essential to take measures to prevent high-frequency noise from the output buffer circuit 50, etc. from being superimposed on the ground voltage.

Figure 10 shows an example of the configuration of the temperature sensor circuit 90. The temperature sensor circuit 90 includes a current source IST and a bipolar transistor BPT that are connected in series between a power supply node and a GND node. The collector node and base node of the bipolar transistor BPT are connected to form a diode connection. This allows a temperature detection voltage VT having temperature dependency to be output from the output node NCQ of the temperature sensor circuit 90. For example, a temperature detection voltage VT having a negative temperature characteristic generated by the temperature dependency of the base-emitter voltage is output. Note that the configuration of the temperature sensor circuit 90 is not limited to the configuration of Figure 10, and various modifications are possible. For example, a resistor may be provided between the output node NCQ of the temperature sensor circuit 90 and the collector node of the bipolar transistor BPT, and a variable resistor may be provided between the emitter node of the bipolar transistor BPT and the GND node. With this configuration, it is possible to realize zero-order correction of temperature compensation using the temperature sensor circuit 90.

Figure 11 shows an example of the configuration of the temperature compensation circuit 80. The temperature compensation circuit 80 includes a zero-order correction circuit 82, a primary correction circuit 84, a high-order correction circuit 86, and a current-voltage conversion circuit 88. For example, when performing third-order correction, fourth-order correction, fifth-order correction, etc., a plurality of correction circuits, such as a third-order correction circuit, a fourth-order correction circuit, and a fifth-order correction circuit, are provided as the high-order correction circuit 86. The high-order correction circuit 86 is also called a function generating circuit, and generates a function current corresponding to a polynomial that approximates the characteristics of the temperature compensation voltage VCP. For example, the polynomial is a function with temperature as a variable.

The temperature compensation circuit 80 performs analog temperature compensation using polynomial approximation. Specifically, the temperature compensation circuit 80 generates and outputs a temperature compensation voltage VCP by approximating a polynomial, which is a function with temperature as a variable. For example, the non-volatile memory 78 in FIG. 2 stores the zeroth-order coefficient, the first-order coefficient, and the high-order coefficient of a polynomial that approximates the characteristics of the temperature compensation voltage VCP as zeroth-order correction data, first-order correction data, and high-order correction data. The zeroth-order correction circuit 82, the first-order correction circuit 84, and the high-order correction circuit 86 output a zeroth-order correction current signal, a first-order correction current signal, and a high-order correction current signal based on the zeroth-order correction data, the first-order correction data, and the high-order correction data. The zeroth-order correction current signal, the first-order correction current signal, and the high-order correction current signal can be said to be the zeroth-order component signal, the first-order component signal, and the high-order component signal of the function current. Based on the temperature detection voltage VT, which changes linearly with temperature, the primary correction circuit 84 and the high-order correction circuit 86 generate and output a primary correction current signal and a high-order correction current signal. The current-voltage conversion circuit 88 performs an addition process of the zeroth-order correction current signal, the primary correction current signal, and the high-order correction current signal, and also performs current-voltage conversion to output a temperature compensation voltage VCP. This realizes analog temperature compensation using polynomial approximation. Note that when zeroth-order correction of temperature compensation is performed using the temperature sensor circuit 90 as described above, the configuration of the zeroth-order correction circuit 82 can be omitted.

2. Layout arrangement FIG. 12 shows an example of the layout arrangement of the integrated circuit device 20 of this embodiment. The external shape of the integrated circuit device 20 includes a side SD1 and a side SD2 opposite to the side SD1. The side SD1 is the first side, the side SD2 is the second side, and the side SD2 is the opposite side to the side SD1. The external shape of the integrated circuit device 20 also includes sides SD3 and SD4 intersecting the sides SD1 and SD2. The side SD3 is the third side, the side SD4 is the fourth side, and the side SD4 is the opposite side to the side SD3. The external shape of the integrated circuit device 20 is the external shape of, for example, a rectangular semiconductor chip which is the integrated circuit device 20. For example, the sides SD1, SD2, SD3, and SD4 are the sides of the substrate of the semiconductor chip. The semiconductor chip is also called a silicon die. Here, the direction from the side SD1 toward the side SD2 is defined as DR1, and the direction from the side SD3 toward the side SD4 is defined as DR2. The direction opposite to the direction DR1 is a direction DR3, and the direction opposite to the direction DR2 is a direction DR4. The directions DR1, DR2, DR3, and DR4 are the first direction, the second direction, the third direction, and the fourth direction, respectively.

As shown in FIG. 12, the integrated circuit device 20 is provided with a ground pad PGND, a power pad PVDD, a clock pad PCK, an output enable pad POE, and pads PX1 and PX2 for connecting an oscillator. For example, the power pad PVDD is arranged at a first corner where the sides SD1 and SD3 intersect. The output enable pad POE is arranged at a second corner where the sides SD2 and SD3 intersect. The clock pad PCK is arranged on the side SD1, and the ground pad PGND is arranged on the side SD2. For example, the clock pad PCK is arranged in a first region between the center line of the sides SD1 and SD2 and the side SD1, and the ground pad PGND is arranged in a second region between the center line of the sides SD1 and SD2 and the side SD2. The pads PX1 and PX2 for connecting an oscillator are arranged along the side SD3 between the power pad PVDD and the output enable pad POE. For example, the oscillator circuit 30 and pads PX1 and PX2 are arranged in the area along side SD3.

In FIG. 12, the reference voltage generation circuit 62 is arranged as the DC voltage generation circuit 61 so as to overlap the ground pad PGND in a plan view. That is, as explained in FIG. 4 and FIG. 5, the reference voltage generation circuit 62 is arranged below the ground pad PGND. In this way, the shielding effect of the ground pad PGND suppresses the transmission of high-frequency noise to the reference voltage generation circuit 62, and it is possible to prevent potential fluctuations in the reference voltage generated by the reference voltage generation circuit 62, which would result in a decrease in the accuracy of the clock frequency. In addition, the reference voltage generation circuit 62 can be arranged by effectively utilizing the placement area of the ground pad PGND, thereby realizing a reduction in the area of the integrated circuit device 20.

As shown in FIG. 12, in the integrated circuit device 20 of this embodiment, the clock pad PCK and the output buffer circuit 50 are arranged to overlap in a planar view. That is, similar to the positional relationship of the ground pad PGND and the DC voltage generating circuit 61 in FIGS. 4 and 5, the output buffer circuit 50 is arranged below the clock pad PCK. Note that it is not necessary for all circuit parts of the output buffer circuit 50 to overlap with the clock pad PCK in a planar view, and for example, the layout may be such that a portion of the output buffer circuit 50 does not overlap with the clock pad PCK.

In this way, by arranging the clock pad PCK and the output buffer circuit 50 so that they overlap in a plan view, the clock signal CKQ from the output buffer circuit 50 can be output to the clock pad PCK through a short-path clock wiring route from the output buffer circuit 50 to the clock pad PCK arranged directly above it. This makes it possible to minimize the impedance of the clock wiring and suppress the potential fluctuation caused by the impedance. The output buffer circuit 50 has high driving capability because it needs to drive a large external load. Therefore, if the impedance of the clock wiring is high, the potential fluctuation will also be large, and the signal quality of the clock signal CKQ will deteriorate. In this regard, if the clock pad PCK and the output buffer circuit 50 are arranged so that they overlap in a plan view, the clock wiring route connecting the output buffer circuit 50 and the clock pad PCK can be a short-path route, and the impedance of the clock wiring can be minimized, making it possible to suppress deterioration of the signal quality of the clock signal CKQ. In addition, because the output buffer circuit 50 has a high driving capability so that it can drive an external load, it generates a large amount of high-frequency noise, and the output buffer circuit 50 and the clock pad PCK from which the clock signal CKQ is output become sources of high-frequency noise. In this regard, if the clock pad PCK and the output buffer circuit 50 are arranged so that they overlap in a plan view, such high-frequency noise sources can be arranged together in one place. This makes it easy to implement measures such as layout arrangements to reduce the adverse effects of noise from these high-frequency noise sources.

As shown in FIG. 12, the external shape of the integrated circuit device 20 includes a side SD1 and a side SD2 opposite to side SD1, with the output buffer circuit 50 and clock pad PCK arranged on the side SD1, and the reference voltage generation circuit 62, which is a DC voltage generation circuit 61, and the ground pad PGND arranged on the side SD2. Side SD1 is the first side, and side SD2 is the second side. For example, the output buffer circuit 50 and the clock pad PCK are arranged at a location closer to side SD1 than side SD2. Furthermore, the reference voltage generation circuit 62, which is a DC voltage generation circuit 61, and the ground pad PGND are arranged at a location closer to side SD2 than side SD1. For example, the output buffer circuit 50 and the clock pad PCK are arranged in a first region between the side SD1 and the center line of the sides SD1 and SD2, and the reference voltage generating circuit 62 and the ground pad PGND are arranged in a second region between the side SD2 and the center line of the sides SD1 and SD2. In this way, the output buffer circuit 50 and the clock pad PCK, which are high-frequency noise sources, are arranged on the side SD1, while the reference voltage generating circuit 62 and the ground pad PGND, which need to avoid high-frequency noise, are arranged on the side SD2. This makes it possible to separate the output buffer circuit 50 and the clock pad PCK, which are high-frequency noise sources, from the reference voltage generating circuit 62 and the ground pad PGND. Therefore, it is possible to suppress the transmission of high-frequency noise from the output buffer circuit 50 and the clock pad PCK to the reference voltage generating circuit 62 and the ground pad PGND, and to prevent deterioration of the accuracy of the clock frequency caused by high-frequency noise.

The integrated circuit device 20 also includes a PLL circuit 40 that performs a PLL operation to generate a clock signal CKQ that is phase-synchronized with the oscillation signal OSC. For example, the PLL circuit 40 outputs a clock signal CK that is phase-synchronized with the oscillation signal OSC, and the output buffer circuit 50 buffers the clock signal CK and outputs it as a clock signal CKQ. This causes the clock signal CKQ that is phase-synchronized with the oscillation signal OSC to be output from the integrated circuit device 20. The DC voltage generation circuit 61 is a reference voltage generation circuit 62 that generates a reference voltage used for the operation of the PLL circuit 40. Taking FIG. 3 as an example, the regulators 66 and 67 generate regulated power supply voltages VREG2 and VREG3 based on the reference voltage VREF generated by the reference voltage generation circuit 62, and the PLL circuit 40 operates based on these regulated power supply voltages VREG2 and VREG3. Alternatively, the charge pump circuit 42 and the voltage controlled oscillator circuit 44 of the PLL circuit 40 perform charge pump operation and oscillation operation based on a bias current and a bias voltage based on the reference voltage VREF generated by the reference voltage generating circuit 62. By providing such a PLL circuit 40, the integrated circuit device 20 can output a clock signal CKQ that is phase-synchronized with the oscillation signal OSC and has a desired frequency. The reference voltage generating circuit 62 that generates the reference voltage required for the operation of the PLL circuit 40 is arranged so as to overlap the ground pad PGND in a plan view. This makes it possible to prevent a decrease in the accuracy of the clock frequency caused by high-frequency noise, and to realize a reduction in the size of the integrated circuit device 20 by arranging the reference voltage generating circuit 62 in a way that effectively utilizes the area of the ground pad PGND.

As described in FIG. 3, the PLL circuit 40 includes a phase comparator 41, a charge pump circuit 42, and a loop filter 43. As shown in FIG. 12, the charge pump circuit 42 is provided on the side SD2, which is the second side. For example, in FIG. 12, the charge pump circuit 42 is provided between the side SD2 and the ground pad PGND. For example, if the direction from the side SD1 to the side SD2 is DR1, the charge pump circuit 42 is arranged on the direction DR1 side of the ground pad PGND. Specifically, the charge pump circuit 42 is arranged along the side SD2 together with the phase comparator 41. In other words, it is arranged so that its long side direction is along the side SD2. In this way, the charge pump circuit 42 can be arranged together with the reference voltage generating circuit 62 and the ground pad PGND on the side SD2. Therefore, the charge pump circuit 42, the reference voltage generating circuit 62, and the ground pad PGND can be arranged together at a distance from the output buffer circuit 50 and the clock pad PCK arranged on the side SD1. Therefore, it is possible to suppress the transmission of high-frequency noise from the output buffer circuit 50 and the clock pad PCK to the charge pump circuit 42, the reference voltage generating circuit 62, and the ground pad PGND, and to prevent the deterioration of the accuracy of the clock frequency caused by the high-frequency noise. That is, as shown in FIG. 3, there is a capacitive coupling due to the parasitic capacitance CP between the output of the output buffer circuit 50 and the output of the charge pump circuit 42, and this capacitive coupling may cause the high-frequency noise from the output buffer circuit 50 to be superimposed on the output signal of the charge pump circuit 42. If high-frequency noise is superimposed on the output signal of the charge pump circuit 42, the potential of the control voltage input to the voltage controlled oscillator circuit 44 fluctuates, and the accuracy of the clock frequency of the clock signal CK output by the PLL circuit 40 decreases, and the accuracy of the clock frequency of the clock signal CKQ output by the integrated circuit device 20 also decreases. In this regard, by arranging the charge pump circuit 42 on the side SD2, it is possible to increase the distance from the output buffer circuit 50 and clock pad PCK arranged on the side SD1, and the transmission of noise from these high-frequency noise sources can be suppressed, thereby preventing a decrease in the accuracy of the clock frequency.

As shown in FIG. 12, the loop filter 43 is provided on the side SD2. For example, in FIG. 12, the loop filter 43 is provided at the third corner where the sides SD2 and SD4 intersect. For example, if the direction from the side SD3 to the side SD4 is DR2, the loop filter 43 is provided on the DR2 side of the ground pad PGND and the charge pump circuit 42. In this way, the loop filter 43 can be arranged together with the charge pump circuit 42, the reference voltage generating circuit 62, and the ground pad PGND on the side SD2. Therefore, the loop filter 43, the charge pump circuit 42, the reference voltage generating circuit 62, and the ground pad PGND can be arranged together at a distance from the output buffer circuit 50 and the clock pad PCK arranged on the side SD1. Therefore, it is possible to prevent high-frequency noise from the output buffer circuit 50 and the clock pad PCK from being transmitted to the loop filter 43, the charge pump circuit 42, the reference voltage generation circuit 62, and the ground pad PGND, and to prevent deterioration of the accuracy of the clock frequency caused by high-frequency noise.

3, the integrated circuit device 20 also includes a regulator 66 that supplies the regulated power supply voltage VREG2 generated based on the reference voltage VREF to the charge pump circuit 42. The regulator 66 is provided on the side SD2. For example, if high-frequency noise is superimposed on the output signal of the charge pump circuit 42, the potential of the control voltage input to the voltage-controlled oscillator circuit 44 fluctuates, and the accuracy of the clock frequency of the clock signal CK output by the PLL circuit 40 decreases. For this reason, in this embodiment, a regulator 66 is provided for the charge pump circuit 42, and the charge pump circuit 42 is operated by the regulated power supply voltage VREG2 generated by this regulator 66. However, if high-frequency noise from the output buffer circuit 50 or the like is superimposed on the regulated power supply voltage VREG2, the high-frequency noise is also superimposed on the output signal of the charge pump circuit 42, and the accuracy of the clock frequency of the clock signal CK output by the PLL circuit 40 decreases, and the accuracy of the clock frequency of the clock signal CKQ output by the integrated circuit device 20 also decreases. In this regard, in FIG. 12, not only the charge pump circuit 42 but also the regulator 66 that supplies the regulated power supply voltage VREG2 to the charge pump circuit 42 are arranged together on the side SD2. In this way, it is possible to separate the regulator 66 from the high-frequency noise source such as the output buffer circuit 50. This makes it possible to suppress the superimposition of high-frequency noise on the regulated power supply voltage VREG2, and to prevent a decrease in the accuracy of the clock frequency. In addition, the regulated power supply voltage VREG2 from the regulator 66 can be supplied to the charge pump circuit 42 via a short-path power supply line, which makes it possible to suppress fluctuations in the regulated power supply voltage VREG2 caused by the impedance of the power supply line.

In FIG. 12, the regulator 65 that supplies the regulated power supply voltage VREG1 to the oscillator circuit 30 and the like is arranged on the side SD3. For example, the regulator 65 is arranged along the side SD3 between the side SD1 and the oscillator circuit 30, and is arranged in the vicinity of the oscillator circuit 30. This allows the regulated power supply voltage VREG1 from the regulator 65 to be supplied to the oscillator circuit 30 and the like through a short-path power supply line, making it possible to suppress fluctuations in the regulated power supply voltage VREG1 caused by the impedance of the power supply line. In addition, the regulator 67 that supplies the regulated power supply voltage VREG3 to the voltage-controlled oscillator circuit 44 and the like is arranged on the side SD1. For example, the regulator 67 is arranged between the side SD1 and the voltage-controlled oscillator circuit 44. In addition, the regulator 68 that supplies the regulated power supply voltage VREG4 to the logic circuit 70 and the like is also arranged on the side SD1. For example, the regulator 68 is arranged between the logic circuit 70 and the temperature compensation circuit 80, and is arranged in the vicinity of the logic circuit 70. This allows the regulated power supply voltages VREG3 and VREG4 from the regulators 67 and 68 to be supplied to the voltage controlled oscillator circuit 44, logic circuit 70, etc. via a short-path power supply line, making it possible to suppress fluctuations in the regulated power supply voltages VREG3 and VREG4 caused by the impedance of the power supply line.

The integrated circuit device 20 also includes a logic circuit 70 that controls the PLL circuit 40. Taking FIG. 3 as an example, the logic circuit 70 controls the setting of the division ratio of the divider circuit 45 of the PLL circuit 40 by delta-sigma modulation. Alternatively, the logic circuit 70 may control the enable and disable of the operation of the PLL circuit 40, or control the setting of various operation modes of the PLL circuit 40. In FIG. 12, the logic circuit 70 that controls the PLL circuit 40 is provided on the side SD1. For example, the logic circuit 70 operates based on a clock signal for logic, and generates high-frequency noise due to the logic operation. If this high-frequency noise is superimposed on the reference voltage generated by the reference voltage generation circuit 62 or the output signal of the charge pump circuit 42, a problem of reduced accuracy of the clock frequency occurs. In this regard, in FIG. 12, the logic circuit 70 is also arranged together with the output buffer circuit 50 and the like on the side SD1. This makes it possible to increase the distance between the reference voltage generation circuit 62, charge pump circuit 42, etc., which are arranged on the side SD2, and the logic circuit 70, output buffer circuit 50, etc., which are sources of high-frequency noise, and prevents a decrease in the accuracy of the clock frequency caused by high-frequency noise.

As shown in FIG. 3, the PLL circuit 40 includes a voltage-controlled oscillator circuit 44. For example, the PLL circuit 40 includes a voltage-controlled oscillator circuit 44 that performs an oscillation operation at an oscillation frequency according to the control voltage from the loop filter 43 and outputs a clock signal CKV. As shown in FIG. 12, the voltage-controlled oscillator circuit 44 is provided between the clock pad PCK and the ground pad PGND. For example, the voltage-controlled oscillator circuit 44 is provided on the DR1 side of the clock pad PCK, and the ground pad PGND is provided on the DR1 side of the voltage-controlled oscillator circuit 44. In this way, the area between the clock pad PCK and the ground pad PGND can be effectively used to arrange the voltage-controlled oscillator circuit 44, enabling an efficient layout arrangement. In addition, the clock signal CKV generated by the voltage-controlled oscillator circuit 44 can be input to the output buffer circuit 50 as a clock signal CK via the output divider circuit 46, for example, through a short-path clock signal wiring. Then, the output buffer circuit 50 can output a signal obtained by buffering this clock signal CK as a clock signal CKQ. For example, shortening the clock signal wiring also makes it possible to reduce high-frequency noise generated from the clock signal wiring. The voltage-controlled oscillator circuit 44 has a resonant circuit that uses an inductor, and most of the layout area of the voltage-controlled oscillator circuit 44 is the layout area for the inductor. This inductor is realized, for example, by wiring a metal wire in a spiral shape.

The external shape of the integrated circuit device 20 also includes a side SD3, which is a third side intersecting the sides SD1 and SD2, and the oscillator circuit 30 is provided on the side SD3. For example, the oscillator circuit 30 is provided along the side SD3. Specifically, the oscillator circuit 30 is arranged so that, for example, the long side of the oscillator circuit 30 is along the side SD3. By arranging the oscillator circuit 30 on the side SD3 in this way, the distance between the output buffer circuit 50 and the oscillator circuit 30 arranged on the side SD1 side can be increased, and it is possible to prevent a situation in which high-frequency noise from the output buffer circuit 50 is superimposed on the oscillation signal OSC and the oscillation characteristics are deteriorated. In addition, by arranging the oscillator circuit 30 on the side SD3 side, the distance between the reference voltage generation circuit 62 and the oscillator circuit 30 arranged on the side SD2 side can be increased, and it is possible to prevent a situation in which the oscillation noise from the oscillator circuit 30 is superimposed on the reference voltage of the reference voltage generation circuit 62 and the accuracy of the clock frequency is reduced.

The integrated circuit device 20 also includes a temperature compensation circuit 80 that performs temperature compensation for the oscillation frequency of the oscillation signal OSC. As shown in FIG. 12, the temperature compensation circuit 80 is provided between the oscillation circuit 30 and the clock pad PCK and ground pad PGND. For example, the temperature compensation circuit 80 is provided on the DR2 side of the oscillation circuit 30, and the clock pad PCK and ground pad PGND are provided on the DR2 side of the temperature compensation circuit 80. The temperature compensation circuit 80 is also provided between the oscillation circuit 30 and the voltage controlled oscillation circuit 44, and the temperature compensation circuit 80 is provided on the DR2 side of the oscillation circuit 30, and the voltage controlled oscillation circuit 44 is provided on the DR2 side of the temperature compensation circuit 80. By providing the temperature compensation circuit 80 between the oscillation circuit 30 and the clock pad PCK and ground pad PGND in this way, the temperature compensation circuit 80 can be arranged by effectively utilizing the area between the oscillation circuit 30 and the clock pad PCK and ground pad PGND, making it possible to arrange the temperature compensation circuit 80 in an efficient layout. It also becomes possible to place the temperature compensation circuit 80 near the oscillation circuit 30, and the temperature compensation voltage VCP from the temperature compensation circuit 80 can be input to the oscillation circuit 30 via a short-path signal path, thereby realizing temperature compensation of the oscillation frequency.

The integrated circuit device 20 also includes a temperature sensor circuit 90 for detecting temperature, a temperature compensation circuit 80 for performing temperature compensation of the oscillation frequency of the oscillation signal OSC based on the output of the temperature sensor circuit 90, and an output enable pad POE for controlling the output enable of the clock signal CKQ. As shown in FIG. 12, the temperature sensor circuit 90 and the output enable pad POE are arranged so as to overlap in a plan view. That is, as described in FIG. 4 and FIG. 5, the temperature sensor circuit 90 is arranged below the output enable pad POE. In this way, the area of the output enable pad POE can be effectively utilized to arrange the temperature sensor circuit 90, and the area of the output enable pad POE can be prevented from becoming a dead space. In this way, by arranging the temperature sensor circuit 90 in the area of the output enable pad POE, which would otherwise be a dead space, it is possible to reduce the layout area of the integrated circuit device 20 even when the proportion of the pad area in the total area of the integrated circuit device 20 becomes high, and the integrated circuit device 20 can be made smaller. In addition, if the temperature sensor circuit 90 and the output enable pad POE are arranged so as to overlap in a plan view, the output enable pad POE functions as a shielding member, and transmission of high-frequency noise to the temperature sensor circuit 90 can be suppressed. For example, the shielding effect of the output enable pad POE reduces electromagnetic coupling and electrostatic coupling between the output buffer circuit 50 and the temperature sensor circuit 90, thereby preventing high-frequency noise from being superimposed on the output signal of the temperature sensor circuit 90. Therefore, it is possible to prevent the occurrence of a situation in which the output signal of the temperature sensor circuit 90 fluctuates due to high-frequency noise, making it impossible to perform proper temperature compensation processing, and thus reducing the accuracy of the clock frequency. In FIG. 12, the temperature sensor circuit 90 and the output enable pad POE are arranged so as to overlap, but it is also possible to modify the arrangement so that the temperature sensor circuit 90 and the ground pad PGND are arranged so as to overlap in a plan view. In this way, it is possible to improve layout efficiency and suppress fluctuations in the output signal of the temperature sensor circuit 90 due to the shielding effect, as in the case where the temperature sensor circuit 90 and the output enable pad POE are arranged so as to overlap.

The test circuit 92 and interface circuit 94 in FIG. 2 may be arranged so as to overlap the output enable pad POE in a plan view. For example, the test circuit 92 is a circuit for testing internal circuits such as analog circuits of the integrated circuit device 20 using the output enable pad POE, so it is preferable to arrange it below the output enable pad POE. The interface circuit 94 also uses the output enable pad POE as an input/output terminal for serial data, so it is preferable to arrange it below the output enable pad POE.

The layout arrangement of the integrated circuit device 20 of this embodiment is not limited to the arrangement shown in FIG. 12, and various modifications are possible. For example, FIG. 13 shows another layout arrangement example of the integrated circuit device 20. In FIG. 13, the phase comparator 41, the charge pump circuit 42, and the loop filter 43 are arranged on the side SD2, but in FIG. 12, the phase comparator 41, the charge pump circuit 42, and the loop filter 43 are arranged on the side SD1. In FIG. 12, the logic circuit 70 is arranged on the side SD1, but in FIG. 13, the logic circuit 70 is arranged on the side SD2. In FIG. 12, the circuit blocks that are sources of high-frequency noise are arranged together on the side SD1, and the circuit blocks that are to be prevented from being adversely affected by high-frequency noise are arranged on the side SD2. From the viewpoint of preventing a decrease in the accuracy of the clock frequency due to high-frequency noise, the layout arrangement of FIG. 12 is more desirable.

For example, FIG. 14 is an explanatory diagram of phase noise, with the horizontal axis representing the offset frequency and the vertical axis representing the phase noise. A1 in FIG. 14 is the noise characteristic of the clock signal CKQ when the PLL circuit 40 is operated freely without phase synchronization. Meanwhile, A2 and A3 are the noise characteristics of the clock signal CKQ when the PLL circuit 40 is phase-synchronized with the oscillation signal OSC. Since the phase noise of the oscillation signal OSC is small, the inbound noise on the left side of the line shown in A4 in FIG. 14 can be reduced by having the PLL circuit 40 phase-synchronize with the oscillation signal OSC. A2 in FIG. 14 is the noise characteristic when the layout arrangement in FIG. 13 is adopted, and A3 is the noise characteristic when the layout arrangement in FIG. 12 is adopted. As shown in FIG. 12, the output buffer circuit 50, logic circuit 70, etc., which are sources of high frequency noise, are arranged together on the side SD1, and the reference voltage generation circuit 62, charge pump circuit 42, etc., which should be kept away from the high frequency noise sources, are arranged together on the side SD2, making it possible to reduce the phase noise of the clock signal CKQ, as shown by A3 in FIG. 14.

3. Oscillator Fig. 15 shows an example of the structure of the oscillator 4 of this embodiment. The oscillator 4 has a resonator 10, an integrated circuit device 20, and a package 15 that houses the resonator 10 and the integrated circuit device 20. The package 15 is formed of, for example, ceramics, and has an accommodation space inside, in which the resonator 10 and the integrated circuit device 20 are accommodated. The accommodation space is hermetically sealed, and is preferably in a reduced pressure state that is close to a vacuum. The package 15 can suitably protect the resonator 10 and the integrated circuit device 20 from impact, dust, heat, moisture, and the like.

The package 15 has a base 16 and a lid 17. Specifically, the package 15 is composed of a base 16 that supports the vibrator 10 and the integrated circuit device 20, and a lid 17 that is joined to the upper surface of the base 16 so as to form a storage space between the base 16 and the lid 17. The vibrator 10 is supported via a terminal electrode on a step provided on the inside of the base 16. The integrated circuit device 20 is also arranged on the inner bottom surface of the base 16. Specifically, the integrated circuit device 20 is arranged so that the active surface faces the inner bottom surface of the base 16. The active surface is the surface on which the circuit elements of the integrated circuit device 20 are formed. A bump BMP is also formed on the pad, which is the terminal of the integrated circuit device 20. The integrated circuit device 20 is supported on the inner bottom surface of the base 16 via a conductive bump BMP. The conductive bump BMP is, for example, a metal bump, and the vibrator 10 and the integrated circuit device 20 are electrically connected via the bump BMP, the internal wiring of the package 15, the terminal electrodes, and the like. Furthermore, the integrated circuit device 20 is electrically connected to external terminals 18, 19, which are external connection terminals of the oscillator 4, via the bumps BMP and the internal wiring of the package 15. The external terminals 18, 19 are formed on the outer bottom surface of the package 15. The external terminals 18, 19 are connected to an external device via external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. This makes it possible to output a clock signal, etc. to the external device.

15, the integrated circuit device 20 is flip-mounted so that the active surface of the integrated circuit device 20 faces downward, but this embodiment is not limited to such mounting. For example, the integrated circuit device 20 may be mounted so that the active surface of the integrated circuit device 20 faces upward. That is, the integrated circuit device 20 is mounted so that the active surface faces the vibrator 10. Alternatively, the oscillator 4 may be a wafer-level package (WLP) oscillator. In this case, the oscillator 4 includes a semiconductor substrate, a base having a through electrode penetrating between the first surface and the second surface of the semiconductor substrate, the vibrator 10 fixed to the first surface of the semiconductor substrate via a conductive bonding member such as a metal bump, and an external terminal provided on the second surface side of the semiconductor substrate via an insulating layer such as a relocation wiring layer. Then, an integrated circuit that becomes the integrated circuit device 20 is formed on the first surface or the second surface of the semiconductor substrate. In this case, a first semiconductor wafer having a plurality of bases on which the vibrators 10 and integrated circuits are arranged is attached to a second semiconductor wafer having a plurality of lids, and the plurality of bases and the plurality of lids are then bonded together, and the oscillators 4 are then separated into individual pieces using a dicing saw or the like. In this way, it becomes possible to realize a wafer-level packaged oscillator 4, and it becomes possible to manufacture the oscillators 4 with high throughput and at low cost.

As described above, the integrated circuit device of this embodiment includes an oscillation circuit that generates an oscillation signal using an oscillator, an output buffer circuit that outputs a clock signal based on the oscillation signal, a DC voltage generation circuit that generates a DC voltage used to generate the oscillation signal or the clock signal, a power supply pad to which a power supply voltage is supplied, a ground pad to which a ground voltage is supplied, and a clock pad to which a clock signal is output. In a plan view, the ground pad and the DC voltage generation circuit are arranged to overlap.

According to this embodiment, the power supply voltage and ground voltage are supplied to the integrated circuit device by the power supply pad and ground pad, an oscillation signal is generated by the oscillator circuit using an oscillator, and a clock signal based on the oscillation signal is output from the clock pad by the output buffer circuit. The DC voltage generation circuit that generates the DC voltage used to generate the oscillation signal or clock signal and the ground pad are arranged so as to overlap in a plan view. In this way, the ground pad functions as a shielding member, and it is possible to suppress the transmission of high-frequency noise to the DC voltage generation circuit, and it is possible to prevent problems such as a decrease in the accuracy of the clock frequency due to high-frequency noise. In addition, since it is possible to effectively utilize the area of the ground pad that would otherwise be dead space to arrange the DC voltage generation circuit, an efficient layout arrangement is possible, and the integrated circuit device can be made smaller. Thus, according to this embodiment, it is possible to provide an integrated circuit device or the like that can achieve both prevention of a decrease in the accuracy of the clock frequency due to the shielding effect of the ground pad and an efficient layout arrangement that effectively utilizes the pad area.

In addition, in this embodiment, the clock pad and the output buffer circuit may be arranged to overlap in a plan view.

In this way, the clock signal from the output buffer circuit can be output to the clock pad via a short-path clock wiring route that runs from the output buffer circuit to the clock pad placed directly above it. This makes it possible to minimize the impedance of the clock wiring and suppress potential fluctuations caused by that impedance. In addition, because the output buffer circuit and the clock pad, which are sources of high-frequency noise, can be placed together in one location, it becomes possible to easily implement measures such as layout arrangements to reduce the adverse effects of noise from high-frequency noise sources.

In this embodiment, the DC voltage generation circuit may be a reference voltage generation circuit that generates a reference voltage for generating at least one of a bias current, a bias voltage, or a regulated power supply voltage.

In this way, the shielding effect of the ground pad reduces electromagnetic and electrostatic coupling between the output buffer circuit or clock pad and the reference voltage generation circuit, preventing high-frequency noise from being superimposed on the reference voltage output by the reference voltage generation circuit.

In this embodiment, the DC voltage generating circuit may be a regulator that generates a regulated power supply voltage based on the power supply voltage.

In this way, the shielding effect of the ground pad prevents high-frequency noise from being superimposed on the regulated power supply voltage output by the regulator, and prevents the accuracy of the clock frequency from being reduced due to high-frequency noise.

In this embodiment, the PLL circuit performs PLL operation to generate a clock signal that is phase-synchronized with the oscillation signal, and the PLL circuit includes a phase comparator, a charge pump circuit, and a loop filter. The DC voltage generation circuit may be a charge pump circuit, a loop filter, or a regulator that supplies a regulated power supply voltage to the charge pump circuit.

In this way, the shielding effect of the ground pad can prevent high-frequency noise from being superimposed on the output voltage of the charge pump circuit, loop filter, or regulator, and can prevent the accuracy of the clock frequency from decreasing due to high-frequency noise.

In addition, in this embodiment, the external shape of the integrated circuit device may include a first side and a second side opposite to the first side, with the output buffer circuit and clock pads arranged on the first side, and the DC voltage generating circuit and ground pads arranged on the second side.

This makes it possible to separate the output buffer circuit and clock pad, which are sources of high-frequency noise, from the DC voltage generation circuit and ground pad, and prevents high-frequency noise from the output buffer circuit and clock pad from being transmitted to the DC voltage generation circuit and ground pad.

In addition, this embodiment includes a PLL circuit that performs PLL operation to generate a clock signal that is phase-synchronized with the oscillation signal, and the DC voltage generation circuit may be a reference voltage generation circuit that generates a reference voltage used in the operation of the PLL circuit.

By providing such a PLL circuit, it becomes possible to output a clock signal that is phase-synchronized with the oscillation signal and has a frequency set to the desired frequency. The reference voltage generation circuit that generates the reference voltage required for the operation of such a PLL circuit is arranged so that it overlaps the ground pad in a plan view, making it possible to prevent deterioration of the accuracy of the clock frequency due to high-frequency noise, etc.

In this embodiment, the PLL circuit includes a phase comparator, a charge pump circuit, and a loop filter, and the charge pump circuit may be provided on the second side.

In this way, the charge pump circuit, reference voltage generation circuit, and ground pad can be placed together at a distance from the output buffer circuit and clock pad located on the first side, making it possible to prevent high-frequency noise from the output buffer circuit and clock pad from being transmitted to the charge pump circuit, etc.

In this embodiment, the loop filter may also be provided on the second side.

In this way, the loop filter, reference voltage generation circuit, ground pad, etc. can be placed together at a distance from the output buffer circuit and clock pad located on the first side, making it possible to prevent high-frequency noise from the output buffer circuit and clock pad from being transmitted to the loop filter, etc.

The present embodiment also includes a regulator that supplies a regulated power supply voltage generated based on the reference voltage to the charge pump circuit, and the regulator may be provided on the second side.

This makes it possible to separate the regulator from sources of high-frequency noise such as the output buffer circuit, suppressing the superposition of high-frequency noise on the regulated power supply voltage and preventing a decrease in the accuracy of the clock frequency.

In this embodiment, a logic circuit that controls the PLL circuit may also be included, and the logic circuit may be provided on the first side.

In this way, the logic circuits are also arranged together with the output buffer circuits, etc., on the first side. This makes it possible to increase the distance between the reference voltage generation circuits, etc., arranged on the first side, and the logic circuits, output buffer circuits, etc., which are sources of high-frequency noise, and makes it possible to prevent a decrease in the accuracy of the clock frequency caused by high-frequency noise.

In this embodiment, the PLL circuit may also include a voltage-controlled oscillator circuit, which may be provided between the clock pad and the ground pad.

This allows the voltage-controlled oscillator circuit to be placed by effectively utilizing the area between the clock pad and the ground pad, enabling an efficient layout arrangement.

In addition, in this embodiment, the external shape of the integrated circuit device may include a third side that intersects with the first side and the second side, and the oscillator circuit may be provided on the third side.

In this way, the distance between the output buffer circuit etc. arranged on the first side and the oscillation circuit can be increased, making it possible to prevent a situation in which high-frequency noise from the output buffer circuit is superimposed on the oscillation signal and the oscillation characteristics deteriorate. In addition, the distance between the reference voltage generation circuit etc. arranged on the second side and the oscillation circuit can be increased, making it possible to prevent a situation in which oscillation noise from the oscillation circuit is superimposed on the reference voltage etc. of the reference voltage generation circuit and the accuracy of the clock frequency decreases.

In addition, this embodiment includes a temperature compensation circuit that performs temperature compensation for the oscillation frequency of the oscillation signal, and the temperature compensation circuit may be provided between the oscillation circuit and the clock pad and ground pad.

This allows the temperature compensation circuit to be placed by effectively utilizing the area between the oscillator circuit and the clock and ground pads, enabling an efficient layout arrangement.

In this embodiment, the circuit may also include a temperature sensor circuit that detects temperature, a temperature compensation circuit that performs temperature compensation for the oscillation frequency of the oscillation signal based on the output of the temperature sensor circuit, and an output enable pad for controlling the output enable of the clock signal. In addition, the temperature sensor circuit and the output enable pad or the ground pad may be arranged to overlap each other in a plan view.

In this way, the shielding effect of the output enable pad or ground pad reduces electromagnetic and electrostatic coupling between the output buffer circuit and the temperature sensor circuit, preventing high-frequency noise from being superimposed on the output signal of the temperature sensor circuit.

This embodiment also relates to an oscillator that includes the integrated circuit device described above and a resonator.

Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or similar meaning may be replaced with that different term anywhere in the specification or drawings. All combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the integrated circuit device and oscillator are not limited to those described in the present embodiment, and various modifications are possible.

Reference Signs List 4: oscillator, 5: passivation film, 6: pad metal, 7, 8, 9: conductive layer, 10: resonator, 15: package, 16: base, 17: lid, 18, 19: external terminal, 20: integrated circuit device, 30: oscillation circuit, 40: PLL circuit, 41: phase comparator, 42: charge pump circuit, 43: loop filter, 44: voltage controlled oscillation circuit, 45: frequency divider circuit, 46: output frequency divider circuit, 50: output buffer circuit circuit, 60...power supply circuit, 61...DC voltage generation circuit, 62...reference voltage generation circuit, 64, 65, 66, 67, 68...regulator, 70...logic circuit, 72...delta-sigma modulation circuit, 78...non-volatile memory, 80...temperature compensation circuit, 82...zeroth-order correction circuit, 84...first-order correction circuit, 86...higher-order correction circuit, 88...current-voltage conversion circuit, 90...temperature sensor circuit, 92...test circuit, 94...interface circuit,
BMP...bump, BP1, BP2, BP3, BPT...bipolar transistor, CA...capacitor, CK, CKQ, CKV...clock signal, CP...parasitic capacitance, DI1, DI2, DI3...diode, DR, DR1, DR2, DR3, DR4...direction, FCK...feedback clock signal, IST...current source, NWL...well, OE...output enable signal, OPA...operational amplifier, OSC...oscillator signal, PCK...clock pad, PGND...ground pad, POE...output enable pad, PSUB ...substrate, PVDD...power supply pad, PWL...well, PX1, PX2...pad, RA1 to RA3, RD1 to RD3, RE1, RE2...resistors, SD1, SD2, SD3, SD4...sides, TA1, TA2, TD1 to TD3, TE1 to TE5...transistors, TCK, TGND, TOE, TVDD...external terminals, VB...bias voltage, VCP...temperature compensation voltage, VDD...power supply voltage, VREF...reference voltage, VREG, VREG1, VREG2, VREG3, VREG4...regulated power supply voltage, VT...temperature detection voltage

Claims (16)

an oscillator circuit for generating an oscillation signal using an oscillator;
an output buffer circuit that outputs a clock signal based on the oscillation signal;
a DC voltage generating circuit for generating a DC voltage used to generate the oscillation signal or the clock signal;
a power supply pad to which a power supply voltage is supplied;
a ground pad to which a ground voltage is supplied;
a clock pad to which the clock signal is output;
Including,
2. An integrated circuit device comprising: a first insulating layer and a second insulating layer disposed on the first insulating layer; 2. The integrated circuit device according to claim 1,
4. An integrated circuit device, comprising: a clock pad and an output buffer circuit disposed so as to overlap each other in a plan view. 3. The integrated circuit device according to claim 1,
2. An integrated circuit device according to claim 1, wherein the DC voltage generating circuit is a reference voltage generating circuit that generates a reference voltage for generating at least one of a bias current, a bias voltage, and a regulated power supply voltage. 3. The integrated circuit device according to claim 1,
The integrated circuit device, wherein the DC voltage generating circuit is a regulator that generates a regulated power supply voltage based on the power supply voltage. 3. The integrated circuit device according to claim 1,
a PLL circuit that performs a PLL operation for generating the clock signal that is phase-locked with the oscillation signal,
the PLL circuit includes a phase comparator, a charge pump circuit, and a loop filter;
The integrated circuit device, wherein the DC voltage generating circuit is the charge pump circuit, the loop filter, or a regulator that supplies a regulated power supply voltage to the charge pump circuit. 2. The integrated circuit device according to claim 1,
the external shape of the integrated circuit device includes a first side and a second side opposite to the first side,
the output buffer circuit and the clock pad are arranged on the first side;
The integrated circuit device, wherein the DC voltage generating circuit and the ground pad are arranged on the second side. 7. The integrated circuit device according to claim 6,
a PLL circuit that performs a PLL operation for generating the clock signal that is phase-locked with the oscillation signal,
The integrated circuit device, wherein the DC voltage generating circuit is a reference voltage generating circuit that generates a reference voltage used for the operation of the PLL circuit. 8. The integrated circuit device according to claim 7,
the PLL circuit includes a phase comparator, a charge pump circuit, and a loop filter;
The integrated circuit device, wherein the charge pump circuit is provided on the second side. 9. The integrated circuit device according to claim 8,
The integrated circuit device, wherein the loop filter is provided on the second side. 10. The integrated circuit device according to claim 8,
a regulator that supplies a regulated power supply voltage generated based on the reference voltage to the charge pump circuit;
The integrated circuit device, wherein the regulator is provided on the second side. 11. The integrated circuit device according to claim 7,
a logic circuit for controlling the PLL circuit;
The integrated circuit device, wherein the logic circuit is provided on the first side. 12. An integrated circuit device according to claim 7,
the PLL circuit includes a voltage controlled oscillator circuit,
The integrated circuit device according to claim 1, wherein the voltage controlled oscillator circuit is provided between the clock pad and the ground pad. 13. An integrated circuit device according to any one of claims 6 to 12,
the outer shape of the integrated circuit device includes a third side intersecting the first side and the second side,
The integrated circuit device, wherein the oscillator circuit is provided on the third side. 14. An integrated circuit device according to any one of claims 1 to 13,
a temperature compensation circuit for performing temperature compensation for an oscillation frequency of the oscillation signal;
The integrated circuit device according to claim 1, wherein the temperature compensation circuit is provided between the oscillator circuit and the clock pad and between the oscillator circuit and the ground pad. 14. An integrated circuit device according to any one of claims 1 to 13,
A temperature sensor circuit for detecting a temperature;
a temperature compensation circuit that performs temperature compensation for an oscillation frequency of the oscillation signal based on an output of the temperature sensor circuit;
an output enable pad for controlling an output enable of the clock signal;
Including,
2. An integrated circuit device comprising: a temperature sensor circuit and an output enable pad or a ground pad, the temperature sensor circuit and the output enable pad being arranged to overlap each other in the plan view. An integrated circuit device according to any one of claims 1 to 15;
The oscillator;
16. An oscillator comprising:

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