JP7625978B2 - Semiconductor device and its manufacturing method - Google Patents

Description

This disclosure relates to a semiconductor device and a method for manufacturing the same.

There is known a semiconductor light receiving element that receives light and outputs an electrical signal (see, for example, Patent Document 1). In the light receiving element, multiple mesas are arranged in a two-dimensional array. The mesa includes a light receiving layer that is sensitive to, for example, infrared light. The surface of the mesa is covered with an insulating passivation film.

JP 2020-47639 A

When damage occurs to the surface of the mesa, leakage current increases and light receiving sensitivity decreases. Therefore, the objective of the present invention is to provide a semiconductor device and a manufacturing method thereof that can suppress damage to the mesa surface.

The method for manufacturing a semiconductor device according to the present disclosure includes the steps of: forming a first mesa protruding in a thickness direction in the semiconductor layer by etching the semiconductor layer; forming a first insulating film covering the first mesa and the semiconductor layer after the step of forming the first mesa; forming a mask on the first insulating film; removing portions of the mask and the first insulating film that are separated from the first mesa; etching the semiconductor layer in the portion from which the mask and the first insulating film have been removed to form a second mesa protruding in the thickness direction in the semiconductor layer; and forming a second insulating film covering the first insulating film and the second mesa.

The semiconductor device according to the present disclosure comprises a first mesa, a second mesa spaced apart from the first mesa, a first insulating film, and a second insulating film, the first recess is adjacent to the first mesa and recessed in the thickness direction from the first mesa, the second recess is adjacent to the second mesa and recessed in the thickness direction from the first recess, the first insulating film covers the first mesa and the first recess, and the second insulating film covers the first mesa, the first recess, the second mesa, and the second recess.

This disclosure makes it possible to provide a semiconductor device and a method for manufacturing the same that can suppress damage to the mesa surface.

FIG. 1A is a plan view illustrating a semiconductor device according to an embodiment. FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A. FIG. 2A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 2B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 3A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 3B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 4A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 4B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 5A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 5B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 6A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 6B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 7A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 7B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 8A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 8B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 9A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 9B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 10A is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 10B is a cross-sectional view illustrating a method for manufacturing a semiconductor device. FIG. 11A is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a comparative example. FIG. 11B is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a comparative example.

[Description of the embodiments of the present disclosure]
First, the contents of the embodiments of the present disclosure will be listed and described.

One aspect of the present disclosure is a method for manufacturing a semiconductor device, including: (1) forming a first mesa protruding in a thickness direction in the semiconductor layer by etching the semiconductor layer, forming a first insulating film covering the first mesa and the semiconductor layer after the step of forming the first mesa, forming a mask on the first insulating film, removing a portion of the mask and the first insulating film that is separated from the first mesa, forming a second mesa protruding in the thickness direction in the semiconductor layer by etching the semiconductor layer in the portion from which the mask and the first insulating film have been removed, and forming a second insulating film covering the first insulating film and the second mesa. Since the first insulating film covers the first mesa, damage to the first mesa can be suppressed in the step of forming the mask.
(2) The step of forming the mask may include a step of forming an insulating film for the mask by plasma-enhanced chemical vapor deposition. Since the first insulating film covers the first mesa, damage to the first mesa caused by plasma-enhanced chemical vapor deposition can be suppressed in the step of forming the mask.
(3) The step of forming the first insulating film may include a step of forming an inorganic insulating film by plasma-enhanced chemical vapor deposition, and the step of forming the second insulating film may include a step of forming an inorganic insulating film by plasma-enhanced chemical vapor deposition. Since the first insulating film covers the first mesa, damage to the first mesa can be suppressed in the step of forming a mask. The first insulating film and the second insulating film can protect the semiconductor device.
(4) The method may include a step of removing a part of the first insulating film so that an end of the first insulating film is spaced apart from an end of the second mesa, and a step of removing, by etching, damage that occurs in a portion of the semiconductor layer that is etched in the step of forming the second mesa after the step of removing the part of the first insulating film. After the step of removing the damage by etching, the end of the first insulating film does not protrude from the end of the second mesa. The coverage of the second insulating film is improved.
(5) The semiconductor layer may include a first semiconductor layer, a light receiving layer, a second semiconductor layer, and a third semiconductor layer, the first semiconductor layer and the second semiconductor layer having a first conductivity type, the third semiconductor layer having a second conductivity type different from the first conductivity type, and the first semiconductor layer, the light receiving layer, the second semiconductor layer, and the third semiconductor layer may be stacked in this order in the thickness direction. The semiconductor device functions as a light receiving element.
(6) The step of forming the first mesa may be a step of forming the first mesa by etching the third semiconductor layer and the second semiconductor layer, and the step of forming the second mesa may be a step of forming the second mesa by etching the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer. The first insulating film and the second insulating film can protect the first semiconductor layer, the light receiving layer, the second semiconductor layer, and the third semiconductor layer.
(7) The method may further include forming a first electrode on the first mesa, the first electrode being electrically connected to the second semiconductor layer, and forming a second electrode on the second mesa and a portion of the semiconductor layer etched in the step of forming the second mesa. The first electrode and the second electrode can be used to connect the semiconductor device to an external device.
(8) The step of forming the first mesa may be a step of forming a plurality of the first mesas arranged in an array. The semiconductor device is a two-dimensional array sensor.
(9) A semiconductor device comprising a first mesa, a second mesa spaced apart from the first mesa, a first insulating film, and a second insulating film, a first recess adjacent to the first mesa and recessed in a thickness direction relative to the first mesa, a second recess adjacent to the second mesa and recessed in a thickness direction relative to the first recess, the first insulating film covering the first mesa and the first recess, and the second insulating film covering the first mesa, the first recess, the second mesa, and the second recess. Since the first insulating film covers the first mesa, damage to the first mesa can be suppressed.

[Details of the embodiment of the present disclosure]
Specific examples of semiconductor devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

(Semiconductor device)
FIG. 1A is a plan view illustrating a semiconductor device 100 according to an embodiment. FIG. 1B is a cross-sectional view taken along line A-A in FIG. 1A. The semiconductor device 100 is, for example, a rectangular light receiving element in an XY plane. The X-axis direction is the extension direction of two sides of the semiconductor device 100. The Y-axis direction is the extension direction of two sides of the semiconductor device 100, and is perpendicular to the X-axis direction. The length of the side in the X-axis direction and the length of the side in the Y-axis direction of the semiconductor device 100 are, for example, 2 mm or more and 15 mm or less. The Z-axis direction is the thickness direction, and is perpendicular to the X-axis direction and the Y-axis direction.

1A, the semiconductor device 100 has a plurality of mesas 30 (first mesa), mesa 34 (second mesa), and mesa 37. The plurality of mesas 30 are arranged in a two-dimensional array in the XY plane. The shape of the mesa 30 in the XY plane is circular. As shown in FIGS. 1A and 1B, a recess 32 (first recess) is provided between two adjacent mesas 30 and between the mesa 30 and the mesa 34. A recess 36 (second recess) is provided between the mesa 34 and the mesa 37. The mesa 34 is located outside the plurality of mesas 30 in the XY plane and surrounds the plurality of mesas 30. The mesa 37 is located outside the mesa 34 in the XY plane and surrounds the mesa 34. The shapes of the mesas 34 and 37 in the XY plane are ring-shaped.

An electrode 26 (first electrode) is provided at the tip of the mesa 30. As shown by the diagonal lines in FIG. 1A, an electrode 28 (second electrode) is provided from the bottom surface of the recess 36 to the top surface of the mesa 34 and the top surface of the mesa 37. The electrode 28 surrounds the multiple mesas 34 in the XY plane.

As shown in FIG. 1B, the semiconductor device 100 has a substrate 10, a first n-type semiconductor layer 12 (first semiconductor layer), an absorption layer 14, a second n-type semiconductor layer 16 (second semiconductor layer), a p-type semiconductor layer 18, and a contact layer 22. The p-type semiconductor layer 18 and the contact layer 22 correspond to a third semiconductor layer. The first n-type semiconductor layer 12 is provided on one surface of the substrate 10. The absorption layer 14 is provided on the upper surface of the first n-type semiconductor layer 12. The second n-type semiconductor layer 16 is provided on the upper surface of the absorption layer 14. The p-type semiconductor layer 18 is provided on the upper surface of the second n-type semiconductor layer 16. The contact layer 22 is provided on the upper surface of the p-type semiconductor layer 18. An anti-reflection film 24 is provided on the surface of the substrate 10 opposite to the surface on which the first n-type semiconductor layer 12 is provided.

The substrate 10 is formed of n-type (first conductive type) indium phosphide (InP) having a thickness of, for example, 500 μm or more and 700 μm or less. The first n-type semiconductor layer 12 is formed of n-type InP having a thickness of, for example, 1 μm or more and 3 μm or less. The light receiving layer 14 is formed of indium gallium arsenide (InGaAs) having a thickness of, for example, 1 μm or more and 3 μm or less. The second n-type semiconductor layer 16 is formed of n-type InP having a thickness of, for example, 0.2 μm or more and 0.8 μm or less. The p-type (second conductive type) semiconductor layer 18 is formed of p-type InP having a thickness of, for example, 0.1 μm or more and 0.5 μm or less. The contact layer 22 is formed of p-type InGaAs having a thickness of, for example, 0.1 μm or more and 0.3 μm or less. A dopant such as silicon (Si) is added to the n-type layer. The p-type layer is doped with a dopant such as zinc (Zn). The anti-reflection film 24 is made of an insulator such as silicon nitride (SiN).

The recess 32 extends in the Z-axis direction to the middle of the contact layer 22, the p-type semiconductor layer 18, and the second n-type semiconductor layer 16. The width W1 of the recess 32 is, for example, 1 μm or more and 7 μm or less. The recess 36 is deeper in the Z-axis direction than the recess 32, and extends to the middle of the contact layer 22, the p-type semiconductor layer 18, the second n-type semiconductor layer 16, the light receiving layer 14, and the first n-type semiconductor layer 12. The width W3 of the recess 36 is, for example, 100 μm or more and 300 μm or less.

Mesa 30 is formed of second n-type semiconductor layer 16, p-type semiconductor layer 18, and contact layer 22. Diameter D1 of mesa 30 is, for example, 30 μm or more and 100 μm or less. Mesas 34 and 37 are formed of first n-type semiconductor layer 12, absorption layer 14, second n-type semiconductor layer 16, p-type semiconductor layer 18, and contact layer 22. Width W2 of mesa 34 is, for example, 100 μm or more and 300 μm or less. Mesas 30, 34, and 37 protrude upward in the Z-axis direction from the bottom surface of recess 32. The height from the bottom surface of recess 32 to the top surface of mesa 30 is equal to the height of mesa 34 and the height of mesa 37.

The semiconductor device 100 has an insulating film 40 and an insulating film 41. The insulating film 40 (first insulating film) is continuously provided on the multiple mesas 30, the recess 32, and the mesa 34, and covers the side and upper surfaces of the multiple mesas 30, the bottom surface of the recess 32, and part of the upper surface of the mesa 34. The insulating film 40 covers the part of the upper surface of the mesa 34 that faces the recess 32, but does not cover the part that faces the recess 36. The insulating film 40 is a passivation film formed of silicon nitride (SiN) with a thickness of, for example, 100 nm or more and 400 nm or less.

The insulating film 41 (second insulating film) covers the surface of the insulating film 40. The insulating film 41 is continuously provided on the multiple mesas 30, the recesses 32, the mesas 34, the recesses 36, and the mesas 37, and covers the side and top surfaces of the multiple mesas 30, the bottom surface of the recesses 32, the side and top surface of the mesa 34, the bottom surface of the recesses 36, and the side and top surface of the mesa 37. The insulating film 41 is a passivation film formed of SiN, for example, with a thickness of 100 nm or more and 400 nm or less.

The insulating films 40 and 41 have an opening 42 on the upper surface of the mesa 34. The electrode 26 is a p-type electrode, provided on the upper surface of the mesa 34, and contacts the upper surface of the contact layer 22 through the opening 42. The insulating film 41 has an opening 43 on the bottom surface of the recess 36. The electrode 28 is provided on the surface of the insulating film 41, and is extended from the bottom surface of the recess 36 to the upper surface of the mesa 34 and the upper surface of the mesa 37. The electrode 28 is an n-type electrode, and contacts the upper surface of the first n-type semiconductor layer 12 through the opening 43.

The semiconductor device 100 is flip-chip mounted, for example, on an external circuit board (not shown) using bumps. The bumps are connected to electrodes 26 and 28.

When the semiconductor device 100 receives light, such as infrared light, the light receiving layer 14 generates electron-hole pairs. An electrical signal is output from the semiconductor device 100 to a read circuit on the circuit board through the electrodes 26 and 28.

(Production method)
2A to 10B are cross-sectional views illustrating a method for manufacturing the semiconductor device 100, and show cross sections corresponding to FIG. 1B.

As shown in FIG. 2A, the first n-type semiconductor layer 12, the light receiving layer 14, the second n-type semiconductor layer 16, the p-type semiconductor layer 18, and the contact layer 22 are epitaxially grown in this order on the upper surface of the substrate 10 by, for example, metal-organic vapor phase epitaxy (MOVPE). An insulating film 50 is formed on the upper surface of the contact layer 22 by, for example, plasma enhanced chemical vapor deposition (PECVD). The insulating film 50 is formed of, for example, silicon nitride (SiN) or silicon oxide (SiO ₂ ). The thickness of the insulating film 50 is, for example, 0.2 μm or more and 0.5 μm or less. A photoresist 52 having a thickness of, for example, 1 μm or more and 3 μm or less is applied to the upper surface of the insulating film 50. A plurality of openings are formed in the photoresist 52 by photolithography.

As shown in FIG. 2B, the portions of the insulating film 50 that are exposed from the photoresist 52 are dry-etched using, for example, a fluorine-based gas to form a plurality of openings 50a in the insulating film 50. The contact layer 22 is exposed from the openings 50a.

As shown in FIG. 3A, the photoresist 52 is removed. As shown in FIG. 3B, dry etching is performed using a halogen-based gas with the insulating film 50 as a mask. The contact layer 22, the p-type semiconductor layer 18, and the second n-type semiconductor layer 16 are etched in the inner portions of the opening 50a. In the Z-axis direction, the etching proceeds from the upper surface of the contact layer 22 to the middle of the second n-type semiconductor layer 16. A recess 32 is formed in the dry-etched portion, and a mesa 30 is formed in the portion surrounded by the recess 32. Damage occurs in the dry-etched surfaces of the contact layer 22, the p-type semiconductor layer 18, and the second n-type semiconductor layer 16.

As shown in FIG. 4A, wet etching is performed using the insulating film 50 as a mask. For example, a chlorine-based or bromine-based chemical is used as an etchant. The dry-etched surfaces of the contact layer 22, the p-type semiconductor layer 18, and the second n-type semiconductor layer 16 are wet-etched to remove damage caused by the dry etching. In the Z-axis direction, the wet etching proceeds halfway through the second n-type semiconductor layer 16 and does not reach the light-receiving layer 14. In the XY plane, the contact layer 22, the p-type semiconductor layer 18, and the second n-type semiconductor layer 16 are side-etched. The width of the recess 32 becomes larger than the width of the opening 50a of the insulating film 50. The insulating film 50 protrudes inward from the recess 32. As shown in FIG. 4B, the insulating film 50 is removed using hydrofluoric acid.

As shown in FIG. 5A, a SiN insulating film 40 is formed, for example, by plasma CVD. The insulating film 40 covers the surfaces of the mesa 30, the recess 32, and the contact layer 22. The deposition temperature of the insulating film 40 is, for example, 260° C. or higher, 340° C.

As shown in FIG. 5B, an insulating film 54 for a mask is formed on the upper surface of the insulating film 40 by, for example, a plasma CVD method. The insulating film 54 is formed of an insulator such as SiN or SiO _2. The thickness is, for example, 600 nm or more and 2000 nm or less. In the process of forming the insulating film 54, the insulating film 40 covers the semiconductor layers such as the contact layer 22, the p-type semiconductor layer 18, and the second n-type semiconductor layer 16. The insulating film 40 protects the semiconductor layer from ions generated in the plasma CVD method when the insulating film 54 is formed. Damage to the semiconductor layer caused by ion collision is suppressed. The film formation temperature of the insulating film 54 is, for example, 180° C. or more and 260° C. or less, and is lower than the film formation temperature of the insulating film 40. Since the film formation temperature of the insulating film 54 is lower than the film formation temperature of the insulating film 40, the etching rate of the insulating film 54 is higher than the etching rate of the insulating film 40. The ratio of ammonia (NH ₃ ) to silane (SiH ₄ ) in the raw materials may be decreased in the formation of the insulating film 40 and increased in the formation of the insulating film 54 .

As shown in FIG. 6A, a photoresist 53 having a thickness of, for example, 1 μm or more and 3 μm or less is applied to the upper surface of the insulating film 54. As shown in FIG. 6B, an opening 53a is formed in the photoresist 53 by photolithography. The opening 53a is spaced apart from the mesa 30 and the recess 32 in the XY plane. The width of the opening 53a is, for example, 100 μm or more and 300 μm or less. A part of the insulating film 54 is exposed from the opening 53a.

As shown in FIG. 7A, the insulating films 54 and 40 are dry-etched using, for example, a fluorine-based gas in the portion of the opening 53a of the photoresist 53. An opening 55 is formed in the insulating films 54 and 40 by dry etching. The width of the opening 55 is equal to the width of the opening 53a. The contact layer 22 is exposed from the opening 55. The end 54a of the insulating film 54 and the end 40a of the insulating film 40 form the inner wall of the opening 55. As shown in FIG. 7B, the photoresist 53 is removed.

As shown in FIG. 8A, dry etching is performed using a halogen-based gas, using a mask made of insulating film 54. The contact layer 22, p-type semiconductor layer 18, second n-type semiconductor layer 16, light-receiving layer 14, and first n-type semiconductor layer 12 are etched in the opening 55. In the Z-axis direction, etching progresses to the middle of the first n-type semiconductor layer 12. The dry etching forms recess 36, mesa 34, and mesa 37. Damage occurs in the dry-etched surfaces. Surface 36a is the inner wall of recess 36, and forms the side (end) of mesa 34 and the side of mesa 37.

As shown in FIG. 8B, a portion of the insulating films 40 and 54 is etched by wet etching using, for example, buffered hydrofluoric acid. The portions of the insulating films 40 and 54 on the recess 36 side are etched to make the opening 55 wider than the recess 36. The end 40a of the insulating film 40 is spaced apart from the surface 36a of the recess 36 and is positioned outside the surface 36a. The end 54a of the insulating film 54 is spaced apart from the surface 36a and the end 40a and is positioned outside the surface 36a and the end 40a.

As shown in FIG. 9A, wet etching is performed using, for example, a chlorine-based etchant or a bromine-based etchant. The dry-etched surfaces of the contact layer 22, the p-type semiconductor layer 18, the second n-type semiconductor layer 16, the light-receiving layer 14, and the first n-type semiconductor layer 12 are wet-etched, thereby removing damage caused by the dry etching. In the Z-axis direction, the wet etching proceeds halfway through the first n-type semiconductor layer 12 and does not reach the substrate 10. The surface 36a of the recess 36 is side-etched, but does not reach the end 40a of the insulating film 40 or the end 54a of the insulating film 54. The insulating films 40 and 54 do not protrude above the recess 36, but are located outside the recess 36.

As shown in FIG. 9B, the insulating film 54 is removed by wet etching using buffered hydrofluoric acid. The insulating film 40 remains. The etching rate of the insulating film 54 is at least twice as high as the etching rate of the insulating film 40. Therefore, while the insulating film 54 is removed by etching, the insulating film 40 remains. The portion of the insulating film 40 exposed from the insulating film 54 is etched and becomes thinner than the other portions.

As shown in FIG. 10A, a SiN insulating film 41 is formed, for example, by plasma CVD. The insulating film 41 covers the surface of the insulating film 40, the mesa 34, the mesa 37, and the recess 36. The deposition temperature of the insulating film 41 is, for example, 260° C. or higher, 340° C.

A resist pattern (not shown) is provided on the insulating film 41 by photolithography. Openings 42 and 43 are provided in the insulating films 40 and 41 by etching using buffered hydrofluoric acid. As shown in FIG. 10B, an electrode 26 is formed on the mesa 30 by vacuum deposition and lift-off. An electrode 28 is formed on the mesa 34, the recess 36, and the mesa 37. The electrode 26 is connected to the contact layer 22 through the opening 42. The electrode 28 is connected to the first n-type semiconductor layer 12 through the opening 43. An anti-reflection film 24 is formed on the lower surface of the substrate 10. Through the above steps, the semiconductor device 100 is formed.

Figures 11A and 11B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a comparative example. The steps from Figures 2A to 4B are also performed in the comparative example. As shown in Figure 11A, an insulating film 54 is formed before providing the insulating film 40. The insulating film 54 contacts the surface of the mesa 30, the bottom surface of the recess 32, and the surface of the contact layer 22. Dry etching is performed using the insulating film 54 as a mask to form the recess 36. As shown in Figure 11B, after removing the mask (insulating film 54), an insulating film 40 is formed. The insulating film 41 is not provided, and electrodes 26 and 28 are provided.

In the comparative example, in the process of forming the insulating film 54, for example, a plasma CVD method is performed, which causes ions to collide with the surface of the mesa 30. The ion collisions cause damage to the surface of the mesa 30. As a result, there is a risk that the leakage current will increase and the light receiving sensitivity will decrease.

According to this embodiment, an insulating film 40 is formed to cover the mesa 30 as shown in FIG. 5A, and an insulating film 54 is formed on the insulating film 40 as shown in FIG. 5B. Because the mesa 30 is covered with the insulating film 40, damage is unlikely to occur on the surface of the mesa 30 when the insulating film 54 is formed. Damage to the mesa 30 is suppressed, so that the leakage current can be reduced and the light receiving sensitivity can be increased.

As shown in FIG. 8A, etching is performed using insulating film 54 as a mask to form mesa 34. Insulating film 40 covers mesa 30 and recess 32. As shown in FIG. 10A, insulating film 41 covers insulating film 40 and further covers mesa 34, mesa 37, and recess 36. Insulating films 40 and 41 are passivation films and can protect semiconductor device 100 from foreign matter, moisture, and the like.

The insulating film 54 is formed by plasma CVD. Because the semiconductor layer is covered with the insulating film 40, damage caused by ion collisions is suppressed. The insulating film 41 is also formed using plasma CVD. Because the semiconductor layer is covered with the insulating film 40, damage during the formation of the insulating film 41 is also suppressed.

The insulating films 40 and 41 are inorganic insulating films and may be silicon nitride (SiN) films, silicon oxide (SiO ₂ ) films, or oxynitride (SiON) films. The material of the insulating film 40 may be the same as or different from the material of the insulating film 41. The insulating films 50 and 54 that serve as etching masks are also inorganic insulating films.

As shown in FIG. 8B, after the mesa 34 is formed, the insulating films 40 and 54 are etched on the recess 36 side. The etching causes the end 40a of the insulating film 40 and the end 54a of the insulating film 54 to be separated from the surface 36a of the recess 36. Even if wet etching is performed to remove damage as shown in FIG. 9A, the ends 40a and 54a do not protrude into the recess 36. As shown in FIG. 10A, the insulating film 41 adheres to and covers the upper surface and end 40a of the insulating film 40, as well as the surface 36a. The insulating film 41 improves the coverage and can effectively protect the semiconductor device 100. If the end 40a protrudes into the recess 36, the coverage of the insulating film 41 near the end 40a may be deteriorated.

A first n-type semiconductor layer 12, a light-receiving layer 14, a second n-type semiconductor layer 16, a p-type semiconductor layer 18, and a contact layer 22 are laminated on the substrate 10. Carriers are generated when the light-receiving layer 14 receives light. The carriers flow from the light-receiving layer 14 to other semiconductor layers. The semiconductor device 100 functions as a light-receiving element. As shown in FIG. 1A, the multiple mesas 30 are arranged in a two-dimensional array. The semiconductor device 100 is an array sensor.

The mesa 30 and the recess 32 are formed by etching the contact layer 22, the p-type semiconductor layer 18, and the second n-type semiconductor layer 16. After etching, the contact layer 22, the p-type semiconductor layer 18, and the second n-type semiconductor layer 16 are exposed. As shown in FIG. 5A, these layers are covered with an insulating film 40, which can suppress damage during the process of forming the insulating film 54. As shown in FIG. 8A, the contact layer 22, the p-type semiconductor layer 18, the second n-type semiconductor layer 16, the light-receiving layer 14, and the first n-type semiconductor layer 12 are etched to form the mesa 34 and the recess 36. After etching, these semiconductor layers are exposed. The insulating film 41 is a passivation film that covers the semiconductor layer and the insulating film 40. The two insulating films 40 and 41 can protect the semiconductor device 100.

Electrode 26 is a p-type electrode and is connected to the p-type contact layer 22. Electrode 28 is an n-type electrode and is connected to the first n-type semiconductor layer 12. Electrode 26 is provided on the upper surface of mesa 30, and electrode 28 is extended to the upper surface of mesa 34. Since electrodes 26 and 28 are located at the same height, electrodes 26 and 28 can be used to electrically connect the semiconductor device 100 to a read circuit.

Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure as described in the claims.

REFERENCE SIGNS LIST 10 Substrate 12 First n-type semiconductor layer 14 Light receiving layer 16 Second n-type semiconductor layer 18 P-type semiconductor layer 22 Contact layer 24 Anti-reflection film 26, 28 Electrode 30, 34, 37 Mesa 32, 36 Recess 36a Surface 40a, 54a End 40, 41, 50, 54 Insulating film 42, 43, 50a, 53a, 55 Opening 52, 53 Photoresist 100 Semiconductor device

Claims (8)

forming a first mesa protruding in a thickness direction of the semiconductor layer by etching the semiconductor layer;
forming a first insulating film covering the first mesa and the semiconductor layer after the step of forming the first mesa;
forming a mask on the first insulating film;
removing the mask and the first insulating film at a portion away from the first mesa;
forming a second mesa protruding in the thickness direction in the semiconductor layer by etching the semiconductor layer in a portion from which the mask and the first insulating film have been removed;
forming a second insulating film covering the first insulating film and the second mesa;
The method for manufacturing a semiconductor device , wherein the step of forming the mask includes a step of forming an insulating film for the mask by plasma enhanced chemical vapor deposition . forming a first mesa protruding in a thickness direction of the semiconductor layer by etching the semiconductor layer;
forming a first insulating film covering the first mesa and the semiconductor layer after the step of forming the first mesa;
forming a mask on the first insulating film;
removing the mask and the first insulating film at a portion away from the first mesa;
forming a second mesa protruding in the thickness direction in the semiconductor layer by etching the semiconductor layer in a portion from which the mask and the first insulating film have been removed;
forming a second insulating film covering the first insulating film and the second mesa;
removing a portion of the first insulating film such that an end of the first insulating film is spaced from an end of the second mesa;
a step of removing , after the step of removing a portion of the first insulating film, damage caused to a portion of the semiconductor layer that is etched in the step of forming the second mesa by etching. forming a first mesa protruding in a thickness direction of the semiconductor layer by etching the semiconductor layer;
forming a first insulating film covering the first mesa and the semiconductor layer after the step of forming the first mesa;
forming a mask on the first insulating film;
removing the mask and the first insulating film at a portion away from the first mesa;
forming a second mesa protruding in the thickness direction in the semiconductor layer by etching the semiconductor layer in a portion from which the mask and the first insulating film have been removed;
forming a second insulating film covering the first insulating film and the second mesa;
the semiconductor layer includes a first semiconductor layer, a light receiving layer, a second semiconductor layer, and a third semiconductor layer;
the first semiconductor layer and the second semiconductor layer have a first conductivity type;
the third semiconductor layer has a second conductivity type different from the first conductivity type;
A method for manufacturing a semiconductor device, in which the first semiconductor layer, the light receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order in the thickness direction. the step of forming the first mesa is a step of forming the first mesa by etching the third semiconductor layer and the second semiconductor layer;
4. The method for manufacturing a semiconductor device according to claim 3 , wherein the step of forming the second mesa is a step of forming the second mesa by etching the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer. forming a first electrode on the first mesa, the first electrode being electrically connected to the second semiconductor layer;
5. The method for manufacturing a semiconductor device according to claim 3, further comprising the step of forming a second electrode electrically connected to the first semiconductor layer on a portion of the semiconductor layer etched in the step of forming the second mesa and on the second mesa . the step of forming the first insulating film includes a step of forming an inorganic insulating film by plasma enhanced chemical vapor deposition;
6. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the second insulating film includes the step of forming an inorganic insulating film by plasma enhanced chemical vapor deposition. 7. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of forming the first mesa is a step of forming a plurality of the first mesas arranged in an array. a first mesa formed of a semiconductor layer ;
a second mesa formed of the semiconductor layer and spaced apart from the first mesa;
A first insulating film;
A second insulating film;
A first electrode;
a second electrode ;
the semiconductor layer includes a first semiconductor layer, a light receiving layer, a second semiconductor layer, and a third semiconductor layer;
the first semiconductor layer and the second semiconductor layer have a first conductivity type;
the third semiconductor layer has a second conductivity type different from the first conductivity type;
the first semiconductor layer, the light receiving layer, the second semiconductor layer, and the third semiconductor layer are stacked in this order in a thickness direction;
the first recess is adjacent to the first mesa, recessed further in the thickness direction than the first mesa, and extending halfway through the second semiconductor layer;
a second recess adjacent to the second mesa, recessed in the thickness direction more than the first recess, and extending halfway through the first semiconductor layer;
the first insulating film covers the first mesa and the first recess;
the second insulating film covers the first mesa, the first recess, the second mesa, and the second recess;
the first electrode is provided on the first mesa and is electrically connected to the second semiconductor layer;
The second electrode is provided on the second recess and the second mesa, and is electrically connected to the first semiconductor layer .

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