JP7626615B2 - Solar cell unit and method for manufacturing the solar cell unit - Google Patents

Description

The present invention relates to a solar cell unit and a method for manufacturing a solar cell unit.

Patent Documents 1 to 4 disclose solar cells mounted on electronic devices such as wearable devices or wristwatches. Such electronic devices come in a variety of shapes from the standpoint of design, and some are small. Therefore, solar cells mounted on such electronic devices must be small or of various shapes that fit the shape of the electronic device.

Such solar cells are obtained by forming one or more solar cells on a large-sized semiconductor substrate (wafer) of a specified size (e.g., a 6-inch semi-square shape) and then cutting out the one or more solar cells, for example, by laser dicing. Hereinafter, the large-sized semiconductor substrate on which one or more solar cells are formed before laser dicing is referred to as a solar cell unit. In addition, in the solar cell unit, the area in which the solar cells are formed is referred to as the cell area, and the other area is referred to as the blank area.

International Publication No. 2019/111491 International Publication No. 2019/163750 International Publication No. 2019/163751 International Publication No. 2019/181835

The inventor(s) of the present application are considering measuring the photoluminescence characteristics of such solar cell units as a defect inspection (evaluation). However, it is difficult to distinguish between the cell area and the blank area, and it is difficult to identify (distinguish) the cell area to be inspected (evaluated).

The present invention aims to provide a solar cell unit and a method for manufacturing a solar cell unit that can simplify the identification of cell areas in measuring photoluminescence characteristics.

The solar cell unit according to the present invention is a solar cell unit having a cell region in which a back electrode type solar cell is formed on a large-sized semiconductor substrate, and a marginal region other than the cell region, in which a first semiconductor layer is formed on a part of the back side of the large-sized semiconductor substrate, a second semiconductor layer is formed on another part of the back side of the large-sized semiconductor substrate, a first electrode layer is formed corresponding to the first semiconductor layer, and a second electrode layer is formed corresponding to the second semiconductor layer. In the marginal region, at least a passivation layer in the second semiconductor layer is formed on the back side of the large-sized semiconductor substrate, and a light emission suppression region in which light emission of photoluminescence characteristics is suppressed is formed in a part of the marginal region.

The method for manufacturing a solar cell unit according to the present invention is a method for manufacturing a solar cell unit having a cell region in which a back electrode type solar cell is formed and a blank region other than the cell region on a large-sized semiconductor substrate, and includes a semiconductor layer forming process of forming a first semiconductor layer in a part of the cell region on the back side of the large-sized semiconductor substrate, forming a second semiconductor layer in another part of the cell region on the back side of the large-sized semiconductor substrate, and forming at least a passivation layer in the second semiconductor layer in the blank region on the back side of the large-sized semiconductor substrate, an electrode layer forming process of forming a first electrode layer corresponding to the first semiconductor layer in the cell region and a second electrode layer corresponding to the second semiconductor layer in the cell region, and a PL inspection process of measuring the photoluminescence characteristics of the cell region from the light receiving surface side of the large-sized semiconductor substrate. In the semiconductor layer forming process or the electrode layer forming process, a light emission suppression region in which the light emission of the photoluminescence characteristics is suppressed is formed in a part of the blank region, and in the PL inspection process, the light emission suppression region is used as an alignment mark to identify the position of the cell region.

The present invention makes it possible to simplify the identification of cell areas when measuring the photoluminescence characteristics of a solar cell unit.

FIG. 2 is a diagram showing the solar cell unit according to the embodiment as viewed from the back side. 2 is a cross-sectional view taken along line II-II of the solar cell unit shown in FIG. 1. 5A to 5C are diagrams illustrating a semiconductor layer forming step in the method for manufacturing a solar cell unit according to the embodiment. 5A to 5C are diagrams illustrating an electrode layer forming step in the manufacturing method of the solar cell unit according to the embodiment. 11 is a diagram showing a PL inspection step in the manufacturing method of the solar cell unit according to the embodiment. FIG. 2 is a cross-sectional view of a solar cell unit according to a modified example of the embodiment, taken along line II-II in FIG. 1 . FIG. 13 is a diagram showing a solar cell unit according to a comparative example as viewed from the back surface side. 6 is a cross-sectional view taken along line VI-VI of the solar cell unit shown in FIG. 5. 11A and 11B are diagrams showing a PL inspection of a solar cell unit according to a comparative example.

Below, an example of an embodiment of the present invention will be described with reference to the attached drawings. Note that the same reference numerals will be used to refer to the same or equivalent parts in each drawing. For convenience, hatching and component reference numerals may be omitted, in which case other drawings should be referenced.

(Solar cell unit)
Fig. 1 is a view of a solar cell unit according to this embodiment as viewed from the back side, and Fig. 2 is a cross-sectional view of the solar cell unit shown in Fig. 1 taken along line II-II. The solar cell unit 1 shown in Figs. 1 and 2 includes a semiconductor substrate (large-sized semiconductor substrate) (Wafer) 11 of a specified size (e.g., a 6-inch semi-square shape). The solar cell unit 1 has, on the main surface of the semiconductor substrate 11, a plurality of cell regions 2 in which a plurality of solar cells are formed, and a marginal region 3 other than the cell regions 2. The solar cell unit 1 also has, in a portion of the marginal region 3, a plurality of emission suppression regions 4 in which emission of photoluminescence characteristics is suppressed.

(Cell area)
The cell region 2 is a region that becomes a back electrode type (also called a back contact type or back junction type) heterojunction type solar cell by being cut out from the solar cell unit 1 by, for example, laser dicing.

The solar cell is a solar cell that is mounted on electronic devices such as wearable devices or wristwatches. Such electronic devices come in a variety of shapes from the standpoint of design, and some are small. Therefore, solar cells mounted on such electronic devices require solar cells of various shapes that fit the shape of the electronic device, or small solar cells.

As shown in FIG. 2, the cell region 2 has a first region 7 and a second region 8 on the main surface of the semiconductor substrate 11. Hereinafter, the main surface of the semiconductor substrate 11 that receives light is referred to as the light-receiving surface, and the main surface of the semiconductor substrate 11 opposite the light-receiving surface is referred to as the back surface.

In the cell region 2, a passivation layer 13 and an optical adjustment layer 15 are formed in order on the light receiving surface side of the semiconductor substrate 11. In addition, in the cell region 2, a passivation layer (first passivation layer) 23, a first conductive type semiconductor layer 25, and a first electrode layer 27 are formed in order on a part (first region 7) of the back side of the semiconductor substrate 11. In addition, in the cell region 2, a passivation layer (second passivation layer) 33, a second conductive type semiconductor layer 35, and a second electrode layer 37 are formed in order on another part (second region 8) of the back side of the semiconductor substrate 11. Note that the passivation layer (first passivation layer) 23 and the first conductive type semiconductor layer 25 are the first semiconductor layer, and the passivation layer (second passivation layer) 33 and the second conductive type semiconductor layer 35 are the second semiconductor layer.

The semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon. The semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. The semiconductor substrate 11 may be, for example, a p-type semiconductor substrate in which a crystalline silicon material is doped with a p-type dopant. An example of an n-type dopant is phosphorus (P). An example of a p-type dopant is boron (B). The semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light-receiving surface side and generates photocarriers (electrons and holes).

By using crystalline silicon as the material for the semiconductor substrate 11, the dark current is relatively small, and a relatively high output (stable output regardless of illuminance) can be obtained even when the intensity of the incident light is low.

The passivation layer 13 is formed on the light receiving surface side of the semiconductor substrate 11. The passivation layer 23 is formed in the first region 7 on the back side of the semiconductor substrate 11. The passivation layer 33 is formed in the second region 8 on the back side of the semiconductor substrate 11. The passivation layers 13, 23, and 33 are formed of a material mainly composed of an intrinsic (i-type) amorphous silicon material, or a dielectric material such as SiOx (x is any positive number). The passivation layers 13, 23, and 33 suppress the recombination of carriers generated in the semiconductor substrate 11 and increase the carrier recovery efficiency.

The optical adjustment layer 15 is formed on the passivation layer 13 on the light-receiving surface side of the semiconductor substrate 11. The optical adjustment layer 15 functions as an anti-reflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light-receiving surface side of the semiconductor substrate 11 and the passivation layer 13. The optical adjustment layer 15 is formed of an insulating material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON).

The first conductive type semiconductor layer 25 is formed on the passivation layer 23, i.e., in the first region 7 on the back side of the semiconductor substrate 11. On the other hand, the second conductive type semiconductor layer 35 is formed on the passivation layer 33, i.e., in the second region 8 on the back side of the semiconductor substrate 11. A portion of the second conductive type semiconductor layer 35 may overlap a portion of the adjacent first conductive type semiconductor layer 25 (not shown).

The first conductive type semiconductor layer 25 is formed of, for example, an amorphous silicon material. The first conductive type semiconductor layer 25 is, for example, a p-type semiconductor layer in which an amorphous silicon material is doped with a p-type dopant (for example, the above-mentioned boron (B)).

The second conductive type semiconductor layer 35 is formed of, for example, an amorphous silicon material. The second conductive type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, the above-mentioned phosphorus (P)). Note that the first conductive type semiconductor layer 25 may be an n-type semiconductor layer, and the second conductive type semiconductor layer 35 may be a p-type semiconductor layer.

The first electrode layer 27 corresponds to the first conductive type semiconductor layer 25, that is, is formed in the first region 7 on the back side of the semiconductor substrate 11. On the other hand, the second electrode layer 37 corresponds to the second conductive type semiconductor layer 35, that is, is formed in the second region 8 on the back side of the semiconductor substrate 11.

The first electrode layer 27 has a first transparent electrode layer 28 and a first metal electrode layer 29 formed in sequence on the first conductive type semiconductor layer 25. On the other hand, the second electrode layer 37 has a second transparent electrode layer 38 and a second metal electrode layer 39 formed in sequence on the second conductive type semiconductor layer 35.

The first transparent electrode layer 28 and the second transparent electrode layer 38 are formed of a transparent conductive material. Examples of transparent conductive materials include ITO (Indium Tin Oxide: a composite oxide of indium oxide and tin oxide), ZnO (Zinc Oxide: zinc oxide), etc.

The first metal electrode layer 29 and the second metal electrode layer 39 include a metal material such as silver, copper, or aluminum formed using, for example, a printing method, a PVD method such as sputtering, or a plating method.

(Margin area)
2, in the marginal region 3, a passivation layer 13 and an optical adjustment layer 15 are formed in this order on the light-receiving surface side of the semiconductor substrate 11. Also, in the marginal region 3, a passivation layer 33 and a second conductive type semiconductor layer 35 are laminated in this order on the back surface side of the semiconductor substrate 11. Note that the second conductive type semiconductor layer 35 does not necessarily have to be formed in the marginal region 3, and at least the passivation layer 33 may be formed.

Here, FIG. 5 is a view of the solar cell unit according to the comparative example seen from the back side, and FIG. 6 is a cross-sectional view of the solar cell unit shown in FIG. 5 taken along line VI-VI. The solar cell unit 1X of the comparative example shown in FIGS. 5 and 6 differs from this embodiment in that, compared to the solar cell unit 1 shown in FIGS. 1 and 2, the marginal area 3 does not have a light emission suppression area 4.

The inventor(s) of the present application are considering simultaneously inspecting (evaluating) defects in multiple cell regions 2 (i.e., multiple solar cell cells) by measuring the photoluminescence characteristics in such a solar cell unit 1X state. However, in this case, as shown in FIG. 7, it is difficult to distinguish between the cell region 2 and the blank region 3 from the light receiving surface side, making it difficult to identify (distinguish) the cell region 2 to be inspected (evaluated).

For example, when the semiconductor layers 13, 23, 25, 33, and 35 are formed using a CVD method or a PVD method, the semiconductor layers 13, 33, and 35 may be formed not only in the cell region 2 but also in the marginal region 3. In this case, as shown in FIG. 7, the cell region 2 and the marginal region 3, i.e., the entire surface of the solar cell unit 1X, emit light.

For example, in a double-sided electrode solar cell, an electrode is formed on the light-receiving surface side. Therefore, in a solar cell unit for a double-sided electrode solar cell, even if the entire surface is illuminated, the cell area can be identified from the light-receiving surface side due to the light-shielding position of the electrode. In contrast, in a back-side electrode solar cell, no electrode is formed on the light-receiving surface side. Therefore, in the solar cell unit 1X of Comparative Example 1 for a back-side electrode solar cell, when the entire surface is illuminated, there is no light-shielding position by the electrode, making it difficult to identify the cell area 2 from the light-receiving surface side.

It is also possible to identify the cell region 2 from the light receiving surface side using an edge or corner of the semiconductor substrate 11 as a reference. However, as shown in FIG. 7, the light emitted from the edge and corner of the semiconductor substrate 11 is weak, making it difficult to identify the edge or corner of the semiconductor substrate 11.

In this regard, in this embodiment, as shown in FIG. 1, a plurality of emission suppression regions 4 in which the emission of the photoluminescence characteristic is suppressed are formed in a part of the margin region 3. More specifically, in the emission suppression region 4, the emission is suppressed by promoting the non-radiative annihilation of carriers generated in the semiconductor substrate 11 in the photoluminescence characteristic. Promoting the non-radiative annihilation of carriers means, for example, promoting the annihilation of excess minority carriers through an annihilation process that results in non-radiative photoluminescence characteristics. As a result, the emission suppression region 4 can be used as an alignment mark for identifying the position of the cell region 2 when measuring the photoluminescence characteristic of the cell region 2 from the light receiving surface side of the semiconductor substrate 11 (see FIG. 3C).

As shown in FIG. 2, in the emission suppression region 4, a passivation layer 13 and an optical adjustment layer 15 are formed in this order on the light receiving surface side of the semiconductor substrate 11. In addition, in the emission suppression region 4, a passivation layer 23 and a first conductive type semiconductor layer 25 are formed in this order on a portion of the back surface side of the semiconductor substrate 11, and a passivation layer 33 and a second conductive type semiconductor layer 35 are stacked in this order on another portion of the back surface side of the semiconductor substrate 11. In addition, in the emission suppression region 4, a third electrode layer 37A is formed that corresponds to the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 and electrically shorts them.

The third electrode layer 37A includes a first transparent electrode layer 28 and a second transparent electrode layer 38 that correspond to the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35, respectively, and are spaced apart from each other, and a third metal electrode layer 39A that corresponds to the first transparent electrode layer 28 and the second transparent electrode layer 38 and electrically shorts them. The material and method of formation of the third metal electrode layer 39A may be the same as those of the first metal electrode layer 29 and the second metal electrode layer 39 described above.

Although the embodiment in which the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 are electrically short-circuited by a metal electrode layer has been exemplified, the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 may also be electrically short-circuited by a transparent electrode layer.

The multiple emission suppression regions 4 may be arranged regularly. As shown in FIG. 1, the multiple emission suppression regions 4 may be arranged at equal intervals, such as at the intersections of a lattice pattern, or may be arranged in any characteristic pattern that makes it easy to identify the emission suppression regions 4 in image analysis. Even if the multiple emission suppression regions 4 are arranged at random positions with different intervals between each other, as long as the emission suppression regions 4 are arranged at the same relative positions to the cell regions in which the solar cells are formed in all of the multiple large-sized semiconductor substrates, they can be considered to be arranged regularly between the multiple large-sized semiconductor substrates and can be used as alignment marks. This makes it easy to distinguish between dark areas caused by irregular defects and alignment marks caused by the emission suppression regions 4 when measuring photoluminescence characteristics.

The multiple emission suppression regions 4 may also have an artificial shape that can be distinguished from the shape of a defect. An example of an artificial shape is a shape in which two lines are crossed. This makes it easy to distinguish between dark areas caused by defects of natural shapes and alignment marks created by the emission suppression regions 4 when measuring the photoluminescence characteristics.

(Method of manufacturing solar cell unit)
Next, a method for manufacturing a solar cell unit according to this embodiment will be described with reference to Figures 3A to 3C. Figure 3A is a diagram showing a semiconductor layer formation step in the method for manufacturing a solar cell unit according to this embodiment, and Figure 3B is a diagram showing an electrode layer formation step in the method for manufacturing a solar cell unit according to this embodiment. Also, Figure 3C is a diagram showing a PL inspection step in the method for manufacturing a solar cell unit according to this embodiment.

First, as shown in FIG. 3A, a passivation layer 23 and a first conductive type semiconductor layer 25 are formed on a portion of the back surface side of the semiconductor substrate 11, specifically, on a portion of the first region 7 in the cell region 2 and the emission suppression region 4 in the margin region 3 (semiconductor layer formation process).

For example, a passivation layer material film and a first conductive type semiconductor layer material film may be formed on the entire back surface side of the semiconductor substrate 11 using a CVD method or a PVD method, and then the passivation layer 23 and the first conductive type semiconductor layer 25 may be patterned using an etching method that uses a resist or a metal mask generated using a photolithography technique or a printing technique.

The etching solution for the p-type semiconductor layer material film can be, for example, an acidic solution such as hydrofluoric acid containing ozone or a mixture of nitric acid and hydrofluoric acid, and the etching solution for the n-type semiconductor layer material film can be, for example, an alkaline solution such as an aqueous solution of potassium hydroxide.

Alternatively, when a passivation layer and a first conductive type semiconductor layer are laminated on the back side of the semiconductor substrate 11 using a CVD method or a PVD method, a mask may be used to simultaneously form and pattern the passivation layer 23 and the first conductive type semiconductor layer 25.

Next, a passivation layer 33 and a second conductive type semiconductor layer 35 are formed on another part of the back surface of the semiconductor substrate 11, specifically, on another part of the second region 8 in the cell region 2, the marginal region 3, and the emission suppression region 4 (semiconductor layer formation process). Note that the second conductive type semiconductor layer 35 does not necessarily have to be formed on the marginal region 3, and at least the passivation layer 33 may be formed.

For example, as described above, a passivation layer material film and a second conductive type semiconductor layer material film may be formed on the entire back surface side of the semiconductor substrate 11 using a CVD method or a PVD method, and then the passivation layer 33 and the second conductive type semiconductor layer 35 may be patterned using an etching method that uses a resist or a metal mask generated using a photolithography technique or a printing technique.

Alternatively, when a passivation layer and a second conductive type semiconductor layer are laminated on the back side of the semiconductor substrate 11 using a CVD method or a PVD method, a mask may be used to simultaneously form and pattern the passivation layer 33 and the second conductive type semiconductor layer 35.

In addition, in this semiconductor layer formation process, a passivation layer 13 and an optical adjustment layer 15 may be formed on the entire light-receiving surface of the semiconductor substrate 11, i.e., the entire light-receiving surface of the cell region 2, the margin region 3, and the emission suppression region 4.

Next, as shown in FIG. 3B, a first transparent electrode layer 28 is formed on the first conductive type semiconductor layer 25 in the cell region 2 and the emission suppression region 4, and a second transparent electrode layer 38 is formed on the second conductive type semiconductor layer 35 in the cell region 2 and the emission suppression region 4 (electrode layer formation process).

For example, a transparent electrode layer material film may be formed on the entire back surface of the semiconductor substrate 11 using a CVD or PVD method, and then the first transparent electrode layer 28 and the second transparent electrode layer 38 may be patterned using an etching method that utilizes a resist generated using a photolithography technique or a printing technique, or a metal mask.

Examples of etching solutions for the transparent electrode layer material film include acidic solutions such as hydrofluoric acid containing ozone, or a mixture of nitric acid and hydrofluoric acid.

Alternatively, when the first transparent electrode layer and the second transparent electrode layer are laminated on the back side of the semiconductor substrate 11 using the CVD method or the PVD method, the first transparent electrode layer 28 and the second transparent electrode layer 38 may be simultaneously formed and patterned using a mask.

Next, a first metal electrode layer 29 is formed on the first transparent electrode layer 28 in the cell region 2, and a second metal electrode layer 39 is formed on the second transparent electrode layer 38 in the cell region 2. At this time, a third metal electrode layer 39A is formed across the first transparent electrode layer 28 and the second metal electrode layer 39 in the light emission suppression region 4 (electrode layer formation process).

Methods for forming the metal electrode layer include press printing such as screen printing or gravure printing, and pattern printing such as ejection printing such as inkjet printing. In the pattern printing method, a printing material containing Ag particles, a resin material, and a solvent, i.e., an Ag paste material, is printed and baked (cured) to form the metal electrode layer.

This forms a first electrode layer 27 corresponding to the first conductive type semiconductor layer 25 in the cell region 2, and a second electrode layer 37 corresponding to the second conductive type semiconductor layer 35 in the cell region 2.

A third electrode layer 37A is formed corresponding to the first conductive type semiconductor layer 25 and the second conductive type semiconductor layer 35 of the emission suppression region 4 and electrically shorting them. This promotes non-luminescent annihilation of carriers generated in the semiconductor substrate 11 in the photoluminescence characteristics, forming the emission suppression region 4 in part of the margin region 3, where the emission of the photoluminescence characteristics is suppressed.

Through the above steps, the solar cell unit 1 of this embodiment shown in Figures 1 and 2 is obtained.

Next, as shown in FIG. 3C, for example, light is irradiated onto the light-receiving surface side of the solar cell unit 1, and the photoluminescence characteristics of the cell region 2 (i.e., the solar cell) are measured from the light-receiving surface side of the solar cell unit 1 (i.e., the light-receiving surface side of the semiconductor substrate 11), thereby inspecting the cell region 2 for defects (PL inspection process). At this time, the position of the cell region 2 is identified using the light emission suppression region 4 as an alignment mark.

As described above, according to the solar cell unit 1 and the manufacturing method of the solar cell unit of this embodiment, a light emission suppression region 4 in which the light emission of the photoluminescence characteristics is suppressed is formed in a part of the marginal region 3. As a result, when measuring the photoluminescence characteristics of the cell region 2 from the light receiving surface side of the solar cell unit 1 (i.e., the light receiving surface side of the semiconductor substrate 11), the light emission suppression region 4 can be used as an alignment mark to easily identify the position of the cell region 2 to be inspected (evaluated) (see FIG. 3C).

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various changes and modifications are possible.
(Modification)
Fig. 4 is a cross-sectional view of a solar cell unit according to a modified example of this embodiment, and is a cross-sectional view corresponding to the line II-II shown in Fig. 1. The solar cell unit 1A of modified example 1 shown in Fig. 4 is different from the solar cell unit 1 shown in Fig. 2 in the configuration of the light emission inhibiting region 4.

4, in the emission suppression region 4, the passivation layers 23 and 33, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, and the third electrode layer 37A are not formed on the back surface side of the semiconductor substrate 11. Specifically, in the semiconductor layer forming step and the electrode layer forming step, the passivation layers 23 and 33, the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, and the third electrode layer 37A are not formed in the emission suppression region 4 on the back surface side of the semiconductor substrate 11.
In the emission suppression region 4, at least the passivation layers 23, 33 need not be formed, and the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35, which have a small contribution to light emission due to photoluminescence characteristics, may be formed. Specifically, in the semiconductor layer forming step and the electrode layer forming step, at least the passivation layers 23, 33 need not be formed in the emission suppression region 4 on the back surface side of the semiconductor substrate 11, and the first conductivity type semiconductor layer 25 and the second conductivity type semiconductor layer 35 may be formed.

In the emission suppression region 4, the passivation layer 13 and the optical adjustment layer 15 may not be formed on the light receiving surface side of the semiconductor substrate 11. In the emission suppression region 4, at least the passivation layer 13 may not be formed, and the optical adjustment layer 15, which has a small contribution to the emission of photoluminescence characteristics, may be formed.

As a result, in part of the marginal region 3, a light emission suppression region 4 is formed in which the recombination of carriers (i.e., non-light emission annihilation) that occurs in the semiconductor substrate 11 during photoluminescence characteristics is promoted, and light emission during photoluminescence characteristics is suppressed. Even in this modified example, when measuring the photoluminescence characteristics of the cell region 2 from the light receiving surface side of the solar cell unit 1 (i.e., the light receiving surface side of the semiconductor substrate 11), the light emission suppression region 4 can be used as an alignment mark to easily identify the position of the cell region 2 to be inspected (evaluated).

(Other Modifications)
In the above-described embodiment and modified example, the solar cell unit 1 having a plurality of cell regions 2 on the semiconductor substrate 11 and the manufacturing method thereof have been exemplified. However, the present invention is not limited thereto and can be applied to a solar cell unit having one or more cell regions on a semiconductor substrate and a manufacturing method thereof.

In addition, in the above-described embodiment and modified example, a solar cell unit 1 in which multiple luminescence suppression regions 4 are formed in the marginal region 3 and a manufacturing method thereof are exemplified. However, the present invention is not limited to this, and can be applied to a solar cell unit in which one or more luminescence suppression regions are formed in the marginal region 3 and a manufacturing method thereof.

In addition, in the above-described embodiment and modified example, a solar cell unit 1 in which solar cells using a crystalline silicon material are formed and a manufacturing method thereof are exemplified. However, the present invention is not limited to this, and can be applied to a solar cell unit in which solar cells using various materials are formed and a manufacturing method thereof.

In addition, in the above-described embodiment and modified example, a solar cell unit 1 in which a heterojunction type solar cell is formed and a manufacturing method thereof are exemplified. However, the present invention is not limited to this, and can be applied to solar cell units in which various solar cells such as a homojunction type solar cell are formed and manufacturing methods thereof.

REFERENCE SIGNS LIST 1, 1A, 1X solar cell unit 2 cell region 3 blank region 4 emission suppression region 7 first region 8 second region 11 semiconductor substrate (large semiconductor substrate)
13 Passivation layer 15 Optical adjustment layer 23 Passivation layer (first passivation layer, first semiconductor layer)
25 First conductive type semiconductor layer (first semiconductor layer)
27 First electrode layer 28 First transparent electrode layer 29 First metal electrode layer 33 Passivation layer (second passivation layer, second semiconductor layer)
35 Second conductive type semiconductor layer (second semiconductor layer)
37 Second electrode layer 37A Third electrode layer 38 Second transparent electrode layer 39 Second metal electrode layer 39A Third metal electrode layer

Claims (7)

A solar cell unit having a cell region in which a back electrode type solar cell is formed and a marginal region other than the cell region, on a large-sized semiconductor substrate having photoluminescence characteristics and functioning as a photoelectric conversion substrate ,
A first semiconductor layer including a first passivation layer and a first conductive type semiconductor layer made of a semiconductor, and a second semiconductor layer including a second passivation layer and a second conductive type semiconductor layer made of a semiconductor are formed on a back surface side of the large-sized semiconductor substrate,
In the cell region, a part of the first semiconductor layer is formed on a part of the back surface side of the large-sized semiconductor substrate, a part of the second semiconductor layer is formed on another part of the back surface side of the large-sized semiconductor substrate, a first electrode layer is formed corresponding to a part of the first semiconductor layer, and a second electrode layer is formed corresponding to a part of the second semiconductor layer,
In the blank area, at least the second passivation layer of the second semiconductor layer and the second conductive type semiconductor layer in another part of the second semiconductor layer is formed on the back surface side of the large-sized semiconductor substrate,
a light emission suppression region is formed in a portion of the marginal region, in which light emission of the photoluminescence characteristic is suppressed more than in a portion other than the marginal region and the cell region ;
In the light emission suppression region,
another part of the first semiconductor layer and a further part of the second semiconductor layer are formed on the rear surface side of the large-sized semiconductor substrate, and a third electrode layer is formed corresponding to the other part of the first semiconductor layer and the further part of the second semiconductor layer and electrically short-circuiting them;
The photoluminescence characteristic promotes non-radiative annihilation of carriers occurring in the large-sized semiconductor substrate;
Solar cell unit. A solar cell unit having a cell region in which a back electrode type solar cell is formed and a marginal region other than the cell region, on a large-sized semiconductor substrate having photoluminescence characteristics and functioning as a photoelectric conversion substrate ,
A first semiconductor layer including a first passivation layer and a first conductive type semiconductor layer made of a semiconductor, and a second semiconductor layer including a second passivation layer and a second conductive type semiconductor layer made of a semiconductor are formed on a back surface side of the large-sized semiconductor substrate,
In the cell region, the first semiconductor layer is formed on a portion of the back surface side of the large-sized semiconductor substrate, a portion of the second semiconductor layer is formed on another portion of the back surface side of the large-sized semiconductor substrate, a first electrode layer is formed corresponding to the first semiconductor layer, and a second electrode layer is formed corresponding to a portion of the second semiconductor layer,
In the blank area, at least the second passivation layer of the second semiconductor layer and the second conductive type semiconductor layer in another part of the second semiconductor layer is formed on the back surface side of the large-sized semiconductor substrate,
a light emission suppression region is formed in a portion of the marginal region, in which light emission of the photoluminescence characteristic is suppressed more than in a portion other than the marginal region and the cell region ;
In the light emission suppression region,
A first passivation layer and a second passivation layer are not formed on the rear surface side of the large-sized semiconductor substrate,
The photoluminescence characteristic promotes non-radiative annihilation of carriers occurring in the large-sized semiconductor substrate;
Solar cell unit. 3. The solar cell unit according to claim 1, wherein the light emission suppression region is used as an alignment mark for identifying the position of the cell region when measuring the photoluminescence characteristics of the cell region from the light receiving surface side of the large-sized semiconductor substrate. The large-sized semiconductor substrate has a plurality of the cell regions,
A plurality of the light emission suppression regions are formed in the margin region,
The plurality of light emission suppression regions are regularly arranged.
The solar cell unit according to any one of claims 1 to 3 . The solar cell unit according to claim 1 , wherein the light emission suppression region has an artificial shape that is distinguishable from the shape of a defect. A method for manufacturing a solar cell unit comprising: a large-sized semiconductor substrate having a photoluminescence characteristic and functioning as a photoelectric conversion substrate , the large-sized semiconductor substrate having a cell region in which a back electrode type solar cell is formed; and a blank region other than the cell region; and a first semiconductor layer including a first passivation layer and a first conductive type semiconductor layer made of a semiconductor, and a second semiconductor layer including a second passivation layer and a second conductive type semiconductor layer made of a semiconductor , the method comprising the steps of:
a semiconductor layer forming process of forming a part of the first semiconductor layer in a part of the cell region on the back surface side of the large-sized semiconductor substrate, forming a part of the second semiconductor layer in another part of the cell region on the back surface side of the large-sized semiconductor substrate, and forming at least a second passivation layer of the second conductive type semiconductor layer and a second passivation layer in the other part of the second semiconductor layer in the margin region on the back surface side of the large-sized semiconductor substrate ;
an electrode layer forming step of forming a first electrode layer corresponding to a part of the first semiconductor layer in the cell region and a second electrode layer corresponding to a part of the second semiconductor layer in the cell region;
a PL inspection step of measuring the photoluminescence characteristics of the cell region from the light receiving surface side of the large-sized semiconductor substrate;
Including,
In the semiconductor layer forming step or the electrode layer forming step, a light emission suppression region is formed in a part of the blank region, in which light emission of the photoluminescence characteristic is suppressed more than in the other part of the blank region and in the cell region ;
In the semiconductor layer forming step, another part of the first semiconductor layer and a further part of the second semiconductor layer are formed in the emission suppression region on the back surface side of the large-sized semiconductor substrate,
In the electrode layer forming step, a third electrode layer is formed in a manner to correspond to another part of the first semiconductor layer and a further other part of the second semiconductor layer in the emission suppression region and to electrically short-circuit them;
In the semiconductor layer forming step or the electrode layer forming step, the light emission suppression region is formed in which non-light emitting annihilation of carriers generated in the large-sized semiconductor substrate is promoted in the photoluminescence characteristics,
In the PL inspection step, the position of the cell region is specified using the light emission suppression region as an alignment mark.
A method for manufacturing a solar cell unit. A method for manufacturing a solar cell unit comprising: a large-sized semiconductor substrate having a photoluminescence characteristic and functioning as a photoelectric conversion substrate , the large-sized semiconductor substrate having a cell region in which a back electrode type solar cell is formed; and a blank region other than the cell region; and a first semiconductor layer including a first passivation layer and a first conductive type semiconductor layer made of a semiconductor, and a second semiconductor layer including a second passivation layer and a second conductive type semiconductor layer made of a semiconductor , the method comprising the steps of:
a semiconductor layer forming process of forming the first semiconductor layer in a part of the cell region on the back surface side of the large-sized semiconductor substrate, forming a part of the second semiconductor layer in another part of the cell region on the back surface side of the large-sized semiconductor substrate, and forming at least a second passivation layer of the second conductive type semiconductor layer and a second passivation layer in the other part of the second semiconductor layer in the margin region on the back surface side of the large-sized semiconductor substrate ;
an electrode layer forming step of forming a first electrode layer corresponding to the first semiconductor layer in the cell region and a second electrode layer corresponding to a part of the second semiconductor layer in the cell region;
a PL inspection step of measuring the photoluminescence characteristics of the cell region from the light receiving surface side of the large-sized semiconductor substrate;
Including,
In the semiconductor layer forming step or the electrode layer forming step, a light emission suppression region is formed in a part of the blank region, in which light emission of the photoluminescence characteristic is suppressed more than in the other part of the blank region and in the cell region ;
In the semiconductor layer forming step, a first passivation layer and a second passivation layer are not formed on the back surface side of the large-sized semiconductor substrate in the emission suppression region,
In the semiconductor layer forming step or the electrode layer forming step, the light emission suppression region is formed in which non-light emitting annihilation of carriers generated in the large-sized semiconductor substrate is promoted in the photoluminescence characteristics,
In the PL inspection step, the position of the cell region is specified using the light emission suppression region as an alignment mark.
A method for manufacturing a solar cell unit.

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