JP7628493B2 - Current interruption device for high voltage direct current with capacitive buffer circuit and control method - Google Patents

Description

The present invention relates to the field of networks transporting and/or supplying high voltage direct current, commonly referred to as HVDC networks. The present invention relates in particular to a fault current interruption device for such networks.

HVDC networks are considered in particular as a solution for the interconnection of dissimilar or non-synchronized electric production sites. They are considered in particular for the transport and supply of energy produced by offshore wind farms, rather than AC technology, due to the lower line losses and the absence of parasitic capacitance effects in long-distance networks. Typically, such networks have a voltage level of the order of 100 kV or even higher.

In this specification, devices with a nominal operating voltage greater than 1500V DC are considered high voltage with respect to DC. Additionally, such high voltages are classified as extra-high voltage when they are greater than 75,000V (75kV) DC. Naturally, the high voltage region includes the extra-high voltage region.

The interruption of DC current in such networks is an important consideration that directly affects the feasibility and development of such networks.

Mechanical circuit breaker type interrupting devices are known which realize the interruption of alternating current, i.e. the interruption of the current is realized only by opening a mechanical switching element. Such a mechanical switching element comprises two contact-making conductive parts which are in mechanical and electrical contact when the switching element is closed and which are mechanically separated when the switching element is opened. Such mechanical circuit breakers have various disadvantages when large currents flow through them.

Under high currents and/or voltages, mechanical separation can lead to the formation of an electric arc between the two conductive parts. This is due to the large energy stored in the network that the device protects. If an electric arc is formed due to mechanical separation, the interrupting device does not achieve an electrical interruption, because the current continues to flow through the device due to the presence of the arc. An electrical interruption, in the sense of effectively preventing the current flow, can be very difficult to achieve in situations where an electric arc is likely to be maintained, such as direct current and high voltage. Moreover, this electric arc deteriorates the two contact-making conductive parts by erosion on the one hand, and the surrounding environment by ionization on the other hand. Moreover, due to this ionization, it takes some time to stop the current. This requires maintenance work on the interrupting device, which is troublesome and expensive.

Fault currents in HVDC networks are very violent and destructive. When a fault occurs that produces a large current, it may be necessary to interrupt the current quickly or it may be necessary to limit the current while waiting for the interruption to be possible. Furthermore, interrupting HVDC currents is more difficult to achieve than interrupting alternating current (AC), where the zero crossing of the current is used to achieve the interruption. However, this is not the case for direct current, especially HVDC.

PRIOR ART Various solutions have been proposed to facilitate current interruption in HVDC lines, see for example documents DE 10.2011.083514, WO 2015/078525, WO 2015/166600, US 2017/0178844 or DE 2136865.

Some solutions use a large number of active semiconductor switching elements, mainly thyristors and IGBTs. However, these elements are expensive/power efficient. Excessive use of such semiconductor switches increases the cost of the solution.

WO2015/185096 describes a current interruption device for high voltage direct current. The device comprises a first mechanical switch and a second mechanical switch. The first mechanical switch and the second mechanical switch are inserted in series in the main line between a first point and a second point, but are located on opposite sides of the main line from a midpoint. Each of the two mechanical switches is controlled between an open state and a closed state. The device comprises a first surge suppressor arranged in parallel with the first switch between the first point and the midpoint. The device further comprises a second surge suppressor arranged electrically in parallel with the assembly formed by the first switch and the second switch. The device further comprises a first capacitor arranged in parallel with the first switch, a second capacitor arranged in parallel with the second switch, and a third capacitor arranged electrically in parallel with the assembly formed by the first switch and the second switch. These capacitors are responsible for balancing the voltage between the terminals of these surge suppressors (tensions aux bornes des parasurtenseurs) and therefore between the terminals of the two switches. The device further comprises an LC oscillator circuit arranged electrically in parallel with the assembly formed by the first and second switches. This oscillator circuit is capable of generating a counter current in the main line so as to form a zero crossing of the current in the main line and thus through the two switches. It should be noted, however, that the calibration of the oscillator current is difficult, since the calibration requires that the zero crossing must be performed simultaneously with the elimination of the arc in the two switches. Even if this is possible for a given value of the magnitude of the fault current, it is very difficult to obtain the desired result for another value of the magnitude of the fault current.

The device shown in FIG. 9 of document US 4442469 includes three switches arranged in series in the main line. By opening the three (41a, 41b and 42), an arc is formed between the contacts of each switch. The first switch 42 interrupts the current by means of the capacitor 5 and the negative impedance characteristic of the arc. The discharge gap 8 is then activated, which creates a reverse current and a zero crossing in the switches 41a and 41b, completing the current interruption in the switches 41a and 41b. The resistor 14 and the capacitor 15 are used to balance the voltage between the two switches 41a and 41b. As this solution creates a zero crossing in the first switch 42 based on the voltage of the switching arc, it is very difficult to interrupt large fault currents. Current interruption with this technique is limited to currents below 8 kA.

In the device of document US3758790, the switch S1 is opened to form an arc between its contacts, after which the switch HS is thrown to switch the current in the oscillator circuit LC1 in order to create a zero crossing of the current in S1 and complete the opening of S1. The current is switched to the resistor R1 and drops. Then S2 is opened, the spark gap FS operates and the residual current is switched to the branch C2R2. This creates a zero crossing of the current in S2 and the switch S2 completes the current interruption. With this solution it is difficult to interrupt currents of large magnitude. Moreover, this solution requires that both main switches S1 and S2 have a holding voltage greater than the network voltage. Moreover, this design does not limit surges.

In documents WO 2015/103857, EP 3.091.626, CN 103.296.636 and WO 2012/100831, oscillator circuits are described that combine a capacitor in series with a dedicated inductive element to generate an oscillating current for applying a zero crossing of the current in the switch. As mentioned above, these circuits necessarily require a pre-charged capacitor in the initial state, i.e. before their operation. The charge on the capacitor is used to generate an oscillating current that can counteract the current through the switch. Similarly, these circuits require the presence of a dedicated inductive element to generate the current oscillation in the oscillator circuit and to limit the rate of change of the current.

In short, the prior art does not provide a solution with a current interruption capacity of more than 10 kiloamperes (kA) at a reasonable size and cost. The present invention aims to provide a solution with a current interruption capacity capable of interrupting currents of the order of tens of kiloamperes, e.g., 20 kiloamperes, at a reasonable size and cost.

The invention therefore proposes a current interruption device for high voltage direct current, of the type comprising:
- a main line between the first point and the second point;
a first mechanical switch and a second mechanical switch inserted successively in the main line between a first point and a second point, but arranged on opposite sides of an intermediate point of the main line, each of these two mechanical switches being controlled between an open state and a closed state;
a first surge suppressor arranged in parallel with the first switch between the first point and the intermediate point;
a second surge suppressor arranged electrically in parallel with the second switch;

The second surge suppressor is electrically disposed between the intermediate point and the second point, and the device includes a capacitive buffer circuit disposed between the first point and the second point, electrically in parallel with the assembly formed by the first switch and the second switch, and electrically in parallel with the assembly formed by the first surge suppressor and the second surge suppressor, the capacitive buffer circuit including an actuation switch and a buffer capacitor.

The device according to the invention may also comprise any other feature of the invention, either alone or in combination.

The capacitive buffer circuit preferably does not include a dedicated inductive element.

The actuation switch and the buffer capacitor may be electrically arranged in series in a line of the capacitive buffer circuit extending from the first point to the second point.

The capacitive buffer circuit may include circuitry for discharging the buffer capacitor.

The capacitive buffer circuit may include a third surge suppressor arranged in parallel with the activation switch, for example a third surge suppressor connected directly to multiple terminals of the activation switch and across the area between the terminals.

The device may include an oscillator circuit arranged electrically in parallel with the first switch between the first point and an intermediate point, the oscillator circuit being capable of generating a zero crossing of a current through the first switch.

The oscillator circuit may include at least an inductor, a capacitor, and an oscillation trigger arranged electrically in series with each other in the oscillator circuit.

The device may include at least one damping resistor in the oscillator circuit, electrically in series with the inductor, the capacitor, and the oscillation trigger of the oscillator circuit, and a controllable device for varying the resistance value, inserted in series with the oscillator circuit.

The device may include at least one bypass switch of the damping resistor, the bypass switch being switchable between an open state and an on state, the damping resistor and the bypass switch being arranged such that, when the bypass switch is in one state, the damping resistor is electrically inserted in series with the inductor, the capacitor and the oscillation trigger of the oscillation circuit (the resistance d'amortissement is electrically inserted in series with the inductance, the capacitor and the oscillation trigger of the oscillation circuit), while, when the bypass switch is in another state, the damping resistor is short-circuited with the oscillation circuit (the resistance d'amortissement is short-circuited with the oscillation circuit).

The oscillator circuit may include at least one permanent resistor permanently inserted in the oscillator circuit and electrically in series with the inductor, capacitor and oscillation trigger of the oscillator circuit.

The oscillator circuit may include a plurality of damping resistors, each of the plurality of damping resistors associated with a separate bypass switch for that damping resistor, each bypass switch being switchable between an open state and an on state, and the damping resistors and associated bypass switches may be arranged such that when the bypass switch is in one state, the damping resistor associated with the switch is inserted electrically in series with the oscillator circuit and is in electrical series with the inductor, capacitor and oscillation trigger of the oscillator circuit, while when the bypass switch is in another state, the damping resistor associated with the switch is shorted with the oscillator circuit.

The first switch may be or may include at least one vacuum switch.

The second switch may be or may include at least one insulating gas switch. Alternatively, the second switch may be or may include at least one vacuum switch.

In one embodiment, the second surge suppressor is electrically disposed between the intermediate point and the second point, and the device includes a capacitive buffer circuit disposed between the first point and the second point, electrically in parallel with the assembly formed by the first switch and the second switch, and electrically in parallel with the assembly formed by the first surge suppressor and the second surge suppressor, the capacitive buffer circuit including an actuation switch, a buffer capacitor, and a circuit for discharging the buffer capacitor, and the device is characterized in that the capacitive buffer circuit does not include a dedicated inductive element.

The present invention also relates to a method for controlling the above-mentioned shutoff device, comprising the steps of:
- mechanically opening the first switch and the second switch;
interrupting the current in the open first switch and generating voltages across the terminals of the first switch that are higher than the transition voltage of the first surge suppressor and are suitable for switching the first surge suppressor into current carrying mode;
- switching the activation switch in the capacitive buffer circuit so that a suitable current flows to charge the buffer capacitor and to divert the current in the second switch.

The method may comprise the steps of:
- mechanically closing the first switch;
determining one or more parameters of the current through the device or the phase-to-ground voltage and provoking an action to cause a rapid reopening of the device as a function of the parameters of the current through the device or the phase-to-ground voltage;
- Mechanically closing a second switch if the device is not promptly reopened.

Such a method may further comprise determining a value of the magnitude of the current flowing through the device that is to be interrupted and determining a state in which at least one bypass switch is to be switched (de l'état dans lequel l'au moins un interrupteur de bypass doit etre bascule) depending on the determined value of the magnitude of the fault current.

In some methods of the present invention, at least some of the multiple bypass switches of the oscillator circuit may be switched with a time lag relative to one another.

In some methods of the present invention, the buffer capacitor is initially discharged such that when the actuation switch is switched, a current suitable for charging the buffer capacitor flows in the capacitive buffer circuit.

FIG. 1 is a schematic diagram of a first embodiment of a cutoff device according to the present invention. FIG. 2 is a schematic diagram of a second embodiment of a shutoff device according to the present invention. FIG. 3 is a graph showing, in a schematic manner, the variation of some quantitative characteristics relating to the operation of the device during the opening process according to a first embodiment of the invention. FIG. 4 is a schematic diagram of a variant of an oscillator circuit that can be implemented in a shutdown device according to the present invention.

Figure 1 shows a schematic diagram of a first embodiment of a circuit breaker device 10 according to the present invention. The device is for direct current at high or even extra-high voltages.

As seen in FIG. 1, the current interruption device 10 includes a first point, which may be a first terminal 12, and a second point, which may be a second terminal 14. The first point 12 and the second point 14, or these terminals, form the current input/output of the device 10. Each of these points may correspond to a physical terminal of the device 10, e.g., a physical connection terminal of the device 10, or a virtual terminal that is a (long) point on a conductor.

The device 10 includes a main line 16. The main line 16 extends between a first terminal 12 and a second terminal 14. A first switch 18 having a first terminal 20 and a second terminal 22 and a second switch 24 having a first terminal 26 and a second terminal 28 are inserted in series in the main line 16 between the first point 12 and the second point 14. The first terminal 20 of the first switch 18 is at the same potential as the first point 12. The second terminal 28 of the second switch 24 is at the same potential as the second point 14. The second terminal 22 of the first switch 18 and the first terminal 28 of the second switch 24 are at the same potential, and are at the same potential as the intermediate point 13 of the main line 16 disposed between the two switches 18, 24. When the first switch 18 and the second switch 24 are in a current-carrying on state, a current flows in the main line 16 through the device 10. The main line 16 is the line with the lowest impedance between the first point 12 and the second point 14 in the device 10. One or both of the first switch 18 and the second switch 24 can be switched to an open state or a closed state.

The device 10 is intended to be incorporated into an electrical installation. For example, the first terminal 12 of the device 10 may be connected to a part of the installation that may include a high voltage source. The high voltage source may be, for example, greater than 100 kilovolts. The second terminal 14 may be connected to, for example, a current consuming circuit. The current consuming circuit may be, for example, an electrical load or an electrical network. In this aspect, in the illustrated example, the first terminal 12 may be considered to be an upstream terminal or current input terminal, while the second terminal 14 may be considered to be a downstream terminal or current output terminal, with respect to the direction of current flow. In this example, the main line 16 of the device is intended to carry a nominal current applied by a DC voltage source. However, the device 10 according to the invention is reversible, and the flow of current through the device may be in the opposite direction.

The electrical equipment is adapted to operate at a nominal direct current voltage in the high voltage range, i.e. at least greater than 1500 volts, preferably in the extra high voltage range, i.e. greater than 75000 V. The invention may be advantageously applied in particular to interrupting devices capable of interrupting currents of up to 3000 Amperes, preferably up to 10000 Amperes or even up to 20000 Amperes, at voltages of at least greater than 100000 Volts (100 kV).

The first switch 18 and the second switch 24 may be, in particular, a circuit breaker type, a disconnector type, or a fuse type. In a more specific example below, each of the first switch 18 and the second switch 24 is formed, for example, by a circuit breaker.

Both the first switch 18 and the second switch 24 are preferably mechanical electrical interruption devices in which electrical interruption is achieved by moving, in particular moving apart, two electrical contacts or a pair of electrical contacts. In mechanical devices, the movement of the electrical contacts is generally performed by a mechanical, pneumatic, hydraulic or electrical operating member or actuator and may be by motion transmission kinematics. This movement may be monitored electronically. As mentioned above, in the presence of high currents and/or high voltages, the mechanical separation of the electrical contacts may cause an electrical arc to form between the two electrical contacts in the switch. This is due to the large energy stored in the network that the device protects. If the electrical arc remains formed due to the mechanical interruption, the switch does not achieve electrical interruption because the current continues to flow through the switch due to the presence of the arc. As will be explained below, the present invention provides a means for achieving electrical interruption in the sense of effectively preventing the flow of current.

Each of the first switch 18 and/or the second switch 24 may be a single mechanical electrical interrupting device, or may be a number of mechanical electrical interrupting devices arranged electrically in series and/or in parallel. This may be what is called a "metal-encased" device, in which the current supply means (also called a "busbar") is housed in a sealed container filled with an insulating fluid. In particular, a metal-encased device may be designed to be more compact than a device in which isolation is achieved in air.

The mechanical electrical cutoff switch may be of conventional type, in particular comprising two electrodes held by an insulating support in a fixed position away from the periphery of the vessel at earth potential. The electrodes are electrically connected or electrically separated depending on the position of a movable connecting member forming part of one of the electrodes. The movable connecting member may be, for example, a sliding tube driven by command. The tube is generally held by the electrode to which it is electrically connected, and the separation of the tube from the opposite electrode tends to cause an electric arc. This electric arc may be sustained for the duration of the opening operation of the switch, during which the tube moves away from the opposite electrode. The mechanical electrical cutoff switch usually comprises two pairs of electrical contacts held by the tubes and two electrodes. The first pair is the pair through which the nominal current flows in the fully closed state of the device. This contact pair may be supported by a second pair of contacts, which may be called the arcing contact pair or the second contact pair. The two contacts in this pair are intended to remain in direct contact during separation of the first pair to minimize arcing in the first pair and ensure good electrical conductivity in the fully closed state. Conversely, the contacts of the second pair are separated last and an electrical arc is formed.

In some embodiments of the invention, the second switch 24 is an insulating fluid switch or includes at least one insulating fluid switch. The insulating fluid switch is in particular an insulating gas switch. This type of switch is particularly suitable for interrupting currents under high voltages, even very high voltages. In such a device, the active interrupting member, in particular the electrical contacts, are contained in a sealed container in which an insulating fluid is present. The insulating fluid can be a gas, usually sulfur hexafluoride (SF ₆ ), but a liquid or oil can also be used. The insulating fluid is a pressurized fluid, for example at a pressure of 3 bar absolute or more. This fluid is chosen for its insulating properties, in particular to have a dielectric strength greater than that of dry air at an equivalent pressure.

In some embodiments, the first switch 18 is a vacuum switch or includes at least one vacuum switch. In the first switch 18, the active interrupting member, in particular the electrical contacts, are contained in a sealed container at a pressure below atmospheric pressure, in particular below 100 mbar, in particular below 10 microbar. Such a switch has the advantage that complete electrical interruption can be achieved even when the rate of change of the current intensity is high, i.e. the derivative of the intensity with respect to time (dI/dt) is high.

In some embodiments, including those described in more detail below, the first switch 18 is or includes a vacuum switch, and the second switch 24 is or includes an insulating fluid switch, particularly an insulating gas switch, although other combinations are possible. For example, the device may include a combination of a first switch and a second switch of the same technology, particularly both of the vacuum switch type.

As seen in FIG. 1, the device 10 includes a first surge suppressor 30 disposed in parallel with the first switch 18 between the first point 12 and the intermediate point 13 and thus electrically in parallel with the first switch 18, and a second surge suppressor 32 disposed in parallel with the second switch 24 and thus electrically in parallel with the intermediate point 13 and the second point 14.

Such surge suppressors limit the magnitude of the potential difference between the terminals of the switches placed in parallel with them. A surge suppressor 30, 32 or "voltage surge arrester" is therefore a device that limits the peak voltage across its terminals. The surge suppressor 30, 32 typically comprises an electrical element having a variable resistance that varies with the voltage across its terminals. The change in resistance is typically non-linear with respect to the voltage across the terminals of the surge suppressor 30, 32. Typically, when the voltage across the terminals of the surge suppressor 30, 32 is below the transition voltage, the resistance of the surge suppressor 30, 32 is high and there is zero or a relatively small drop in resistance with increasing voltage, and the surge suppressor preferably conducts a leakage current of less than 1 ampere (A), or even less than 100 milliamperes (mA). On the other hand, when the voltage across the terminals of the surge suppressor is higher than the transition voltage, the resistance of the surge suppressor drops rapidly with increasing voltage, leading to a clipping voltage value or protection voltage, at which the resistance of the surge suppressor is low or even very low. In other words, the surge suppressor acts as a limiter of the voltage across its terminals over a selected current range. The surge suppressor applies a protection voltage when passing a maximum current according to the size of the surge suppressor. Below the transition voltage, the surge suppressor prevents the current from passing. Above the transition voltage, the surge suppressor allows current to pass through the surge suppressor, and the voltage across its terminals rises slightly. As is known, the transition voltage usually does not correspond to an exact value, but rather to a range of transition voltages. However, in this specification, the transition voltage of a surge suppressor is defined as the voltage at which one ampere (A) of current passes through the surge suppressor. The protection voltage is the voltage across the terminals of the surge suppressor when the surge suppressor carries a maximum current according to its size. Among surge suppressors, lightning arresters are known which may in particular comprise a number of varistors and TVS diodes (transient voltage suppression diodes such as "Transil" diodes). In particular, within the scope of the present invention, each of the first surge suppressor 30 and/or the second surge suppressor 32 may comprise a metal oxide varistor (or MOV).

Advantageously, in the illustrated example, the first surge suppressor 30 may be a surge suppressor having a transition voltage in the range of, for example, 10,000 volts (10 kV) to 100,000 volts (100 kV). The second surge suppressor 32 is typically a surge suppressor having a transition voltage higher than the transition voltage of the first surge suppressor 30. More specifically, the surge suppressors preferably have transition voltages such that the transition voltage ratio between the second surge suppressor 32 and the first surge suppressor 30 is between 1 and 10.

The transition voltage of the first surge suppressor 30 is strictly less than the nominal voltage of the electrical equipment into which the interruption device 10 is inserted. In a particularly optimized embodiment, the first surge suppressor 30 and the second surge suppressor 32 are selected such that the sum of the transition voltage of the first surge suppressor 30 and the transition voltage of the second surge suppressor 32 is equal to or greater than the nominal voltage of the electrical equipment.

By selecting a first surge suppressor 30 with a protection voltage less than 200 kV, the voltage across the terminals of the first switch 18 is maintained at or below this protection voltage, allowing the use of a switch with significantly lower cost and space requirements than an equivalent high voltage system. Electrical interruption at the first switch 18 is also facilitated.

Each of the first surge suppressor 30 and/or the second surge suppressor 32 may be formed by an assembly of multiple discrete elements arranged electrically in series and/or in parallel. For example, each discrete element is a lightning arrester, a varistor, in particular a metal oxide varistor, or a TVS diode. Preferably, the assembly of multiple discrete elements arranged electrically in series and/or in parallel behaves, in the eyes of the rest of the device, as a single surge suppressor with an equivalent transition voltage as an assembly and an equivalent protection voltage as an assembly.

1 and 2, the interrupter 10 according to the present invention includes a capacitive buffer circuit 34 without a dedicated inductive element, which is provided between the first point 12 and the second point 14, electrically in parallel with the assembly formed by the first switch 18 and the second switch 24, and electrically in parallel with the assembly formed by the first surge suppressor 30 and the second surge suppressor 32. The capacitive buffer circuit 34 includes an operating switch 36 and a buffer capacitor 38. In the illustrated example, the circuit includes an electric line 35. One end of the electric line 35 is electrically connected to the main line 16 at a point at the same potential as the first point 12 and the same potential as the first terminal 20 of the first switch 18. The other end of the electric line 35 is electrically connected to the main line 16 at a point at the same potential as the second point 14 and the same potential as the second terminal 28 of the second switch 24. The operating switch 36 and the buffer capacitor 38 are electrically inserted in series into the line 35. The buffer capacitor 38 may, for example, comprise one or more capacitors having a total electrical capacitance C38, or may be formed by one or more capacitors having a total electrical capacitance C38.

The capacitive buffer circuit 34, like any other circuit, may have a parasitic inductance, which arises in particular from the nature of the electrical elements it comprises and from the geometry of the circuit. However, within the meaning of the present invention, the capacitive buffer circuit 34 does not contain a dedicated inductive element, i.e. does not contain any discrete elements with the desired inductive function, and therefore does not contain any elements with an inductance greater than the parasitic inductance, in particular does not contain any coils or inductive ferromagnetic cores. The inductance of the capacitive buffer circuit is therefore very low, for example less than 50 microhenries or even less than 1 microhenry per 10 kilovolt range of nominal network voltage.

In some embodiments, such as those shown in Figs. 1 and 2, the capacitive buffer circuit 34 includes a circuit for discharging the buffer capacitor 38. In the example of Figs. 1 and 2, the discharge circuit is a passive discharge circuit and does not have an active element. In this example, the discharge circuit includes a resistor 39 arranged in parallel with the buffer capacitor 38. Preferably, the resistor 39 has a high electrical resistance value R39. The electrical resistance value R39 is such that the dipole of the parallel buffer capacitor 38 and resistor 39, inserted in the electrical line 35, has a time constant that is important compared to the electrical interruption time in the second switch 24. This time constant is, for example, a time constant greater than 50 milliseconds, preferably greater than 100 milliseconds. In this example, the time constant is equal to the product R39 x C38. Other types of discharge circuits not shown may include at least one active element, such as a controlled switch. The discharge circuit may comprise a control switch connected directly to and electrically in series with the resistor 39, the assembly of these two elements being arranged in parallel with the buffer capacitor 38. When the control switch is switched on and current is flowing, a discharge circuit may be formed between the two plates of the buffer capacitor 38.

1 and 2 differ from each other only by the presence of a third surge suppressor 37 arranged in parallel with the activation switch 36 in the capacitive buffer circuit 34 of the interrupter device 10 of FIG. 2. The third surge suppressor 37 is advantageously arranged, as shown, so as to be connected directly to the terminals of the activation switch 36 and only across the area between the terminals, and is electrically connected in series with the buffer capacitor 38 in the line 35 of the capacitive buffer circuit 34, in the sense that it is arranged on the opposite side (this third surge suppressor 37 can be used either directly or in series with the buffer capacitor 38, as shown in the figure, directly and uniquely connected to the activation switch 36, which is opposite to the line 35 of the charging capacitor 34). The third surge suppressor 37 may advantageously be sized to limit the voltage across the terminals of the actuation switch 36. For example, a surge suppressor may be selected that has a protection voltage in the range of 10,000 volts (10 kV) to 200,000 volts (200 kV). By selecting a third surge suppressor 37 with a protection voltage in this voltage range, the voltage across the terminals of the actuation switch 36 is maintained in this voltage range, thereby allowing the use of a switch that has significantly less cost and space requirements than an equivalent higher voltage system.

However, it should be noted that if such a third surge suppressor 37 is present in the capacitive buffer circuit 40, the third surge suppressor is preferably selected to have a transition voltage greater than the protection voltage of the first surge suppressor 30. Specifically, this prevents current from flowing through the third surge suppressor 37 before the activation switch 36 is closed, thereby avoiding charging of the buffer capacitor 38 before the activation switch 36 is closed.

The role of such a buffer circuit 34 and the advantages of its presence will become more clearly apparent from the description of the operation of the device given therewith. For this purpose, reference is made to FIG. 3, which shows the variation of some parameters of the device during a breaking operation implemented with such a breaker device 10. However, before describing the role of the buffer circuit 34 and the advantages of its presence, supplementary elements of another variant of the breaker device 10 are generally described below. These supplementary elements are optional.

In the illustrated example, the interruption device 10 advantageously includes an oscillator circuit 40 arranged electrically in parallel with the first switch 18 between the first point 12 and the intermediate point 13. The oscillator circuit 40 is designed and capable of generating a zero crossing of the current flowing through the first switch 18, in this case a current flowing only through the first switch 18 and not through the second switch 24.

The purpose of such an oscillator circuit 40 is to facilitate electrical interruption at the first switch 18 when the first switch 18 is mechanically opened. Even after such switch opening, electrical arcing may continue to form between spaced contacts in the switch, which may prevent effective electrical interruption from being achieved. The zero crossing of the current through the first switch, generated by the oscillator circuit 40, facilitates electrical interruption at the first switch 18.

Other embodiments of the oscillator circuit 40 are possible. In particular, oscillator circuits described in the prior art mentioned in the preamble of this specification or derived from such prior art may be used.

In some embodiments, such as those shown diagrammatically in FIGS. 1, 2 and 5, the oscillator circuit 40 includes at least an inductor 42, a capacitor 44 and an oscillation trigger 46. These are electrically connected in series with the oscillator circuit 40 and are arranged to be electrically parallel with the first switch 18 between the first point 12 and the intermediate point 13. FIG. 4 shows an embodiment of the oscillator circuit 40. This oscillator circuit 40 includes only an inductor 42, a capacitor 44 and an oscillation trigger 46. These are electrically connected in series with the oscillator circuit 40 and are arranged to be electrically parallel with the first switch 18 between the first point 12 and the intermediate point 13. To operate such an oscillator circuit 40, the capacitor is advantageously precharged before the oscillator circuit 40 starts its operation. In this case, the circuit 40 may further include a circuit (not shown) for precharging the capacitor 44. Furthermore, in the example shown in FIGS. 1 and 2, it is advantageously possible to provide at least one damping resistor 48 and at least one bypass switch 50 for the damping resistor in such an oscillator circuit. The bypass switch 50 is switchable between an open state and an on state. The damping resistor 48 and the bypass switch 50 are arranged such that when the bypass switch 50 is in one state, the damping resistor 48 is electrically in series with the oscillator circuit 40 and is electrically in series with the inductor 42, the capacitor 44, and the oscillation trigger 46, while when the bypass switch 50 is in another state, the damping resistor 48 is shorted in the oscillator circuit 40.

It should be noted that the damping resistor 48 may be formed by an assembly of multiple discrete elements arranged electrically in series and/or in parallel. In that case, the associated bypass switch 50 is typically arranged electrically in parallel with that assembly.

1 and 2, the oscillator circuit 40 extends from the first point 12 to the intermediate point 13, where it is directly connected to the first switch 18 and is arranged in parallel with only the first switch 18. In the electrical line of the oscillator circuit 40, the damping resistor 48 is electrically in series with the inductor 42, the capacitor 44, and the oscillation trigger 46. The bypass switch 50 is directly connected to the damping resistor 48 and arranged in parallel with only the damping resistor 48. When the bypass switch 50 is open, the damping resistor 48 is electrically in series with the oscillator circuit 40 and is electrically in series with the inductor 42, the capacitor 44, and the oscillation trigger 46, while when the bypass switch 50 is closed, the damping resistor 48 is short-circuited with the oscillator circuit 40.

The oscillation trigger 46 is a switch, advantageously a semiconductor switch, but may also be a mechanical switch. The oscillation trigger 46 is preferably a bidirectional switch. As in the example of Figs. 1 and 2, the oscillation trigger 46 may be formed by an assembly of two thyristors 46a and 46b parallel and oriented in opposite directions. Such an assembly is similar to a TRIAC. However, other semiconductor elements, such as IGBTs or other types of controlled spark gaps, may be used. From the point of view of voltage resistance or current handling, the oscillation trigger 46 may also be formed by an assembly of several switches arranged electrically in series and/or in parallel. However, the oscillation trigger 46 may preferably be controlled to behave as a single switch with respect to the rest of the device.

The bypass switch 50 is advantageously a semiconductor switch, but may also be a mechanical switch. The bypass switch 50 is preferably a bidirectional switch. As in the example of Figs. 1 and 2, the bypass switch 50 may be formed by an assembly of two thyristors 50a and 50b parallel to each other and oriented in opposite directions. Such an assembly is similar to a TRIAC. However, other semiconductor elements such as IGBTs or other types of controlled spark gaps may be used. From the viewpoint of voltage resistance or current handling, the bypass switch 50 may also be formed by an assembly of several switches arranged electrically in series and/or in parallel. However, the bypass switch 50 may preferably be controlled to behave as a single switch with respect to the rest of the device.

In a variant not shown, the oscillator circuit 40 includes at least one permanent resistor permanently inserted in the oscillator circuit 40 and electrically in series with the inductor 42, the capacitor 44 and the oscillation trigger 46, thereby determining the minimum value of the resistance of the oscillator circuit when the damping resistor 48 is shorted in the oscillator circuit 40. The permanent resistor may be formed by an assembly of multiple discrete elements arranged electrically in series and/or in parallel.

In yet another variation of the oscillator circuit 40, the oscillator circuit 40 may include at least one second damping resistor and at least one second bypass switch associated with the second damping resistor. For example, the second damping resistor and the second bypass switch are arranged in parallel with each other in such a manner that when the second bypass switch is in one state, the second damping resistor is electrically in series with the oscillator circuit 40 and is electrically in series with the inductor 42, the capacitor 44 and the oscillation trigger 46, and when the first damping resistor 48 is inserted in the oscillator circuit 40, the second damping resistor is electrically in series with the first damping resistor 48. In another state of the second bypass switch, the second damping resistor is shorted in the oscillator circuit 40. Of course, this variation can be generalized to more than two damping resistors and therefore more than two bypass switches. By having multiple damping resistors, each associated with a bypass switch, the bypass switches can be controlled simultaneously. Conversely, at least some of the multiple bypass switches of the oscillator circuit may be switched with a time lag from each other. More than two resistance steps can be applied to the total resistance of the oscillator circuit.

The two variants described above are incorporated into an oscillator circuit that simultaneously includes at least one permanent resistor and multiple damping resistors, all of which are or can be inserted in series with each other in the oscillator circuit.

Other embodiments of the oscillator circuit 40 may include control switches, exemplified by semiconductor switches configured according to, for example, an H-Bridge, half-point, etc. Each of these switches may be formed by an IGBT (insulated gate bipolar transistor), a thyristor, or other type of transistor.

In FIG. 3 the variation over time of the following parameters is depicted for a disconnection device according to the invention switching from a closed state, with current flowing through the device, to an open state, with the first point 12 electrically isolated from the second point 14:
- voltage V24 across the terminals of the second switch 24;
- the intensity I24 of the current through the second switch 24;
- the intensity I46 of the current through the oscillation trigger 46;
- the intensity I50 of the current through the bypass switch 50;
- voltage V18 across the terminals of the first switch 18
- the intensity I18 of the current through the first switch 18;
- the intensity I30 of the current flowing through the first surge suppressor 30;
- the intensity I32 of the current flowing through the second surge suppressor 32;
- the intensity I12 of the current flowing through the device 10; and - the voltage V1214 across the terminals of the device 10;

The control method for controlling the interrupting device 10 according to the present invention comprises a step of mechanically opening the first switch 18 and the second switch 24 with a view to transitioning the device from the closed state to the open state. The two switches may be mechanically opened simultaneously or successively in any order. In the example of FIG. 3, the opening is effective at time t0. The step of opening the two switches may be initiated by a simple request to open the interrupting device, for example at a nominal load with a nominal current flowing through the device 10, in order to electrically isolate a part of the electrical equipment electrically connected to the first point 12 of the device 10 from another part of the electrical equipment electrically connected to the second point 14 of the device 10. The step of opening the two switches may be initiated by the occurrence of an electrical fault in the electrical equipment, for example with a fault current flowing through the interrupting device 10. The fault current may be greater than the maximum nominal current flowing through the device 10. Such opening upon occurrence of a fault may be based on detection of the fault, in particular detection of one or more parameters of the current flowing through the device 10, for example detection of the intensity of the current flowing through the device 10. It should be noted that, as mentioned above, the mechanical opening of the two switches 18, 24 may not by itself result in an electrical opening in the sense of interrupting the flow of current through the interruption device 10 due to the formation of an electric arc in each of the two switches. The following method description is based on this premise.

In this premise, the method creates a voltage across the terminals of the first switch 18 suitable for interrupting the current in the open first switch 18 and switching the first surge suppressor 30 to a current conduction mode above the transition voltage of the first surge suppressor 30. Any of the oscillator circuits 40 described above can be used to interrupt the current in the open first switch 18. However, interrupting the current in the open first switch 18 may also be achieved by other means, in particular by appropriately sizing the first switch 18, although such sizing would make the first switch larger and/or more expensive than if the oscillator circuit were present. In the example of FIG. 3, the implementation of the oscillator circuit 40 is initiated at time t1, which corresponds to the turning on of the oscillation trigger 46, and the electrical opening of the first switch 18 is effective at time t3.

In all cases, when the current through the first switch 18 is interrupted, the current through the device 10 charges the capacitor 44, which causes a rise in voltage across the capacitor 44, which in turn causes the same voltage across the first surge suppressor 30, which in turn causes the same voltage across the first switch 18. If the fault current is large, this voltage reaches the transition voltage of the first surge suppressor 30 at time t4 in FIG. 3, and the resistance of the first surge suppressor 30 changes, limiting the rise in voltage and causing the voltage to plateau. At this stage, the first surge suppressor 30 is considered to be conducting current. From time t4, the current through the device 10 flows through the first surge suppressor 30, but continues to flow through the second switch 24 due to the presence of an arc between the contacts of the second switch 24.

In order to interrupt the electric arc in the second switch 24, it is necessary to wait for the current in the oscillation trigger 46 to disappear, the insulation of the oscillation trigger 46 to be restored, and then for the capacitive buffer circuit 34 to be activated by closing the activation switch 36. This corresponds to the time t5 in FIG. 3. In other words, the activation switch 36 is switched so that in the capacitive buffer circuit 34, a suitable current flows to charge the buffer capacitor 38 and to divert the current from the second switch 24. In the initial state, the buffer capacitor 38 is discharged, for example, due to the presence of a discharge circuit formed here by the discharge resistor 39. In other words, the interruption device 10 is configured such that in the initial state, when the activation switch 36 is switched, a suitable current flows in the capacitive buffer circuit 34 to charge the buffer capacitor 38. Therefore, and due to the presence of a potential difference between the terminals of the first surge suppressor 30, the current flowing through the device 10 is switched to the capacitive buffer circuit 34, charging the buffer capacitor 38. Firstly, in the illustrated example, the resistance value R39 of the resistor 39 is sufficiently large so that the discharge current through it can be neglected. Conversely, the value of the electrical impedance of the capacitive buffer circuit 34 is significantly smaller than it was before the time t5. The charging period of the buffer capacitor 38, which in FIG. 3 lasts until the time t6, is very important, since during this period the current through the device 10 flows substantially through the capacitive buffer circuit 34 in the form of a current I36 through the actuation switch 36, which reduces or cancels the current through the second switch 24. It should be recalled here that the second switch 24 is in a mechanically interrupted state with its contacts separated from each other. The reduction or even cancellation of the current I24 through the second switch 24 advantageously causes the extinction of the electric arc in the second switch 24. It should be noted that the period from time t5 to time t6, during which current should be diverted from the second switch 24 to the buffer circuit 34 and may be referred to as the diversion period d2t, does not need to be very long. The period d2t during which the capacitive buffer circuit 34 passes current only needs to be longer than the period required to deionize the gas present between the spaced contacts of the second switch 24. Once the gas is deionized, the gap in the contacts of the second switch 24 is sufficient to prevent restrike of the arc. The period d2t is on the order of a few microseconds, and is preferably less than 20 microseconds.

The deviation period d2t, during which the current I24 in the second switch 24 is reduced or even cancelled, can be adjusted to the required period by appropriately sizing the circuit elements. Typically, an increase in the total electrical capacitance C38 of the buffer capacitor 38 tends to increase the deviation period d2t.

In a first approximation, the deviation term d2t can be assumed to be governed by the following law:
d2t=Vt30×C38/Idef,
Where:
d2t is the desired deviation period;
Vt30 is the transition voltage of the first surge suppressor 30;
C38 is the total electrical capacitance of the buffer capacitor 38;
Idef is the value of the fault current flowing through the device.

As a guideline, an advantageous value for the total electrical capacitance C38 of the buffer capacitor 38 is this value multiplied by the maximum fault current value Idefmax expected to flow through the device during the desired deflection period d2t divided by the transition voltage Vt30 of the first surge suppressor 30, i.e.:
C38=d2t×Idefmax/Vt30
It can be determined so that the above is the case.

After time t6, the second switch 24 is electrically opened and it is considered that a voltage can develop across the terminals of the second switch 24 without the risk of re-igniting the electric arc. This voltage is mirrored across the terminals of the second surge suppressor 32, which can serve to limit the voltage across the terminals of the second switch. The sum of the voltage across the terminals of the surge suppressor 30 and the voltage across the terminals of the surge suppressor 32 is the voltage 1214. The sum of the voltages can be greater than the nominal voltage of the network as long as there is a current flowing through the surge suppressor, i.e. as long as the current I32 is different from zero. This has a direct connection with the absorption of energy into the network.

From time t7 onwards, the interruption device 10 is considered to be open, since only leakage current can flow through the device 10, via the first surge suppressor 30 and the second surge suppressor 32. In this regard, it should be noted that the voltage across the terminals of the interruption device 10 is the sum of the voltage across the terminals of the first surge suppressor 30 and the voltage across the terminals of the second surge suppressor 32. Typically, this voltage is equal to the nominal voltage of the installation in the steady state with the interruption device 10 open. It is therefore wise to select the first surge suppressor 30 and the second surge suppressor 32 such that the sum of their transition voltages is equal to or greater than the nominal voltage of the installation.

It should be noted that the interrupting device 10 according to the invention may be associated electrically in series with other interrupting devices in the electrical installation, for example of the disconnector type, which are able to completely and reliably interrupt the current in the line. The other interrupting devices may be sized such that their insulation performance is optimized without the need to optimize their current interrupting capacity, since the current interrupting capacity is primarily ensured by the interrupting device according to the invention.

It should further be noted that the interrupting device of the present invention is a bidirectional device capable of interrupting current flowing through the device regardless of the direction of flow, and therefore capable of interrupting current flowing in both directions through the device. Thus, such an interrupting device may be implemented in an installation that includes a mesh network in which direct current may flow in either direction on the line, depending on the configuration of the network at a given time.

The device according to the invention allows for rapid and reliable electrical opening, stopping the flow of high-intensity (particularly greater than 10 kA) fault currents at high voltages, especially greater than 100 kV. However, once the device has been opened, it is necessary to be able to electrically reclose the interrupting device 10 in order to restore the current, if the cause of the fault appears to have disappeared. In this example, the device 10 is controlled so that the first switch 18 and the second switch 24 are mechanically closed, preferably sequentially and in that order, i.e. the first switch 18 is mechanically closed and then the second switch 24. It should be noted that by observing this sequence, the second surge suppressor 32 allows for limiting the inrush current when the first switch 18 is mechanically closed again.

Immediately after the first switch 18 has been closed, one or more parameters of the current through the interrupting device 10 and/or of the phase-to-ground voltage or in the installation may be determined in order to verify, inter alia, that the fault has been cleared. However, the fault may not have been cleared. Depending on the detected parameters of the current through the device and/or the phase-to-ground voltage, a rapid reopening of the device may then be triggered without waiting for the reclosing of the second switch 24, which would be a complete reclosing of the device 10.

To achieve an effective electrical interruption at the first switch as described above, another oscillator circuit 40 can be used. The oscillator circuit shown in FIG. 5 is relatively simple to implement. However, this circuit must be configured so that it can interrupt all possible fault currents, especially those with the maximum magnitude that can be imagined. However, in use, fault currents that do not reach this maximum value can occur. In this example, it can be seen that an oscillator circuit such as that shown in FIG. 5 is too large in the sense that the reverse current it generates is very large compared to the fault current. Furthermore, in this example, the oscillator circuit 40 generates one or more zero crossings of the current through the first switch 18, but such zero crossings occur in a situation where the rate of change of the magnitude d(I18)/dt at the first switch 18 is too high. In a situation where the rate of change of the magnitude d(I18)/dt at the first switch 18 is too high, the zero crossings may not result in an electrical interruption.

It is therefore proposed to implement the oscillator circuit 40 depicted in Figures 1 and 2 and described above. Such a device allows the insertion, if desired, of a damping resistor 48 in a controllable manner, even temporarily, in the oscillation loop formed by the oscillator circuit 40 and the part of the main line 16 including the first switch 18. This allows the oscillation current injected into the oscillation loop by the oscillator circuit 40 to be changed at lower cost, without the oscillation capacitor 44 being charged or its initial charge level increasing, or the inductor 42 being charged. The presence of the bypass switch 50 allows the oscillator circuit 40 to be changed instantly from an RLC series circuit to an LC series circuit and vice versa. In another embodiment, the presence of a bypass switch 50 associated with the damping resistor 48 allows the oscillator circuit 40, which is an RLC series circuit, to be instantly changed to another RLC series circuit with a different total electrical resistance.

Depending on the fault current flowing through the main line 16, an oscillating current can be injected into the oscillation loop, originating from the discharge of one RLC series circuit, the discharge of one LC series circuit, or the discharge of another RLC series circuit with a different total electrical resistance, in order to achieve effective electrical interruption in the first switch 18.

In this manner, a control method for controlling the interrupting device 10 including the oscillator circuit 40 shown in Figs. 1 and 2 can be provided, which includes determining at least one parameter of the current to be interrupted flowing through the device at a certain time, for example determining the value of the intensity of this current. This determination can be direct, for example by the presence of a current intensity sensor in the part of the main line 16 including the first switch 18. This determination can be indirect, for example by analyzing other parameters of the interrupting device or of the installation. This determination can be a combination of both direct and indirect determination. This determination can be made before the start of the process of opening the interrupting device, in particular before the mechanical opening of the first switch 18. This determination can be made after the start of the process of opening the interrupting device, in particular after the mechanical opening of the first switch 18. Of course, for this determination, it is also possible to take into account parameters determined before and after the start of the process of opening the interrupting device 10.

Based on this determination, for example depending on the determined value of the fault current intensity, the control method can determine the state to which the bypass switch 50 should be brought by switching the bypass switch 50.

3 illustrates an example of the operation of the device shown in FIG. 1, in which the oscillation circuit 40 is driven by the closing of the oscillation trigger 46 at time t1. Note that at this time and immediately thereafter, the current I50 through the bypass switch 50 remains zero, indicating that the bypass switch 50 is open until time t2. Between times t1 and t2, the damping resistor 48 is effectively inserted into the oscillation circuit 40, forming an RLC series circuit. The start of the discharge of the oscillation capacitor 44 corresponds to the discharge of the RLC series circuit. From time t2, the bypass switch 50 is switched to the closed state so as to short out the damping resistor 48. The remainder of the discharge of the oscillation capacitor 44 corresponds to the discharge of the LC series circuit.

Of course, it is possible to determine the period or time interval d1t between times t1 and t2, which is the time interval during which the damping resistor 48 is effectively inserted into the oscillator circuit 40. This period may be predetermined or may be determined based on some parameters of the current in the device, in particular the parameters of the fault current flowing through the first switch 18.

1 and 2, the interruption device 10 including the oscillator circuit 40 can be controlled such that, at the time of closure of the oscillation trigger 46, a damping resistor 48 is inserted into the oscillator circuit 40, or conversely, the damping resistor 48 is shorted in this circuit. When the damping resistor 48 is inserted into the oscillator circuit 40, the rate of change d(I18)/dt of the intensity of the current in the first switch 18 generated by the oscillator circuit 40, particularly at the time of the start of discharging of the oscillation capacitor 44, can be limited. In the example in which the damping resistor 48 is effectively inserted into the oscillator circuit at the time of closure of the oscillation trigger 46, the damping resistor 48 can be selected to be shorted after a certain time interval, including before the electrical interruption is effective in the first switch 18, as shown in FIG. 3, or conversely, the damping resistor 48 is selected so that the damping resistor 48 remains inserted in the oscillator circuit during the entire operation period of the oscillator circuit 40.

In the device shown in FIG. 1, the optimum relationships between the characteristic parameters of the oscillator circuit are:
Here,
-d1t: the time interval during which the damping resistor 48 is effectively inserted into the oscillator circuit 40;
-(dI18/dt)max: the maximum value of dI18/dt at the zero crossing of the current in the first switch 18, at which the first switch 18 can perform an electrical cutoff by itself;
-V44i: initial voltage across the terminals of the capacitor 44 of the oscillator circuit;
- Idef: the intensity of the current to be interrupted through the device 10;
-R48: electrical resistance value of the damping resistor 48;
- C44: the capacitance value of the capacitor 44 of the oscillator circuit 40;
- L72: the inductance value of the inductor 42 of the oscillator circuit 40.

In either example, the electrical resistance value of the damping resistor 48 need not be large. Therefore, the element or elements forming the damping resistor or resistors can be compact and inexpensive. Furthermore, with a low resistance value, the value of the voltage applied to the bypass switch 50 associated with the resistor is also relatively low. Therefore, the element or elements forming the bypass switch 50 can be compact and inexpensive.

Claims (22)

1. A current interruption device for high voltage direct current, comprising:
- a main line (16) between the first point (12) and the second point (14);
a first mechanical switch (18) and a second mechanical switch (24) inserted in succession in the main line between the first point and the second point but arranged opposite each other with respect to a midpoint (13) of the main line, each of these two mechanical switches being controlled between an open state and a closed state;
a first surge suppressor (30) arranged in parallel with said first switch between said first point and said intermediate point;
a second surge suppressor (32) arranged electrically in parallel with said second switch;
of a type including
the second surge suppressor is electrically disposed between the intermediate point and the second point, and the device (10) includes a capacitive buffer circuit (34) disposed between the first point and the second point, electrically in parallel with an assembly formed by the first switch and the second switch, and electrically in parallel with an assembly formed by the first surge suppressor and the second surge suppressor, the capacitive buffer circuit including an activation switch (36) and a buffer capacitor (38). The current interruption device for high voltage direct current as described in claim 1, characterized in that the capacitive buffer circuit (34) does not include a dedicated inductive element. The current interruption device for high voltage direct current according to claim 1 or 2, characterized in that the actuation switch (36) and the buffer capacitor (38) are electrically arranged in series in the line (35) of the capacitive buffer circuit extending from the first point (12) to the second point (14). The current interruption device for high voltage direct current according to any one of claims 1 to 3, characterized in that the capacitive buffer circuit (34) includes a circuit (39) for discharging the buffer capacitor (38). The current interruption device for high voltage direct current according to any one of claims 1 to 4, characterized in that the capacitive buffer circuit (34) includes a third surge suppressor (37) arranged in parallel with the actuation switch (36). The current interruption device for high voltage direct current according to claim 5, characterized in that the third surge suppressor (37) is connected directly to multiple terminals of the operating switch (36) and across the area between the terminals. The current interruption device for high voltage direct current according to any one of claims 1 to 6, characterized in that the device includes an oscillator circuit (40) arranged electrically in parallel with the first switch (18) between the first point (12) and the intermediate point (13), the oscillator circuit being capable of generating a zero crossing of the current flowing through the first switch. The current interruption device for high voltage direct current according to claim 7, characterized in that the oscillator circuit (40) includes at least an inductor (42), a capacitor (44) and an oscillation trigger (46) electrically arranged in series with each other. The current interruption device for high voltage direct current according to claim 8, characterized in that the device includes at least one damping resistor (48) electrically connected in series with the inductor, the capacitor and the oscillation trigger of the oscillation circuit (40) in the oscillation circuit (40), and a controllable device for changing the resistance value inserted in series with the oscillation circuit. 10. The current interruption device for high voltage direct current according to claim 9, characterized in that the device includes at least one bypass switch (50) of the damping resistor (48), the bypass switch being switchable between an open state and an on state, the damping resistor (48) and the bypass switch (50) being arranged such that when the bypass switch is in one state, the damping resistor (48) is inserted in electrical series with the oscillator circuit (40) and is electrically in series with the inductor (42), the capacitor (44) and the oscillation trigger (46) of the oscillator circuit (40), while when the bypass switch (50) is in another state, the damping resistor ( 48 ) is short-circuited with the oscillator circuit (40). The current interruption device for high voltage direct current according to claim 9 or 10, characterized in that the oscillator circuit (40) includes at least one permanent resistor permanently inserted in the oscillator circuit and electrically in series with the inductor (42), the capacitor (44) and the oscillation trigger (46) of the oscillator circuit (40). 12. The current interruption device for high voltage direct current according to claim 9, wherein the oscillator circuit (40) includes a plurality of damping resistors, each of the plurality of damping resistors associated with a separate bypass switch for that damping resistor, each bypass switch being switchable between an open state and an on state, and the damping resistors and the associated bypass switches are arranged such that when the bypass switch is in one state, the damping resistor associated with the bypass switch is inserted electrically in series with the oscillator circuit and is electrically in series with the inductor, the capacitor and the oscillation trigger of the oscillator circuit (40), while when the bypass switch is in another state, the damping resistor associated with the bypass switch is short-circuited with the oscillator circuit. A current interruption device for high voltage direct current according to any one of claims 1 to 12, characterized in that the first switch (18) includes at least one vacuum switch. A current interruption device for high voltage direct current according to any one of claims 1 to 13, characterized in that the second switch (24) includes at least one insulating gas switch. A current interruption device for high voltage direct current according to any one of claims 1 to 13, characterized in that the second switch (24) includes at least one vacuum switch. A current interruption device for high voltage direct current according to any one of claims 1 to 15, in combination with claim 4, characterized in that the circuit for discharging the buffer capacitor (38) includes a resistor (39) arranged in parallel with the buffer capacitor (38). A current interruption device for high voltage direct current according to any one of claims 1 to 16, in combination with claim 4, characterized in that the circuit for discharging the buffer capacitor (38) is a passive discharge circuit and does not include any active elements. A method for controlling a current interruption device for high voltage direct current according to any one of claims 1 to 17, comprising: - mechanically opening the first switch (18) and the second switch (24); - creating a voltage across the terminals of the first switch (18) suitable for interrupting the current in the opened first switch (18) and switching the first surge suppressor (30) into a current carrying mode, the voltage being higher than a transition voltage of the first surge suppressor (30);
- switching the actuation switch (36) in the capacitive buffer circuit so as to pass a current suitable for charging the buffer capacitor (38) and diverting the current in the second switch (24);
A control method comprising the steps of: - mechanically closing said first switch (18);
- determining one or more parameters of the current through said device (10) or the phase-to-ground voltage and taking actions to cause a rapid reopening of said device depending on said parameters of the current through said device or the phase-to-ground voltage;
- mechanically closing the second switch (24) if the device is not promptly reopened;
20. The method for controlling a current interruption device for high voltage direct current according to claim 18, comprising the steps of: A control method for controlling a current interruption device for high voltage direct current according to claim 18 or 19, in combination with claim 10 or 12, characterized in that the control method includes determining a value of the intensity of the current to be interrupted flowing through the device (10) and determining a state to which the at least one bypass switch (50) should be switched depending on the determined value of the intensity of the fault current. A control method for controlling a current interruption device for high voltage direct current according to claim 18, in combination with claim 12, characterized in that at least some of the plurality of bypass switches of the oscillator circuit are switched with a time difference from each other. A control method for controlling a current interruption device for high voltage direct current according to any one of claims 18 to 21, characterized in that in an initial state, the buffer capacitor (38) is discharged.

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