JP7628865B2 - Diode and its manufacturing method - Google Patents

Description

The technology disclosed in this specification relates to a diode and a method for manufacturing the same.

In the diode disclosed in Non-Patent Document 1, as shown in FIG. 11, a recess 280 is provided on the outer periphery of the upper surface of the semiconductor substrate 212. For this reason, a convex portion 282 is provided in the center of the upper surface of the semiconductor substrate 212. The side surface 282a of the convex portion 282 is inclined so as to approach the outer periphery of the semiconductor substrate 212 as it approaches the lower side. A p-type anode layer 220 is disposed within the convex portion 282. An n-type drift layer 226 is disposed below the anode layer 220. The pn junction 227, which is the interface between the anode layer 220 and the drift layer 226, extends laterally within the convex portion 282 and reaches the side surface 282a. When this diode is in an off state, a depletion layer spreads around the pn junction 227. In the vicinity of the side surface 282a, the thickness of the anode layer 220 is thin, so the depletion layer is distributed so as to bend upward. This reduces the electric field around the end 227a of the pn junction 227 (i.e., the outer peripheral edge of the anode layer 220).

T. Maeda at el. Parallel-Plane Breakdown Fields of 2.8-3.5 MV/cm in GaN-on-GaN p-n Junction Diodes with Double-Side-Depleted Shallow Bevel Termination. 2018 IEEE International Electron Devices Meeting. p30.1.1-30.1.4

In the diode of Non-Patent Document 1, a drift layer 226 with a low n-type impurity concentration is distributed from the bottom of the protrusion 282 to the range on the outer periphery side of the protrusion 282 (i.e., the range facing the recess 222). When the diode is turned on, it is difficult for current to flow through the drift layer 226 on the outer periphery side of the protrusion 282. For this reason, the on-resistance of the diode is high. This specification proposes a technology for alleviating electric field concentration around the outer periphery end of the anode layer in a diode and achieving low on-resistance.

The diode disclosed in this specification has a semiconductor substrate. The semiconductor substrate has an anode layer, a neutral layer, a current diffusion layer, and a drift layer. The anode layer is a p-type layer provided in a range facing the upper surface of the semiconductor substrate. The neutral layer is provided in a range facing the upper surface of the semiconductor substrate located between the anode layer and the outer peripheral surface of the semiconductor substrate, contacts the side of the anode layer, and has a carrier concentration of 10% or less of the carrier concentration of the anode layer. The current diffusion layer is an n-type layer contacting the neutral layer from below. The drift layer is an n-type layer contacting the anode layer and the current diffusion layer from below, and has a carrier concentration lower than that of the current diffusion layer. The side of the anode layer is inclined so as to approach the outer peripheral surface of the semiconductor substrate as it approaches the lower side.

As long as the carrier concentration of the neutral layer is 10% or less of the carrier concentration of the anode layer, the neutral layer may be n-type, i-type, or p-type.

In this diode, similar to the diode of Non-Patent Document 1, the anode layer is disposed at a position protruding upward from the drift layer, and the side of the anode layer is inclined so that it approaches the outer peripheral surface of the semiconductor substrate as it moves downward. In addition, the neutral layer in contact with the side of the anode layer has a low carrier concentration and is therefore electrically neutral. Therefore, the neutral layer has almost no effect on the distribution of the depletion layer. Therefore, in this diode, the depletion layer is distributed similarly to the diode of Non-Patent Document 1, and the electric field concentration around the outer edge of the anode layer is alleviated. In addition, in this diode, a current diffusion layer with a high n-type impurity concentration is provided in the surface layer of the drift layer (i.e., between the drift layer and the neutral layer) in the range on the outer periphery side of the anode layer. Therefore, when this diode is turned on, the current is easily diffused to the range on the outer periphery side of the anode layer through the current diffusion layer. Therefore, this diode has a low on-resistance.

The method for manufacturing a diode disclosed in this specification includes an epitaxial growth step and an injection step. In the epitaxial growth step, a p-type anode layer is epitaxially grown on an n-type drift layer. In the injection step, n-type impurities are injected into the upper surface of the anode layer. In the injection step, an injection region, a non-injection region, and a transition region located between the injection region and the non-injection region are set on the upper surface of the anode layer, and n-type impurities are injected into the injection region to an injection depth that reaches the drift layer, n-type impurities are not injected into the non-injection region, and n-type impurities are injected into the transition region so that the injection depth becomes deeper as the non-injection region approaches the injection region.

In this manufacturing method, in the injection process, n-type impurities are injected into the injection region to an injection depth that reaches the drift layer. That is, in the injection region, n-type impurities are injected into the anode layer and the drift layer. By injecting n-type impurities into the anode layer, the carrier concentration of the anode layer decreases and a neutral region is formed. Also, by injecting n-type impurities into the drift layer below the anode layer, the carrier concentration of the drift layer increases and a current diffusion layer is formed. That is, in the injection region, the part that was the anode layer becomes a neutral region, and a current diffusion layer is formed below the neutral region. Since n-type impurities are not injected into the non-injection region, the anode layer remains in the non-injection region. In the transition region, n-type impurities are injected so that the injection depth becomes deeper as the non-injection region approaches the injection region. Therefore, in the surface layer of the transition region, a neutral region is formed whose depth becomes deeper as the non-injection region approaches the injection region. Therefore, the side of the anode layer (i.e., the interface between the anode layer and the neutral region) is inclined so that it approaches the outer peripheral surface of the semiconductor substrate as it approaches the lower side. As described above, this manufacturing method makes it possible to manufacture a diode in which the side of the anode layer is inclined so that it approaches the outer peripheral surface of the semiconductor substrate as it approaches the lower side, and a current diffusion layer is provided below the neutral region. Therefore, this manufacturing method makes it possible to reduce electric field concentration around the outer peripheral end of the anode layer and to manufacture a diode with low on-resistance.

FIG. 2 is a cross-sectional view of a diode according to an embodiment. 2 is an enlarged cross-sectional view of the periphery of a side surface 20c of the anode layer 20. FIG. 1 is a graph showing the distribution of current density in the drift layer. 4A to 4C are explanatory views of a manufacturing method according to an embodiment. 4A to 4C are explanatory diagrams of a manufacturing method according to an embodiment. 4A to 4C are explanatory diagrams of a manufacturing method according to an embodiment. 4A to 4C are explanatory views of a manufacturing method according to an embodiment. 4A to 4C are explanatory views of a manufacturing method according to an embodiment. 1 is a graph showing the relationship between the withstand voltage and the ratio Ni/Na. FIG. 11 is a cross-sectional view of a modified diode. FIG. 1 is a cross-sectional view of a diode disclosed in Non-Patent Document 1.

In one example of the method for manufacturing a diode disclosed herein, in the step of injecting an n-type impurity, the n-type impurity may be injected into the anode layer in the injection region at a concentration that is 0.9 times or more and 1.1 times or less the p-type impurity concentration of the anode layer.

This configuration allows the carrier concentration in the neutral region to be reduced, making it possible to manufacture diodes with higher breakdown voltages.

In the example diode manufacturing method disclosed in this specification, in the step of injecting n-type impurities, n-type impurities may be injected into the upper surface of the anode layer through a mask that covers the non-injection region and the transition region of the upper surface of the anode layer. Also, within the transition region, the thickness of the mask may decrease as it approaches the injection region from the non-injection region.

With this configuration, n-type impurities can be injected into the transition region so that the injection depth becomes deeper as one approaches the injection region from the non-injection region.

The diode 10 of the embodiment shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of GaN (i.e., gallium nitride). However, the semiconductor substrate 12 may be made of other semiconductors such as silicon or silicon carbide. An upper electrode 14 is disposed on an upper surface 12a of the semiconductor substrate 12. The upper electrode 14 is in contact with an area including the center of the upper surface 12a. A lower electrode 16 is disposed on a lower surface 12b of the semiconductor substrate 12. The lower electrode 16 is in contact with the entire area of the lower surface 12b of the semiconductor substrate 12.

The semiconductor substrate 12 has an anode layer 20, a neutral layer 22, a current spreading layer 24, a drift layer 26, and a cathode layer 28.

The anode layer 20 is p-type and is disposed in an area facing the upper surface 12a of the semiconductor substrate 12. The anode layer 20 is disposed in an area including the center of the upper surface 12a of the semiconductor substrate 12, and is in contact with the upper electrode 14 at the upper surface 12a.

The neutral layer 22 is a semiconductor layer with a low carrier concentration. That is, in the neutral layer 22, the n-type impurity concentration and the p-type impurity concentration are balanced, so the carrier concentration is low. The carrier concentration of the neutral layer 22 is 10% or less of the carrier concentration of the anode layer 20. The neutral layer 22 is a low-concentration n-type, i-type, or low-concentration p-type. Since the carrier concentration of the neutral layer 22 is low, the conductivity of the neutral layer 22 is extremely low. The neutral layer 22 has electrical characteristics close to those of an insulating layer. The neutral layer 22 is disposed in a range facing the upper surface 12a of the semiconductor substrate 12. The neutral layer 22 is disposed between the anode layer 20 and the outer peripheral surface 12c of the semiconductor substrate 12. That is, the neutral layer 22 is disposed on the outer peripheral side of the anode layer 20 (i.e., the side closer to the outer peripheral surface 12c). The neutral layer 22 is not in contact with the upper electrode 14. The neutral layer 22 is in contact with the anode layer 20 laterally. That is, as shown in FIG. 2, the neutral layer 22 is in contact with the side surface 20a of the anode layer 20. In other words, the side surface 20a of the anode layer 20 is the interface between the anode layer 20 and the neutral layer 22.

As shown in Figures 1 and 2, the side surface 20a of the anode layer 20 is inclined so that it approaches the outer peripheral surface 12c of the semiconductor substrate 12 as it approaches the lower side. In the range 20b where the inclined side surface 20a exists, the anode layer 20 is disposed below the neutral layer 22. In the range 20b, the thickness of the anode layer 20 decreases and the thickness of the neutral layer 22 increases as it approaches the outer peripheral surface 12c. In the following, the portion of the semiconductor substrate 12 that is on the outer peripheral side of the outer peripheral end 20c of the anode layer 20 is referred to as the outer peripheral portion 80. In addition, the portion of the semiconductor substrate 12 that is inside the outer peripheral end 20c is referred to as the central portion 82.

The current spreading layer 24 is an n-type layer with a relatively high n-type impurity concentration. The n-type impurity concentration of the current spreading layer 24 is higher than the n-type impurity concentration of the drift layer 26. Therefore, the carrier concentration of the current spreading layer 24 is higher than the carrier concentration of the drift layer 26. Therefore, the resistivity of the current spreading layer 24 is lower than the resistivity of the drift layer 26. The current spreading layer 24 is disposed below the neutral layer 22 and is in contact with almost the entire lower surface of the neutral layer 22.

The drift layer 26 is an n-type layer with a lower n-type impurity concentration than the current diffusion layer 24. The drift layer 26 is disposed below the anode layer 20 and the current diffusion layer 24. The drift layer 26 is distributed from the central portion 82 to the peripheral portion 80 of the semiconductor substrate 12. The drift layer 26 contacts the anode layer 20 and the current diffusion layer 24 from below.

The cathode layer 28 is an n-type layer having a higher n-type impurity concentration than the current diffusion layer 24. Therefore, the carrier concentration of the cathode layer 28 is higher than the carrier concentration of the current diffusion layer 24. The cathode layer 28 is disposed below the drift layer 26. The cathode layer 28 is distributed from the center 82 to the outer periphery 80 of the semiconductor substrate 12. The cathode layer 28 is in contact with the drift layer 26 from below. The cathode layer 28 is in contact with the lower electrode 16 on the lower surface 12b of the semiconductor substrate 12.

When a higher potential than that of the lower electrode 16 is applied to the upper electrode 14, a current flows from the anode layer 20 to the drift layer 26. The current flowing from the anode layer 20 to the drift layer 26 is distributed to the central portion 82 and the peripheral portion 80, flows downward, and flows to the cathode layer 28. In the diode 10 of the embodiment, the current diffusion layer 24 provided on the upper portion of the drift layer 26 in the peripheral portion 80 has a lower resistance than the drift layer 26. For this reason, as shown by the arrow 100 in FIG. 1, the current flowing from the anode layer 20 to the drift layer 26 is likely to diffuse laterally through the current diffusion layer 24. The current flowing into the current diffusion layer 24 flows through the drift layer 26 in the peripheral portion 80 to the cathode layer 28. In this way, since the current diffusion layer 24 is provided, the current is likely to diffuse to the peripheral portion 80. Therefore, in the diode 10, the current in the drift layer 26 is likely to flow distributed to the central portion 82 and the peripheral portion 80. Therefore, the on-resistance of the diode 10 is low.

Figure 3 shows the results of simulating the current density in the drift layer 26 (more specifically, in the central portion 82 and the outer peripheral portion 80) when the diode 10 is on. In Figure 3, graph A shows the results for the diode 10 of the embodiment, and graph B shows the results for the diode of the comparative example. The diode of the comparative example does not have a current spreading layer 24. As shown in Figure 3, the diode 10 of the embodiment has a higher current density in the outer peripheral portion 80 than the diode of the comparative example. In this way, the diode 10 of the embodiment can distribute the current over a wide range, so the diode 10 of the embodiment has a low on-resistance.

In addition, when a potential higher than that of the upper electrode 14 is applied to the lower electrode 16, a reverse voltage is applied to the pn junction 27 at the interface between the anode layer 20 and the drift layer 26. Then, as shown in FIG. 2, the depletion layer 90 spreads from the pn junction 27 to the surrounding anode layer 20 and drift layer 26. As described above, the carrier concentration of the neutral layer 22 is extremely low. Therefore, the neutral layer 22 is electrically neutral and functions almost the same as an insulator. Therefore, the neutral layer 22 does not affect the distribution of the depletion layer 90. In addition, the side surface 20a of the anode layer 20 is inclined so as to approach the outer periphery as it approaches the lower side. Therefore, the thickness of the anode layer 20 is thin near the outer periphery end 20c of the anode layer 20. Therefore, near the outer periphery end 20c, the depletion layer 90 extends widely within the anode layer 20. As a result, the depletion layer 90 is distributed so as to bend upward near the outer periphery end 20c. With this distribution of the depletion layer 90, the electric field generated near the outer periphery end 20c is alleviated. Therefore, the diode 10 has a high breakdown voltage.

Next, a method for manufacturing the diode 10 will be described. The diode 10 is manufactured from a semiconductor substrate whose entirety is composed of the cathode layer 28. First, as shown in FIG. 4, the drift layer 26 is epitaxially grown on the cathode layer 28. Next, the anode layer 20 is epitaxially grown on the drift layer 26. Here, the anode layer 20 is formed over the entire upper surface of the drift layer 26.

5, a resist layer 60 is formed on the upper surface of the anode layer 20 (i.e., the upper surface 12a of the semiconductor substrate 12). Here, the resist layer 60 is patterned so that the area including the center of the upper surface 12a is covered by the resist layer 60 and the area on the outer periphery of the upper surface 12a is exposed from the resist layer 60. Next, the semiconductor substrate 12 is annealed together with the resist layer 60. Then, as shown in FIG. 6, the resist layer 60 softens and flows. As a result, in the portion 60b near the end 60a of the resist layer 60, the thickness of the resist layer 60 becomes thinner as it approaches the end 60a. Hereinafter, the portion of the upper surface 12a of the semiconductor substrate 12 that is covered by the portion 60b is referred to as a transition region 12y. Also, the portion of the upper surface 12a that is covered by the resist layer 60 with a constant thickness is referred to as a non-implantation region 12x. Also, the portion of the upper surface 12a that is not covered by the resist layer 60 is referred to as an implantation region 12z. The transition region 12y is disposed between the non-implanted region 12x and the implanted region 12z. The thickness of the resist layer 60 in the transition region 12y decreases from the non-implanted region 12x toward the implanted region 12z.

Next, an ion implantation process is performed. In the ion implantation process, as shown in FIG. 7, n-type impurities are ion-implanted into the upper surface 12a of the semiconductor substrate 12 through the resist layer 60.

As shown in FIG. 7, the non-implanted region 12x is covered with a thick resist layer 60, so that n-type impurities are not implanted into the non-implanted region 12x. Therefore, as shown in FIG. 8, the anode layer 20 remains in the non-implanted region 12x after the ion implantation process.

As shown in FIG. 7, the implantation region 12z is not covered with the resist layer 60, so that n-type impurities are implanted into the implantation region 12z. In the ion implantation process, the implantation energy is set so that the implantation depth of the n-type impurities implanted into the implantation region 12z reaches the drift layer 26 below the anode layer 20. Therefore, in the implantation region 12z, n-type impurities are implanted not only into the anode layer 20 but also into the portion 26a of the drift layer 26 near the anode layer 20. In the ion implantation process, the n-type impurities may be distributed in a depth range from the upper surface 12a to the portion 26a by implanting the n-type impurities while changing the implantation energy (i.e., while changing the implantation depth). In the implantation region 12z, n-type impurities are implanted into the p-type anode layer 20. As a result, as shown in FIG. 8, a neutral layer 22 with a reduced carrier concentration is formed in the portion that was the anode layer 20 in the implantation region 12z. If the concentration of the n-type impurity injected into the anode layer 20 is equal to the p-type impurity concentration of the anode layer 20, the neutral layer 22 becomes i-type. If the concentration of the n-type impurity injected into the anode layer 20 is higher than the p-type impurity concentration of the anode layer 20, the neutral layer 22 becomes n-type. If the concentration of the n-type impurity injected into the anode layer 20 is lower than the p-type impurity concentration of the anode layer 20, the neutral layer 22 becomes p-type. Here, the n-type impurity is injected so that the concentration Ni of the n-type impurity injected into the anode layer 20 is 0.9 times or more and 1.1 times or less than the p-type impurity concentration Na of the anode layer 20. When the n-type impurity is injected in this manner, the carrier concentration of the neutral layer 22 becomes 10% or less of the carrier concentration of the anode layer 20 remaining in the non-injection region 12x. Also, as shown in FIG. 7, in the injection region 12z, n-type impurities are injected into the portion 26a of the drift layer 26 (i.e., the portion below the anode layer 20), so the n-type impurity concentration in the portion 26a increases. As a result, the portion 26a becomes the current diffusion layer 24 with a high n-type impurity concentration. That is, as shown in FIG. 8, the current diffusion layer 24 is formed below the neutral layer 22 in the injection region 12z.

7, on the transition region 12y, the thickness of the resist layer 60 becomes thinner from the non-implanted region 12x toward the implanted region 12z. Therefore, in the transition region 12y, the implantation depth of the n-type impurity becomes deeper from the non-implanted region 12x toward the implanted region 12z. Within a range in which the implantation depth of the n-type impurity is shallower than the thickness of the anode layer 20, as shown in FIG. 8, a neutral layer 22 is formed near the upper surface 12a of the semiconductor substrate 12, and the anode layer 20 remains below the neutral layer 22. Since the implantation depth of the n-type impurity becomes deeper from the non-implanted region 12x toward the implanted region 12z, the thickness of the anode layer 20 remaining in the transition region 12y becomes thinner from the non-implanted region 12x toward the implanted region 12z. Therefore, the side surface 20a of the anode layer 20 is inclined so as to approach the outer peripheral surface 12c of the semiconductor substrate 12 as it approaches the lower side.

After the ion implantation process, the resist layer 60 is removed. Then, as shown in FIG. 1, the upper electrode 14 and the lower electrode 16 are formed to complete the diode 10.

In this manufacturing method, the anode layer 20 with the inclined side surface 20a can be formed without forming a recess on the upper surface 12a of the semiconductor substrate 12. That is, the neutral layer 22 is formed by ion implantation, so that the side surface 20a of the anode layer 20 can be inclined. According to this manufacturing method, the anode layer 20 with the inclined side surface 20a can be formed more easily than in the past. In addition, since the neutral layer 22 in contact with the side surface 20a is electrically neutral, the diode 10 of the embodiment can suppress electric field concentration near the outer peripheral end 20c of the anode layer 20, as in the diode in which the side surface of the anode layer is inclined by a recess. Therefore, the diode manufactured by this manufacturing method has a high breakdown voltage.

Figure 9 shows the relationship between the breakdown voltage of the diode 10 and the ratio Ni/Na. As described above, the concentration Ni is the concentration of the n-type impurity implanted in the implantation region 12z. As described above, the concentration Na is the concentration of the p-type impurity in the anode layer 20. When the ratio Ni/Na = 1, the neutral layer 22 is i-type, when the ratio Ni/Na > 1, the neutral layer 22 is n-type, and when the ratio Ni/Na < 1, the neutral layer 22 is p-type. Also, graph X in Figure 9 shows the case where the ratio Na/Nd of the p-type impurity concentration Na of the anode layer 20 to the n-type impurity concentration Nd of the drift layer 26 is 20. Graph Y in Figure 9 shows the case where the ratio Na/Nd is 50. As shown in Figure 9, in both graphs X and Y, a high breakdown voltage is obtained when the ratio Ni/Na is in the range of 0.9 to 1.1. When the ratio Ni/Na is between 0.9 and 1.1, the carrier concentration of the neutral layer 22 is 10% or less of the carrier concentration of the anode layer, and the neutral layer 22 has characteristics close to those of an insulator. This suppresses electric field concentration around the outer peripheral edge 20c of the anode layer 20, and increases the withstand voltage.

In addition, according to the manufacturing method of the embodiment, a current diffusion layer 24 with a high n-type impurity concentration is formed below the neutral layer 22. Therefore, a diode 10 with a low on-resistance can be manufactured.

As shown in FIG. 10, the neutral layers 22 and the current diffusion layers 24 may be provided discretely in the outer peripheral portion 80. In FIG. 10, a p-type layer exists between the discretely provided neutral layers 22. The configuration in FIG. 10 can be obtained by discretely injecting n-type impurities into the implantation region 12z in the ion implantation process described above.

In addition, in the above-mentioned embodiment, a diode is described as a single element, but the diode may be combined with other elements. For example, the anode layer may also serve as the body layer of the field effect transistor, and the cathode layer may also serve as the drain layer of the field effect transistor. In other words, the diode may be the body diode of the field effect transistor.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples given above. The technical elements described in this specification or drawings demonstrate technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

10: Diode, 12: Semiconductor substrate, 20: Anode layer, 20a: Side, 22: Neutral layer, 24: Current diffusion layer, 26: Drift layer, 28: Cathode layer

Claims (4)

A diode,
A semiconductor substrate is provided.
The semiconductor substrate is
a p-type anode layer provided in an area facing an upper surface of the semiconductor substrate;
a neutral layer provided in an area facing the upper surface of the semiconductor substrate between the anode layer and an outer peripheral surface of the semiconductor substrate, in contact with a side surface of the anode layer, and having a carrier concentration of 10% or less of the carrier concentration of the anode layer;
an n-type current spreading layer in contact with the neutral layer from below;
an n-type drift layer in contact with the anode layer and the current spreading layer from below and having a carrier concentration lower than that of the current spreading layer;
having
The side surface of the anode layer is inclined so as to approach the outer peripheral surface of the semiconductor substrate as it goes downward.
diode. 2. A method for manufacturing the diode according to claim 1, comprising the steps of :
epitaxially growing the p- type anode layer on the n- type drift layer;
a step of injecting n-type impurities into an upper surface of the anode layer, comprising: setting an injection region, a non-injection region, and a transition region located between the injection region and the non-injection region on the upper surface of the anode layer; injecting n-type impurities into the injection region to an injection depth that reaches the drift layer; not injecting n-type impurities into the non-injection region; and injecting n-type impurities into the transition region such that the injection depth becomes deeper as the injection region approaches the injection region from the non-injection region ; the region of the drift layer into which the n-type impurities are injected becomes the current spreading layer; and the region of the anode layer into which the n-type impurities are injected becomes the neutral layer ;
A method for manufacturing a diode having the above structure. The manufacturing method according to claim 2, wherein in the step of injecting n-type impurities, n-type impurities are injected into the anode layer in the injection region at a concentration that is 0.9 times or more and 1.1 times or less the p-type impurity concentration of the anode layer. In the step of injecting n-type impurities, n-type impurities are injected into the upper surface of the anode layer through a mask that covers the non-injection region and the transition region of the upper surface of the anode layer;
Within the transition region, the thickness of the mask decreases from the non-implanted region to the implanted region.
The method according to claim 2 or 3.

Images