JP7628874B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

Patent document 1 discloses a semiconductor device having a semiconductor substrate, an upper electrode, and a lower electrode. The semiconductor substrate has an element region and a peripheral region. The element region is located in the center of the semiconductor substrate when viewed from above, and has an element that passes a current between the upper electrode and the lower electrode. The peripheral region is located around the element region. The peripheral region has an n-type drift region and multiple p-type voltage-resistance regions. Each voltage-resistance region goes around the element region, is exposed on the upper surface of the semiconductor substrate, and is separated from each other by the drift region.

When this semiconductor device is turned off, a depletion layer spreads in the drift region from the element region toward the peripheral region (i.e., from the center of the semiconductor substrate toward the outer periphery). When the depletion layer extending into the peripheral region reaches the innermost voltage-resistance holding region, the depletion layer extends further from that voltage-resistance holding region toward the outer periphery. In this way, the depletion layer extends toward the outer periphery, passing through multiple voltage-resistance holding regions. This maintains the voltage-resistance of the semiconductor device.

JP 2016-92168 A

Each breakdown voltage holding region in Patent Document 1 has the same p-type impurity concentration. Here, if the p-type impurity concentration of the breakdown voltage holding region is increased in order to ensure the breakdown voltage of the peripheral region, the width of the depletion layer spreading to the drift region in the peripheral region increases. When the depletion layer reaches the outer edge of the semiconductor substrate, an electric field is applied to the outer edge, and the breakdown voltage decreases. In this case, in order to ensure a sufficient breakdown voltage, it is necessary to ensure a large width of the peripheral region (the distance from the outer edge of the element region to the outer edge of the semiconductor substrate), which increases the size of the semiconductor device. On the other hand, if the p-type impurity concentration of the breakdown voltage holding region is reduced, the width of the depletion layer spreading to the drift region in the peripheral region decreases, and the breakdown voltage of the peripheral region decreases. This specification provides a technology that can reduce the size of the peripheral region while ensuring the breakdown voltage of the peripheral region.

The semiconductor device (10, 100) disclosed in this specification includes a semiconductor substrate (12), an upper electrode (70) in contact with the upper surface of the semiconductor substrate, and a lower electrode (72) in contact with the lower surface of the semiconductor substrate. When the semiconductor substrate is viewed from above, the semiconductor substrate has an element region (60) that overlaps with the contact surface between the upper electrode and the semiconductor substrate, and a peripheral region (62) arranged around the element region. The element region has an element that can pass a current between the upper electrode and the lower electrode. The peripheral region has an n-type drift region (34) exposed on the upper surface of the semiconductor substrate, and a plurality of breakdown voltage holding regions (42) that each surround the element region, are exposed on the upper surface of the semiconductor substrate, and are separated from each other by the drift region. The plurality of breakdown voltage holding regions include a plurality of first breakdown voltage holding regions (42a) and a plurality of second breakdown voltage holding regions (42b) that have a lower p-type impurity concentration than the plurality of first breakdown voltage holding regions. The first and second voltage-resistant regions are arranged alternately.

In the above semiconductor device, the first breakdown voltage holding region and the second breakdown voltage holding region having a lower p-type impurity concentration than the first breakdown voltage holding region are alternately arranged in the peripheral region. By arranging the second breakdown voltage holding region having a relatively low p-type impurity concentration, the spread of the depletion layer into the drift region in the peripheral region is generally suppressed. As a result, the width of the peripheral region can be made smaller than in the conventional case. On the other hand, since the p-type impurity concentration of the first breakdown voltage holding region is relatively high, the breakdown voltage of the peripheral region can be ensured by arranging the first breakdown voltage holding region. In this manner, in this semiconductor device, the balance between the spread of the depletion layer in the drift region and the breakdown voltage of the peripheral region can be appropriately controlled by alternately arranging the first breakdown voltage holding region and the second breakdown voltage holding region. Therefore, in this semiconductor device, the size of the peripheral region can be reduced while ensuring the breakdown voltage of the peripheral region.

The method for manufacturing a semiconductor device disclosed in this specification includes the steps of: etching the upper surface of a first p-type region of a semiconductor substrate having an n-type drift region (34) and the first p-type region (80) disposed on the drift region to form a plurality of annular grooves (84) that extend concentrically when the upper surface of the first p-type region is viewed from above, each of the annular grooves penetrating the first p-type region and reaching the drift region; forming an n-type region (86) that covers the inner surfaces of the plurality of annular grooves by epitaxial growth; and forming a second p-type region (88) inside the plurality of annular grooves by epitaxial growth, the second p-type region having a lower p-type impurity concentration than the first p-type region.

In this manufacturing method, each of the multiple annular first p-type regions separated by the annular grooves can function as a voltage-resistance region with a high p-type impurity concentration, and each of the second p-type regions formed within the multiple annular grooves can function as a voltage-resistance region with a low p-type impurity concentration.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 3 is a diagram showing a potential distribution in the cross section of FIG. 2 when the semiconductor device is turned off. 3A to 3C are diagrams for explaining a manufacturing process of the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining a manufacturing process of the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining a manufacturing process of the semiconductor device according to the first embodiment; 3A to 3C are diagrams for explaining a manufacturing process of the semiconductor device according to the first embodiment. 3A to 3C are diagrams for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view of a semiconductor device according to a second embodiment, the cross-sectional view corresponding to FIG. 2 . 10A to 10C are diagrams for explaining a manufacturing process of a semiconductor device according to a second embodiment.

The technical elements disclosed in this specification are listed below. Note that each of the technical elements below is useful independently.

In one example configuration disclosed in this specification, the width of the first voltage-resistance holding region may be wider from the top surface of the semiconductor substrate toward the bottom, and the width of the second voltage-resistance holding region may be narrower from the top surface of the semiconductor substrate toward the bottom.

In one example configuration disclosed in this specification, the semiconductor substrate may be made of gallium nitride.

In one example of the manufacturing method disclosed herein, in the step of forming the multiple annular grooves, etching may be performed so that the width of each annular groove narrows from the top surface of the semiconductor substrate toward the bottom.

In the above configuration, the width of the annular groove that is formed increases toward the upper surface of the semiconductor substrate. Therefore, in the subsequent process, when an n-type region and a second p-type region are epitaxially grown in the annular groove, the inner surface of the annular groove can be suitably covered with the n-type region, and the inside of the annular groove can be suitably filled with the second p-type region. This makes it possible to suppress the formation of voids inside the second p-type region, etc.

In one example of the manufacturing method disclosed herein, the semiconductor substrate may be made of gallium nitride.

It is difficult to form a p-type region in gallium nitride by ion implantation. For this reason, the manufacturing method disclosed in this specification is particularly useful when manufacturing a semiconductor device using a semiconductor substrate made of gallium nitride.

Example 1
The semiconductor device 10 of the first embodiment shown in FIG. 1 and FIG. 2 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device 10 includes a semiconductor substrate 12, electrodes, an insulating layer, and the like. As shown in FIG. 1, the semiconductor substrate 12 has an element region 60 and a peripheral region 62. The element region 60 is a region that functions as an element (i.e., a main current flows) and is disposed in the center of the semiconductor substrate 12. The peripheral region 62 is disposed around the element region 60. The peripheral region 62 is a region between the element region 60 and the outer peripheral end 12c of the semiconductor substrate 12. Note that, in FIG. 1, for ease of viewing, the electrodes and insulating layer on the upper surface 12a of the semiconductor substrate 12 are omitted. Also, the structure within the element region 60 is omitted. In the following, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction. The semiconductor substrate 12 is made of GaN (gallium nitride). However, the material of the semiconductor substrate 12 is not particularly limited, and other semiconductor materials such as SiC (silicon carbide) and Si (silicon) may be used.

As shown in FIG. 2, a gate insulating film 24 and a peripheral insulating film 46 are disposed on the upper surface 12a of the semiconductor substrate 12. The gate insulating film 24 covers a portion of the upper surface 12a of the semiconductor substrate 12 in the element region 60. The peripheral insulating film 46 covers substantially the entire upper surface 12a of the semiconductor substrate 12 in the peripheral region 62, and also covers the upper surface 12a of the semiconductor substrate 12 across a portion of the element region 60.

An upper electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 contacts a part of the upper surface 12a of the semiconductor substrate 12 in the element region 60. The upper electrode 70 contacts the upper surface 12a of the semiconductor substrate 12 in a portion where the gate insulating film 24 and the peripheral insulating film 46 are not provided. The upper electrode 70 functions as a source electrode. A gate electrode 26 is disposed on the upper surface of the gate insulating film 24. The gate electrode 26 faces the upper surface 12a of the semiconductor substrate 12 via the gate insulating film 24. The gate electrode 26 faces the body region 32 (described later) in an area that contacts the gate insulating film 24 via the gate insulating film 24. A lower electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is formed over substantially the entire lower surface 12b of the semiconductor substrate 12. The lower electrode 72 functions as a drain electrode.

As shown in FIG. 2, in the element region 60, a plurality of source regions 30, a plurality of body regions 32, a JFET region 33, a drift region 34, and a drain region 35 are provided inside the semiconductor substrate 12.

Each source region 30 is an n-type region. Each source region 30 is disposed at a position exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in contact with the upper electrode 70 and the gate insulating film 24. The source region 30 is in ohmic contact with the upper electrode 70.

Each body region 32 is a p-type region. Each body region 32 is disposed around the corresponding source region 30. The body region 32 is exposed on the upper surface 12a of the semiconductor substrate 12. The body region 32 is in contact with the gate insulating film 24, the upper electrode 70, and the peripheral insulating film 46. The body region 32 is in ohmic contact with the upper electrode 70.

The JFET region 33 is an n-type region. The JFET region 33 is disposed in a region sandwiched between two body regions 32. The JFET region 33 is separated from the source region 30 by the body region 32. The JFET region 33 is exposed on the upper surface 12a of the semiconductor substrate 12. The JFET region 33 is in contact with the gate insulating film 24.

The drift region 34 is an n-type region. The drift region 34 is disposed below the body region 32 and the JFET region 33. The drift region 34 contacts the body region 32 and the JFET region 33 from below. The drift region 34 is separated from the source region 30 by the body region 32. As described later, the drift region 34 is also disposed in the peripheral region 62. The drift region 34 is disposed across from the element region 60 to the peripheral region 62.

The drain region 35 is an n-type region. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 is disposed below the drift region 34. Like the drift region 34, the drain region 35 is disposed across the element region 60 and the peripheral region 62. The drain region 35 is exposed at the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72.

As shown in FIG. 2, in the peripheral region 62, a drift region 34, a drain region 35, and a plurality of breakdown voltage holding regions 42 are provided inside the semiconductor substrate 12.

The drift region 34 in the peripheral region 62 is exposed to the upper surface 12a of the semiconductor substrate 12. The drift region 34 is in contact with the peripheral insulating film 46. The configuration of the drain region 35 is similar to the configuration of the drain region 35 in the element region 60.

Each breakdown voltage holding region 42 is a p-type region. As shown in FIG. 1, each breakdown voltage holding region 42 goes around the element region 60 and is arranged concentrically. Each breakdown voltage holding region 42 is exposed to the upper surface 12a of the semiconductor substrate 12. Each breakdown voltage holding region 42 is in contact with the peripheral insulating film 46. Each breakdown voltage holding region 42 is separated from each other by the drift region 34. The breakdown voltage holding region 42 has a plurality of first breakdown voltage holding regions 42a and a plurality of second breakdown voltage holding regions 42b. The second breakdown voltage holding region 42b has a lower p-type impurity concentration than the first breakdown voltage holding region 42a. The first breakdown voltage holding region 42a and the second breakdown voltage holding region 42b are arranged alternately. Each first pressure-resistance holding region 42a is disposed in a range sandwiched between two second pressure-resistance holding regions 42b, and each second pressure-resistance holding region 42b is disposed in a range sandwiched between two first pressure-resistance holding regions 42a. The number of pressure-resistance holding regions 42 is not particularly limited, and can be set appropriately according to the pressure-resistance to be secured.

Next, the operation of the semiconductor device 10 will be described. When the semiconductor device 10 is used, the semiconductor device 10, a load (e.g., a motor), and a power source are connected in series. A power supply voltage is applied to the series circuit of the semiconductor device 10 and the load. The power supply voltage is applied in a direction in which the lower electrode 72 side has a higher potential than the upper electrode 70. When an on-potential (potential higher than the gate threshold) is applied to the gate electrode 26, a channel is formed in the body region 32 (the body region 32 located between the source region 30 and the JFET region 33) in the range in contact with the gate insulating film 24. Then, electrons flow from the upper electrode 70 to the lower electrode 72 through the source region 30, the channel, the JFET region 33, the drift region 34, and the drain region 35, thereby turning on the semiconductor device 10. When the potential of the gate electrode 26 is lowered to an off-potential (potential lower than the gate threshold), the channel disappears, the flow of electrons stops, and the semiconductor device 10 turns off. In this way, the semiconductor device 10 can control the current flowing between the upper electrode 70 and the lower electrode 72 based on the potential of the gate electrode 26.

When the semiconductor device 10 is turned off, a reverse voltage is applied to the pn junctions at the interfaces between the body region 32 and the drift region 34 and the JFET region 33, causing a depletion layer to spread from the pn junction into the drift region 34 and the JFET region 33. In the element region 60, the depletion layer spreads from the upper surface 12a toward the lower surface 12b of the semiconductor substrate 12. The drift region 34 in the element region 60 is depleted by the depletion layer spreading from the body region 32. The depleted drift region 34 holds the voltage between the body region 32 and the drain region 35.

In the peripheral region 62, the depletion layer spreads from the center of the semiconductor substrate 12 toward the outer periphery (i.e., from the left side to the right side in FIG. 2). When the depletion layer extending into the peripheral region 62 reaches the innermost breakdown voltage holding region 42, the depletion layer extends from that breakdown voltage holding region 42 toward the outer periphery. In this way, each breakdown voltage holding region 42 promotes the extension of the depletion layer toward the outer periphery. In the peripheral region 62, the depletion layer extends toward the outer periphery while passing through multiple breakdown voltage holding regions 42, and extends to the vicinity of the outer periphery end 12c of the semiconductor substrate 12. When the semiconductor device 10 is turned off, the outer periphery end 12c of the semiconductor substrate 12 has approximately the same potential as the lower electrode 72. Therefore, a potential difference occurs between the body region 32 and the outer periphery end 12c. The potential difference between the body region 32 and the outer periphery end 12c is maintained by the depleted drift region 34 in the peripheral region 62.

As described above, the multiple breakdown voltage holding regions 42 are composed of the first breakdown voltage holding region 42a having a relatively high p-type impurity concentration and the second breakdown voltage holding region 42b having a relatively low p-type impurity concentration. By arranging the second breakdown voltage holding region 42b having a low p-type impurity concentration, the spread of the depletion layer to the drift region 34 in the peripheral region 62 is generally suppressed. Therefore, in this embodiment, by arranging the second breakdown voltage holding region 42b, the width of the peripheral region 62 can be made smaller than in the past. On the other hand, since the first breakdown voltage holding region 42a has a high p-type impurity concentration, the breakdown voltage of the peripheral region 62 can be ensured by arranging the first breakdown voltage holding region 42a.

When the depletion layer reaches each voltage-resistance holding region 42, the depletion layer also spreads inside each voltage-resistance holding region 42. The first voltage-resistance holding region 42a, which has a high p-type impurity concentration, is hardly depleted. Therefore, almost no potential difference occurs inside each first voltage-resistance holding region 42a. On the other hand, the depletion layer spreads over a wide area inside the second voltage-resistance holding region 42b, which has a low p-type impurity concentration.

Figure 3 shows the potential distribution in the semiconductor device 10 when the semiconductor device 10 is off. The dashed lines in Figure 3 are equipotential lines. As described above, when the semiconductor device 10 is off, the drift region 34 in the depleted element region 60 holds the voltage between the body region 32 and the drain region 35. Therefore, equipotential lines extend horizontally in the element region 60. Also, the drift region 34 in the depleted peripheral region 62 holds the potential difference between the body region 32 and the outer periphery. Therefore, equipotential lines extend vertically in the peripheral region 62. The equipotential lines in the peripheral region 62 are curved and connected to the equipotential lines in the element region 60.

As described above, the first voltage-resistance holding region 42a, which has a high p-type impurity concentration, is hardly depleted, and no potential difference occurs in the first voltage-resistance holding region 42a, so the equipotential lines hardly penetrate into the first voltage-resistance holding region 42a. On the other hand, the second voltage-resistance holding region 42b is depleted, so the equipotential lines are distributed to pass through the second voltage-resistance holding region 42b. In this way, even if the second voltage-resistance holding region 42b, which has a low p-type impurity concentration, is arranged, a potential difference occurs in the second voltage-resistance holding region 42b, so the voltage-resistance of the peripheral region 62 can be ensured.

As described above, in the semiconductor device 10, the width of the peripheral region 62 can be reduced while ensuring the breakdown voltage of the peripheral region 62 compared to the conventional technology.

Next, a method for manufacturing the semiconductor device 10 will be described. First, as shown in FIG. 4, a semiconductor substrate 12x is prepared having an n-type drain region 35, an n-type drift region 34 arranged on the drain region 35, and a first p-type region 80 arranged on the drift region 34. For example, the drift region 34 is formed by epitaxial growth on the surface of the drain region 35, and the first p-type region 80 is formed by epitaxial growth on the surface of the drift region 34, thereby manufacturing the semiconductor substrate 12x.

5, a mask having a plurality of openings 63a is formed on the upper surface of the semiconductor substrate 12x. Each opening 63a is formed at a position corresponding to the JFET region 33 in the element region 60 and the second voltage-resistance holding region 42b in the peripheral region 62. Then, the upper surface of the semiconductor substrate 12x is etched through the mask 63. As a result, a recess 82 is formed in the element region 60, penetrating the first p-type region 80 and reaching the drift region 34, and a plurality of annular grooves 84 are formed in the peripheral region 62, penetrating the first p-type region 80 and reaching the drift region 34. Each annular groove 84 is formed in a ring shape extending concentrically when the semiconductor substrate 12x is viewed from above. Also, each annular groove 84 is formed to have a width greater than the width of the second voltage-resistance holding region 42b.

Next, as shown in FIG. 6, an n-type region 86 having an n-type impurity concentration approximately equal to that of the drift region 34 is formed by epitaxial growth in the recess 82 and the annular groove 84. In the element region 60, the n-type region 86 is grown so as to fill the recess 82. Meanwhile, in the peripheral region 62, the n-type region 86 is grown so as to cover the inner surface of each annular groove 84. That is, the n-type region 86 is formed so as not to fill the entire inside of each annular groove 84. The width of the recess 82 is narrower than the width of each annular groove 84. Therefore, by epitaxially growing the n-type region 86, the n-type region 86 fills the entire recess 82 earlier than the annular grooves 84.

Next, as shown in FIG. 7, a second p-type region 88 having a lower p-type impurity concentration than the first p-type region 80 is formed inside each annular groove 84 by epitaxial growth. Here, the second p-type region 88 is formed so as to fill each annular groove 84. Note that the process shown in FIG. 7 is carried out consecutively to the process shown in FIG. 6 by switching the dopant gas during the growth of the n-type region 86 shown in FIG. 6.

Next, as shown in FIG. 8, the second p-type region 88 and the n-type region 86 are removed using CMP (Chemical Mechanical Polishing) technology until the first p-type region 80 is exposed. This forms the body region 32 and JFET region 33 located in the element region 60, and the first voltage-resistance holding region 42a and the second voltage-resistance holding region 42b located in the peripheral region 62.

Then, the source region 30 is formed by ion implantation or the like, and the gate insulating film 24, the peripheral insulating film 46, the gate electrode 26, the upper electrode 70, and the lower electrode 72 are formed by conventional methods, completing the semiconductor device 10 shown in Figures 1 and 2.

In this manufacturing method, each of the multiple annular first p-type regions 80 separated by the multiple annular grooves 84 can function as the first voltage-resistant region 42a, and each of the second p-type regions 88 formed in the multiple annular grooves 84 can function as the second voltage-resistant region 42b. In addition, the first p-type region 80 located on the innermost side of the annular groove 84 can function as the body region 32. In this way, in this manufacturing method, the body region 32 and the first voltage-resistant region 42a can be formed from the same first p-type region 80, reducing the number of manufacturing steps.

In addition, in this manufacturing method, as shown in FIG. 6, after the inner surface of the annular groove 84 is covered with an n-type region 86, the dopant gas is switched to continuously form a second p-type region 88 in the annular groove 84. This makes it possible to omit a process of filling the annular groove 84 with the n-type region 86 and then forming another annular groove to form the second p-type region 88. This reduces the number of manufacturing steps, and allows the semiconductor device 10 to be manufactured efficiently.

It should be noted that it is difficult to form a p-type region by ion implantation in GaN-based semiconductors (semiconductors whose main material is a compound of gallium and nitrogen). In this manufacturing method, the p-type body region 32 and the breakdown voltage holding region 42 (i.e., the first p-type region 80 and the second p-type region 88) are formed by epitaxial growth. In this way, the above-described manufacturing method is a particularly useful technique for GaN-based semiconductors, and allows the semiconductor device 10 to be manufactured appropriately.

Example 2
Next, a description will be given of a semiconductor device 100 according to a second embodiment. The semiconductor device 100 according to the second embodiment differs from that according to the first embodiment in the configuration of the breakdown voltage holding region 142 in the peripheral region 62. The other configurations are the same as those according to the first embodiment.

9, in the peripheral region 62 of the semiconductor device 100, the width of the first voltage-resistance holding region 142a increases from the upper surface 12a of the semiconductor substrate 12 downward. From the upper surface 12a of the semiconductor substrate 12 downward, both side surfaces of the first voltage-resistance holding region 142a are inclined so as to increase in width relative to the upper surface 12a of the semiconductor substrate 12. Also, the width of the second voltage-resistance holding region 142b decreases from the upper surface 12a of the semiconductor substrate 12 downward. From the upper surface 12a of the semiconductor substrate 12 downward, both side surfaces of the second voltage-resistance holding region 142b are inclined so as to decrease in width relative to the upper surface 12a of the semiconductor substrate 12.

The semiconductor device 100 of the second embodiment can be manufactured by modifying the process shown in FIG. 5 of the first embodiment. In the manufacturing method of the semiconductor device 100, as shown in FIG. 10, when forming the multiple annular grooves 184, etching is performed so that the width of each annular groove 184 narrows from the upper surface of the semiconductor substrate 12x downward. Then, the semiconductor device 100 can be manufactured by performing the process from FIG. 6 onward of the first embodiment (such as forming the n-type region 86 and the second p-type region 88).

In the manufacturing method of Example 2, each annular groove 184 is formed so that the width of each annular groove 184 narrows from the upper surface of the semiconductor substrate 12x downward. Therefore, in the subsequent formation of the n-type region 86 and the second p-type region 88, the inside of each annular groove 184 can be suitably covered and filled, and the occurrence of voids in the n-type region 86 and the second p-type region 88 can be suppressed.

In each of the above-mentioned embodiments, a MOSFET is formed in the element region 60, but the structure of the element formed in the element region 60 is not particularly limited. For example, an IGBT may be formed in the element region 60. In addition, in each of the above-mentioned embodiments, a semiconductor device having a planar type gate electrode is described, but the technology disclosed in this specification may be applied to a semiconductor device having, for example, a trench type gate electrode.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples given above. The technical elements described in this specification or drawings demonstrate technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

10: Semiconductor device 12: Semiconductor substrate 24: Gate insulating film 26: Gate electrode 30: Source region 32: Body region 33: JFET region 34: Drift region 35: Drain region 42a: First voltage holding region 42b: Second voltage holding region 46: Peripheral insulating film 60: Element region 62: Peripheral region 70: Upper electrode 72: Lower electrode 80: First p-type region 82: Recess 84: Annular groove 86: N-type region 88: Second p-type region

Claims (6)

A semiconductor device (10, 100),
A semiconductor substrate (12);
an upper electrode (70) in contact with an upper surface of the semiconductor substrate;
A lower electrode (72) in contact with the lower surface of the semiconductor substrate;
It is equipped with
The semiconductor substrate has an element region (60) overlapping a contact surface between the upper electrode and the semiconductor substrate when viewed from above, and a peripheral region (62) arranged around the element region;
the element region has an element capable of passing a current between the upper electrode and the lower electrode,
The peripheral region is
an n-type drift region (34) exposed on an upper surface of the semiconductor substrate;
a plurality of p-type first breakdown voltage holding regions ( 42a ), each of which surrounds the element region, is exposed on the upper surface of the semiconductor substrate, and is separated from one another by the drift region;
a plurality of second voltage holding regions (42b) of p-type each of which surrounds the element region, is exposed on the upper surface of the semiconductor substrate, is separated from each other by the drift region, is separated from the first voltage holding region by the drift region, and has a p-type impurity concentration lower than that of the first voltage holding region;
having
The first and second voltage-resistant regions are alternately arranged.
Semiconductor device. a width of the first voltage-resistance holding region increases from the upper surface of the semiconductor substrate toward a lower side,
2. The semiconductor device according to claim 1, wherein a width of said second voltage-resistant region narrows from said upper surface of said semiconductor substrate toward a lower side. The semiconductor device of claim 1 or 2, wherein the semiconductor substrate is made of gallium nitride. A method for manufacturing a semiconductor device, comprising:
a semiconductor substrate having an n-type drift region (34) and a first p-type region (80) disposed on the drift region, the upper surface of the first p-type region being etched to form a plurality of annular grooves (84) extending concentrically when the upper surface of the first p-type region is viewed from above, each of the annular grooves penetrating the first p-type region and reaching the drift region;
forming an n-type region (86) covering the inner surfaces of the plurality of annular grooves by epitaxial growth;
forming a second p-type region (88) having a lower p-type impurity concentration than the first p-type region by epitaxial growth within the plurality of annular grooves;
A manufacturing method comprising: 5. The method of claim 4 , wherein in the step of forming the plurality of annular grooves, etching is performed so that the width of each of the annular grooves narrows from the upper surface of the semiconductor substrate downward. The method of claim 4 or 5, wherein the semiconductor substrate is made of gallium nitride.

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