JP7628903B2 - Pulse Power Supply - Google Patents

Description

The present invention relates to a pulse power supply device.

The plasma generating device is provided with a pulse power supply device that generates a pulsed voltage (pulse voltage) (see, for example, Patent Document 1). The pulse power supply device is configured, for example, to convert DC power into AC power using an inverter circuit, then convert the AC power into AC power of a different voltage value using a transformer, and further generate a pulse voltage using a switching circuit or the like.

However, in conventional pulse power supplies, it was difficult to accurately control the voltage value of the pulse voltage. Specifically, a difference in the timing of the conduction/non-conduction of switching elements in a switching circuit or the like causes the output voltage value to differ from the target voltage value, resulting in an error in the voltage value of the generated pulse voltage.

JP 2013-125729 A

The present invention was made in consideration of these problems, and aims to provide a pulse power supply device that can accurately control the voltage value of the pulse voltage.

In order to solve the above problem, the pulse power supply device of the present invention includes a first switching circuit having a first switching element and a second switching element connected in series between a power supply voltage terminal and a ground terminal, and outputting a first pulse voltage from a first output node which is a connection point between the first switching element and the second switching element; a boost circuit having one output terminal connected to the first output node and a capacitor connected between the one output terminal and the other output terminal; a second switching circuit having a third switching element and a fourth switching element connected between the first output node and the other output terminal of the boost circuit, and outputting a second pulse voltage obtained by superimposing the first pulse voltage as an offset on the output voltage of the boost circuit from a second output node which is a connection point between the third switching element and the fourth switching element; a charge absorption circuit connected between the output terminals of the boost circuit and having a variable resistance means; and a control unit for controlling the variable resistance means of the charge absorption circuit. The control unit is characterized by comprising a controller that converts analog signals indicating the voltage and current of the charge absorption circuit into digital signals and further converts them into optical signals, and outputs a control signal for controlling the variable resistance means, and an arithmetic control circuit that receives the optical signal output from the controller via an optical transmission line, converts it into a digital signal, performs an arithmetic operation based on the digital signal, converts the digital signal indicating the arithmetic operation result into an optical signal, and transmits it to the controller via the optical transmission line.

The present invention provides a pulse power supply device that can accurately control the voltage value of the pulse voltage.

1 is a schematic diagram showing an overall configuration of a plasma processing system 100 according to an embodiment of the present invention. 1 is a circuit diagram showing a configuration example of a pulse power supply device 1 of the present embodiment. 1 is a circuit diagram showing a configuration example of a pulse power supply device 1 of the present embodiment. FIG. 2 is a circuit diagram showing a configuration example of a pulse power supply device 1' of a comparative example. FIG. 11 is an explanatory diagram of the operation of a comparative pulse power supply device 1' when there is no mismatch between the timing of conduction/non-conduction of transistors Q5 and Q6 and the timing of conduction/non-conduction of the corresponding transistors Q7 and Q8. 1 is an explanatory diagram of an operation of a comparative pulse power supply device 1' when there is a discrepancy between the timing of conduction/non-conduction of transistors Q5 and Q6 and the timing of conduction/non-conduction of the corresponding transistors Q7 and Q8. FIG. 5 is a graph illustrating the operation of the charge absorption circuit DI in the pulse power supply 1. 2 is a graph showing the characteristics of tables 2302A and 2302B.

Hereinafter, the present embodiment will be described with reference to the attached drawings. In the attached drawings, functionally identical elements may be indicated by the same numbers. Note that the attached drawings show embodiments and implementation examples according to the principles of the present disclosure, but these are for understanding the present disclosure and are in no way used to interpret the present disclosure in a restrictive manner. The descriptions in this specification are merely typical examples and do not limit the scope or application examples of the present disclosure in any sense.

In this embodiment, the disclosure is described in sufficient detail for a person skilled in the art to implement the disclosure, but it should be understood that other implementations and forms are possible, and that changes to the configuration and structure and substitutions of various elements are possible without departing from the scope and spirit of the technical ideas of the disclosure. Therefore, the following description should not be interpreted as being limited to this.

A plasma processing system 100 according to this embodiment will be described with reference to Figures 1 to 2B. Figure 1 is a schematic diagram showing the overall configuration of the plasma processing system 100 according to this embodiment, and Figures 2A and 2B are circuit diagrams showing an example configuration of a pulse power supply device 1.

As shown in FIG. 1, the plasma processing system 100 includes a pulse power supply 1, a first high frequency power supply 2, a first matching box 3, a second high frequency power supply 4, a second matching box 5, a plasma processing unit 6, and a host controller 7. The plasma processing system 100 also includes a gas introduction device and an exhaust device (not shown), but their description will be omitted. The host controller 7 controls each device, such as the pulse power supply 1 and the first high frequency power supply 2. For example, the host controller 7 issues an output command for the pulse voltage to be output from the pulse power supply 1, and issues an output command for the high frequency power to be output from the first high frequency power supply 2. The connection lines between the host controller 7 and each device are not shown.

In FIG. 1, the plasma processing unit 6 has a processing vessel (chamber) in which a first electrode 61 to which high frequency power and a pulse voltage described later are applied, and a second electrode 62 arranged to face the first electrode 61 are provided. A workpiece 63 such as a semiconductor wafer is placed on top of the first electrode 61. The plasma processing system 100 performs processing such as etching on the workpiece 63 using plasma generated in the plasma processing unit 6.

The first high frequency power supply device 2 and the second high frequency power supply device 4 output high frequency power having a high frequency voltage of a frequency in the RF (Radio Frequency) band (e.g., 400 kHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 60 MHz, etc.). The high frequency power output from the first high frequency power supply device 2 is supplied to the first electrode 61 via the first matching device 3 that performs impedance matching. The high frequency power output from the second high frequency power supply device 4 is supplied to the second electrode 62 via the second matching device 5 that performs impedance matching.

The output frequencies of the first high frequency power supply device 2 and the second high frequency power supply device 4 vary depending on the application. There are also cases where the first high frequency power supply device 2 and the first matching device 3 are not present, or where the second high frequency power supply device 4 and the second matching device 5 are not present. A low pass filter for blocking high frequencies caused by the first high frequency power supply device 2 and the second high frequency power supply device 4 may be provided between the pulse power supply device 1 and the plasma processing unit 6. The plasma processing system 100 shown in FIG. 1 is of a capacitive coupling type, but there are also inductively coupled plasma processing systems 100. The pulse power supply device 1 described in this embodiment is applicable to such various types of plasma processing systems 100.

The pulse power supply 1 outputs a pulse voltage whose amplitude of DC voltage changes at a predetermined frequency. The pulse power supply 1 of this embodiment has two output systems, and is configured to output pulse voltages having different voltages. The first output system outputs a first pulse voltage, for example, 0V and -10kV alternately repeated. The second output system (a second pulse voltage generating circuit 302 described later) outputs a second pulse voltage, for example, 0V and -11.5kV alternately repeated. The first output system and the second output system are connected to a predetermined location in the processing vessel that serves as a load of the pulse power supply 1. The frequency of the pulse voltage output from the pulse power supply 1 is, for example, in a frequency range of about 100Hz to 10MHz, but is not limited to this. In the above, the voltage values of the first pulse voltage and the second pulse voltage are about -10kV, but are not limited to this. The polarity of the pulse voltage output from the pulse power supply 1 is not limited to negative.

The plasma processing system 100 shown in FIG. 1 is a capacitively coupled type, but there are also inductively coupled type plasma processing systems 100. The pulse power supply device 1 described in this embodiment can be applied to such various types of plasma processing systems 100.

With reference to FIG. 2A, an example of the configuration of the pulse power supply 1 will be described. The pulse power supply 1 is configured to include a DC power supply 31, an inverter circuit INV, a clamp circuit CP, a transformer TF, a rectifier circuit RC, a series circuit SC (composite capacitance Cin) of capacitors C3 and C4 functioning as a smoothing circuit, a charge absorption circuit DI, a first switching circuit SW1, a second switching circuit SW2, and a control unit 20. Of these, the first switching circuit SW1 forms a first pulse voltage generating circuit 301. The inverter circuit INV, the clamp circuit CP, the transformer TF, the rectifier circuit RC, the composite capacitance Cin, and the second switching circuit SW2 form a second pulse voltage generating circuit 302.

The inverter circuit INV, the clamp circuit CP, the transformer TF, the rectifier circuit RC, and the composite capacitance Cin form a DC/DC converter 303 (boost circuit) that boosts the DC power supply voltage (e.g., 375 V) of the DC power supply 31 to supply the boosted voltage. Therefore, it can be said that the second pulse voltage generating circuit 302 is formed by the DC/DC converter 303 and the second switching circuit SW2.

The control unit 20 that controls the pulse power supply device 1 includes a first controller 210 (first control unit), a second controller 220 (second control unit), and an arithmetic control circuit 230. The first controller 210 is a control device for controlling the inverter circuit INV, and the second controller 220 is a circuit for controlling the charge absorption circuit DI. In addition, an arithmetic control circuit 230 is provided as a circuit for generating a control signal in the second controller 220. The second controller 220 and the arithmetic control circuit 230 are connected by an optical fiber OF (optical transmission line) and are electrically insulated from each other. In addition, a DC voltage output from an insulating power supply 280 is supplied to the second controller 220 in order to operate ICs such as an AD converter and a DA converter inside the second controller 220. The voltage output from the insulating power supply 280 is a plurality of voltages, such as 12V, 5V, and 3.3V, suitable for ICs such as an AD converter and a DA converter.

The first controller 210 controls the control signal Sc1 so that the output voltage value of the DC/DC converter 303, i.e., the voltage value Vcin across the composite capacitance Cin, becomes the target voltage value Vcintg (a signal indicating the target voltage value). The target voltage value Vcintg is set in advance or by a higher-level control device 7 or the like. A drive circuit (not shown) inputs the control signal Sc1 and generates gate signals for the transistors Q1 to Q4 of the inverter circuit INV (described later). Note that in this embodiment, the transistors Q1 to Q4 and the transistors Q5 to Q9 (described later) are described as field effect transistors as an example, but they may be bipolar transistors or the like.

The second controller 220 controls the control signals Sc21 and Sc22 so that the power consumption values Pabs1 and Pabs2 of the charge absorption circuit DI become the target power values Ptg1 and Ptg2 (signals indicating the target power values). The target power values Ptg1 and Ptg2 (signals indicating the target power values) are set by tables 2302A and 2302B in the calculation control circuit 230 described later. The second controller 220 receives the current and voltage in the charge absorption circuit DI and outputs the control signals Sc21 and Sc22 according to the current and voltage. The calculation operation for generating the control signals Sc21 and Sc22 is performed in the calculation control circuit 230 connected to the second controller 220 by the optical fiber OF. The calculation control circuit 230 is electrically insulated from the second controller 220 and is connected only by the optical fiber OF. The calculation control circuit 230 operates in a low-voltage environment (e.g., 3.3 V, 5 V, etc.).

The control signals Sc21 and Sc22 output by the second controller 220 are supplied to the drive operational amplifiers 250 and 260, which generate gate signals according to the control signals Sc21 and Sc22 and supply them to the gates of the transistors Q11 and Q12. Although not shown, the drive operational amplifiers 250 and 260 are supplied with a DC voltage (e.g., 24 V) output from the insulated power supply 280. The second controller 220 also changes the control signal Sc21 according to the comparison result (error information) between the target power value Ptg1 and the output of the multiplier 2301A. Similarly, the second controller 220 changes the control signal Sc22 according to the comparison result (error information) between the target power value Ptg2 and the output of the multiplier 2301B. The transistors Q11 and Q12 are an example of a variable resistance means.

The first switching circuit SW1 forming the first pulse voltage generating circuit 301 is configured by connecting transistor Q5 and transistor Q6 (first switching element and second switching element) in series between the power supply voltage terminal Nv (e.g., -10 kV) and the ground terminal (GND). As transistor Q5 and transistor Q6 are alternately turned on, a first pulse voltage with an amplitude of -10 kV (0 V to -10 kV) is output from output node N11. The gate signals of transistors Q5 and Q6 are controlled by a control circuit not shown.

In the second pulse voltage generating circuit 302, the output node N11 (first output node) of the first switching circuit SW1 is connected to the second switching circuit SW2, forming a so-called floating connection. This causes the output voltage of the DC/DC converter 303 and the first pulse voltage generated by the first pulse voltage generating circuit 301 to be superimposed. This superimposed voltage is converted into a pulse voltage by the second switching circuit SW2 to generate the second pulse voltage. As will be described later, the second pulse voltage is, for example, a pulse voltage that alternates between 0V and -11.5kV. The second pulse voltage generating circuit 302 will be described below.

The inverter circuit INV is, for example, a full-bridge inverter circuit that converts DC power supplied from the DC power source 31 into AC power. That is, the inverter circuit INV includes a first arm Am1 and a second arm Am2. The first arm Am1 is formed by connecting transistors Q1 and Q2 in series between the positive and negative terminals of the DC power source 31 via a first node N1. The second arm Am2 is formed by connecting transistors Q3 and Q4 in series between the positive and negative terminals of the DC power source 31 via a second node N2. The DC power is converted into AC power by repeating a first state in which the transistors Q1 and Q4 are in a conductive state and the transistors Q2 and Q3 are in a non-conductive state and a second state in which the transistors Q2 and Q3 are in a conductive state and the transistors Q1 and Q4 are in a non-conductive state (AC power is generated between the first node N1 and the second node N2). In addition, although the transistors Q1 to Q4 in FIG. 2A are illustrated including body diodes, separate diodes may be used instead of body diodes. This also applies to the transistors Q5 to Q8 and Q11 to Q12 described below.

The clamp circuit CP includes an inductor 32, an inductor 33, and diodes D1 to D4 (first to fourth diodes). The inductor 32 is connected between the first node N1 and the first terminal N3 of the transformer TF, and the inductor 33 is connected between the second node N2 and the second terminal N4 of the transformer TF.

Diode D1 is connected between the positive terminal of the DC power supply 31 and the first terminal N3. Diode D2 is connected between the first terminal N3 and the negative terminal of the DC power supply 31. Diode D3 is connected between the positive terminal of the DC power supply 31 and the second terminal N4. Diode D4 is connected between the second terminal N4 and the negative terminal of the DC power supply 31. In other words, diodes D1 and D2 are connected in series between the negative terminal and the positive terminal of the DC power supply 31, with the first terminal N3 as the midpoint. Diodes D3 and D4 are connected in series between the negative terminal and the positive terminal of the DC power supply 31, with the second terminal N4 as the midpoint. All of the diodes D1 to D4 are connected in the forward direction from the negative terminal to the positive terminal of the DC power supply 31.

The inductors 32 and 33 have the role of increasing the input impedance when viewed from the transformer TF to the inverter circuit INV, and thus, when a common mode current flows from the secondary winding of the transformer TF to the primary winding via the parasitic capacitance, they suppress the common mode current from flowing into the transistors Q1 to Q4 that constitute the inverter circuit INV. The diodes D1 to D4 function as a detour to prevent such a common mode current from flowing into the inverter circuit INV and to allow it to flow to the DC power supply 31 or the ground terminal. Note that, although it is preferable that the inductors 32 and 33 have approximately the same inductance, this is not limited to this. Also, a resistive element may be connected in series with the inductors 32 and 33.

The transformer TF has a primary winding and a secondary winding arranged opposite each other, and further converts the AC power output by the inverter circuit INV via the clamp circuit CP into AC power of a different voltage value. As shown in FIG. 2A, an inductor L1 may be additionally connected to the primary side of the transformer TF. The output voltage of the transformer TF is applied to a rectifier circuit RC. The rectifier circuit RC may be configured as a quadruple voltage rectifier circuit as shown in FIG. 2A. The quadruple voltage rectifier circuit is configured by capacitors C1 and C2 and diodes D5 to D8.

Diodes D5 to D8 are connected in series with the same forward direction. Capacitor C1 is connected between the first output terminal of transformer TF and the connection node N5 of diodes D5 and D6. Capacitor C2 is connected between the first output terminal of transformer TF and the connection node N7 of diodes D7 and D8.

The combined capacitance Cin, which functions as a smoothing circuit, is connected in parallel with the diodes D5 to D8, and the connection node N8 between the capacitors C3 and C4 is connected to the node N6. This causes the capacitors C3 and C4 to store electricity.

The charge absorption circuit DI is, for example, composed of a plurality of resistor series circuits (for example, a first resistor series circuit RS1 having a transistor Q11 and a resistor R14, a second resistor series circuit RS2 having a transistor Q12 and a resistor R15, and a voltage divider circuit RS3 having resistors R11 and R12. The charge absorption circuit DI has a function of forcibly consuming the charge stored in the capacitors C3 and C4, thereby lowering the voltage value Vcin across the combined capacitance Cin. The first resistor series circuit RS1, the second resistor series circuit RS2, and the voltage divider circuit RS3 in the charge absorption circuit DI are connected to the combined capacitance Ci n. That is, it is connected between the output terminals of the DC/DC converter 303. The gate signal of the transistor Q11 is supplied from the drive operational amplifier 250 under the control of the second controller 220. The gate signal of the transistor Q12 is supplied from the drive operational amplifier 260 under the control of the second controller 220. The reason why the charge absorption circuit DI is provided with a plurality of resistor series circuits (in the example of FIG. 2, there are two, the first resistor series circuit RS1 and the second resistor series circuit RS2) having a plurality of transistors and resistors will be described later.

The transistor Q11 of the first resistor series circuit RS1 is used in the saturation region. Therefore, by increasing the magnitude of the gate signal of the transistor Q11, the drain-source resistance value (hereinafter referred to as the resistance value) of the transistor Q11 can be reduced. For example, the resistance value of the transistor Q11 can be adjusted from 10 Ω to 1 MΩ, and the resistance value of the resistor R14 is 1 Ω. By changing the resistance value of the transistor Q11, the combined resistance value of the transistor Q11 and the resistor R14 changes, and the current value Ina1 of the current flowing through the first resistor series circuit RS1 changes. The current value Ina1 can be calculated by detecting the voltage of the connection node NA1 between the transistor Q11 and the resistor R14 and performing a predetermined conversion process on the detected voltage using a conversion circuit not shown. The current value Ina1 (a signal indicating the current value) is input to the second controller 220.

The transistor Q12 of the second resistor series circuit RS2 is also used in the saturation region. Therefore, by increasing the magnitude of the gate signal of the transistor Q12, the resistance value between the drain and source of the transistor Q12 (hereinafter referred to as the resistance value) can be reduced. For example, the resistance value of the transistor Q12 can be adjusted from 10 Ω to 1 MΩ, and the resistance R15 is 1 Ω. By changing the resistance value of the transistor Q12, the combined resistance value of the transistor Q12 and the resistor R15 changes, so the current value Ina2 of the current flowing through the second resistor series circuit RS2 changes. The current value Ina2 can be calculated by detecting the voltage of the connection node NA2 between the transistor Q12 and the resistor R15 and performing a predetermined conversion process on the detected voltage using a conversion circuit not shown. The current value Ina2 (a signal indicating the current value) is input to the second controller 220.

When a bipolar transistor is used as transistor Q11, the resistance between the collector and emitter can be changed by changing the magnitude of a control signal such as the base current or gate voltage. As can be seen from the above, other variable resistance means such as a variable resistor may be used instead of transistor Q11. However, this is not practical unless the resistance can be adjusted by a control signal such as a gate signal. Field effect transistors, etc. are suitable because their resistance can be changed by a control signal and the resistance adjustment range is wide.

The voltage Vnb across the voltage divider circuit RS3 can be calculated by detecting the voltage at the connection node NB between resistors R11 and R12, and performing a predetermined conversion process on the detected voltage using a conversion circuit (not shown). This voltage value Vnb (a signal indicating a voltage value) indicates the voltage value across the first and second resistor series circuits RS1 and RS2, as well as the voltage value Vcin across the combined capacitance Cin. The voltage value Vnb is input to the second controller 220. The voltage divider circuit RS3 is basically used for voltage detection, and therefore has a relatively high combined resistance value. For example, 1 MΩ. Furthermore, the voltage value Vnb (= the voltage value Vcin across the combined capacitance Cin) is used to control the first controller 210, as described above.

The second switching circuit SW2 is configured by connecting transistor Q7 and transistor Q8 (third switching element and fourth switching element) in series between output node N11 and output node N9 (boosted voltage output node). That is, the second switching circuit SW2 is connected between the output terminals of the DC/DC converter 303. A control circuit (not shown) provides gate signals to transistor Q7 and transistor Q8 so that transistor Q7 and transistor Q8 are alternately turned on.

The timing of switching the conduction/non-conduction of the transistor Q7 is controlled to be synchronized with the transistor Q5, and the timing of switching the conduction/non-conduction of the transistor Q8 is controlled to be synchronized with the transistor Q6. A voltage obtained by superimposing the output voltage of the DC/DC converter 303 and the first pulse voltage generated by the first pulse voltage generating circuit 301 is applied between the output node N11 and the output node N9, so that when the transistors Q5 and Q7 are in a conductive state, the potential of the ground terminal GND (for example, 0V) is output from the output terminal Vout2 via the output node N12 (second output node). Also, when the transistors Q6 and Q8 are in a conductive state, the transistors Q5 and Q7 are in a non-conductive state, so that one end of the capacitor C3 is connected to the power supply voltage terminal Nv, and the other end of the capacitor C4 is connected to the output terminal Vout2. As described above, since the floating connection is made, the output of the DC/DC converter 303 is based on the potential of the power supply voltage terminal Nv (for example, -10 kV). If the output voltage of the DC/DC converter 303 is 1.5 kV, then -11.5 kV is output from the output terminal Vout2. Therefore, a pulse voltage in which 0V and -11.5 kV are alternately repeated is output from the output terminal Vout2. In other words, the second pulse voltage generating circuit 302 generates a second pulse voltage in which the first pulse voltage generated by the first pulse voltage generating circuit 301 is superimposed as an offset on the output voltage of the DC/DC converter 303.

An example of the detailed configuration of the second controller 220 and the arithmetic control circuit 230 will be described with reference to FIG. 2B. As described above, the second controller 220 and the arithmetic control circuit 230 are connected by an optical fiber OF and are electrically insulated from each other. The second controller 220 needs to be placed in a high-voltage environment, but the arithmetic control circuit 230 can be placed in a low-voltage environment that is electrically insulated from the high-voltage environment, allowing for stable operation. For example, in a low-voltage environment, a high-precision, high-speed processor such as a CPU or FPGA can be used, making it possible to change the target power value in real time.

The second controller 220 has the same number of sets of AD converters 2201 and DA converters 2202 as the number of resistor series circuits in the charge absorption circuit DI. In the example of FIG. 2B, since there are two resistor series circuits, two sets of AD converters 2201 and DA converters (2201A, 2202A, 2201B, 2202B) are provided. The AD converter 2201A and the DA converter 2202A are provided for controlling the first resistor series circuit RS1 (transistor Q11). On the other hand, the AD converter 2201B and the DA converter 2202B are provided for controlling the second resistor series circuit RS2 (transistor Q12).

The AD converter 2201A receives the current Ina1 flowing through the node NA1 of the transistor Q11 and the voltage Vnb across the voltage divider circuit RS3 as analog signals from the first resistor series circuit RS1, and converts them into a corresponding digital signal. The digital signal is converted into an optical signal by the photoelectric conversion circuit 2204, and transmitted to the arithmetic control circuit 230 via the optical fiber OF. The voltage Vnb across the voltage divider circuit RS3 converted into a digital signal can be used to control the first controller 210. In that case, the first controller 210 may also be configured to be controlled by a digital signal. The AD converter 2201B receives the current Ina2 flowing through the node NA2 of the transistor Q12 and the voltage Vnb across the voltage divider circuit RS3 as analog signals from the second resistor series circuit RS2, and converts them into a corresponding digital signal. The digital signal is converted into an optical signal by the photoelectric conversion circuit 2204, and transmitted to the arithmetic control circuit 230 via the optical fiber OF.

The arithmetic control circuit 230 multiplies the current value Ina1 and the voltage value Vnb as digital signals in the multiplier 2301A to calculate the power consumption value Pabs1 consumed by the first resistor series circuit RS1. The power consumption value Pabs1 is compared with the target power value Ptg1 in the comparator 2303A, and the control signal Sc21D is generated in the control signal generation circuit 2304A according to the comparison result (error information). The target power value Ptg1 is supplied from the table 2302A. The table 2302A is a table showing the relationship between the voltage value Vnb and the target voltage Ptg1, and the target power value Ptg1 is set according to the voltage value Vnb. The control signal Sc21D is converted into an optical signal by the photoelectric conversion circuit 2304, received by the photoelectric conversion circuit 2204 of the second controller 220 via the optical fiber OF, converted back into a digital signal, and further converted into an analog control signal Sc21 by the DA converter 2202A.

The arithmetic control circuit 230 also multiplies the current value Ina2 and the voltage value Vnb as digital signals in the multiplier 2301B to calculate the power consumption value Pabs2 consumed by the second resistor series circuit RS2. The power consumption value Pabs2 is compared with the target power value Ptg2 in the comparator 2303B, and the control signal Sc22D is generated in the control signal generation circuit 2304B according to the comparison result (error information). The target power value Ptg2 is supplied from the table 2302B. The table 2302B is a table showing the relationship between the voltage value Vnb and the target voltage Ptg2, and the target power value Ptg2 is set according to the voltage value Vnb. The control signal Sc22D is converted into an optical signal by the photoelectric conversion circuit 2304, received by the photoelectric conversion circuit 2204 of the second controller 220 via the optical fiber OF, converted back into a digital signal, and further converted into an analog control signal Sc22 by the DA converter 2202B.

As described above, the resistance values of transistors Q11 and Q12 can be changed via drive operational amplifiers 250 and 260 by control signals Sc21 and Sc22, so that the current values Ina1 and Ina2 flowing through the first resistor series circuit RS1 and the second resistor series circuit RS2 can be adjusted. In addition, since a small amount of current also flows through voltage divider circuit RS3, it is possible to consume power in the charge absorption circuit DI as a whole. In other words, the charge stored in capacitors C3 and C4 can be forcibly consumed, thereby lowering the voltage value Vcin across the combined capacitance Cin. The effect of this will be described later.

Next, the effects of the pulse power supply 1 of this embodiment will be described in comparison with a pulse power supply 1' according to a comparative example in FIG. 3. The pulse power supply 1' according to this comparative example differs from this embodiment in that it does not include a charge absorption circuit DI. Since there is no charge absorption circuit DI, the second controller 220 and the arithmetic control circuit 230 are also not provided.

In this comparative example, due to a mismatch between the timing of the conduction/non-conduction of the transistors Q5 and Q6 constituting the first switching circuit SW1 and the timing of the conduction/non-conduction of the corresponding transistors Q7 and Q8 constituting the second switching circuit SW2, the voltages across the capacitors C3 and C4 are charged to exceed the target voltage, which may make it difficult for the DC/DC converter 303 to adjust the voltage value of the second pulse voltage. There are various causes for the variation in the timing of the conduction, such as the characteristics of the controller (control IC), the characteristics of the transistors, and the variation in the circuit constants of the drive OP amplifier. In addition, for other reasons, it may be necessary to intentionally control the timing of the conduction/non-conduction of the transistors Q5 and Q6 to be misaligned with the timing of the conduction/non-conduction of the corresponding transistors Q7 and Q8, which may result in the voltage value Vcin across the composite capacitance Cin being charged to exceed the target voltage value Vcintg.

With reference to FIG. 4, the operation of the pulse power supply device 1' of the comparative example will be described when the transistors Q5 and Q6 are turned on/off at normal timing without any discrepancy with the timing of the corresponding transistors Q7 and Q8 turning on/off. In FIG. 4, Lil and Ril indicate the reactance and resistance components from the output node N11 of the first switching circuit SW1 to the output terminal Vout1. Li2 and Ri2 indicate the inductance and resistance components from the output node N12 of the second switching circuit SW2 to the output terminal Vout2. Ro1, Co1, Ro2, and Co2 indicate the reactance and resistance components on the load side. The combined capacitance of the capacitors C3 and C4 is represented as Cin. The resistor Rin' connected in parallel to the combined capacitance Cin virtually represents the resistor connected in parallel to both ends of the series circuit of the capacitors C3 and C4. In FIG. 4 and FIG. 5 described later, the first resistor series circuit RS1 and the second resistor series circuit RS2 shown in FIG. 2A are not included, but a voltage detection circuit equivalent to the voltage divider circuit RS3, a resistance component of the load, cable loss, etc. are included. The resistance value of resistor Rin' is, for example, 1 kΩ.

In normal operation, the pulse power supply device 1' of the comparative example repeats the following two states S1 and S2.
(State S1)
The transistors Q6 and Q8 are simultaneously turned on (ON), and the transistors Q5 and Q7 are simultaneously turned off (OFF).
(State S2)
Transistors Q5 and Q7 are simultaneously in a conductive state, and transistors Q6 and Q8 are simultaneously in a non-conductive state.

In addition, in the first switching circuit SW1 and the second switching circuit SW2, in order to prevent the power supply from being short-circuited due to transistors Q5 and Q6 being simultaneously conductive, or transistors Q7 and Q8 being simultaneously conductive, a period (dead time) during which all transistors Q5 to Q8 are simultaneously non-conductive is set between state 1 and state 2.

In state S1, a current I1 flows from the load connected to the output terminal of the first switching circuit SW1 toward the power supply voltage terminal Nv via transistor Q6. A current I2 flows from the load connected to the output terminal of the second switching circuit SW2 toward the power supply voltage terminal Nv via the body diode of transistor Q7 and transistor Q6. A current I3 flows from the load connected to the output terminal of the second switching circuit SW2 toward the power supply voltage terminal Nv via transistor Q8, composite capacitance Cin, and transistor Q6.

On the other hand, in state S2, current I4 flows from the ground terminal GND of the first switching circuit SW1 through the conductive transistor Q5 toward the load connected to the output terminal of the first switching circuit SW1. Similarly, current I5 flows from the ground terminal GND of the first switching circuit SW1 through the conductive transistors Q5 and Q7 toward the load connected to the output terminal of the second switching circuit SW2. Similarly, current I6 flows from the ground terminal GND of the first switching circuit SW1 through the conductive transistor Q5, the combined capacitance Cin, and the body diode of transistor Q8 toward the load connected to the output terminal of the second switching circuit SW2. Note that the current values in parentheses along with the current symbols I1 to I6 in FIG. 4 are examples of current values (average currents) obtained under certain conditions for currents I1 to I6.

When there is no mismatch between the timing of the conduction/non-conduction of transistors Q5 and Q6 and the timing of the conduction/non-conduction of the corresponding transistors Q7 and Q8, the current flowing from the first switching circuit SW1 to the composite capacitance Cin is balanced with the current flowing from the composite capacitance Cin to the first switching circuit SW1. Therefore, the current from the first switching circuit SW1 does not increase the voltage across the composite capacitance Cin.

Next, referring to FIG. 5, the operation of the comparative pulse power supply device 1' will be described when there is a mismatch between the timing of conduction/non-conduction of transistors Q5 and Q6 and the timing of conduction/non-conduction of the corresponding transistors Q7 and Q8. As an example, a case will be described where the switching timing of transistors Q7 and Q8 is delayed compared to the switching timing of transistors Q5 and Q6. Also, the conduction/non-conduction of transistors Q5 to Q8 is switched in the order of states S11, S12, S13, and S14 shown in FIG. 5. States S11 to S14 are as follows:

(State S11)
If the transistors Q6 and Q8 are operating at normal timing, they will be in a conducting state at the same time, and the transistors Q5 and Q7 will be in a non-conducting state at the same time. However, the timing at which the transistor Q7 switches from a conducting state to a non-conducting state is delayed from the timing at which the transistor Q5 switches from a conducting state to a non-conducting state, and the transistor Q7 switches to a non-conducting state in the middle of state S11. Also, the timing at which the transistor Q8 switches from a non-conducting state to a conducting state is delayed from the timing at which the transistor Q6 switches from a conducting state to a non-conducting state, and the transistor Q7 switches to a conducting state after a dead time has elapsed after switching from a conducting state to a non-conducting state. That is, the transistor Q8 is in a non-conducting state during state S11, and switches to a conducting state when state S12, which will be described later, is reached. In this state S11, a large current I1' flows from a load connected to the output terminal of the first switching circuit SW1 to the power supply voltage terminal Nv via the transistor Q6. Also, a large current I2' flows from the load connected to the output terminal of the second switching circuit SW2 toward the power supply voltage terminal Nv through the transistor Q7 and the transistor Q6. That is, in the case of Fig. 5, a current does not flow from the composite capacitance Cin toward the power supply voltage terminal Nv through the transistor Q6, as in Fig. 4, the current I3. Also, in the case of Fig. 4, when the transistors Q6 and Q8 are in a conductive state (ON), the transistors Q5 and Q7 are in a non-conductive state (OFF), so that a current flows only when the body diode of the transistor Q7 is forward biased during the period when the transistors Q6 and Q8 are in a conductive state (ON). In contrast, in the case of Fig. 5, when the transistor Q6 is in a conductive state (ON), the transistor Q7 is also in a conductive state (ON), so that a large current I2' flows toward the first switching circuit SW1 during the period until the transistor Q7 is in a non-conductive state (OFF).

(State S12)
The transistor Q8 switches to a conductive state with a delay, the transistors Q5 and Q7 are non-conductive, and the transistors Q6 and Q8 are conductive. In this state, a current I1'' flows from the load connected to the output terminal of the first switching circuit SW1 toward the power supply voltage terminal Nv via the transistor Q6. Also, a current I3'' flows from the load connected to the output terminal of the second switching circuit SW2 toward the power supply voltage terminal Nv via the conductive transistor Q8, the composite capacitance Cin, and the conductive transistor Q6. At this time, the composite capacitance Cin is discharged.

(State S13)
If the transistors Q5 and Q7 are operating at normal timing, they will simultaneously switch from a non-conductive state to a conductive state, and the transistors Q6 and Q8 will simultaneously switch from a conductive state to a non-conductive state. However, contrary to state S11, the timing at which the transistor Q8 switches from a conductive state to a non-conductive state is delayed from the timing at which the transistor Q6 switches from a conductive state to a non-conductive state, and the transistor Q8 switches to a non-conductive state in the middle of state S13. Also, the timing at which the transistor Q7 switches from a non-conductive state to a conductive state is delayed from the timing at which the transistor Q5 switches from a non-conductive state to a conductive state, and the transistor Q8 switches to a conductive state after a dead time has elapsed after switching from a conductive state to a non-conductive state. That is, the transistor Q7 is in a non-conductive state during state S13, and switches to a conductive state when state S14, which will be described later, is reached. In this case, the capacitive load (negative potential) connected to the output terminal Vout1 of the first switching circuit SW1 is connected to the ground terminal GND via the transistor Q5. Therefore, a large current I4' flows from the ground terminal GND via the transistor Q5 in a conductive state. In addition, the capacitive load (negative potential) connected to the output terminal Vout2 of the second switching circuit SW2 is connected to the ground terminal GND via the composite capacitance Cin and the transistor Q8 in a conductive state. Therefore, a large current I6' flows from the ground terminal GND to the load connected to the second switching circuit SW2 via the transistor Q5 in a conductive state, the composite capacitance Cin, and the transistor Q8 in a conductive state. At this time, the composite capacitance Cin is charged with an electric charge.

(State S14)
The transistor Q7 switches to a conductive state with a delay, the transistors Q5 and Q7 are conductive, and the transistors Q6 and Q8 are non-conductive. In this state, the capacitive load (negative potential) connected to the output terminal Vout1 of the first switching circuit SW1 and the capacitive load (negative potential) connected to the output terminal Vout2 of the second switching circuit SW2 are connected to the ground terminal GND. Therefore, a current I4'' flows from the ground terminal GND through the transistor Q5. Also, a current I5'' flows from the ground terminal GND through the transistors Q5 and Q7 toward the load connected to the second switching circuit SW2. In FIG. 5, the current values indicated in parentheses with the symbols I1' to I6', I1'', I3'', I4'', and I5'' are examples of current values (average currents) obtained under certain conditions for each current.

Here, when we look at the composite capacitance Cin, the period between states S11 and S12 is the discharge period, and the period between states S13 and S14 is the charge period. If the period between states S11 and S13 is 150 ns and the period between states S12 and S14 is 1100 ns, the current flowing out of the composite capacitance Cin during the discharge period is 3.16 A ((0 A x 150 ns + 3.59 A x 1,100 ns) / 1,250 ns), and the current flowing into the composite capacitance Cin during the charge period is 3.19 A ((26.6 A x 150 ns + 0 A x 1,100 ns) / 1,250 ns). In other words, a 0.03 A balance discrepancy occurs during one cycle, so the voltage Vcin across the composite capacitance Cin rises little by little. As the voltage rises, the loss in resistor Rin increases, so the voltage Vcin across the composite capacitance Cin is suppressed from rising in relation to the loss in resistor Rin, and stabilizes at a balanced point. That is, as shown in FIG. 4, the voltage Vcin across the composite capacitance Cin when there is a discrepancy in the timing of conduction between transistors Q5 and Q6 and transistors Q7 and Q8 is greater than the voltage Vcin across the composite capacitance Cin when transistors Q5 and Q6 and transistors Q7 and Q8 are operating at normal timing.

Normally, the voltage value Vcin across the composite capacitance Cin can be brought closer to the target voltage value Vcintg by reducing the control signal Sc1 output from the first controller 210. However, since the above deviation is due to the charge stored in the composite capacitance Cin, the voltage value Vcin across the composite capacitance Cin does not become 0 even if the control signal Sc1 is set to 0. Under certain conditions, the voltage value Vcin across the composite capacitance Cin may rise to about twice the target voltage value Vcintg. When this happens, it becomes impossible to accurately control the voltage value of the second pulse voltage.

In order to solve such problems, the pulse power supply device of the embodiment includes a charge absorption circuit DI connected in parallel to the series circuit of the capacitors C3 and C4. As described above, the charge absorption circuit DI can forcibly consume the charge stored in the capacitors C3 and C4 to reduce the voltage value Vcin across the composite capacitance Cin. Therefore, even if the above-mentioned problem occurs and the voltage Vcin across the composite capacitance Cin rises little by little, the charge absorption circuit DI can consume power to cancel out the increase, thereby controlling the voltage value Vcin across the composite capacitance Cin to the target voltage value Vcintg. Appropriate values are determined by experiments, etc. to determine how much power to consume, that is, how much the target power values Ptg1 and Ptg2 should be. Note that the target power values Ptg1 and Ptg2 are preferably set using a table so that they change based on the voltage across the charge absorption circuit DI (the voltage Vnb across the voltage divider circuit RS3) as described later, but are not limited to this. For example, the target power values Ptg1 and Ptg2 may be set to constant values, and control may be performed so that a constant amount of power is consumed at all times.

The operation of the charge absorption circuit DI in this pulse power supply device 1 will be described with reference to FIG. 6. Here, a case will be described in which the operation starts from state (i) and transitions sequentially to states (ii), (iii), and (iv). Note that what is described here is an example in which the control of the transistors Q11 and Q12 (control of power consumption) by the second controller 220 is faster than the control of the DC/DC converter 303 by the first controller 210. Also, in order to simplify the explanation, the target power values Ptg1 and Ptg2 will be described as constant values.

In state (i), the target voltage value Vcintg of the voltage across the composite capacitance Cin is set to Vcintg1, and the control signal Sc1 of the first controller 210 changes so that this target voltage value Vcintg1 is obtained. The control signals Sc21 and Sc22 of the second controller 220 also change to match this target voltage value Vcintg1. Note that state (i) indicates a state in which the control by the first controller 210 and the control by the second controller 220 are stable.

In the subsequent state (ii) (from time t1), the target voltage value Vcintg switches from Vcintg1 to the smaller voltage value Vcintg2. The first controller 210 reduces the level of the control signal Sc1 from Sc11 to Sc12. This causes the voltage value Vcin across the combined capacitance Cin to gradually decrease.

When the voltage value Vcin across the composite capacitance Cin starts to decrease, the power consumption values Pabs1 and Pabs2 of the charge absorption circuit DI also start to decrease after time t1. In response to this, the second controller 220 gradually increases the control signals Sc21 and Sc22 from tg1 (tg1') to a larger value tg2 (tg2') in order to keep the power consumption values Pabs1 and Pabs2 of the charge absorption circuit DI constant. The increase in the control signals Sc21 and Sc22 increases the gate voltages of the transistors Q11 and Q12, which decreases the resistance value of the charge absorption circuit DI and increases the current flowing through the transistors Q11 and Q12.

In state (iii) (from time t2), the power consumption values Pabs1 and Pabs2 of the charge absorption circuit DI return to their original constant values. In this way, the charge absorption circuit DI is controlled to consume a constant amount of power regardless of fluctuations in the voltage value Vcin across the combined capacitance Cin. By controlling the gate voltages of transistors Q11 and Q12 and using the saturation regions of transistors Q11 and Q12, the power consumption values Pabs1 and Pabs2 of the charge absorption circuit DI can be controlled to constant values. In state (iv) (from time t3), the voltage value Vcin across both ends reaches the target value Vcintg2, and the series of operations ends.

Next, the characteristics of the charge absorption circuit DI are explained using Table 1. In the circuit of FIG. 2A, the first switching circuit SW1 can be considered as a constant current source that supplies a constant current value Isw1.

Here, the combined resistance value of the first resistor series circuit RS1 and the second resistor series circuit RS2 is defined as Ra (variable by the gate signals of the transistors Q11 and Q12), and the resistance value of other resistance components (such as the voltage divider circuit RS3 and the resistance components of the load and cable loss) connected in parallel to the combined capacitance Cin other than the resistance value Ra is defined as Rb (constant value). In addition, the resistance value of the combined resistance of the first resistor series circuit RS1 and the second resistor series circuit RS2 and the other resistance components is defined as the combined resistance value Rab, the power value consumed by the first resistor series circuit RS1 and the second resistor series circuit RS2 is defined as the power consumption value PRa, the power value consumed by the other resistance components is defined as the power consumption value PRb, and the sum of the power consumption values PRa and PRb is defined as the total power consumption value PRab. In this way, the voltage value Vcin across the combined capacitance Cin can be expressed as Rab x Isw1. Let us also assume that the constant current value Isw1 is 1A, the adjustment range of the resistance value Ra is 10Ω to 1MΩ, and the resistance value Rb is 1kΩ. As mentioned above, the voltage divider circuit RS3 is basically used for voltage detection, so it has a relatively high resistance value. For example, 1MΩ. However, due to the influence of the resistance components of the voltage divider circuit RS3 and the load, cable loss, etc., the resistance value Rb of the other resistance components is lower than the resistance value of the voltage divider circuit alone (1MΩ). Here, the resistance value Rb is set to 1kΩ.

Under such conditions, as shown in Table 1, as the resistance value Ra increases, the combined resistance value Rab and the voltage value Vcin across the combined capacitance Cin increase. Therefore, if the resistance value Ra of the first resistor series circuit is small (for example, 10 Ω), the voltage value Vcin across the combined capacitance Cin becomes too small (for example, 10 V). When the resistance value Ra is large (for example, 1 MΩ), the voltage value Vcin across the combined capacitance Cin is large (for example, 999 Ω), so it is difficult to say that the charge stored in the capacitors C3 and C4 is forcibly consumed. When the resistance value Ra = resistance value Rb = 1 kΩ, the power consumption value PRa consumed by the first resistor series circuit is maximum (250 W). Since the power consumption value PRb consumed by the other resistance components at this time is 250 W, the total power consumption value PRab is 500 W. In addition, the voltage Vcin across the combined capacitance Cin at this time is 500V, which is a sufficient voltage drop compared to the 1000V when the charge absorption circuit DI is not present.

As can be seen from the above, reducing the resistance value Ra does not necessarily increase the total power consumption value PRab, but rather the resistance value Ra must be adjusted in consideration of the relationship between the voltage value Vcin across the composite capacitance Cin and the total power consumption value PRab. In this embodiment, the first controller 210 controls the control signal Sc1 so that the voltage value Vcin across the composite capacitance Cin becomes the target voltage value Vcintg. In addition, the second controller 220 controls the control signal Sc2 so that the power consumption values Pabs1 and Pabs2 of the charge absorption circuit DI become the target power values Ptg1 and Ptg2 of the power consumption value Pabs1, so that the resistance value Ra can be adjusted in consideration of the relationship between the voltage value Vcin across the composite capacitance Cin and the total power consumption value PRab.

As described above, the pulse power supply device of this embodiment includes a charge absorption circuit DI connected in parallel with the series circuit of capacitors C3 and C4, and controls the resistance values of transistors Q11 and Q12 by controlling the gate signals of transistors Q11 and Q12. This controls the power consumption in the charge absorption circuit DI to the target power value, so that the charge stored in capacitors C3 and C4 is forcibly consumed by the charge absorption circuit DI, and the voltage value Vcin across the composite capacitance Cin can be reduced. Therefore, even if the amount of current flowing from the first switching circuit SW1 to the composite capacitance Cin becomes greater than the amount of current flowing from the composite capacitance Cin to the first switching circuit SW1, it is possible to control the voltage value Vcin across the composite capacitance Cin to the target voltage value Vcintg.

Next, the reason why the charge absorption circuit DI is provided with resistor series circuits (two, a first resistor series circuit RS1 and a second resistor series circuit RS2 in the example of FIG. 2) each having a plurality of transistors and resistors will be described.
As described above, the charge absorption circuit DI forcibly consumes the charge stored in the capacitors C3 and C4, lowering the voltage value Vcin across the combined capacitance Cin, which causes loss in the transistor. However, there is a specification limit to the loss in the transistor. Therefore, when the loss in the transistor is large, it is not possible to deal with it with only one resistor series circuit. In such a case, for example, as shown in FIG. 2A, two resistor series circuits may be provided to distribute the current flowing through the transistor, thereby reducing the loss in one transistor. Of course, the number of resistor series circuits is not limited and may be set appropriately depending on the usage situation.

As described above, in this embodiment, the calculation control circuit 230 is placed in a low-voltage environment, making it possible to perform calculations with high accuracy and high speed. Therefore, as described above, when multiple resistor series circuits are used, even if variations in the current values flowing through each transistor occur due to variations in the transistor characteristics, high-speed control is possible for each transistor. For example, the gate voltage of a transistor with large losses can be manipulated to lower losses, thereby reducing the variation in losses among each transistor. In this way, it is effective not only in terms of control stability but also in terms of equipment protection.

Next, the characteristics of the above-mentioned tables 2302A and 2302B will be described based on the embodiment of FIG. 2A and FIG. 2B. As shown in Table 1, when the voltage value Vcin (voltage Vnb of the voltage divider circuit RS3) across the composite capacitance Cin increases, the power consumption value PRa consumed by the first resistor series circuit RS1 and the second resistor series circuit RS2 initially increases. After that, after the power consumption value PRa of the first resistor series circuit RS1 and the second resistor series circuit RS2 and the power consumption value PRb of the other resistance components become equal, as the voltage value Vcin across the composite capacitance Cin increases, the power consumption value PRa decreases. In other words, when the horizontal axis represents the voltage value Vcin [V] across the composite capacitance Cin and the vertical axis represents the power value [W], the power consumption value PRa is a graph that is convex upward as shown in FIG. 7. In this embodiment, the voltage Vnb across the voltage divider circuit RS3 is detected as the voltage value Vcin across the combined capacitance Cin, so by determining the target power values Ptg1 and Ptg2 consumed by the first resistor series circuit RS1 and the second resistor series circuit RS2 according to the voltage Vnb across the voltage divider circuit RS3, it is possible to forcibly consume the charge stored in the capacitors C3 and C4 by the charge absorption circuit DI while reducing losses.

In this case, if the power consumption value PRa estimated from the voltage Vnb across the voltage divider circuit RS3 using the relationship shown in Table 1 is set as the target power value Ptg (in the case of FIG. 2B, Ptg is the sum of Ptg1 and Ptg2), the comparison result (error information) in the comparators 2303A and 2303B will be 0 (zero) or close to 0. If this happens, the magnitude of the control signals Sc21 and Sc22 will be 0 or close to 0, and the second controller 220 will not be able to perform voltage control properly. Therefore, as shown in FIG. 7, the target power value Ptg is set to be slightly larger than the power consumption value PRa. How much larger it should be can be determined appropriately taking into account the usage environment. By setting the target power value Ptg slightly larger than the power consumption value PRa, some power loss will occur, but the first controller 210 will be able to perform voltage control properly.

These characteristics are tabulated in tables 2302A and 2302B. That is, as shown in FIG. 2B, the voltage Vnb across the voltage divider circuit RS3 is input to tables 2302A and 2302B, and the target power value Ptg for the voltage Vnb across the voltage divider circuit RS3 is defined in tables 2302A and 2302B. Note that the target power value Ptg is the sum of the target power value Ptg1 and the target power value Ptg2, so each target power value can be determined taking into account the characteristics of the transistors used and the current flowing therethrough. For example, if the transistors and resistors used in the first resistor series circuit RS1 and the second resistor series circuit RS2 have the same specifications, the target power value Ptg1 and the target power value Ptg2 can be set to half the target power value Ptg.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment and includes various modified examples. For example, the above embodiment has been described in detail to clearly explain the present invention, and is not necessarily limited to having all of the configurations described. It is also possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. It is also possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

1...pulse power supply, 2...first high frequency power supply, 3...first matching box, 4...second high frequency power supply, 5...second matching box, 6...plasma processing unit, 7...host control device, 31...DC power supply, 32, 33...inductor, 63...workpiece, 100...plasma processing system, C1 to C4...capacitors, Am1...first arm, Am2...second arm, CP...clamp circuit, TF...transformer, CT...rectifier circuit, DI...charge absorption circuit, D1 to D8...diodes, 210...first controller, 220...second controller, 230...arithmetic and control circuit, 250, 260...drive Eve OP amplifier, 301...first pulse voltage generating circuit, 302...second pulse voltage generating circuit, 303...DC/DC converter, GND...ground terminal, INV...inverter circuit, Q1-Q12...transistor, SW1...first switching circuit, SW2...second switching circuit, 2201A, 2201B...AD converter, 2202A, 2202B...DA converter, 2204, 2304...photoelectric conversion circuit, 2301A, 2301B...multiplier, 2302A, 2302B...table, 2303A, 2303B...comparator, 2304A, 2304B...controller.

Claims (4)

a first switching circuit including a first switching element and a second switching element connected in series between a power supply voltage terminal and a ground terminal, and outputting a first pulse voltage from a first output node which is a connection point between the first switching element and the second switching element;
a boost circuit having one output terminal connected to the first output node and a capacitor connected between the one output terminal and the other output terminal;
a second switching circuit including a third switching element and a fourth switching element connected between the first output node and the other of the output terminals of the boost circuit, and outputting a second pulse voltage obtained by superimposing the first pulse voltage as an offset on an output voltage of the boost circuit from a second output node which is a connection point between the third switching element and the fourth switching element;
a charge absorption circuit connected between output terminals of the boost circuit and having a variable resistance means;
a control unit for controlling the variable resistance means of the charge absorption circuit,
The control unit is
a controller for converting analog signals indicating the voltage and current of the charge absorption circuit into digital signals, and further converting the digital signals into optical signals, and outputting a control signal for controlling the variable resistance means;
a calculation control circuit that receives an optical signal output from the controller via an optical transmission line, converts it into a digital signal, performs a calculation based on the digital signal, converts the digital signal indicating the result of the calculation into an optical signal, and transmits it to the controller via the optical transmission line. The pulse power supply device according to claim 1, wherein the variable resistance means is a transistor, and the resistance value of the variable resistance means is variable by adjusting the control signal. the variable resistance means is configured by connecting a plurality of resistor series circuits, each of which is formed by connecting the transistor and a resistor in series, in parallel with each other;
3. The pulse power supply according to claim 2, wherein said controller comprises a pair of an AD converter and a DA converter corresponding to each of said plurality of resistor series circuits. a multiplier which multiplies a voltage across the charge absorbing circuit by a value of a current flowing through the variable resistance means and outputs the multiplied value;
a power consumption control means for changing a resistance value of the variable resistance means in accordance with a comparison result between the multiplied value and a set target value so that the multiplied value becomes the target value,
4. The pulse power supply according to claim 1, wherein said set target value is set so as to vary based on a voltage across said charge absorption circuit.

Images