JP7629065B2 - Receiving method and receiver - Google Patents

Description

The present invention relates to a receiver for receiving radio signals, and in particular to reception processing under the influence of interference.

Interference cancellers are known as a technology for improving reception quality by suppressing the effects of interference from other radio stations, etc. Patent Document 1 describes an OFDM signal transmission method in which, in an OFDM signal transmission system, an OFDM signal transmitter inserts a training signal consisting of no signal and a known pattern into a data signal at regular intervals, and an OFDM signal receiver uses the training signal contained in a received signal received by two receiving antennas to generate an interference canceller control signal for suppressing an interference signal in the received signal, suppresses the interference signal in the received signal based on the interference canceller control signal, and performs transmission path correction on the output based on the training signal (see abstract).

In addition, by improving the noise resistance of the receiver, it is also possible to improve resistance to interference from other systems. Non-Patent Document 1 describes a technology that improves noise resistance performance by repeating processing between differential demodulation processing and decoding processing corresponding to the convolutional coding when receiving a signal that has been differentially modulated and transmitted using convolutional coding.

JP 2007-288263 A International Publication No. 2016/162993 International Publication No. 2017/013767

P. Hoeher and J. Lodge, "Turbo DPSK":Iterative Differential PSK Demodulation and Channel Decoding, IEEE Transactions on Communications, Vol. 47, No. 6, pp.837-843, June 1999

There is a technology that improves the receiver's noise immunity by transmitting the same data multiple times to increase the possibility of successful demodulation on the receiving side, but Non-Patent Document 1 does not take into consideration its application to such systems that transmit the same data multiple times. Therefore, the primary objective of the invention disclosed in this application is to apply the technology described in Non-Patent Document 1 to a system that transmits the same data multiple times to improve noise immunity and interference resistance.

In addition, in the technology described in Patent Document 1, FFT (Fast Fourier Transform) is performed to demodulate the OFDM (Orthogonal Frequency Division Multiplex) signal before interference suppression, and it is necessary to identify the FFT timing (OFDM symbol boundary) using a preamble consisting of a known pattern. However, in a situation where the preamble is subject to strong interference, it becomes difficult to capture the preamble. Therefore, the second object of the invention disclosed in this application is to improve the interference resistance of both the preamble and the data portion.

A representative example of the invention disclosed in the present application is as follows. That is, a receiving method in which a receiver receives a radio signal transmitted n times from a transmitter, where n is an integer equal to or greater than 2, the receiver has a demodulator that performs demodulation processing on n sets of signals received corresponding to the radio signals transmitted n times, a decoder that collectively performs decoding processing on the demodulated n sets of demodulation results, a deinterleaver that performs deinterleaving processing to change the order of codes of the demodulated results by the demodulator, and an interleaver that performs interleaving processing to change the order of codes of the decoded results by the decoder, and the receiving method is characterized in that after the decoded results by the decoder are copied into n sets to be input to the demodulator, each of the n sets of demodulated results by the demodulator or each of the n sets of demodulated results by the demodulator that have been deinterleaved is subtracted from each of the copied n sets of signals.

According to one aspect of the present invention, communication is possible even in an environment where there is significant interference. Problems, configurations, and advantages other than those described above will become clear from the description of the following embodiment.

FIG. 2 is a diagram illustrating an interference suppression method for a preamble and a data signal in the first embodiment. FIG. 2 is a diagram illustrating a configuration of a receiver according to a first embodiment. FIG. 2 is a diagram illustrating a configuration of an interference canceller for a data signal in the first embodiment. FIG. 11 is a diagram illustrating the operation of an interference canceller for a preamble in the first embodiment. FIG. 2 is a diagram illustrating a configuration of an antenna selection unit in the first embodiment. FIG. 2 is a diagram illustrating a configuration of a demodulator/decoder according to the first embodiment. FIG. 11 is a diagram illustrating a configuration of a demodulator/decoder according to a second embodiment. FIG. 13 is a diagram illustrating a configuration of a demodulator/decoder according to a third embodiment. FIG. 1 is a diagram illustrating a configuration of a demodulator/decoder of a comparative example.

A representative example of the invention disclosed in the present application is as follows: That is, a receiving method in which a receiver receives a radio signal transmitted n times from a transmitter, where n is an integer equal to or greater than 2, the receiver has a demodulator that performs demodulation processing of n sets of signals received corresponding to the radio signals transmitted n times, a decoder that performs decoding processing on a collection of the demodulated n sets of demodulation results, a deinterleaver that performs deinterleaving processing to rearrange the order of codes of the demodulated results by the demodulator, and an interleaver that performs interleaving processing to rearrange the order of codes of the decoded results by the decoder, and the receiving method is characterized in that after the decoded results by the decoder are copied into n sets to be input to the demodulator, each of the n sets of demodulated results by the demodulator or each of the n sets of demodulated results by the demodulator that have been deinterleaved is subtracted from each of the copied n sets of signals.

Example 1
FIG. 1 shows an interference suppression method according to a first embodiment of the present invention. In the present invention, it is assumed that communication is performed in synchronization with a time slot. For example, as shown in the lower part of FIG. 1, transmission 106 and reception 107 are alternately repeated according to a specified time slot. In the reception time slot, the receiver measures interference in a no-signal section 100 immediately before the start of a preamble. The receiver suppresses interference in a preamble section 101 according to an interference suppression coefficient calculated by a preamble interference suppression coefficient calculation unit 104 using the measured interference. In an OFDM (Orthogonal Frequency Division Multiplex) data signal 102 transmitted following the preamble section 101, a plurality of no-signal symbols 103 are arranged. This method is disclosed in, for example, Patent Document 2. Next, interference is measured using the no-signal symbols 103. Then, interference in the OFDM data signal 102 is suppressed according to an interference suppression coefficient calculated by a data signal interference suppression coefficient calculation unit 105 using the interference measured in the OFDM data signal 102.

FIG. 2 shows the configuration of a receiver according to a first embodiment. In FIG. 2, components common to wireless communication devices, such as an RF (Radio Frequency) circuit, that are less relevant to the present invention, are omitted. Antennas 201 and 202 receive the same signal transmitted from a transmitter. In particular, in the embodiment of the present invention, the transmitter transmits the same signal multiple times. Also, the receiver receives signals with different propagation paths using multiple antennas. In the no-signal section 100 in FIG. 1, the signals received by antennas 201 and 202 are converted into frequency domain signals by overlapping FFTs (Fast Fourier Transforms) 203 and 204, respectively.

The operation of the overlap FFTs 203 and 204 will be described with reference to FIG. 4. The input signal is divided into predetermined sample intervals. For example, in FIG. 4, it is divided into intervals of N/2 samples. Two N/2 sample intervals are combined to form an N sample interval, which is multiplied by a first window function to perform FFT (Fast Fourier Transform) operation. At this time, the next N samples are overlapped by N/2 samples with the previous N samples using the signal N/2 samples behind. The next N samples are also subjected to FFT operation in the same way to convert them into frequency domain signals. Similarly, window function processing and FFT operation are performed sequentially while shifting by N/2 samples. The signals converted into frequency domain signals by the overlap FFTs 203 and 204 are input to the antenna selection unit 205.

The antenna selection unit 205 is configured, for example, as shown in FIG. 5. A power comparison unit 500 compares the signal power from multiple antennas (two in the figure), and selectors 501 and 502 select the signal so that the one with the larger average power is output from the top and the one with the smaller average power is output from the bottom.

Then, phase calculation unit 206 calculates the phase of the upper signal (the one with the larger average power) output from antenna selection unit 205. Then, phase rotation calculation units 207 and 208 rotate the phase of the signal output from antenna selection unit 205 in the opposite direction to the phase calculated by phase calculation unit 206. The phase-rotated signal is averaged over multiple nearby frequencies and multiple overlapping FFT intervals by average calculation units 209 and 210, and the average value is held over preamble interval 101. The held average value is multiplied by different outputs of antenna selection unit 205 by multipliers 211 and 212 in preamble interval 101, and one is subtracted from the other using adder 213.

In this way, the first interference suppression unit 231 that removes interference from the preamble signal is configured by the configuration from the overlap FFTs 203 and 204 to the adder 213, and a frequency domain preamble signal from which interference has been removed is obtained. The frequency domain preamble signal from which interference has been removed is converted into a time domain signal by the overlap IFFT (Inverse Fast Fourier Transform) 214. The operation of the overlap IFFT will be described with reference to FIG. 4. The frequency domain preamble signal from which interference has been removed is subjected to IFFT calculations for N samples at a time, and is converted into a time domain preamble signal from which interference has been removed for N samples. The time domain preamble signal from which interference has been removed for N samples is multiplied by a second window function to obtain an output of N samples. The output of the N samples is sequentially added to the output of the next N samples while shifting them by N/2 samples, and a continuous signal from which interference has been removed is obtained. The first window function and the second window function are functions that have small values at the start and end of N samples and large values in the center, and when the product of the first window function and the second window function are added sequentially while shifting them by N/2 samples, the product becomes a constant value. For example, if sin((i/N) * π) (i = 0 to N-1) is used as the first window function and the second window function, the product of the first window function and the second window function becomes sin2((i/N) * π) = (1 - cos(2 * (i/N) * π))/2, and when this is added while shifting it by N/2 samples, the product becomes 1, which satisfies the above condition.

Then, the preamble acquisition unit 215 detects the preamble of the interference-removed continuous-time domain preamble signal output from the overlap IFFT 214. The preamble acquisition unit 215 can adopt a conventional method of performing cross-correlation calculation using a matched filter, or performing auto-correlation calculation in the case of a preamble signal containing a repetition of the same pattern. Based on the timing of the preamble detected by the preamble acquisition unit 215, the FFT calculation units 216 and 217 perform FFT calculations on the OFDM data signals received by the antennas 201 and 202, respectively.

The data signal interference suppression coefficient calculation unit 105 calculates an interference suppression coefficient using the FFT calculation result. The calculated interference suppression coefficient is calculated with the FFT calculation result in the interference suppression weight application unit 218, and the interference is suppressed and output. The data signal interference suppression coefficient calculation unit 105 and the interference suppression weight application unit 218 form a second interference suppression unit 232 that removes interference from the data signal. The data signal interference suppression coefficient calculation unit 105 can be configured, for example, as shown in FIG. 3. The signal separation unit 300 separates the output of the FFT calculation units 216 and 217 into symbols that do not contain data signals (Null in FIG. 3), reference symbols (Reference in FIG. 3), and data symbols (Data in FIG. 3). The interference propagation path estimation unit 301 measures interference for symbols that do not contain data signals. The first interference suppression unit 302 performs interference suppression on symbols that do not contain data signals based on the measured interference. The calculation for interference suppression here can be the same as the interference suppression coefficient calculation method in the preamble interference suppression coefficient calculation unit 104 and the interference removal calculation in the multipliers 211, 212 and adder 213. Since only interference and noise are received in symbols that do not contain a data signal, only noise remains as a result of the interference suppression calculation. Therefore, the noise power can be estimated by measuring the power after the interference suppression calculation. The noise level can be estimated by the noise level estimation unit 304.

Similarly, the first interference suppression unit 303 performs an interference suppression calculation on the reference symbol. At this time, since the reference symbol is different from the symbol not including a data signal in at least one of time and frequency, it is necessary to estimate the interference propagation path for symbols other than the symbol not including a data signal by interpolation using a moving average calculation or the like in the interference propagation path estimation unit 301. The signal propagation path estimation unit 305 estimates the propagation path of the signal using at least one of the reference symbol output from the signal separation unit 300 and the reference symbol subjected to interference suppression processing. For example, when the interference of the received signal is small, it is preferable to estimate using the reference symbol output from the signal separation unit 300, and when the interference of the received signal is large, it is preferable to estimate using the reference symbol subjected to interference suppression processing. In addition, it is preferable to change the weighting coefficient of the reference symbol output from the signal separation unit 300 and the weighting coefficient of the reference symbol subjected to interference suppression processing depending on the magnitude of the interference of the received signal to estimate the propagation path.

The output I of the interference propagation path estimation unit 301, the output N of the noise level estimation unit 304, and the output S of the signal propagation path estimation unit 305 are interpolated in the time and frequency directions and output. These outputs I, N, and S are used as interference suppression coefficients in the interference suppression weight application unit 218 (306, 307) to suppress interference for symbols not including data signals, reference symbols, and data symbols. The calculations performed by the interference suppression weight application units 306 and 307 are preferably MMSE (Minimum Mean Square Error) processing. This processing can be realized by multiplying the signal propagation path estimation results by the interference suppression coefficient W n calculated using the following formulas (1) and (2), where S _n1 and S _n2 are the signal propagation path estimation results, Γ _n1 and Γ _n2 are the interference propagation path measurement results, and _σ ² are the noise level estimation results.

The interference suppression result of the symbol not including the data signal is input to the noise level estimation unit 308, which obtains a second noise level estimation result. In addition, the interference suppression result of the reference symbol and the data symbol is input to the demodulator 220 together with the second noise level estimation result, and the demodulation process is performed by the demodulator 220. The demodulation result output from the demodulator 220 is input to the decoder 221, which performs the decoding process.

In the first embodiment, a demodulation/decoding method is provided that reduces the effects of interference by improving noise resistance. In the first embodiment, a transmission method is assumed in which the same data is transmitted multiple times to improve the reliability of data transmission. In addition, in the first embodiment, the transmission signal is differentially modulated.

Figure 6 shows the configuration of the demodulation and decoding unit 219. In this embodiment, the transmitter transmits the same signal n times. In the receiver of the first embodiment, the received signals 1 to n are stored in the memories 600-1 to n, respectively. The differential signal demodulation units 601-1 to n demodulate the stored received signals 1 to n and output n sets of first LLRs (Log Likelihood Ratios). In FIG. 6, the signal line corresponding to the first LLR is labeled with a code (1), and similarly, codes are labeled up to the eighth LLR (8). As the differential signal demodulation units 601-1 to n, for example, a demodulator described in Patent Document 3 can be used. In addition, as another demodulator, a demodulator using the maximum likelihood sequence estimation (MLSE) method may be used. More generally, a demodulator can be used that references more than two surrounding received symbols and outputs the demodulation result.

The n sets of first LLRs are deinterleaved by deinterleavers 603-1 to 603-n, respectively, to rearrange the order of the codes in accordance with the interleaving employed on the transmitting side, and n sets of second LLRs are output. Then, adder 604 adds these n sets of second LLRs and outputs a third LLR. After that, decoder 221 decodes the third LLR and outputs a posteriori LLR (fourth LLR: a posteriori LLR). As decoder 221, a SISO (Soft Input Soft Output) decoder that receives LLRs as input and outputs posteriori LLRs can be used. This is, for example, a decoder that applies the BCJR algorithm.

This fourth LLR is replicated to n sets, and adders 606-1 to 606-n subtract the second LLR to output n sets of fifth LLRs. Interleavers 607-1 to 607-n perform interleaving on the n sets of fifth LLRs, respectively, to rearrange the order of the codes in the same manner as the interleaving employed on the transmitting side, and n sets of sixth LLRs are output. Differential signal demodulators 601-1 to 601-n use the n sets of sixth LLRs input as a priori LLRs to demodulate received signals 1 to n stored in memories 600-1 to 600-n again, and output n sets of seventh LLRs.

Adders 602-1 to 602-n subtract the n sets of sixth LLRs from the n sets of seventh LLRs, respectively, and output the n sets of eighth LLRs. The n sets of eighth LLRs are again deinterleaved by deinterleavers 603-1 to 603-n, and updated second LLRs are output.

Then, the second to eighth LLRs are updated sequentially by repeating the above-mentioned process. After a predetermined number of repetitions, the soft-decision decoding result output from the decoder 221 is subjected to a hard decision to obtain the decoding result.

In this embodiment, the posterior LLR (fourth LLR: a posteriori LLR) output from the decoder 221 includes the LLR of the data bit obtained from all n differential signal demodulation units 601-1 to n and the LLRs of the bits before and after it. Therefore, in the subtraction process in the adders 606-1 to n, the extrinsic LLR is calculated by subtracting the second LLR, which includes the influence of the LLR provided from the differential signal demodulation units 601-1 to n, from the fourth LLR. This makes it possible to calculate a prior LLR (sixth LLR: a priori LLR) provided to the differential signal demodulation unit 601-1 to 601-n that does not include the LLR of the bit output by itself, but includes the LLR of the bit output by the other differential signal demodulation units 601-1 to 601-n and the LLR of other bits output by itself.

Similarly, the seventh LLR, which is the result of the differential signal demodulation process, includes the influence of the a priori LLR (sixth LLR: a priori LLR) of the bit in question and the bits before and after it. For this reason, the subtraction process in adders 602-1 to 602-n calculates the extrinsic LLR by subtracting the a priori LLR (sixth LLR: a priori LLR) of the bit in question from the seventh LLR.

In addition, in FIG. 6, the differential signal demodulation units 601-1 to 601-n are shown in parallel, but one differential signal demodulation unit may be used n times to perform n sets of demodulation processing.

As described above, according to the first embodiment, in a wireless communication device that communicates using a signal consisting of a preamble signal 101 and an OFDM-modulated data signal 102, the signal is received using multiple antennas, interference is suppressed based on the interference measured in the no-signal section 100 before the start of the preamble, and timing synchronization is performed using the preamble (synchronization signal) after interference suppression, and after timing synchronization, interference is suppressed based on the interference measured using the no-signal section 103 arranged in the OFDM signal (data section 102). This makes it possible to communicate even in an environment where there is significant interference. In particular, communication is possible even in an environment where there is interference greater than the signal.

According to the demodulation and decoding unit 219 of the first embodiment, in a communication method in which the same data is transmitted multiple times, both the characteristic improvement by the repeated demodulation and decoding and the characteristic improvement by the synthesis of multiple data can be enjoyed, and demodulation and decoding with improved noise resistance performance is possible. For example, compared to a comparative example without repeated demodulation and decoding (see FIG. 9), interference resistance performance is improved by 6 dB at a packet error rate (PER) of ^10-2 . In other words, interference of about four times the power can be tolerated.

In addition, when the number of identical data transmitted from the transmitter (number of consecutive transmissions) is set to 5, the interference resistance performance is improved by 12 dB compared to the configuration shown in Figure 3 of Non-Patent Document 1. In other words, it can withstand interference of approximately 16 times the power.

Example 2
Next, a second embodiment of the present invention will be described. In the second embodiment, differences from the first embodiment will be mainly described, and the same functions and processes as those in the first embodiment will be denoted by the same reference numerals, and descriptions thereof will be omitted.

Figure 7 shows the configuration of the demodulation/decoding unit 219 of the second embodiment of the present invention. In the second embodiment, the positions of the adders 606-1 to 606-n are different from those of the first embodiment. In the demodulation/decoding unit 219 of the first embodiment, the second LLR is subtracted (606-1 to 606-n) before interleaving (607-1 to 607-n), but in the second embodiment, the eleventh or eighteenth LLR is subtracted (606-1 to 606-n) after interleaving (607-1 to 607-n). The operation of the demodulation/decoding unit 219 of the second embodiment is the same as that of the first embodiment, except for the different order of processing.

The demodulation/decoding unit 219 of the second embodiment can perform equivalent demodulation/decoding processing with a different configuration from that of the first embodiment.

Example 3
Next, a third embodiment of the present invention will be described. In the third embodiment, differences from the first embodiment will be mainly described, and the same functions and processes as those in the first embodiment will be denoted by the same reference numerals, and descriptions thereof will be omitted.

Figure 8 shows a third embodiment of the present invention. The configuration of the third embodiment can be adopted when the interleaving of signals transmitted multiple times is the same, and the deinterleaver and interleaver for each signal are shared, making it possible to reduce the circuit scale compared to the first and second embodiments. In Figure 8, the signal line corresponding to the 21st LLR is labeled with the symbol (21), and similar symbols are used up to the 28th LLR (28).

In the third embodiment, the operations of the memories 600-1 to 600-n and the differential signal demodulation units 601-1 to 601-n are the same as those in the first embodiment. The adder 604 adds the n sets of 21st LLRs output from the differential signal demodulation units 601-1 to 601-n, and outputs a 22nd LLR. The deinterleaver 603 deinterleaves the 22nd LLR, and outputs a 23rd LLR. The decoder 221 decodes the 23rd LLR, and outputs a posteriori LLR (24th LLR: a posteriori LLR).

The interleaver 607 interleaves the 24th LLR and outputs the 25th LLR. The 25th LLR is duplicated into n sets. Each of the adders 606-1 to 606-n subtracts the 21st LLR from the duplicated 25th LLR and outputs the 26th LLR. The differential signal demodulators 601-1 to 601-n use the 26th LLR as a priori LLR to demodulate the received signals 1 to n stored in the memories 600-1 to 600-n again and output n sets of the 27th LLR.

Adders 602-1 to 602-n subtract the 26th LLR of set n from the 27th LLR of set n, respectively, and output the 28th LLR of set n. The 28th LLR of set n is added again by adder 604, and the updated 22nd LLR is output.

Then, the 22nd to 28th LLRs are updated sequentially by repeating the above-mentioned process. Note that in the second and subsequent repetitions, adders 606-1 to 606-n subtract the 28th LLR instead of the 21st LLR. After a predetermined number of repetitions, the soft-decision decoding result output from decoder 221 is subjected to a hard decision to obtain the decoding result.

The demodulation/decoding unit 219 of the third embodiment can achieve the same noise resistance characteristics with a smaller circuit scale than the first and second embodiments.

As described above, the receiver of the embodiment of the present invention receives a radio signal transmitted multiple times from a transmitter, and includes an antenna (e.g., multiple antennas 201, 202) for receiving the radio signal, multiple demodulators 601 for demodulating each of the signals received by the multiple antennas 201, 202, a decoder 221 for decoding the signals demodulated by the multiple demodulators 601, a deinterleaver 603 for performing a deinterleaving process to rearrange the order of the codes in the output of the demodulator 220, an interleaver 607 for performing an interleaving process to rearrange the order of the codes in the output of the decoder 221, and multiple first adders 606 for subtracting the output of the demodulator 601 or the deinterleaved output of the demodulator 601 after the output of the decoder 221 is duplicated to be input to each of the multiple demodulators 601, thereby improving interference resistance performance and enabling communication even in an environment where large interference is present.

In addition, the output of the decoder 221 is interleaved and input to the demodulator 601, which performs demodulation processing using the interleaved decoder output, and the output of the demodulator 601 is deinterleaved and input to the decoder 221. The loop between the demodulator 601 and the decoder 221 is repeated a predetermined number of times to perform demodulation and decoding processing, improving interference resistance and enabling communication even in an environment where there is significant interference.

In addition, the demodulator 601 outputs the demodulation result by referring to more than two surrounding received symbols, so it is possible to obtain a demodulation result that is the most likely estimate.

In addition, each of the multiple demodulators 601 outputs a first LLR (1) as a result of the demodulation process, each of the multiple deinterleavers 603 performs deinterleaving on the first LLR to output a second LLR (2), the decoder 221 performs soft decision decoding using a third LLR (3) obtained by combining the multiple second LLRs, and outputs a fourth LLR (4) which is a post-decoding LLR from the soft decision decoding result, and the fourth LLR is distributed to the number of the multiple demodulators, the first adder 606 subtracts the second LLR from the distributed fourth LLR to output a fifth LLR (5), and the interleaver 607 performs interleaving on the fifth LLR to output the fourth LLR (6). The demodulator 601 uses the sixth LLR as a preliminary LLR to perform demodulation processing again and outputs a seventh LLR (7). The second adder 602 subtracts the sixth LLR from the seventh LLR to output an eighth LLR (8). Each of the multiple deinterleavers 603 performs deinterleaving processing on the eighth LLR again and outputs a second LLR (2). The process of calculating the second to eighth LLRs is repeated a predetermined number of times. After the predetermined number of repetitions, the decoder 221 performs hard decision on the soft decision decoding result and outputs the decoding result. This improves interference resistance and enables communication even in an environment where there is large interference.

In addition, each of the multiple demodulators 601 outputs an eleventh LLR (11) as a result of the demodulation process, each of the multiple deinterleavers 603 performs deinterleaving on the eleventh LLR to output a twelfth LLR (12), the decoder 221 performs soft decision decoding using a thirteenth LLR (13) obtained by combining the multiple twelfth LLRs, and outputs a fourteenth LLR (14) which is a post-LLR from the soft decision decoding result, and the fourteenth LLR is distributed to the number of the multiple demodulators, the interleaver 607 performs interleaving on the distributed fourteenth LLR to output a fifteenth LLR (15), and the first adder 606 subtracts the eleventh LLR from the fifteenth LLR, The demodulator 601 uses the sixteenth LLR as a preliminary LLR to perform demodulation processing again and outputs the seventeenth LLR (17). The second adder 602 subtracts the sixteenth LLR from the seventeenth LLR to output the eighteenth LLR (18). Each of the multiple deinterleavers 603 performs deinterleaving processing on the eighteenth LLR again and outputs the twelfth LLR (12). The process of calculating the twelfth to eighteenth LLRs is repeated a predetermined number of times. After the predetermined number of repetitions, the decoder 221 performs hard decision on the soft decision decoding result and outputs the decoding result. This improves interference resistance and enables communication even in an environment where there is large interference.

Furthermore, each of the multiple demodulators 601 outputs a twenty-first LLR (21) as a result of the demodulation process, the deinterleaver 603 performs deinterleaving on a twenty-second LLR (22) obtained by combining the multiple twenty-first LLRs, and outputs a twenty-third LLR (23), the decoder 221 performs soft decision decoding using the twenty-third LLR, and outputs a twenty-fourth LLR (24) which is an ex-post LLR from the soft decision decoding result, the interleaver 607 performs interleaving on the twenty-fourth LLR, and outputs a twenty-fifth LLR (25), which is distributed to the number of the multiple demodulators 601, the first adder 606 subtracts the twenty-first LLR from the distributed twenty-fifth LLR, and outputs a twenty-sixth LLR (26), and the demodulator 60
The first adder 601 performs demodulation processing again using the 26th LLR as the pre-LLR to output the 27th LLR (27), the second adder 602 subtracts the 26th LLR from the 27th LLR to output the 28th LLR (28), the deinterleaver 603 performs deinterleaving processing again on the 28th LLR to output the 22nd LLR (22), and repeats the process of calculating the 22nd to 28th LLRs a predetermined number of times, and the decoder 221, after the predetermined number of repetitions, performs hard decision on the soft decision decoding result and outputs the decoding result, so that interference resistance performance can be improved with a small circuit scale and communication is possible even in an environment where large interference is present.

Among the inventions disclosed in this specification, the following are representative aspects other than those described in the claims.

(1) A receiver for receiving a radio signal including a preamble signal and an OFDM modulated data signal, comprising:
A plurality of antennas for receiving the radio signals;
a first interference suppression unit that measures interference in a non-signal section before the preamble signal, calculates a first interference suppression coefficient based on the interference measurement result, and performs first interference suppression using the calculated first interference suppression coefficient.

(2) A receiver for receiving a radio signal including a preamble signal and an OFDM modulated data signal, comprising:
A plurality of antennas for receiving the radio signals;
a second interference suppression unit that measures interference in a non-signal portion located in the data signal after timing synchronization using the preamble signal, calculates a second interference suppression coefficient based on the interference measurement result, and performs second interference suppression using the calculated second interference suppression coefficient.

(3) A receiver for receiving a radio signal including a preamble signal and a data signal,
an antenna for receiving the radio signal;
a first interference suppression unit that measures interference in a non-signal section before the preamble signal and performs first interference suppression based on the interference measurement result;
a second interference suppression unit that measures interference in a non-signal portion located in the data signal after timing synchronization using the preamble signal on which the first interference suppression has been performed, and performs second interference suppression based on the interference measurement result.

(4) an FFT calculation unit that multiplies a time domain signal by a first window function to convert the time domain signal into a frequency domain signal;
an IFFT calculation unit that multiplies the frequency domain signal by a second window function to convert it into a time domain signal;
The first interference suppression unit performs the first interference suppression on the signal converted into the frequency domain signal by the FFT calculation unit,
The receiver according to any one of the preceding claims, characterized in that the product of the first window function and the second window function, shifted by a predetermined number of samples and added together, becomes a constant value.

(5) The antenna is a plurality of antennas including at least a first antenna and a second antenna,
The first interference suppression unit,
a phase calculation unit that calculates a phase of an interference wave in a no-signal section received by the first antenna;
a first phase rotation calculation unit that rotates the signal received by the first antenna in a direction opposite to the calculated phase;
a second phase rotation calculation unit that rotates the signal received by the second antenna in a direction opposite to the calculated phase;
a first multiplier that multiplies a signal received by the first antenna by a signal whose phase has been rotated by the second phase rotation calculation unit;
a second multiplier that multiplies the signal received by the second antenna by the signal whose phase has been rotated by the first phase rotation calculation unit;
4. A receiver as described in any preceding claim, further comprising an adder for calculating the difference between the output of the first multiplier and the output of the second multiplier.

(6) The second interference suppression unit includes a signal separation unit that extracts a reference symbol from an input signal, and a propagation path estimation unit that estimates a propagation path of the signal,
The channel estimation unit is
A propagation path is estimated by using at least one of a first reference symbol output from the signal separation unit and a second reference symbol obtained by performing interference suppression on the first reference symbol in the first interference suppression unit,
4. A receiver as described in any of the preceding claims, characterized in that a propagation path is estimated by changing weights of the first reference symbol and the second reference symbol depending on the level of interference of the received signal.

(7) A receiver for receiving a radio signal transmitted multiple times from a transmitter,
an antenna for receiving the radio signal;
a plurality of demodulators for demodulating respective signals received by said antennas;
a decoder for decoding signals demodulated by the plurality of demodulators;
a deinterleaver for performing a deinterleaving process for changing the order of the codes of the output of the demodulator;
an interleaver that performs an interleaving process to change the order of the codes output from the decoder;
and a plurality of first adders for subtracting the output of the demodulator or the deinterleaved demodulator output after the output of the decoder is replicated for input to each of the plurality of demodulators.

(8) A receiving method in which a receiver receives a radio signal transmitted multiple times from a transmitter, comprising the steps of:
The receiver includes:
an antenna for receiving a signal;
a plurality of demodulators for demodulating respective signals received by said antennas;
a decoder for decoding signals demodulated by the plurality of demodulators;
a deinterleaver for performing a deinterleaving process for changing the order of the codes of the output of the demodulator;
an interleaver for performing an interleaving process for changing the order of the codes output from the decoder;
The receiving method includes:
13. A method of receiving a digital signal comprising: subtracting an output of said demodulator or an output of said deinterleaved demodulator after said decoder output has been replicated for input to each of said plurality of demodulators.

The present invention is not limited to the above-described embodiments, but includes various modified examples and equivalent configurations within the spirit of the appended claims. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to having all of the configurations described. Furthermore, part of the configuration of one embodiment may be replaced with the configuration of another embodiment. Furthermore, the configuration of another embodiment may be added to the configuration of one embodiment. Furthermore, part of the configuration of each embodiment may be added, deleted, or replaced with other configurations.

Furthermore, each of the configurations, functions, processing units, processing means, etc. described above may be realized in part or in whole in hardware, for example by designing them as integrated circuits, or may be realized in software by a processor interpreting and executing a program that realizes each function.

Information such as programs, tables, and files that realize each function can be stored in a storage device such as a memory, hard disk, or SSD (Solid State Drive), or in a recording medium such as an IC card, SD card, or DVD.

In addition, the control lines and information lines shown are those considered necessary for explanation, and do not necessarily represent all control lines and information lines necessary for implementation. In reality, it is safe to assume that almost all components are interconnected.

100: No signal section 101: Preamble 102: OFDM data signal 103: No signal OFDM symbol 104: Preamble interference suppression coefficient calculation unit 105: Data signal interference suppression coefficient calculation unit 106: Transmission signal 107: Received signal 201, 202: Antennas 203, 204: Overlap FFT
205: Antenna selection unit 206: Phase calculation unit 207, 208: Phase rotation calculation unit 209, 210: Average calculation unit 211, 212: Multiplier 213: Adder 214: Overlap IFFT
215: Preamble acquisition unit 216, 217: FFT calculation unit 218: Interference suppression weight application unit 219: Demodulation and decoding unit 220: Demodulator 221: Decoder 300: Signal separation unit 301: Interference propagation path estimation unit 302, 303: First interference suppression unit 304, 308: Noise level estimation unit 305: Signal propagation path estimation unit 306, 307: Interference suppression weight application unit 500: Power comparison unit 501, 502: Selectors 600-1 to n: Memories 601-1 to n: Differential signal demodulation units 602-1 to n, 604, 606-1 to n: Adders 603-1 to n, 603: Deinterleavers 607-1 to n, 607: Interleaver

Claims (12)

A receiving method in which a receiver receives a radio signal transmitted from a transmitter a number of times, n being an integer equal to or greater than 2, comprising the steps of:
The receiver includes:
a demodulator for performing demodulation processing of n sets of received signals corresponding to the n transmitted wireless signals;
a decoder for performing a decoding process on the n sets of demodulated results;
a deinterleaver that performs a deinterleaving process to rearrange the order of the codes obtained by the demodulator;
an interleaver that performs an interleaving process to change the order of the codes of the decoded result by the decoder;
The receiving method includes:
A receiving method characterized in that after the decoding results by the decoder are replicated into n sets to be input to the demodulator, each of the n sets of demodulation results by the demodulator or each of the n sets of demodulation results by the demodulator that have been deinterleaved is subtracted from each of the n sets of replicated signals. 2. The receiving method according to claim 1,
The decoded signal is subjected to the interleaving process as an input to the demodulation process;
In the demodulation process, a demodulation process is performed using the interleaved signal;
The demodulated signal is deinterleaved and used as an input for the decoding process;
A receiving method, comprising repeating a loop between the demodulation process and the decoding process a predetermined number of times to execute the demodulation and decoding processes. 2. The receiving method according to claim 1,
A receiving method according to claim 1, wherein the demodulator outputs a demodulated result by referring to more than two neighboring received symbols. 2. The receiving method according to claim 1,
The receiver includes:
The subtraction of the demodulator output or the deinterleaved demodulator output is performed by subtracting each of the n sets of second LLRs, which are the deinterleaved demodulator output, from a fourth LLR, which is the decoder output, and includes a first adder that performs the subtraction;
a second adder for subtracting the interleaved decoder output from the n sets of demodulator outputs;
The receiving method includes:
the demodulator outputs n sets of first LLRs as a result of the demodulation process;
the deinterleaver performs a deinterleaving process on the first LLR in the first iteration and on the eighth LLR in the second or subsequent iterations to output the n sets of second LLRs;
the decoder performs soft-decision decoding using a third LLR obtained by combining the n sets of the second LLRs, and outputs the fourth LLR, which is an a posteriori LLR, from a result of the soft-decision decoding;
the fourth LLR is distributed to the n LLRs;
the first adder subtracts each of the second LLRs from each of the distributed n sets of fourth LLRs to output n sets of fifth LLRs;
the interleaver performs interleaving on each of the n sets of fifth LLRs to output n sets of sixth LLRs;
the demodulator performs the demodulation process again using the n sets of sixth LLRs as pre-LLRs to output n sets of seventh LLRs;
the second adder subtracts each of the n sets of sixth LLRs from each of the n sets of seventh LLRs to output the n sets of eighth LLRs;
The deinterleaver performs a deinterleaving process on the eighth LLR of the n sets again to output a second LLR of the n sets for the second or subsequent iterations;
repeating the process of calculating the second LLR to the eighth LLR a predetermined number of times;
a decoder, after the predetermined number of iterations, making a hard decision on a result of the soft-decision decoding and outputting a decoded result. 2. The receiving method according to claim 1,
The receiver includes:
The subtraction of the demodulator output or the deinterleaved demodulator output is performed by subtracting the n set of eleventh LLRs, which are the outputs of the demodulator, from the n set of fourteenth LLRs, which are the outputs of the interleaved decoder, in the first iteration, and subtracting the n set of eighteenth LLRs, which are the outputs of the demodulator, in the second iteration and thereafter, and includes a first adder that performs the subtraction;
a second adder for subtracting the interleaved decoder output from the n sets of demodulator outputs;
The receiving method includes:
the demodulator outputs the n sets of eleventh LLRs as a result of a demodulation process;
The deinterleaver performs a deinterleaving process on the eleventh LLR of the n set in the first repetition, and performs a deinterleaving process on the eighteenth LLR of the n set in the second or subsequent repetition, and outputs a twelfth LLR of the n set;
the decoder performs soft-decision decoding using a thirteenth LLR obtained by combining the n sets of twelfth LLRs, and outputs the fourteenth LLR, which is an a posteriori LLR, from a result of the soft-decision decoding;
the fourteenth LLR is distributed among the n LLRs;
The interleaver performs an interleaving process on the distributed n sets of fourteenth LLRs to output n sets of fifteenth LLRs;
the first adder subtracts each of the n sets of eleventh LLRs from each of the n sets of fifteenth LLRs to output n sets of sixteenth LLRs;
the demodulator performs the demodulation process again using the n sets of sixteenth LLRs as pre-LLRs to output n sets of seventeenth LLRs;
the second adder subtracts the sixteenth LLR of the n sets from the seventeenth LLR of the n sets to output an eighteenth LLR of the n sets;
The deinterleaver performs a deinterleaving process on the eighteenth LLR of the n sets again to output a twelfth LLR of the n sets for the second or subsequent iterations;
repeating the process of calculating the twelfth LLR to the eighteenth LLR a predetermined number of times;
a decoder, after the predetermined number of iterations, making a hard decision on a result of the soft-decision decoding and outputting a decoded result. 2. The receiving method according to claim 1,
The receiver includes:
The subtraction of the demodulator output or the deinterleaved demodulator output includes a first adder that subtracts the n-th set of the 21st LLR, which is the output of the demodulator, from the 24th LLR, which is the output of the interleaved decoder, in the first iteration, and subtracts the n-th set of the 28th LLR, which is the output of the demodulator, from the 24th LLR, which is the output of the interleaved decoder, in the second iteration and thereafter;
a second adder for subtracting the interleaved decoder output from the n sets of demodulator outputs, said second adder performing said subtraction;
The receiving method includes:
the demodulator outputs the n sets of twenty-first LLRs as a result of a demodulation process;
the deinterleaver performs a deinterleaving process on the 21st LLR of the nth set in the first repetition, and on the 22nd LLR obtained by combining the 28th LLR of the nth set in the second or subsequent repetition, to output a 23rd LLR;
the decoder performs soft-decision decoding using the twenty-third LLR, and outputs the twenty-fourth LLR, which is an a posteriori LLR, from a result of the soft-decision decoding;
the interleaver performs interleaving on the twenty-fourth LLR to output a twenty-fifth LLR;
The twenty-fifth LLR is distributed into n pieces;
the first adder subtracts each of the n sets of twenty-first LLRs from each of the n sets of twenty-fifth LLRs distributed to output n sets of twenty-sixth LLRs;
the demodulator performs the demodulation process again using the n sets of twenty-sixth LLRs as prior LLRs to output n sets of twenty-seventh LLRs;
the second adder subtracts each of the n sets of 26 LLRs from each of the n sets of 27 LLRs to output a 28th LLR of the n sets;
The deinterleaver performs a deinterleaving process on the 22nd LLR again to output the 23rd LLR for the second or subsequent iterations;
repeating the process of calculating the 22nd LLR to the 28th LLR a predetermined number of times;
a decoder, after the predetermined number of iterations, making a hard decision on a result of the soft-decision decoding and outputting a decoded result. A receiver for receiving a radio signal transmitted from a transmitter n times, where n is an integer equal to or greater than 2,
a demodulator for demodulating n sets of received signals corresponding to the n transmitted wireless signals;
a decoder for collectively decoding the n sets of demodulated results;
a deinterleaver that performs a deinterleaving process to rearrange the order of the codes obtained by the demodulator;
an interleaver that performs an interleaving process to rearrange the order of the codes decoded by the decoder;
a first adder that subtracts each of the n sets of demodulation results by the demodulator or each of the n sets of demodulation results by the demodulator that have been deinterleaved from each of the n sets of replicated signals after the decoding results by the decoder are replicated into n sets to be input to the demodulator. 8. The receiver of claim 7,
The output of the decoder is interleaved and input to the demodulator;
The demodulator performs a demodulation process using the interleaved output of the decoder;
The output of the demodulator is deinterleaved and input to the decoder;
A receiver, comprising: a receiver circuit for repeating a loop between said demodulator and said decoder a predetermined number of times to perform demodulation and decoding processes. 8. The receiver of claim 7,
4. A receiver according to claim 3, wherein said demodulator outputs a demodulated result by referring to more than two neighboring received symbols. 8. The receiver of claim 7,
a second adder for subtracting the interleaved decoder output from the n sets of demodulator outputs;
the demodulator outputs n sets of first LLRs as a result of the demodulation process;
Each of the plurality of deinterleavers performs a deinterleaving process on the first LLR of the n sets in the first repetition, and performs a deinterleaving process on the eighth LLR of the n sets in the second or subsequent repetition, and outputs a second LLR of the n sets;
the decoder performs soft-decision decoding using a third LLR obtained by combining the n sets of second LLRs, and outputs a fourth LLR that is an a posteriori LLR from a result of the soft-decision decoding;
the fourth LLR is distributed to the n LLRs;
The first adder for subtracting the demodulator output or the deinterleaved demodulator output subtracts each of the n sets of second LLRs, which are the output of the deinterleaved demodulator, from each of the n sets of distributed fourth LLRs, which are the signal after the output of the decoder is replicated to the n pieces to be input to the demodulator, and outputs n sets of fifth LLRs, which are the result of the subtraction;
the interleaver performs an interleaving process on the n sets of fifth LLRs to output n sets of sixth LLRs;
the demodulator performs the demodulation process again using the n sets of sixth LLRs as pre-LLRs to output n sets of seventh LLRs;
the second adder subtracts each of the n sets of sixth LLRs from each of the n sets of seventh LLRs to output the n sets of eighth LLRs;
The deinterleaver performs a deinterleaving process on the eighth LLR of the n sets again to output a second LLR of the n sets for the second or subsequent iterations;
repeating the process of calculating the second LLR to the eighth LLR a predetermined number of times;
The receiver according to claim 1, wherein the decoder performs a hard decision on a result of the soft decision decoding after the predetermined number of iterations, and outputs a decoded result. 8. The receiver of claim 7,
a second adder for subtracting the interleaved decoder output from the n sets of demodulator outputs;
the demodulator outputs n sets of eleventh LLRs as a result of the demodulation process;
The deinterleaver performs a deinterleaving process on the eleventh LLR of the n set in the first repetition and on the eighteenth LLR of the n set in the second repetition, and outputs a twelfth LLR of the n set;
the decoder performs soft decision decoding using a thirteenth LLR obtained by combining the n sets of twelfth LLRs, and outputs a fourteenth LLR that is an a posteriori LLR from a result of the soft decision decoding;
the fourteenth LLR is distributed among the n LLRs;
The interleaver performs an interleaving process on the distributed n sets of fourteenth LLRs to output n sets of fifteenth LLRs;
The first adder, which subtracts the output of the demodulator or the deinterleaved demodulator output, subtracts each of the eleventh LLR of the n set, which is the output of the demodulator, from each of the fifteenth LLR of the n set, which is a signal obtained by interleaving a signal obtained by replicating the output of the decoder into the n pieces so that the output of the decoder is input to the demodulator, in the first repetition, and subtracts each of the eighteenth LLR of the n set, which is the output of the demodulator, in the second repetition and thereafter, and the first adder outputs a sixteenth LLR of the n set, which is the result of the subtraction;
the demodulator performs the demodulation process again using the n sets of sixteenth LLRs as pre-LLRs to output n sets of seventeenth LLRs;
the second adder subtracts each of the n sets of sixteenth LLRs from each of the n sets of seventeenth LLRs to output the n sets of eighteenth LLRs;
The deinterleaver performs a deinterleaving process again on the eighteenth LLR of the nth set to output a twelfth LLR of the nth set for the second or subsequent repetitions;
repeating the process of calculating the twelfth LLR to the eighteenth LLR a predetermined number of times;
The receiver according to claim 1, wherein the decoder performs a hard decision on a result of the soft decision decoding after the predetermined number of iterations, and outputs a decoded result. 8. The receiver of claim 7,
a second adder for subtracting the interleaved decoder output from the n sets of demodulator outputs;
the demodulator outputs n sets of twenty-first LLRs as a result of the demodulation process;
The deinterleaver performs a deinterleaving process on the 21st LLR of the nth set in the first repetition, and performs a deinterleaving process on the 22nd LLR obtained by combining the 28th LLR of the nth set in the second or subsequent repetition, and outputs a 23rd LLR;
the decoder performs soft decision decoding using the twenty-third LLR, and outputs a twenty-fourth LLR, which is an a posteriori LLR, from a result of the soft decision decoding;
the interleaver performs an interleaving process on the twenty-fourth LLR to output a twenty-fifth LLR;
the twenty-fifth LLR is distributed among the n LLRs;
The first adder, which subtracts the demodulator output or the deinterleaved demodulator output, subtracts each of the n sets of 21st LLRs, which are the output of the demodulator, from each of the n sets of 25th LLRs, which are signals obtained after the signal obtained by interleaving the output of the decoder is replicated to the n pieces so as to be input to the demodulator, in the first repetition, and subtracts each of the n sets of 28th LLRs from the second repetition onward, and the first adder outputs the n sets of 26th LLRs, which are the result of the subtraction;
the demodulator performs the demodulation process again using the n sets of twenty-sixth LLRs as pre-LLRs to output n sets of twenty-seventh LLRs;
the second adder subtracts each of the n sets of 26 LLRs from each of the n sets of 27 LLRs to output a 28th LLR of the n sets;
the deinterleaver performs a deinterleaving process on the twenty-second LLR again to output the twenty-third LLR for the second or subsequent iterations;
repeating the process of calculating the 22nd LLR to the 28th LLR a predetermined number of times;
The receiver according to claim 1, wherein the decoder performs a hard decision on a result of the soft decision decoding after the predetermined number of iterations, and outputs a decoded result.

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