JP7629154B2 - Silicon epitaxial wafer manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a silicon epitaxial wafer.

Currently, silicon wafers used for semiconductor devices are mainly those with a {100} surface. However, attention has recently been focused on silicon wafers with a {110} surface, which has better hole mobility. Silicon wafers with a {110} surface have high carrier mobility, and are known to be able to increase the speed of pMOS transistors. On the other hand, epitaxial wafers have very few surface defects, so they are used for high-performance devices. For this reason, silicon epitaxial wafers with a {110} surface are expected to be used as a material for high-performance devices such as MPUs.

However, silicon epitaxial wafers with a {110} surface have a problem in that the surface quality, such as haze and surface roughness, is significantly worse than that of silicon wafers with a {100} surface. In addition, the worsening haze increases the background noise on the silicon wafer surface using a particle counter, making it difficult to measure LPDs (light point defects), and there are occasional cases where quality assurance of foreign matter, scratches, etc. on the silicon wafer surface cannot be achieved. Furthermore, there is a concern that the roughness (irregularities) of the silicon wafer surface may reduce carrier mobility during device fabrication.

As a countermeasure to these problems, it is known to reduce the haze level by growing homoepitaxially on a silicon single crystal substrate having off-angles tilted in various axial directions (Patent Documents 1-8). In addition, a method has been proposed in which the substrate is doped with a high concentration of carriers to reduce LPDs and haze. However, these methods still result in a level of surface haze that cannot be said to be sufficient.

In addition, there have been proposals to improve surface roughness by polishing away the irregularities that occur on the surface of the silicon epitaxial layer, but this has drawbacks such as the occurrence of PID (Polish-Induced Defects), deterioration of the layer thickness uniformity, and reduced productivity and increased costs due to the addition of additional processes.

JP 2001-253797 A JP 2007-070131 A JP 2008-091887 A JP 2010-001210 A JP 2020-107729 A JP 2020-107730 A JP 2012-043892 A JP 2011-243845 A

The present invention has been made to solve the above problems, and aims to provide a method for efficiently manufacturing high-quality silicon epitaxial wafers by improving haze (surface roughness) by devising epitaxial process conditions for vapor-phase growth of an epitaxial layer on the main surface of a silicon single crystal wafer whose main surface is a {110} plane or a plane inclined by an off-angle from the {110} plane.

In order to achieve the above object, the present invention provides a method for producing a silicon epitaxial wafer, comprising vapor-phase growing an epitaxial layer on a main surface of a silicon single crystal wafer, the main surface of the main surface being a {110} plane or a plane inclined by an off angle from the {110} plane, the method comprising the steps of:
When the epitaxial layer is grown in a vapor phase,
The temperature of the silicon single crystal wafer is set to 1095 to 1115° C., and the growth rate of the epitaxial layer is set to 0.5 to 1.5 μm/min, or
The present invention provides a method for producing a silicon epitaxial wafer, characterized in that the temperature of the silicon single crystal wafer is set to 1135 to 1155° C. and the growth rate of the epitaxial layer is set to 3.0 to 4.0 μm/min.

The method for producing silicon epitaxial wafers of the present invention can efficiently and productively produce silicon epitaxial wafers with reduced haze levels on the main surface of the {110} plane or a surface inclined by an off angle from the {110} plane (hereinafter, these surfaces are collectively referred to as approximately {110} planes). This makes it possible to provide high-quality silicon epitaxial wafers with good carrier mobility compared to silicon epitaxial wafers with a main surface of the {100} plane, for example, with a high yield. In addition, an increase in background noise on the main surface of the wafer is suppressed, making it possible to guarantee the quality of the wafer without any problems. In addition, it is simple and advantageous in terms of cost, as it only requires adjustment of the temperature and growth rate during epitaxial growth.

In this case, the silicon single crystal wafer may be a wafer whose main surface has an off-angle of more than 0 degrees and less than 0.5 degrees from the {110} plane.

In this way, it is possible to obtain a wafer with a lower haze level while suppressing the decrease in carrier mobility compared to when using a wafer with a {110} surface as the main surface.

The method for producing a silicon epitaxial wafer of the present invention allows for highly productive production of high-quality silicon epitaxial wafers in which an epitaxial layer is vapor-grown on the main surface of a silicon single crystal wafer whose main surface is a {110} plane or a plane tilted by an off-angle from the {110} plane, and which have high carrier mobility and reduced haze levels.

FIG. 1 is a flow diagram showing an example of a method for producing a silicon epitaxial wafer according to the present invention. FIG. 1 is a schematic diagram showing an example of the configuration of a single-wafer vapor phase growth apparatus. FIG. 2 is a correlation diagram showing the relationship between the growth temperature, the growth rate, and the haze level in the examples and comparative examples.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
As described above, there has been a demand for a method for producing a silicon epitaxial wafer with a reduced haze level by vapor-growth of an epitaxial layer on a main surface of a silicon single crystal wafer having a main surface of an approximately {110} plane. As a result of intensive research, the present inventors have found that when vapor-growth of an epitaxial layer on a silicon single crystal wafer having a main surface of an approximately {110} plane is performed at a predetermined vapor-growth temperature (growth temperature) and growth rate (1095 to 1115°C and 0.5 to 1.5 μm/min, or 1135 to 1155°C and 3.0 to 4.0 μm/min), a good silicon epitaxial wafer with high carrier mobility and low haze level can be obtained, and have completed the present invention.

First, the configuration of a single-wafer type vapor phase growth apparatus will be described as a suitable example of a vapor phase growth apparatus used in the method for producing a silicon epitaxial wafer of the present invention. Fig. 2 shows an outline of a single-wafer type vapor phase growth apparatus.
As shown in FIG. 2, the vapor phase growth apparatus 1 includes a reaction vessel 2 and a susceptor 3 that is provided inside the reaction vessel 2 and supports a silicon single crystal substrate W on its upper surface.
The reaction vessel 2 is provided with a vapor growth gas inlet pipe 4 that introduces a vapor growth gas containing a source gas (e.g., trichlorosilane) and a carrier gas (e.g., hydrogen) into the reaction vessel 2 to a region above the susceptor 3 and supplies the gas onto the main surface of the silicon single crystal substrate W on the susceptor 3. In addition, on the same side of the reaction vessel 2 as the side on which the vapor growth gas inlet pipe 4 is provided, a purge gas inlet pipe 5 that introduces a purge gas (e.g., hydrogen) into the reaction vessel 2 to a region below the susceptor 3 is provided.
Furthermore, on the side of the reaction vessel 2 opposite to the side where the vapor growth gas inlet pipe 4 and the purge gas inlet pipe 5 are provided, an exhaust pipe 6 is provided through which gases (vapor growth gas and purge gas) within the reaction vessel 2 are exhausted.

In addition, heating devices 7a and 7b for heating the reaction vessel 2 from above and below are provided outside the reaction vessel 2. Examples of the heating devices 7a and 7b include halogen lamps.
The susceptor 3 is made of, for example, graphite coated with silicon carbide. The susceptor 3 is formed, for example, in a substantially circular plate shape, and has a counterbore 3a, which is a recess having a substantially circular shape in a plan view, formed on the upper surface thereof for positioning the silicon single crystal substrate W on the upper surface.
A susceptor support member 8 that supports the susceptor 3 from the back surface is provided on the lower surface of the susceptor 3. The susceptor support member 8 is movable in the vertical direction indicated by the arrow A and rotatable in the direction indicated by the arrow B.

Next, a method for producing a silicon epitaxial wafer according to the present invention will be described. The process flow is shown in FIG.
<Step 1: Preparation of silicon single crystal substrate>
First, a silicon single crystal substrate is prepared on which an epitaxial layer is to be grown in a vapor phase.
A silicon single crystal ingot with a principal axis orientation of <110> is manufactured by a known method such as the floating zone (FZ) method or the Czochralski (CZ) method. The head and tail of the obtained silicon single crystal ingot are then cut off, and the peripheral portion of the ingot is rotated and scraped to accurately determine the diameter and to form the ingot into a perfect cylindrical block.
The cylindrical block thus finished is sliced using a slicer such as an inner diameter blade cutter so that the main surfaces are either exactly aligned with the {110} plane or are inclined at an off angle to the {110} plane (for example, the off angle is greater than 0 degrees and less than 0.5 degrees).

After slicing, the outer peripheral edges of both surfaces of the silicon single crystal substrate are beveled to form chamfers.
After chamfering, the silicon single crystal substrate is double-sided lapped with free abrasive grains to produce a lapped wafer, or double-sided ground with fixed abrasive grains to produce a ground wafer.
Next, the lapped or ground wafer is immersed in an etching solution to perform a chemical etching process on both sides of the wafer in order to remove the damaged layer that has been generated on the surface of the silicon single crystal substrate by lapping or grinding.
After this chemical etching process, the front surface or the front and back surfaces are mirror-polished by mechanochemical polishing, and then a final cleaning is performed.

In this manner, a silicon single crystal substrate is prepared whose main surface is approximately a {110} surface (i.e., a {110} surface or a surface inclined by an off angle from the {110} surface) and which has a higher carrier mobility than a silicon single crystal substrate whose main surface is a {100} surface.
In addition, when preparing a silicon single crystal substrate whose main surface is inclined from the {110} plane by an off angle, the off angle is not limited, but it is particularly preferable to prepare one having an off angle of more than 0 degrees and less than 0.5 degrees. This is because, in step 3 described later, a silicon epitaxial wafer having a further reduced haze level can be obtained while maintaining high carrier mobility.

<Step 2: Removal of natural oxide film>
Next, a silicon single crystal epitaxial layer is vapor-grown on the principal surface of the silicon single crystal substrate having a principal surface of approximately a {110} plane obtained in the above-mentioned step 1, for example, using a vapor-phase growth apparatus 1 as shown in FIG.
Specifically, a silicon single crystal substrate W having a principal surface of approximately a {110} plane is placed in the reaction vessel 2 and placed in the counterbore 3a in the upper surface of the susceptor 3 so that the principal surface faces upward. Before the silicon single crystal substrate W is placed in the reaction vessel 2, hydrogen gas is introduced into the reaction vessel 2 via the vapor phase growth gas introduction pipe 4 and the purge gas introduction pipe 5.
Next, the silicon single crystal substrate W on the susceptor 3 is heated by the heaters 7a and 7b, and vapor-phase etching is performed to remove a natural oxide film formed on the main surface of the silicon single crystal substrate W. The appropriate temperature for this is, for example, in the range of 1050 to 1190° C.

<Step 3: Vapor phase growth of epitaxial layer>
After the vapor-phase etching of the native oxide film in step 2, a silicon single crystal epitaxial layer is grown on the main surface of the silicon single crystal substrate W by vapor phase growth.
At this time, the temperature (growth temperature) of the silicon single crystal substrate W is set to 1095 to 1115° C. (more preferably 1100 to 1110° C.), and the growth rate of the epitaxial layer is set to 0.5 to 1.5 μm/min.
The growth temperature can be adjusted by controlling the heaters 7a and 7b. Furthermore, the source gas and carrier gas are supplied substantially horizontally through the vapor phase growth gas inlet pipe 4, and the purge gas is supplied substantially horizontally through the purge gas inlet pipe 5 onto the main surface of the silicon single crystal substrate W and the underside of the susceptor 3. The growth rate within the above-mentioned growth temperature range can be adjusted by adjusting the flow rate of the source gas or the concentration of the source gas in the vapor phase growth gas (including the source gas and carrier gas).
Alternatively, the growth temperature may be set to 1135 to 1155° C. (more preferably 1140 to 1150° C.) and the growth rate of the epitaxial layer may be set to 3.0 to 4.0 μm/min. In this case, the method of adjusting the growth temperature and growth rate is the same as above.

By controlling the growth temperature and growth rate within these ranges during vapor growth, silicon epitaxial wafers with good haze levels and small surface roughness can be manufactured simply, inexpensively, and efficiently. For example, when the main surface is evaluated using a surface foreign matter inspection device (model Surfscan SP-3) manufactured by KLA in DWO mode (Dark Field Wide Oblique) (low angle incidence/low angle detection), an excellent haze level of 1.4 ppm or even less can be obtained. Because such a good haze level can be obtained, there is no problem with the conventional method in which a poor haze level caused increased background noise in particle counter measurements, making measurement difficult. This makes it possible to more reliably guarantee the quality of the wafer.

The thickness of the silicon single crystal epitaxial layer and electrical properties such as conductivity type and resistivity are not particularly limited, and may be any desired physical property. In the vapor phase growth of step 3, a doping gas can be added to the vapor phase growth gas and supplied as necessary.

The present invention will be described in more detail below with reference to examples and comparative examples of the present invention, but the present invention is not limited to these.
Examples and Comparative Examples
As the silicon single crystal substrates for epitaxial growth, a plurality of P ^- type silicon single crystal substrates having a diameter of 300 mm, a resistivity of 8 to 12 Ω·cm, a thickness of 775 μm, and a main surface with an off-angle of less than 0.5 degrees from the {110} plane (specifically, substrates having a main surface inclined 0.3 degrees from the (110) plane toward the (001) plane) were prepared. In addition, as the epitaxial growth apparatus, a single-wafer epitaxial growth apparatus for diameter 300 mm (Centura, an apparatus manufactured by Applied Materials, Inc.) having the same configuration as the vapor phase growth apparatus 1 shown in FIG. 2 was prepared.

Trichlorosilane was used as the source gas, and hydrogen was used as the carrier gas. The source gas was supplied at various amounts necessary for the desired growth rate as described below, and the carrier gas was supplied at 90 slm. Hydrogen was also selected as the purge gas, and the supply amount was 25 slm. Under these conditions, the temperature of the silicon single crystal substrate was in the range of 1090 to 1160°C, and the growth rate was in the range of 0.5 to 4.5 μm/min, and a silicon single crystal epitaxial layer having a thickness of about 2.0 μm was vapor-grown on the main surface of the prepared silicon single crystal substrate.
The combinations of growth temperature and growth rate in the examples of the present invention are 1095 to 1115° C. and 0.5 to 1.5 μm/min, and 1135 to 1155° C. and 3.0 to 4.0 μm/min. The supply amount of the source gas in the examples is about 1 to 20 slm in both the former and latter combinations.
The comparative examples are combinations other than these.

Thereafter, the haze level of the surface of the grown epitaxial layer was evaluated (unit: ppm) in DWO mode (low angle incidence/low angle detection) using a surface foreign matter inspection device (model Surfscan SP-3) manufactured by KLA. The results (relationship between the growth temperature, growth rate, and haze level) are shown in Figure 3. The area enclosed by a thick frame is the example.
As shown in FIG. 3, the haze level in the comparative examples was 1.5 ppm or more, whereas the haze level in the examples was 1.4 ppm or less, and it was confirmed that a good haze level was obtained within the range of the examples.

However, when the growth temperature is between 1095 and 1115°C and the growth rate is less than 0.5 μm/min, the growth rate is slow and inefficient, making it ineffective in terms of productivity.

The present invention is not limited to the above-mentioned embodiment. The above-mentioned embodiment is merely an example, and anything that has substantially the same configuration as the technical idea described in the claims of the present invention and has similar effects is included within the technical scope of the present invention.

1... single-wafer vapor phase growth apparatus, 2... reaction vessel, 3... susceptor,
3a...spot facing; 4...vapor growth gas introduction pipe; 5...purge gas introduction pipe;
6...exhaust pipe; 7a, 7b...heating device; 8...susceptor support member;
W: silicon single crystal substrate.

Claims (2)

A method for producing a silicon epitaxial wafer, comprising vapor-phase growing an epitaxial layer on a main surface of a silicon single crystal wafer, the main surface of the main surface being a {110} plane or a plane inclined by an off angle from the {110} plane, the method comprising the steps of:
When the epitaxial layer is grown in a vapor phase,
The temperature of the silicon single crystal wafer is set to 1095 to 1115° C., and the growth rate of the epitaxial layer is set to 0.5 to 1.5 μm/min, or
A method for producing a silicon epitaxial wafer, comprising the steps of: setting the temperature of the silicon single crystal wafer to 1135° C. to 1155° C.; and setting the growth rate of the epitaxial layer to 3.0 to 4.0 μm/min (excluding the case where the temperature of the silicon single crystal wafer is 1135° C. and the growth rate of the epitaxial layer is 3.0 μm/min) . 2. The method for producing a silicon epitaxial wafer according to claim 1, wherein the silicon single crystal wafer is a wafer having a main surface with the off angle from a {110} plane being greater than 0 degrees and less than 0.5 degrees.

Images