JP7629267B2 - Semiconductor device, power supply management circuit, and electronic device - Google Patents

Description

The present invention relates to a semiconductor device equipped with an A/D converter.

In various electronic devices, A/D converters are used to convert analog signals representing the electrical state of the internal circuits and the physical state of the electronic device into digital signals for digital signal processing.

Figure 1 is a block diagram of a semiconductor device 10 equipped with an A/D converter. The semiconductor device 10 is mounted on an electronic device 2 together with a processor 4. The semiconductor device 10 includes an A/D converter 12, a logic circuit 14, and an interface circuit 16. The A/D converter 12 converts an analog signal A1, which is input from the outside or generated inside the semiconductor device 10, into a digital signal D1. The logic circuit 14 processes the digital signal D1. Data D2 obtained as a result of the processing is stored in a register and can be accessed by the processor 4 via the interface circuit 16.

In applications where high resolution is required for the A/D converter 12, the offset caused by temperature changes significantly affects the conversion results. Therefore, when the logic circuit 14 receives a calibration instruction from the processor 4, it instructs the A/D converter 12 to perform a calibration operation.

For example, the processor 4 monitors the temperature and outputs a calibration instruction to the semiconductor device 10 if an unacceptable temperature fluctuation occurs.

JP 2014-230012 A

In the circuit system of FIG. 1, the processor 4 must constantly monitor the temperature regardless of the operating state of the electronic device 2. Therefore, the processor 4 cannot be stopped (sleep, suspend, standby), which is one of the factors that hinders low power consumption.

The present invention has been made in consideration of these problems, and one exemplary purpose of one aspect of the present invention is to provide a semiconductor device that can reduce the power consumption of a system.

One aspect of the present invention relates to a semiconductor device used with a processor. The semiconductor device includes an oscillator, an A/D converter configured to be calibrated, and a logic circuit that periodically triggers the A/D converter to be calibrated by a counting operation using the output of the oscillator.

Another aspect of the present invention is a power management circuit that includes a power supply circuit that receives a voltage from a battery and generates a power supply voltage to be supplied to a processor, an A/D converter that converts a current flowing through the battery into a digital value and is configured to be calibrated, a real-time clock that operates continuously, and a logic circuit that performs a counting operation using an output of the real-time clock, triggers the A/D converter to perform A/D conversion in a first period, and triggers the A/D converter to perform calibration in a second period longer than the first period.

In addition, any combination of the above components or mutual substitution of the components or expressions of the present invention between methods, devices, systems, etc. are also valid aspects of the present invention.

The present invention can reduce power consumption.

FIG. 1 is a block diagram of a semiconductor device including an A/D converter. 1 is a block diagram of an electronic device including a semiconductor device according to an embodiment. 3 is a time chart illustrating the operation of the semiconductor device of FIG. 2 . FIG. 2 is a block diagram of a power management circuit. FIG. 11 is a block diagram of an electronic device including a semiconductor device according to a first modification.

(Overview of the embodiment)
An embodiment disclosed in this specification relates to a semiconductor device. The semiconductor device is used together with a processor. The semiconductor device includes an oscillator that constantly oscillates, an A/D converter that is configured to be capable of being calibrated, and a logic circuit that periodically triggers calibration of the A/D converter by a counting operation using an output of the oscillator.

According to this embodiment, the semiconductor device itself uses an oscillator built into it to periodically calibrate the A/D converter, eliminating the need for the processor to determine calibration conditions. This makes it possible to stop the processor when processing by the processor is not required, thereby reducing power consumption.

The logic circuit receives a timing signal with a predetermined period based on the output of the oscillator, triggers the A/D converter to perform A/D conversion in response to the timing signal, and may also trigger the A/D converter to perform calibration each time it counts a predetermined number of timing signals. By managing the A/D conversion operation and calibration based on a common signal, the circuit configuration can be simplified.

The predetermined number may be externally configurable. This allows the frequency of calibration to be optimized depending on the application of the semiconductor device.

The semiconductor device may further include an RTC (Real Time Clock) circuit. The timing signal may be generated by the RTC circuit. Since the RTC circuit operates continuously and consumes very little power, a suitable use for its output is to generate periodic calibration triggers.

The semiconductor device may be connected to a battery of a device in which the semiconductor device is incorporated, and the A/D converter may convert the battery current into a digital value. The semiconductor device may integrate the digital value. This makes it possible to detect the remaining charge of the battery.

The semiconductor device may further include a power supply circuit that supplies a power supply voltage to the processor. The power supply circuit may stop supplying the power supply voltage when the processor is in a stopped state.

The A/D converter may be a ΔΣ type.

(Embodiment)
The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions are omitted as appropriate. In addition, the embodiments are illustrative rather than limiting the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, "a state in which component A is connected to component B" includes cases in which component A and component B are physically connected directly, and cases in which component A and component B are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the function or effect achieved by their combination. Similarly, "a state in which component C is provided between component A and component B" includes cases in which component A and component C, or component B and component C, are directly connected, as well as cases in which component A and component B are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the function or effect achieved by their combination.

FIG. 2 is a block diagram of an electronic device 2 including a semiconductor device 100 according to an embodiment. In addition to the semiconductor device 100, the electronic device 2 includes a processor 4 and a battery 6. The type of electronic device 2 is not limited, but examples include devices that require low power consumption, such as smartphones, tablet terminals, wearable terminals, e-books, and fire alarms.

The semiconductor device 100 includes an oscillator 110, an A/D converter 120, a logic circuit 130, and an interface circuit 140, which are integrated on a single semiconductor substrate. A voltage V _BAT is constantly supplied to the semiconductor device 100 as a power source from a battery 6. The battery 6 may be either a primary battery or a secondary battery.

The oscillator 110 oscillates constantly and generates a clock signal CK. The A/D converter 120 converts an analog signal A1 input from the outside into a digital signal D1. The A/D converter 120 may also receive an internal signal from the semiconductor device 10 as input.

The logic circuit 14 processes the digital signal D1. The data D2 obtained as a result of the processing is stored in a register and can be accessed by the processor 4 via the interface circuit 140.

The A/D converter 120 is configured to be calibrated. For example, in a calibration mode, the input of the A/D converter 120 is fixed, and the output at that time is obtained as an offset. If the A/D converter 120 has a differential input, the two inputs are shorted, and the output at that time is obtained. The calibration method for the A/D converter may be selected according to the type of the A/D converter.

The logic circuit 130 asserts a calibration signal CAL at regular time intervals (calibration period T _CAL ) by a counting operation using the output CK of the oscillator 110, and periodically provides a calibration trigger to the A/D converter 120. In addition, the logic circuit 130 asserts a sampling signal SMP at a sampling period T _S (first period) that is shorter than the calibration period (referred to as the second period), and provides an instruction for A/D conversion to the A/D converter 120.

The semiconductor device 100 preferably includes an RTC circuit 112 to provide a clock function and a calendar function. The RTC circuit 112 continuously updates the current time and date based on a clock signal CK. The time data and date data are accessible from the processor 4 via the interface circuit 140.

The RTC circuit 112 can generate a signal (called a timing signal) TM that is asserted every second. The logic circuit 130 can then use the timing signal TM to generate a sampling period and a calibration period. For example, the sampling period can be the period of the timing signal TM (i.e., 1 second). The calibration period can be a predetermined number N times the period of the timing signal TM. N can be a parameter that can be set externally. In this case, the calibration signal CAL can be calibrated by a counter that counts the timing signal TM.

The above is the configuration of the semiconductor device 100. Next, the operation will be described. Fig. 3 is a time chart for explaining the operation of the semiconductor device 100 of Fig. 2. The A/D converter 120 converts the analog signal A1 into a digital value in response to a sampling signal SMP asserted every predetermined sampling period T _S. The A/D converter 120 is also set to a calibration mode in response to a calibration signal CAL asserted every predetermined calibration period T _CAL , and outputs a digital value required for calibration.

The above is the operation of the semiconductor device 100. According to this semiconductor device 100, the semiconductor device 100 itself uses the built-in oscillator 110 to periodically calibrate the A/D converter 120, eliminating the need for an external processor 4 to determine calibration conditions (for example, temperature monitoring). Therefore, in situations where processing by the processor 4 is not required, such as when the electronic device 2A is not operating, it is possible to stop the processor 4, thereby reducing power consumption.

The logic circuit 130 may generate the calibration signal CAL at all times, regardless of whether the processor 4 is stopped or not. In this case, there is an advantage that it is not necessary to incorporate processing or circuits for determining the calibration conditions on the processor 4 side.

Next, applications of the semiconductor device 100 will be described. The architecture of the semiconductor device 100 can be suitably used for a power management circuit. FIG. 4 is a block diagram of the power management circuit 200. The power management circuit 200 is built into the electronic device 2A together with the processor 4 and the battery 6.

The power management circuit 200 is an IC (Integrated Circuit) that manages the power supply in the electronic device 2A.

The power supply management circuit 200 includes a power supply circuit 210 in addition to the same circuit blocks (110, 112, 120, 130, 140) as those of the semiconductor device 100 described above. The power supply circuit 210 includes a DC/DC converter and a linear regulator, receives a battery voltage V _BAT , and generates a power supply voltage V _DD stabilized to a predetermined voltage level. The power supply voltage V _DD is supplied to the processor 4 from a voltage output terminal (VOUT).

The power management circuit 200 may include multiple power supply circuits that supply power supply voltages to loads other than the processor 4, but these are not shown in the figure as they are not relevant to the present invention.

The power management circuit 200 has a function (fuel gauge) for detecting the remaining battery charge. One method for detecting the remaining charge is the coulomb counting method, which integrates the current I _BAT flowing through the battery 6. The power management circuit 200 detects the amount of charge flowing out of the battery 6 based on the coulomb counting method.

The A/D converter 120 is used to detect the current of the battery 6. A sense resistor Rs is connected in series with the battery 6, and a voltage drop V _SNS proportional to the battery current I _BAT occurs across the sense resistor Rs. The voltage drop V _SNS is input to sense terminals SNSP and SNSN of the power supply management circuit 200. The A/D converter 120 converts the voltage drop V _SNS into a digital value D1. For example, a ΔΣ type A/D converter 120 is used.

The logic circuit 130 includes a coulomb counter circuit 132 that accumulates a digital value D1 indicating the amount of current, and generates a coulomb count value CC. The coulomb count value CC is accessible from the processor 4. The coulomb counter circuit 132 can be configured as an accumulator including a memory and an adder.

A sense amplifier that amplifies the minute voltage drop V _SNS may be provided at the input stage of the A/D converter 120 .

If the battery 6 is a secondary battery, a charging circuit is further integrated into the power management circuit 200.

The above is the configuration of the power management circuit 200. By adopting the architecture of the semiconductor device 100, the power management circuit 200 itself can periodically calibrate the A/D converter 120, so that when the electronic device 2A is in a stopped state, the processor 4 can be stopped, thereby reducing power consumption.

Furthermore, when the processor 4 is in a stopped state, the power management circuit 200 can stop the supply of the power supply voltage V _DD . In other words, the operation of the power supply circuit 210 can be stopped, so that the power consumption of the power management circuit 200 can be further reduced.

The present invention has been described above based on an embodiment. This embodiment is merely an example, and those skilled in the art will understand that various modifications are possible in the combination of each component and each processing process, and that such modifications are also within the scope of the present invention. Below, such modifications are described.

(First Modification)
5 is a block diagram of an electronic device including a semiconductor device according to the first modification. In the first modification, the logic circuit 130 may generate the calibration signal CAL (internal calibration signal CAL _INT ) only when the processor 4 is in a sleep state. While the processor 4 is awake, the processor 4 judges whether or not a calibration condition exists, and when the calibration condition is satisfied, the processor 4 provides a calibration trigger (external calibration signal CAL _EXT ) to the semiconductor device 100.

The external calibration signal CAL _EXT is input to the A/D converter 120 via the interface circuit 140. The logical sum of the external calibration signal CAL _EXT and the internal calibration signal CAL _INT may be provided to the A/D converter 120. Alternatively, the external calibration signal CAL _EXT may be input to the logic circuit 130 via the interface circuit 140, and the logic circuit 130 may provide a calibration instruction to the A/D converter 120.

In many applications, the processor 4 can know various parameters (operating conditions) other than time, such as temperature. Therefore, the processor 4 can set the timing for calibrating the A/D converter 120 by taking into account parameters other than time. This allows for more appropriate calibration than when the calibration timing is determined based only on the internal calibration signal CAL _INT .

(Second Modification)
The lengths of the calibration period T _CAL and the sampling period T _S and the methods of generating the calibration signal CAL and the sampling signal SMP already described are merely examples, and may be determined depending on the object to be monitored by the A/D converter and the application of the semiconductor device 100.

The sampling period T _S may be set to M seconds (M<N). In this case, the sampling signal SMP may also be configured with a counter that counts the timing signal asserted every second.

When the calibration period T _CAL is 60 seconds (1 minute), a timing signal asserted every minute provided by the RTC circuit 112 may be used as the calibration signal CAL. When the calibration period T _CAL is N minutes, the timing signal asserted every minute may be counted. When a slowly changing quantity such as temperature is to be monitored, the sampling period T _S may be N minutes.

(Third Modification)
The application of the semiconductor device 100 is not limited to a power management IC. For example, the A/D converter 120 can receive the output of various sensing devices such as a temperature sensor as an input.

The present invention has been described using specific terms based on the embodiments, but the embodiments merely show the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the concept of the present invention as defined in the claims.

REFERENCE SIGNS LIST 100 Semiconductor device 110 Oscillator 112 RTC circuit 120 A/D converter 130 Logic circuit 140 Interface circuit 2 Electronic device 4 Processor 6 Battery 200 Power supply management circuit 210 Power supply circuit

Claims (14)

A semiconductor device for use with a processor, comprising:
An oscillator,
an A/D converter configured to be calibratable;
a logic circuit that provides an internal calibration signal as a trigger for periodic calibration to the A/D converter, regardless of an instruction from the processor, by a counting operation using an output of the oscillator;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the logic circuit receives a timing signal having a predetermined cycle based on the output of the oscillator, triggers the A/D converter to perform A/D conversion in response to the timing signal, and generates the internal calibration signal each time the timing signal having the predetermined cycle is counted a predetermined number, thereby triggering the A/D converter to perform the periodic calibration. The semiconductor device according to claim 2, characterized in that the predetermined number can be set. The semiconductor device according to claim 2 or 3, further comprising an RTC (Real Time Clock) circuit, the timing signal being generated by the RTC circuit. the semiconductor device is connected to a battery of an equipment in which the semiconductor device is incorporated, and the A/D converter is capable of converting a current of the battery into a digital value;
5. The semiconductor device according to claim 1, wherein the semiconductor device accumulates the digital value. The semiconductor device according to any one of claims 1 to 5, further comprising a power supply circuit that supplies a power supply voltage to the processor. The semiconductor device according to claim 6, characterized in that the power supply circuit stops supplying the power supply voltage when the processor is in a stopped state. the logic circuit provides the internal calibration signal to the A/D converter while the processor is stopped;
8. The semiconductor device according to claim 1, wherein an external calibration signal is applied from said processor to said A/D converter during an operation of said processor. The semiconductor device according to any one of claims 1 to 8, characterized in that the A/D converter is a ΔΣ type. A semiconductor device according to any one of claims 1 to 9, characterized in that it is integrated on a single semiconductor substrate. a power supply circuit that receives a voltage from a battery and generates a power supply voltage to be supplied to the processor;
an A/D converter that converts the current flowing through the battery into a digital value and is configured to be calibrated;
A constantly operating RTC (Real Time Clock) circuit;
a logic circuit which performs a counting operation using an output of the RTC circuit, and based on the counting operation regardless of an instruction from the processor, triggers the A/D converter to perform A/D conversion repeatedly in a first period, and also triggers the A/D converter to perform periodic calibration repeatedly in a second period longer than the first period;
A power management circuit comprising: The power management circuit according to claim 11, further comprising a coulomb counter circuit that integrates the output of the A/D converter. the logic circuit provides the internal calibration signal, which utilizes an output of the RTC circuit, to the A/D converter while the processor is stopped;
13. The power management circuit according to claim 11, wherein an external calibration signal from the processor is applied to the A/D converter during operation of the processor. An electronic device comprising a power management circuit according to any one of claims 11 to 13.

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