JP7630316B2 - Semiconductor device equipped with a reference voltage circuit - Google Patents

Description

The present invention relates to a semiconductor device having a reference voltage circuit with an N-type MOS transistor with a P-type gate electrode.

Using two N-type MOS transistors (enhancement type and depletion type), a reference voltage circuit can be constructed that outputs a constant voltage in response to fluctuations in the power supply voltage.

In a reference voltage circuit, it is often required to suppress fluctuations in output voltage due to temperature. Therefore, as shown in Patent Document 1, there is a method in which the impurity concentration of the channel region is made the same for two N-type MOS transistors (enhancement type and depletion type) that make up a reference voltage circuit (Vref circuit), and the conductivity type of the polycrystalline silicon that makes up the gate electrode is changed from the conventional same N type to P-type polycrystalline silicon for the gate electrode of the enhancement type transistor only. By utilizing the difference in work function brought about by the difference in the conductivity type of the gate electrode, a difference is made in the threshold voltage (Vth) between an enhancement type MOS transistor having polycrystalline silicon with P-type conductivity as its gate electrode and a depletion type MOS transistor having polycrystalline silicon with N-type conductivity as its gate electrode, and a reference voltage is generated.

In this case, the impurity concentration in the channel region is the same, so the effect of temperature changes on the threshold voltage of both transistors is also the same, making it possible to suppress fluctuations in the reference voltage obtained from the difference in the threshold voltages of the two transistors.

In the following, a gate electrode made of polycrystalline silicon having a P-type conductivity is referred to as a P-type gate electrode, a gate electrode made of polycrystalline silicon having an N-type conductivity is referred to as an N-type gate electrode, a MOS transistor having polycrystalline silicon having a P-type conductivity as its gate electrode is referred to as a P-type gate electrode MOS transistor, and a MOS transistor having polycrystalline silicon having an N-type conductivity as its gate electrode is referred to as an N-type gate electrode MOS transistor. A Vref circuit constructed using a P-type gate electrode MOS transistor and an N-type gate electrode MOS transistor is referred to as a Vref circuit using opposite polarity gates.

JP 2008-293409 A

In order to evaluate the reliability of this Vref circuit using a different polarity gate, a high temperature storage test is conducted under environmental conditions more severe than those in actual use, and it has been found that P-type gate electrode MOS transistors can experience a shift in threshold voltage. This shift causes the reference voltage to fluctuate, which leads to a shift in IC characteristics in long-term reliability tests. One of the causes of threshold voltage shift is the effect of hydrogen. However, although the amount of this threshold voltage shift is minute, at only a few millivolts, it cannot be ignored in applications that require a high degree of stability in the reference voltage obtained from the threshold voltage.

The present invention aims to provide a semiconductor device equipped with a reference voltage circuit that utilizes a transistor structure that can suppress the threshold voltage shift that occurs in a P-type gate electrode MOS transistor during a high-temperature storage test.

In order to solve the above problems, the semiconductor device having a reference voltage circuit according to the embodiment of the present invention has the following configuration. That is, the semiconductor device has a reference voltage circuit consisting of an enhancement type MOS transistor having polycrystalline silicon having a P-type conductivity type as a first gate electrode and a depletion type MOS transistor having polycrystalline silicon having an N-type conductivity type as a second gate electrode, and the enhancement type MOS transistor has a non-permeable film locally provided to cover the first gate electrode via an interlayer insulating film arranged on the upper part of the first gate electrode, and a nitride film provided to cover the periphery of the non-permeable film, having an opening larger than the first gate electrode in a plan view and smaller than the non-permeable film, and the depletion type MOS transistor has a nitride film directly provided on the interlayer insulating film arranged on the upper part of the second gate electrode, covering the depletion type MOS transistor without any gaps in a plan view.

In a semiconductor device equipped with a reference voltage circuit according to the present invention, in a P-type gate electrode MOS transistor, the nitride film, which is a protective film that is the source of hydrogen diffusion, which is a factor in causing a shift in the threshold voltage during a high-temperature storage test, is removed from the top of the P-type gate electrode, thereby suppressing hydrogen diffusion and suppressing fluctuations in the interface state due to high-temperature storage. This makes it possible to easily suppress fluctuations in IC characteristics without implementing process changes. The range in which the nitride film is removed is localized, and the area below the opening where the nitride film has been removed is a non-permeable film, so that intrusion of moisture is sufficiently suppressed and there is no risk of reducing reliability.

1 is a plan view of a semiconductor device including a reference voltage circuit according to a first embodiment of the present invention; FIG. 2 is a schematic cross-sectional view taken along the cutting line A in FIG. 1 . 2 is a schematic cross-sectional view taken along the cutting line B in FIG. 1 . 1 is an equivalent circuit diagram of a reference voltage circuit according to a first embodiment. FIG. 11 is a comparison diagram of shift amounts in a high-temperature storage test. FIG. 11 is a schematic cross-sectional view of a semiconductor device including a reference voltage circuit according to a second embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of a semiconductor device including a reference voltage circuit according to a third embodiment of the present invention.

The following describes an embodiment of the present invention with reference to the drawings.

Figure 1 is a plan view of a semiconductor device including a reference voltage circuit according to a first embodiment of the present invention. Figure 2 is a schematic cross-sectional view taken along line A in Figure 1, and Figure 3 is a schematic cross-sectional view taken along line B in Figure 1.

1, a semiconductor device 100 equipped with a reference voltage circuit has an enhancement type MOS transistor 1 and a depletion type MOS transistor 2. The conductivity type of both the enhancement type MOS transistor 1 and the depletion type MOS transistor 2 is N type, and they are sometimes called N channel.
As shown in FIG. 2 and FIG. 3, the enhancement type MOS transistor 1 is provided on the surface of a P-type well 8 disposed on an N-type substrate 7, and a source 9A and a drain 9B, both of which are N-type high concentration layers, are provided on both sides of a P-type gate electrode 3 provided via a gate oxide film. An intermediate insulating film 10 is provided to cover the P-type gate electrode 3, and a first metal wiring 11 is provided on the intermediate insulating film 10. An interlayer insulating film 12 is provided to cover the first metal wiring 11, and a non-water-permeable film 5 is locally disposed on the interlayer insulating film 12 to cover the P-type gate electrode 3. The non-water-permeable film 5 is covered from the periphery of the opening 6 to the outside by a final protective film 13 disposed on the interlayer insulating film 12, but the opening 6 provided on the upper surface of the non-water-permeable film 5 is not covered by the final protective film 13. The final protective film 13 has an opening 6 on the non-water-permeable film 5, exposing the surface of the non-water-permeable film 5.

As can be seen from FIG. 1, in plan view, the non-permeable film 5 covers the entire surface of the P-type gate electrode 3, and is therefore larger than the P-type gate electrode 3. Also, the opening 6 is provided larger than the P-type gate electrode 3 so as to include the entire surface of the P-type gate electrode 3 inside, but since the opening 6 is provided inside the non-permeable film 5, it is smaller than the non-permeable film 5.

As shown in FIG. 2, the depression type MOS transistor 2 is provided on the surface of another P-type well 8 arranged in the N-type substrate 7, which is different from the P-type well 8 in which the enhancement type MOS transistor 1 is provided, and a source 9C and a drain 9D, both of which are N-type high concentration layers, are provided on either side of the N-type gate electrode 4 provided via a gate oxide film. An intermediate insulating film 10 is provided to cover the N-type gate electrode 4, and a first metal wiring 11 is provided on the intermediate insulating film 10. An interlayer insulating film 12 is provided to cover the first metal wiring 11, and the entire surface is covered by a final protective film 13 arranged on the interlayer insulating film 12. Since the final protective film 13 covering the depression type MOS transistor 2 does not have an opening 6, the depression type MOS transistor 2 is completely covered by the final protective film 13.

As shown in FIG. 1, the drain 9B of the enhancement MOS transistor 1 is connected to the source 9C of the depletion MOS transistor 2 by a first metal wiring 11. The same metal wiring also connects the P-type gate electrode 3 of the enhancement MOS transistor 1 and the N-type gate electrode 4 of the depletion MOS transistor 2 to the same potential. Normally, the source 9A of the enhancement MOS transistor 1 is connected to a wiring of ground potential, and the drain 9D of the depletion MOS transistor 2 is connected to a wiring of power supply potential by the first metal wiring 11.

Fig. 4 is an equivalent circuit diagram showing a portion of the reference voltage circuit of a semiconductor device including the reference voltage circuit described with reference to Fig. 1 to Fig. 3. It has an enhancement type MOS transistor 1 and a depletion type MOS transistor 2 connected in series, the source of the enhancement type MOS transistor 1 is connected to the ground potential _VSS , and the drain of the depletion type MOS transistor 2 is connected to the power supply potential V _DD . A reference voltage _Vref is output from the connection point between the enhancement type MOS transistor 1 and the depletion type MOS transistor 2.

Next, a method for manufacturing a semiconductor device equipped with the above-mentioned reference voltage circuit will be described. The enhancement type MOS transistor and the depression type MOS transistor constituting the reference voltage circuit are provided near the surface of an N-type silicon substrate or a P-type well formed separately in an N-type well. After forming an element isolation region by LOCOS or STI, a gate oxide film is formed and a polycrystalline silicon film to become a gate electrode is deposited. After forming the polycrystalline silicon film to a thickness of 100 nm to 400 nm, impurity ion implantation is performed so that, for example, BF ₂ is ion-implanted into the gate electrode region of the enhancement type MOS transistor to make it P-type polycrystalline silicon, and, for example, phosphorus is ion-implanted into the gate electrode region of the depression type MOS transistor to make it N-type polycrystalline silicon. The polycrystalline silicon is then patterned and processed to form a gate electrode.

Next, an intermediate insulating film is formed to cover the gate electrode, and after forming contact holes, a metal film to be a first metal wiring layer is formed, followed by forming an interlayer insulating film and a required number of multi-layer wiring layers.
A water-impermeable layer is formed on the top layer of the multilayer wiring, and the water-impermeable layer is laid out and patterned so as to cover the gate electrodes of at least the enhancement-type MOS transistors constituting the reference voltage circuit, to form a water-impermeable film. It is also possible to dispose the water-impermeable film not only on the gate electrodes of the enhancement-type MOS transistors, but also on the gate electrodes of the depletion-type MOS transistors.
The impermeable layer may be a metal wiring layer that is the top layer. Instead of metal, amorphous silicon formed by sputtering may also be used.

After patterning the non-permeable layer, a final protective film is formed. The structure of the final protective film may be a single-layer structure of plasma nitride film, or a two-layer structure of oxide film and plasma nitride film. Since hydrogen contained in this plasma nitride film is desorbed and captured as an interface state during the high-temperature storage test, the final protective film in the area of the non-permeable film placed on the gate electrode of the aforementioned reference voltage circuit is etched and removed. This makes it possible to prevent diffusion of hydrogen from the plasma nitride film located directly above the P-type gate electrode, and suppress the total amount of hydrogen that diffuses.

Figure 5 compares the amount of shift exhibited by a semiconductor device equipped with the reference voltage circuit shown in Figures 1 to 4 in a high-temperature storage test with the amount of shift exhibited by a semiconductor device equipped with a reference voltage circuit of a conventional structure. If the amount of shift in the conventional structure is taken as 1, it can be seen that the amount of shift is reduced to 0.6 in the structure according to the first embodiment. From this comparison result, it can be seen that by disposing a non-permeable film covering the P-type gate electrode 3 above the P-type gate electrode 3 of the enhancement-type MOS transistor 1, and providing an opening by removing the plasma nitride film, which is the final protective film disposed on top of that, it is possible to suppress the amount of shift in the threshold voltage in a high-temperature storage test.

Figure 6 is a schematic cross-sectional view of a semiconductor device equipped with a reference voltage circuit according to a second embodiment of the present invention. The difference from the first embodiment is that it has a polyimide film 15 that covers the final protective film 13 arranged above the reference voltage circuit. The non-permeable film 5 does not allow moisture to pass through, but moisture may penetrate from the interface between the non-permeable film 5 and the final protective film 13 in the periphery covered by the final protective film 13. Unlike hydrogen, moisture causes corrosion, so it is also important to prevent moisture from penetrating in semiconductor devices. Therefore, by disposing a polyimide film 15 that completely covers the opening 6 located on the surface of the non-permeable film 5 provided in the final protective film 13, a structure is created that suppresses moisture from penetrating from the interface between the non-permeable film 5 and the final protective film 13. Polyimide is hydrophobic, so it has the effect of delaying the penetration of moisture.

Figure 7 is a schematic cross-sectional view of a semiconductor device equipped with a reference voltage circuit according to a third embodiment of the present invention. The difference from the first embodiment is that a corrosion-resistant oxide film is provided on the surface of the non-permeable film 5 that is the bottom of the opening 6. In the first embodiment, the use of a metal wiring layer or amorphous silicon deposited by sputtering was given as an example of the non-permeable film 5. When a metal wiring layer is used, since there is an opening, there is a possibility that corrosion due to moisture or the like will occur in the non-permeable film 5 using the metal wiring layer. Therefore, by providing a corrosion-resistant oxide film 16 that covers at least the surface of the non-permeable film 5 that is the bottom of the opening without any gaps so that the non-permeable film 5 is not corroded, it is possible to increase the reliability of the semiconductor device against corrosion.

Examples of the corrosion-resistant oxide film 16 include alumina (aluminum oxide: _Al2O3 ), which is a metal oxide, and ceramics. When the non-water-permeable film 5 is mainly composed of aluminum, alumina can be formed by oxidation in an _oxygen atmosphere or by anodization. The ceramic film can be formed by coating a thin film mainly composed of ceramic components. These oxides have high corrosion resistance and can be formed at relatively low temperatures, so they can be used in semiconductor devices.

The opening 6 must be longer than the first channel width at least in the first channel width direction and must be provided so as to cover the first channel region. However, the opening 6 may be shorter than the first channel length in the first channel length direction and may be set inside the first channel region.

The change in the interface state due to exposure to high temperatures is thought to occur mainly in the low-bonding region between the gate insulating film and the semiconductor substrate, due to the desorption of hydrogen that is present in this region due to the oxidation process. In particular, this low-bonding region may be concentrated at the boundary between the element isolation region and the channel region. Therefore, by sufficiently covering this region, the opening 6 can suppress the penetration of hydrogen from the nitride film, which is the protective film, and suppress the bonding and desorption of hydrogen that is present in the low-bonding region.

On the other hand, dangling silicon bonds generated by plasma etching during gate electrode formation tend to be unevenly distributed at the boundary between the channel region and the source/drain region. These dangling bonds are not terminated with hydrogen and act as fixed charges, which tend to increase the threshold voltage. Therefore, by actively promoting hydrogen penetration from the protective nitride film and suppressing the increase and variation in the threshold voltage, it is possible to stabilize the reference voltage output by the reference voltage circuit. Therefore, the opening 6 may be configured to be shorter than the first channel length in the first channel length direction and set inside the first channel region to promote hydrogen penetration.

1. N-channel enhancement type transistor 2. N-channel depletion type transistor 3. A gate electrode made of P-type polycrystalline silicon (P-type gate electrode)
4. A gate electrode made of N-type polycrystalline silicon (N-type gate electrode)
5. Non-permeable film 6. Opening provided in final protective film 7. N-type substrate 8. P-type well 9A, 9C. N-type high concentration layer (source)
9B, 9D. N-type high concentration layer (drain)
10. intermediate insulating film 11. first metal wiring 12. interlayer insulating film 13. final protective film 14. element isolation insulating film 15. polyimide film 16. non-permeable film

Claims (7)

an enhancement type MOS transistor including a first channel region having a first channel length direction and a first channel width direction, and a first gate electrode covering the first channel region and made of polycrystalline silicon having a P-type conductivity;
a depletion-type MOS transistor including a second channel region having a second channel length direction and a second channel width direction, the second channel region being covered with polycrystalline silicon having an N-type conductivity as a second gate electrode;
A semiconductor device including a reference voltage circuit having
the enhancement type MOS transistor comprises: a water-impermeable film locally provided to cover the first gate electrode via an interlayer insulating film arranged on an upper portion of the first gate electrode; and a nitride film provided to cover the periphery of the water-impermeable film, the nitride film including the first gate electrode in a plan view and having an opening that is smaller than the water-impermeable film;
a second gate electrode connected to the first insulating film and a second gate electrode connected to the second insulating film, the second gate electrode being electrically connected to the first insulating film and the second gate electrode being electrically connected to the second insulating film; The semiconductor device having the reference voltage circuit according to claim 1, characterized in that the opening is longer than the first channel width in the first channel width direction and shorter than the first channel length in the first channel length direction. an enhancement type MOS transistor having a first gate electrode made of polycrystalline silicon having a P-type conductivity;
a depletion type MOS transistor having a second gate electrode made of polycrystalline silicon having an N-type conductivity;
A semiconductor device including a reference voltage circuit having
the enhancement type MOS transistor comprises: a water-impermeable film locally provided to cover the first gate electrode via an interlayer insulating film arranged on an upper portion of the first gate electrode; and a nitride film provided to cover the periphery of the water-impermeable film, the nitride film having an opening that is larger than the first gate electrode and smaller than the water-impermeable film in a plan view;
a second gate electrode connected to the first insulating film and a second gate electrode connected to the second insulating film, the second gate electrode being electrically connected to the first insulating film and the second gate electrode being electrically connected to the second insulating film; A semiconductor device comprising a reference voltage circuit according to any one of claims 1 to 3, characterized in that the non-permeable film is the uppermost wiring layer. A semiconductor device having a reference voltage circuit according to any one of claims 1 to 3, characterized in that the non-permeable film is made of amorphous silicon. 4. The semiconductor device comprising the reference voltage circuit according to claim 1, further comprising a polyimide film that covers the opening without any gaps . A semiconductor device equipped with a reference voltage circuit according to any one of claims 1 to 3, further comprising a corrosion-resistant oxide film that completely covers the surface of the non-permeable film.

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