JP7632217B2 - Electronic control device and power supply method - Google Patents

Description

This disclosure relates to an electronic control device equipped with a system-on-chip.

In electronic control units installed in vehicles, units that require high processing performance are adopting systems on chips (SoCs) with higher processing capabilities instead of conventional microcontroller units (MCUs). Examples of units that require high processing performance include function integration units that consolidate vehicle control functions, autonomous driving units, and human-machine interface (HMI) units.

An SoC is a semiconductor integrated circuit that includes all elements (such as a CPU and peripheral circuits) required for a certain purpose and is designed to function as a system by itself.
SoCs not only have higher processing performance than MCUs, but also use fine processes and have low operating voltages (e.g., around 1 V). Therefore, the power supply that drives an SoC is required to be able to supply a large current (e.g., 10 to 20 A) at a low voltage.

When the SoC is started, it executes a self-diagnostic control called a built-in self-test (BIST) and then executes start-up control (Boot). BIST and Boot impose a higher load than the normal control that follows. In particular, BIST comprehensively diagnoses the functions within the SoC in a short period of time, so the CPU belonging to the SoC operates at full capacity, causing large load fluctuations, which can cause fluctuations in the power supply voltage of the SoC.

Patent document 1 describes a technology that suppresses voltage fluctuations when a computing device is started by setting the power supply voltage high and increasing the current supply capacity for a predetermined period of time after the computing device is released from reset and before the computing device starts normal control.

JP 2018-121413 A

However, as a result of detailed investigation by the inventors, it has been found that when the conventional technology is applied to SoC, the following problems arise.
That is, when applied to an SoC, current fluctuations of about 1.5 to 6 A occur during application control, whereas current fluctuations of about 0 to 12 A occur during BIST operation. For this reason, in order to keep the power supply voltage fluctuations caused by the load current fluctuations within the normal range, it is necessary to set a higher voltage (hereinafter, the start-up voltage). However, when the start-up voltage is switched to the normal voltage after the start of normal control, a large overshoot occurs because the load during normal control is lighter than during BIST. There is a problem in that this overshoot may be detected as an overvoltage and may be determined to be abnormal.

It is also possible to suppress overshoot while keeping the startup voltage low by providing a large-capacity smoothing capacitor that can withstand the voltage drop due to load fluctuations during BIST operation. However, in this case, the capacity of the smoothing capacitor suitable for BIST will be about twice the capacity of the smoothing capacitor suitable for application control. In other words, not only will a large amount of space be required to accommodate the smoothing capacitors, but it will also be difficult to form an optimal power loop because as many power loops as there are smoothing capacitors, which can lead to problems such as a deterioration in noise resistance.

One aspect of the present disclosure provides a technology for stably operating a system-on-chip without increasing the size of the device.

One aspect of the present disclosure is an electronic control device that includes a system-on-chip (7), a power supply unit (3, 3a), and a control unit (6, 33). When the system-on-chip is started, it is configured to execute self-diagnosis control, which has a larger load than application control, before starting application control. The power supply unit is configured to step down power supplied at a first voltage to a designated voltage and supply it to the system-on-chip. The control unit is configured to set a second voltage adapted to the execution of application control as a default value of the designated voltage, and set the designated voltage to a third voltage higher than the second voltage while self-diagnosis control is being executed in the system-on-chip.

According to this configuration, in the system-on-chip, the power supply voltage is set to the third voltage while the self-diagnosis control is being executed, and is returned to the second voltage before the application control starts.
As a result, while self-diagnosis control is being executed, not only can fluctuations in the power supply voltage due to load fluctuations be suppressed, but also the tolerance for voltage drops that occur when transitioning from a low load to a high load can be increased. In other words, overshoots and undershoots in the power supply voltage waveform caused by load fluctuations, particularly large undershoots that occur at the start of self-diagnosis control, can be suppressed from being detected as abnormal voltages without increasing the capacity of the smoothing capacitor.

One aspect of the present disclosure is a power supply method using a power supply unit (3, 3a) that steps down power supplied at a first voltage to a designated voltage and supplies it to a system-on-chip (7) configured to execute self-diagnosis control upon startup before starting normal control. In the power supply method of the present disclosure, a second voltage adapted to the execution of normal control is set as a default value of the designated voltage, and while the system-on-chip is executing self-diagnosis control, the designated voltage is set to a third voltage higher than the second voltage.
According to this power supply method, it is possible to obtain the same effects as those obtained by the above-mentioned electronic control device.

2 is a block diagram showing a configuration relating to a system-on-chip in the electronic control device of the first embodiment; FIG. 4 is a flowchart of a power supply process executed by a controller. FIG. 4 is a timing diagram showing an operation related to the second power supply unit. 1 is a timing diagram showing the operation of the embodiment in comparison with the prior art; FIG. 11 is a block diagram showing a configuration relating to a system-on-chip in an electronic control device according to a second embodiment.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.
[1. First embodiment]
[1-1. Configuration]
An electronic control unit (hereinafter, ECU) 1 shown in Fig. 1 is mounted on a vehicle and realizes various functions by communicating with other ECUs and on-board devices via an on-board network constructed by a controller area network (hereinafter, CAN) and Ethernet. Both CAN and Ethernet are registered trademarks.

The ECU 1 includes a first power supply unit 2, a second power supply unit 3, a controller power supply 4, a transceiver 5, a controller 6, a system-on-chip (hereinafter, SoC) 7, a memory group 8, and a communication driver group 9.

The ECU 1 has a wake-up state in which all functions can be executed, and a sleep state in which functions are limited. In the wake-up state, all of the components 2 to 8 that make up the ECU 1 are operational, and in the sleep state, only the transceiver 5 is maintained in an operational state.

SoC7 is a semiconductor integrated circuit that contains all the components necessary for a certain purpose and is designed to function as a system on its own. SoC7 is used in place of the microcontroller units (MCUs) that have traditionally been used in ECUs that require high processing power. ECUs that require high processing power include, for example, function integration units that consolidate multiple vehicle control functions, autonomous driving units, and human-machine interface (HMI) units.

When SoC7 functions as an autonomous driving unit, it may also realize functions such as acquiring and storing data from other in-vehicle devices via an in-vehicle network, analyzing the vehicle condition based on the stored data, and controlling driving in accordance with the analysis results.

SoC7 comprises a CPU group 71, a non-volatile memory 72, a memory controller 73, and a communication interface (hereinafter, communication IF) 74. Each of the components 71 to 74 constituting SoC7 is supplied with power via different power supply lines DL1 to DLm. In addition, CPU group 71 may be divided into multiple groups, and each group may be supplied with power via a different power supply line DL.

The non-volatile memory 72 stores application programs for implementing functions assigned to the SoC7, an operating system (hereinafter, OS) required to execute the application programs, firmware, etc. The firmware may include a program for self-diagnosis control called a built-in self-test (hereinafter, BIST), a program for initialization processing called Boot, a shutdown program, etc.

The memory controller 73 controls reads and writes to the memory group 8 that may be provided outside the SoC 7. The memory group 8 may include DRAM, flash memory, etc. The memory group 8 stores at least the data collected and analyzed by the functions of the SoC 7.

The communication IF 74 communicates with other ECUs by controlling the communication driver group 9. The communication driver group 9 may include a CAN transceiver and an Ethernet physical layer, etc.

The CPU group 71 includes n CPUs, and realizes various functions by executing programs stored in the non-volatile memory 72 .
As shown in the SoC processing of Fig. 3, at start-up, the CPU group 71 first executes BIST, then executes Boot including starting the OS, and then executes application control. Application control is control for executing application programs on the OS. When stopping the functions of the SoC 7, the CPU group 71 executes a shutdown program. The CPU group 71 is also configured to output monitoring signals to the second power supply unit 3 and the controller 6. The monitoring signals include a BIST completion signal that is output when the BIST is completed, and a shutdown completion signal that is output when the shutdown is completed.

The first power supply unit 2 steps down the DC power of the battery voltage B (e.g., 12 V) supplied from the battery mounted on the vehicle to a predetermined first voltage V1 (e.g., 5 V) and supplies it to the second power supply unit 3 and the controller power supply 4. The first power supply unit 2 operates when the first enable signal EN1 is at an active level. The first enable signal EN1 is high active.

The second power supply unit 3 includes a circuit unit 31 and an abnormality monitoring unit 32 .
The circuit unit 31 operates when the second enable signal EN2 is at an active level. The second enable signal EN2 is high active. The circuit unit 31 includes a step-down circuit 311 and a voltage setting register 312.

The step-down circuit 311 steps down the DC power of the first voltage V1 supplied from the first power supply unit 2, and supplies the stepped-down DC power to the SoC7 via the power supply lines DL1 to DLm. m is an integer equal to or greater than 2, and is equal to the number of blocks in the SoC7 that need to be individually powered. The stepped-down voltage is set for each of the power supply lines DL1 to DLm using the voltage setting register 312, and is set in the range of 0.9 to 1.2 V, for example. Here, a preset fixed voltage is used to supply power to components other than the CPU group 71. Two types of specified voltages are used to supply power to the CPU group 71. The specified voltages are the normal voltage Vr and the BIST voltage Vb.

The normal voltage Vr is set to suit application control. Specifically, the normal voltage Vr is set to a magnitude that prevents the power supply line voltage (hereinafter, CPU power supply voltage) Vcpu that supplies power to the CPU group 71 from exceeding a preset allowable voltage range due to load fluctuations in the CPU group 71 that occur during application control. The lower limit voltage VL and upper limit value VH of the allowable voltage range are determined by the specifications of the SoC7. Furthermore, the lower limit voltage VL is used as an undervoltage detection threshold, and the upper limit voltage VH is used as an overvoltage detection threshold.

The BIST voltage Vb is set to a value that prevents the CPU power supply voltage Vcpu from fluctuating beyond the allowable voltage range VL to VH due to load fluctuations of the SoC7 expected when the BIST is executed, i.e., fluctuations in current consumption. In particular, the BIST voltage Vb is set so that the undershoot of the CPU power supply voltage Vcpu that occurs when changing from no load to maximum load, such as at the start of the BIST, does not fall below the lower limit voltage VL.

The load fluctuation during BIST is larger than the load fluctuation during application control, so Vr is set to be smaller than Vb. The load fluctuation during Boot is about the same as the high load state during BIST and application control.

The voltage setting register 312 used to set the CPU power supply voltage Vcpu is set to a value that generates the normal voltage Vr as a default value when the second power supply unit 3 is started, and can be rewritten as desired according to instructions from the controller 6.

The abnormality monitoring unit 32 has the function of monitoring the CPU power supply voltage Vcpu to detect abnormal voltages that exceed the allowable voltage range VL to VH of the SoC7, and the function of setting the SoC reset signal RS. The SoC reset signal RS is low active.

When the voltage setting register 312 is rewritten in accordance with instructions from the controller 6 after the second power supply unit 3 is started, the abnormality monitoring unit 32 releases the reset state by switching the SoC reset signal RS to an inactive level. When the abnormality monitoring unit 32 receives an ECU termination notification via the controller 6 or detects an abnormal voltage in the CPU power supply voltage Vcpu, it sets the SoC reset signal RS to an active level to reset the SoC 7.

The controller power supply 4 steps down the power of the first voltage V1 supplied from the first power supply unit 2 to a controller voltage VC and supplies it to the controller 6. The controller voltage VC is set to, for example, about 1.8 to 2 V.

The transceiver 5 operates at all times regardless of whether the ECU 1 is in a wake-up state or a sleep state. When the ECU 1 is in a wake-up state, the transceiver 5 operates as a CAN transceiver, realizing communication between the controller 6 and other ECUs, etc., via the CAN.

When the transceiver 5 receives an ECU startup notification via the CAN while the ECU 1 is in a sleep state, it changes the first enable signal EN1 from an inactive level to an active level. Specifically, the transceiver 5 changes the first enable signal EN1 to an active level by connecting the signal line that supplies the first enable signal EN1 to the power supply line from the battery. This starts the supply of power from the first power supply unit 2 to each of the units 3-4, 6-9 of the ECU 1, and the ECU 1 transitions to a wake-up state.

When the transceiver 5 receives a sleep command from the controller 6 while the ECU 1 is in a wake-up state, it changes the first enable signal EN1 from an active level to an inactive level. This stops the power supply from the first power supply unit 2 to each of the units 3-4 and 6-9 of the ECU 1, causing the ECU 1 to transition to a sleep state.

The controller 6 operates by receiving power from the controller power supply 4. The controller 6 is a one-chip controller equipped with a CPU 61, a memory 62, and a communication IF 63. The communication IF path 63 has a function for realizing communication with other ECUs using the transceiver 5, as well as a communication function for accessing an interface provided for controlling the second power supply unit 3. The controller 6 at least executes power supply processing to control the operation of the second power supply unit 3, etc., according to the ECU end notification acquired via the transceiver 5, the monitoring signal output from the SoC 7, the SoC reset signal RS output from the second power supply unit 3, etc.

[1-2. Processing]
Next, the power supply process executed by the controller 6 will be described with reference to the flow chart of FIG. 2 and the timing chart of FIG.

The power supply process starts when the controller 6 is started by supplying power to the controller 6 via the controller power supply 4. In other words, the power supply process is executed when the ECU 1 is in a wake-up state. When the controller 6 is started, the SoC reset signal RS is at an active level, and the SoC 7 is held in a reset state.

In S110, the controller 6 switches the second enable signal EN2 from the inactive level to the active level.
This activates the second power supply unit 3, and the step-down circuit 311 starts supplying power to the SoC 7. When the second power supply unit 3 is activated, the voltage setting register 312 is set to the normal voltage Vr, which is a default value, so that the CPU power supply voltage Vcpu rises to the normal voltage Vr. When the time that has elapsed since the second enable signal EN2 changed to the active level reaches a predetermined time Tx, the abnormality monitor 32 changes the SoC reset signal RS from the active level to the inactive level, thereby releasing the reset state of the SoC 7. The predetermined time Tx is set to be longer than the time required for the CPU power supply voltage Vcpu to reach the BIST voltage Vb after the second enable signal EN2 becomes active (i.e., after the second power supply unit 3 is activated).

In the next step S120, the controller 6 waits until the first waiting time T1 has elapsed, which is sufficient for the CPU power supply voltage Vcpu to reach the normal voltage Vr, and then changes the setting of the voltage setting register 312 to the BIST voltage Vb. As a result, the CPU power supply voltage Vcpu rises to the BIST voltage Vb.

In the next step S130, the controller 6 determines whether the BIST has been completed on the SoC 7. Specifically, the controller 6 may measure the time that has elapsed since the SoC reset was released, and determine whether the elapsed time has reached the second waiting time T2. The second waiting time T2 is set, for example, to a standard time required from the release of the SoC reset until the BIST ends, plus a margin, and is set so that the elapsed time reaches the second waiting time T2 before the Boot process is completed. The controller 6 may determine that the BIST has been completed when it receives a BIST completion notification from the SoC 7.

If the controller 6 determines that the BIST is not complete, it waits by repeating the same step, and if it determines that the BIST is complete, it advances the process to S140.
In S140, the controller 6 changes the setting of the voltage setting register 312 to the normal voltage Vr, thereby causing the CPU power supply voltage Vcpu to drop to the normal voltage Vr.

Thereafter, while receiving power at the normal voltage Vr, the SoC 7 executes boot and then executes application control.
In the next step S150, the controller 6 determines whether or not an ECU termination notification has been received via the transceiver 5. If the ECU termination notification has not been received, the controller 6 waits by repeating the same step. If the ECU termination notification has been received, the controller 6 proceeds to step S160.

In S160, the controller 6 sends a reset instruction to the second power supply unit 3. When the second power supply unit 3 receives the reset instruction, the abnormality monitoring unit 32 changes the SoC reset signal RS to the active level. This causes the SoC 7 to start a shutdown process, and when the shutdown process is completed, it outputs a shutdown completion notification.

In the next step S170, the controller 6 determines whether or not the shutdown of the SoC 7 has been completed. If the shutdown has not been completed, the controller 6 waits by repeating the same step, and if the shutdown has been completed, the controller 6 proceeds to step S180.

Whether or not the shutdown is complete may be determined based on whether or not a shutdown completion notification has been output from SoC7, or based on whether or not the time that has elapsed since the SoC reset signal RS changed to the active level has reached the third waiting time T3. Note that the third waiting time T3 may be set to, for example, a length that includes a sufficient margin in addition to the standard time required for shutdown.

In S180, the controller 6 changes the second enable signal EN2 to an inactive level, whereby the power supply from the second power supply unit 3 is stopped.
In the next step S190, the controller 6 outputs a sleep instruction to the transceiver 5, and ends the process.

When the transceiver 5 receives a sleep instruction, it changes the first enable signal EN1 to an inactive level. This stops the power supply from the first power supply unit 2, and the ECU 1 transitions to a sleep state.

[1-3. Operation]
3, when the ECU 1 is in a sleep state and the transceiver 5 receives an ECU startup notification, the transceiver 5 changes the first enable signal EN1 to an active level. This starts up the first power supply unit 2 and starts supplying power to the second power supply unit 3 and the controller power supply 4.

The controller power supply 4, started by the power supply from the first power supply unit 2, starts supplying power to the controller 6. The controller 6, started by the power supply from the controller power supply 4, starts the second power supply unit 3 by changing the second enable signal EN2 to the active level. The started second power supply unit 3 starts supplying power to the SoC 7 while keeping the SoC reset signal RS at the active level. At this time, the CPU power supply voltage Vcpu gradually increases and reaches the normal voltage Vr, which is the default value.

When the time that has elapsed since the second enable signal EN2 changes to the active level (i.e., since the second power supply unit 3 is started) reaches the first standby time T1, the controller 6 rewrites the voltage setting register 312 to set the CPU power supply voltage Vcpu to the BIST voltage Vb.

Then, when the abnormality monitoring unit 32 changes the SoC reset signal RS to an inactive level, the SoC reset is released and the SoC 7 starts up and SoC processing begins.

In SoC processing, the high-load BIST is executed first. When BIST starts, the load suddenly changes from no load to high load, causing an undershoot in the waveform of the CPU power supply voltage Vcpu. Then, when switching from BIST to Boot, the load of Boot is lighter than that of BIST, so an overshoot occurs in the waveform of the CPU power supply voltage Vcpu. In addition, the SoC7 may transmit a BIST completion notification when BIST is completed.

When the controller 6 confirms that the BIST on the SoC 7 has been completed, it rewrites the voltage setting register 312 to set the CPU power supply voltage Vcpu to the normal voltage Vr. Completion of the BIST may be confirmed when the time elapsed since the SoC reset was released reaches the second waiting time T2, or when a BIST completion notification is received from the SoC 7.

After BIST is completed, that is, while Boot is running, the voltage is switched from the BIST voltage Vb to the normal voltage Vr. Boot has a smaller load than BIST, but the load is about the same as when application control is under high load.

After that, when the SoC processing switches from Boot to application control, and when the load state switches between low and high load during application control, overshoot and undershoot occur in the waveform of the CPU power supply voltage Vcpu. Note that the hatched sections in the application control of the SoC processing shown in Figure 3 indicate appropriate switching between low and high load states.

When the ECU 1 is in a wake-up state, if the controller 6 receives an ECU termination notification via the transceiver 5, the controller 6 outputs a reset command to the second power supply unit 3. In response to the reset command from the second power supply unit 3, the abnormality monitoring unit 32 resets the SoC 7 by changing the SoC reset signal RS to an active level.

When the SoC reset signal RS goes to active level, the SoC 7 executes a shutdown process, and when the shutdown process is completed, outputs a shutdown completion notification.
When the controller 6 receives a shutdown completion notification from the SoC 7 or confirms that the SoC 7 has been shut down by the elapsed time from the start of the SoC reset reaching the third waiting time T3, it outputs a sleep command to the transceiver 5. When the transceiver 5 receives the sleep command, it changes the first enable signal EN1 to an inactive level to stop the power supply from the first power supply unit 2. This causes the ECU 1 to transition to a sleep state.

[1-4. Response]
In this embodiment, the second power supply unit 3 corresponds to the power supply unit, the controller 6 corresponds to the control unit, and the controller power supply 4 corresponds to the control power supply unit. The normal voltage corresponds to the second voltage, the BIST voltage corresponds to the third voltage, and the controller voltage VC corresponds to the control voltage. The application control corresponds to the normal control.

[1-5. Effects]
According to the first embodiment described above in detail, the following effects are achieved.
(1a) In the ECU 1, the CPU power supply voltage Vcpu during BIST is set to the BIST voltage Vb higher than the normal voltage Vr, so that the magnitude of undershoot appearing in the voltage waveform of the CPU power supply voltage Vcpu due to a sudden load change during BIST can be suppressed. As a result, without adding a smoothing capacitor to the power supply line DL used to supply power to the CPU group 71, it is possible to suppress the undershoot from falling below the lower limit voltage VL of the allowable voltage range and being detected as an abnormal voltage.

(1b) In ECU1, during Boot, which is an intermediate load between the BIST load and the application control load, the BIST voltage Vb is switched to the normal voltage Vr. This makes it possible to suppress the magnitude of the overshoot that occurs when the SoC processing switches to application control, which has a lower load than BIST or Boot. As a result, it is possible to prevent this overshoot from exceeding the upper limit voltage VH of the allowable voltage range and being detected as an abnormal voltage, even when the SoC is operating normally.

In other words, as shown in FIG. 4, when the CPU power supply voltage Vcpu switches to application control while it is at the BIST voltage Vb, an overshoot is added to the BIST voltage Vb, making it easier to exceed the upper limit voltage VH. In contrast, when the CPU power supply voltage Vcpu switches to application control while it is at the normal voltage Vr, an overshoot is added to the normal voltage Vr, making the margin to the upper limit voltage VH larger and preventing it from exceeding the upper limit voltage VH.

(1c) In the ECU 1, the controller 6 is provided separately from the second power supply unit 3. Therefore, in an ECU equipped with a SoC 7, the above-mentioned effects can be obtained by adding a controller power supply 4 and a controller 6 without replacing the existing second power supply unit 3.

[2. Second embodiment]
[2-1. Differences from the first embodiment]
The second embodiment has a basic configuration similar to that of the first embodiment, and therefore differences will be described below. Note that the same reference numerals as those in the first embodiment indicate the same configurations, and the preceding description will be referred to.

In the first embodiment described above, the controller 6 is provided separately from the second power supply unit 3. In contrast, the second embodiment differs from the first embodiment in that a configuration equivalent to the controller 6 is provided integrally with the second power supply unit 3a.

As shown in FIG. 5, an ECU 1a of the second embodiment is different from the ECU 1 in that the controller power supply 4 and the controller 6 are omitted and the second power supply unit 3 is replaced with a second power supply unit 3a.
The second power supply unit 3a includes a circuit unit 31, an abnormality monitoring unit 32, and a voltage control unit 33. That is, compared to the second power supply unit 3, the voltage control unit 33 is added.

The voltage control unit 33 has the same functions as the controller 6 .
[2-2. Operation]
In the ECU 1a, the operation of the controller power supply 4 and the second enable signal EN2 shown in Fig. 3 is omitted. That is, when the ECU 1a is in a sleep state and the transceiver 5 receives an ECU startup notification, the transceiver 5 changes the first enable signal EN1 to an active level. This starts up the first power supply unit 2 and starts supplying power to the second power supply unit 3a.

The second power supply unit 3a, which is started by the power supply from the first power supply unit 2, starts supplying power to the SoC 7 while keeping the SoC reset signal RS at the active level. The operations up to the reception of the ECU end notification are the same as those in the first embodiment, except that the operation of the controller 6 is performed by the voltage control unit 33.

When the ECU 1 is in a wake-up state, if the voltage control unit 33 receives an ECU termination notification via the transceiver 5, the voltage control unit 33 outputs a reset instruction to the abnormality monitoring unit 32. In accordance with the reset instruction from the voltage control unit 33, the abnormality monitoring unit 32 resets the SoC 7 by changing the SoC reset signal RS to an active level.

When the SoC reset signal RS goes to active level, the SoC 7 executes a shutdown process, and when the shutdown process is completed, outputs a shutdown completion notification.
When the voltage control unit 33 receives a shutdown completion notification from the SoC 7 or confirms that the SoC 7 has been shut down by the elapsed time from the start of the SoC reset reaching the third standby time T3, it outputs a sleep command to the transceiver 5. When the transceiver 5 receives the sleep command, it changes the first enable signal EN1 to an inactive level to stop the first power supply unit 2 from supplying power to each unit. This causes the ECU 1 to transition to a sleep state.

[2-3. Response]
In this embodiment, the second power supply unit 3a excluding the voltage control unit 33 corresponds to a power supply unit, and the voltage control unit 33 corresponds to a control unit.

[2-4. Effects]
According to the second embodiment described above in detail, in addition to the effects (1a) and (1b) of the first embodiment described above, the following effects are further achieved.

(2a) In the ECU 1a, the function of the controller 6 in the ECU 1 of the first embodiment is incorporated in the second power supply unit 3a, so that the device configuration can be simplified.
3. Other embodiments
Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms.

(3a) In the present disclosure, the transceiver 5 and the CAN driver belonging to the communication driver group 9 are provided separately, but the transceiver 5 may be configured to also function as the CAN driver belonging to the communication driver group 9.

(3b) The controller 6 and the method described in the present disclosure may be realized by a dedicated computer provided by configuring a processor and a memory programmed to execute one or more functions embodied in a computer program. Alternatively, the controller 6 and the method described in the present disclosure may be realized by a dedicated computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the controller 6 and the method described in the present disclosure may be realized by one or more dedicated computers configured by combining a processor and a memory programmed to execute one or more functions with a processor configured with one or more hardware logic circuits. In addition, the computer program may be stored in a computer-readable non-transient tangible recording medium as instructions executed by a computer. The method for realizing the functions of each unit included in the controller 6 does not necessarily need to include software, and all of the functions may be realized using one or more hardware.

(3c) Multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Also, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Also, part of the configuration of the above embodiments may be omitted. Also, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments.

(3d) In addition to the electronic control device described above, the present disclosure can be realized in various forms, such as a system including the electronic control device as a component, a program for causing a computer to function as the electronic control device, a non-transient physical recording medium such as a semiconductor memory on which the program is recorded, and a method for controlling the power supply voltage to a system-on-chip.

1, 1a...Electronic control unit/ECU, 2...First power supply unit, 3, 3a...Second power supply unit, 4...Controller power supply, 5...Transceiver, 6...Controller, 7...System on chip/SoC, 8...Memory group, 9...Communication driver group, 31...Circuit unit, 32...Abnormality monitoring unit, 33...Voltage control unit, 311...Step-down circuit, 312...Voltage setting register.

Claims (8)

A system-on-chip (7) configured to execute a self-diagnosis control having a larger load than an application control before starting the application control when started;
a power supply unit (3, 3a) configured to step down power supplied at a first voltage to a designated voltage and supply the power to the system-on-chip;
a control unit (6, 33) configured to set a second voltage adapted to execution of the application control as a default value of the designated voltage, and to set the designated voltage to a third voltage higher than the second voltage while the self-diagnosis control is being executed in the system-on-chip;
An electronic control device comprising: 2. The electronic control device according to claim 1,
The control unit is configured to switch the designated voltage, which is set to the third voltage, to the second voltage before the application control is started. a system-on-chip (7) configured to execute, when started, a self-diagnosis control that has a larger load than the application control before starting the application control, and a startup control that has a smaller load than the self-diagnosis control and is in a load state similar to that of the application control when the load is high;
a power supply unit (3, 3a) configured to step down power supplied at a first voltage to a designated voltage and supply the power to the system-on-chip;
a control unit (6, 33) configured to set a second voltage adapted to execution of the application control as a default value of the designated voltage, and to set the designated voltage to a third voltage higher than the second voltage while the self-diagnosis control is being executed in the system-on-chip;
Equipped with
The control unit is configured to switch the designated voltage, which is set to the third voltage, to the second voltage during execution of the start-up control.
Electronic control unit. An electronic control device according to any one of claims 1 to 3 ,
the control unit is configured to switch the designated voltage, which is set to the third voltage, to the second voltage after a waiting time, which is set according to a standard time required for the self-diagnosis control, has elapsed after the reset state of the system-on-chip has been released. An electronic control device according to any one of claims 1 to 4 ,
The control unit is configured to switch the voltage from the second voltage to the third voltage before the self-diagnosis control is started in the system-on-chip. An electronic control device according to any one of claims 1 to 5 ,
The power supply unit (4) is configured to step down the power supplied at the first voltage to a control voltage and supply the control unit with the control voltage;
The control unit is an electronic control device configured as a one-chip controller having a communication function with the power supply unit. An electronic control device according to any one of claims 1 to 5 ,
The control unit (33) is an electronic control device integrally formed with the power supply unit (3a). A power supply method using a power supply unit (3, 3a) for stepping down power supplied at a first voltage to a designated voltage and supplying the power to a system-on-chip (7) configured to execute self-diagnosis control before starting normal control upon startup, comprising:
A power supply method comprising: setting a second voltage adapted to execution of the normal control as a default value of the designated voltage; and setting the designated voltage to a third voltage higher than the second voltage while the self-diagnosis control is being executed in the system-on-chip.

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