JP7633798B2 - FILTERING CIRCUIT AND FILTERING METHOD - Google Patents

Description

The present invention relates to a circuit and method that simplifies the setting of an attenuation frequency band for a noise filtering circuit having a fixed frequency.

Noise with a fixed frequency is known. For example, commercial power sources with frequencies of 50 Hz and 60 Hz are commonly used, and may generate noise with fixed frequencies of 50 Hz and 60 Hz, respectively. In addition, the peripheral circuits of a motor may contain noise with a frequency that depends on the steady-state rotational speed of the motor.

Known noise filtering circuits include chopping circuits, negative feedback circuits, and moving average processing circuits using first-in-first-out (FIFO) memory. Chopping circuits and moving average processing circuits using negative feedback circuits have the problem that the power consumption of the built-in operational amplifier circuit and chopping circuit itself is relatively high. On the other hand, moving average processing circuits using FIFO memory have relatively low power consumption, so it has been proposed to apply them to wearable electrocardiogram signal generating devices (Patent Document 1).

JP 2016-174642 A

For example, when using a 50 Hz or 60 Hz commercial power supply, in order to accurately remove fixed-frequency noise, the frequency characteristic of the filtering circuit that can be most suppressed must be manually set (optimized) to either 50 Hz or 60 Hz, which can be problematic in terms of usability. Hereinafter, this optimization process will be referred to as "setting the attenuation frequency band."

The problem to be solved by the embodiment is to simplify the setting of the attenuation frequency band of the filtering circuit. Other problems and novel features will become apparent from the description of this specification and the drawings.

A filtering circuit according to one embodiment is a device that uses moving average signals with different periods to set the attenuation frequency band of the filtering circuit in a simplified manner. A method according to another embodiment is a method that uses moving average signals with different periods to set the attenuation frequency band of the filtering circuit in a simplified manner.

By using the filtering circuit and method according to the above-described embodiment, it is possible to simplify the setting of the attenuation frequency band according to the fixed frequency of the noise.

FIG. 1 is a block diagram of an electrocardiograph according to a first embodiment. FIG. 2 is a diagram showing the moving average processing circuit, the comparator, the multiplexer circuit, and the processing of the processor according to the first embodiment. FIG. 3A is a diagram showing the filter frequency characteristic (a) and the output signal to the comparator 7 when moving average processing is performed on six consecutive fluctuation amounts (b). FIG. 3B is a diagram showing (a) the filter frequency characteristic and (b) the output signal to the comparator 7 when moving average processing is performed on five consecutive fluctuation amounts. FIG. 4 is a block diagram of an electrocardiogram according to the second embodiment.

The semiconductor device according to the embodiment will be described in detail below with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals, and duplicate explanations will be omitted. In the drawings, configurations may be omitted or simplified for the sake of convenience. In addition, at least a portion of the embodiment and each modified example may be combined with each other in any desired manner.

(Configuration of the Filtering Circuit According to the First Embodiment)
1 is a block diagram of an electrocardiograph including a filtering circuit according to an embodiment of the present invention. The electrocardiograph 1 includes an electrocardiogram waveform acquisition unit 2, an amplifier circuit 3, an anti-aliasing filter 4, an analog-to-digital conversion circuit 5, a moving average processing circuit 6, a comparator 7, a multiplexer circuit 8, and a processor 9.

The electrocardiogram waveform acquisition unit 2 receives an electrocardiogram waveform signal from an externally connected sensor and outputs it to the amplifier circuit 3. The amplifier circuit 3 amplifies the received signal based on a set gain value and outputs the amplified signal to the anti-aliasing filter 4. The anti-aliasing filter 4 attenuates frequency components equal to or greater than half the sampling frequency contained in the input signal from the amplifier circuit 3 and outputs the signal to the analog-digital conversion circuit 5. The analog-digital conversion circuit 5 converts the input signal from the anti-aliasing filter 4 into a digital signal at a predetermined sampling rate and outputs the digital signal to the moving average processing circuit 6. The moving average processing circuit 6 calculates the amount of fluctuation in the input signal from the analog-digital conversion circuit 5 using a built-in difference calculation circuit, and then stores the amount of fluctuation in the FIFO memory in the moving average processing circuit in sequence.

Here, a FIFO memory is a memory that stores data in the order it was input, and after a certain period of time, the data is retrieved in the same order it was input. Therefore, when new data is stored, old data is output and simultaneously deleted.

2 shows the structure and detailed operation of the moving average processing circuit 6, the comparator 7, the multiplexer circuit 8, and the processor 9 in this embodiment. The analog-digital conversion circuit 5 outputs the signal im (m = 0, 1, ...) to the moving average processing circuit 6 in sequence, and the signal is stored in the FIFO memory 10. At the timing when the FIFO memory 10 outputs the signal i0 to the difference calculation circuit 11, the difference calculation circuit 11 receives the signal i1 directly from the analog-digital conversion circuit 5. The difference calculation circuit 11 calculates the difference between the signal i0 and the signal i1, and outputs the fluctuation amount d0 to the FIFO memory 12. Thereafter, as m increases (m = 1, 2, ...), the difference calculation circuit 11 similarly outputs the fluctuation amount dm (m = 1, 2, ...) to the FIFO memory 12. When the fluctuation amount is stored in the FIFO memory 12, the adder 13 adds five consecutive fluctuation amounts, for example, d0 to d4, and outputs the sum to the multiplier 14. Multiplier 14 multiplies that value by six to output value A to comparator 7 and processor 9 via path 100. Meanwhile, adder 15 adds six consecutive fluctuation amounts, for example d0 to d5, and outputs the result to multiplier 16. Multiplier 16 multiplies that value by five to output value B to comparator 7 and processor 9 via path 200.

Comparator 7 compares the absolute value of value A with the absolute value of value B, and outputs the result to processor 9 via path 300.

In this embodiment, as an example, the frequency of commercial power noise is 50 Hz and the sampling rate is 3.33 msec. In this case, it can be seen that the 50 Hz noise can be removed by performing moving average processing on six consecutive fluctuation amounts using the following formula.
1÷(6×0.00333)=50Hz...(Formula 1)

The frequency characteristics of the moving average processing at this time are shown in FIG. 3A(a). It can be seen that the gain drops sharply at 50 Hz, and the noise level can be suppressed by 59.6 dB. That is, as shown in FIG. 3A(b), the output value to the comparator 7 when moving average processing is performed on six consecutive fluctuation amounts has reduced noise. On the other hand, the frequency characteristics when moving average processing is performed on five consecutive fluctuation amounts are shown in FIG. 3B(a) and the output value to the comparator 7 in FIG. 3B(b), but the noise reduction effect at 50 Hz is small at 13.9 dB. That is, in this embodiment, the residual noise after moving average processing contained in value B is larger than the residual noise contained in value A, so the absolute value of value B is larger than the absolute value of value A.

On the other hand, when the frequency of commercial power noise is 60 Hz and the sampling rate is 3.33 msec, performing moving average processing on five consecutive fluctuation amounts results in a greater drop in gain at 60 Hz and suppresses the noise level than performing moving average processing on six consecutive fluctuation amounts. As a result, the residual noise contained in value A is greater than the residual noise contained in value B, and the absolute value of value A is greater than the absolute value of value B.

Therefore, by comparing the absolute value of value A with the absolute value of value B using comparator 7, it is possible to determine whether adder 13 or 15 is better at reducing fixed frequency noise.

The processor 9 sets the multiplexer circuit 8 to output the signal with the reduced noise from the output signal of the multiplier 14 or multiplier 16 based on the comparison result received from the comparator 7 via the path 300. The processor 9 processes the electrocardiogram waveform using the output signal of the multiplier 14 or multiplier 16 received via the path 400.

In order to save power, the adder 13 and the multiplier 14 may be stopped from operating when the processor 9 does not use value A, and the adder 15 and the multiplier 16 may be stopped from operating when the processor 9 does not use value B.

As described above, according to this embodiment, it is possible to provide a filtering circuit that simplifies the setting of the attenuation frequency band according to the fixed frequency of the noise, and to simplify the setting of the filtering circuit.

(Configuration of the Filtering Circuit According to the Second Embodiment)
As described in the first embodiment, the comparison result of the comparator 7 can determine whether the fixed frequency of the noise is 50 Hz or 60 Hz. FIG. 4 shows an embodiment in which the fixed frequency noise can be further reduced by changing the settings of various circuits constituting the electrocardiograph 1 based on the determination result. As described in the first embodiment, the processor 9 determines whether the fixed frequency of the noise is 50 Hz or 60 Hz based on the comparison result of the comparator 7. The processor 9 changes the attenuation frequency band of the anti-aliasing filter 4 to the determined fixed frequency of the noise via a path 500. The processor 9 can also remove the fixed frequency noise by changing the sampling rate of the analog-digital conversion circuit 5 via a path 600 based on the comparison result of the comparator 7. For example, when the frequency of the commercial power supply noise is determined to be 60 Hz, the processor 9 sets the sampling rate of the analog-digital conversion circuit 5 to 2.777 msec via the path 600. In this case, since 60 Hz noise can be removed by performing moving average processing on six consecutive fluctuation amounts using Equation 2, just as when reducing noise with a fixed frequency of 50 Hz, there is an advantage that there is no need to change the settings of the moving average processing circuit 6.
1÷(6×0.002777)=60Hz...(Formula 2)

The invention made by the inventor has been specifically described above based on the embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. In addition, the various circuits may be structurally configured as general-purpose circuits using firmware or software. Furthermore, the fixed frequency of the noise is not limited to 50 Hz or 60 Hz and may be another fixed frequency.

REFERENCE SIGNS LIST 1 Electrocardiograph 2 Electrocardiogram waveform acquisition unit 3 Amplification circuit 4 Anti-aliasing filter 5 Analog-digital conversion circuit 6 Moving average processing circuit 7 Comparator 8 Multiplexer circuit 9 Processor 10 FIFO memory 11 Difference calculation circuit 12 FIFO memory 13 Adder 14 Multiplier 15 Adder 16 Multiplier 100, 200, 300, 400, 500, 600 Path

Claims (6)

an analog-to-digital conversion circuit that samples an analog input signal at a predetermined period, converts it into a digital signal, and outputs it;
a moving average processing circuit that outputs an average signal level of the signal output from the analog-to-digital conversion circuit over a first period and a second period;
a comparison circuit that compares an average signal level over a first period output from the moving average processing circuit with an average signal level over a second period,
The moving average processing circuit is configured to output the smaller of an average signal level over a first period or a second period based on a comparison result in the comparison circuit. 2. A filtering circuit as claimed in claim 1,
The moving average processing circuit is a filtering circuit having a first-in-first-out memory. 2. A filtering circuit as claimed in claim 1,
Equipped with an anti-aliasing filter,
The comparison circuit is configured to change an attenuation frequency band of the anti-aliasing filter based on a result of the comparison. a signal level measuring step of measuring an input signal level at a predetermined period;
an average level output step of outputting an average signal level of the input signal measured by the signal level measuring step over a first period and a second period;
a comparison step of comparing the average signal level over a first period outputted in the average level output step with the average signal level over a second period;
a step of outputting, based on a comparison result in the comparing step, either an average signal level of the input signal measured in the signal level measuring step over a first period or a second period, whichever is smaller;
The filtering method comprises: 5. A filtering method according to claim 4 , comprising the steps of:
storing the input signal in a first-in-first-out memory;
The filtering method comprises: 5. A filtering method according to claim 4 , comprising the steps of:
changing an attenuation frequency band of the anti-aliasing filter based on a result of the comparison in the comparing step.

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