JP7633837B2 - Silicon wafer and its manufacturing method - Google Patents

Description

The present invention relates to a silicon wafer and its manufacturing method, and to a silicon wafer having a defect-free layer (DZ layer) on the surface and an intrinsic gettering layer (IG layer) made of oxygen precipitates (BMD) on the bulk layer, and to a manufacturing method thereof.

When strong thermal stress occurs inside the wafer during heat treatment of silicon wafers in the device manufacturing process, slips can occur starting from oxygen precipitates (BMD). When slips occur during the device manufacturing process, alignment shifts occur before and after dislocation generation, which causes the problem of so-called overlay errors in the photolithography process.

The BMDs (oxygen precipitates) formed inside the silicon wafer (bulk) by heat treatment in the device manufacturing process play a role in gettering impurities. In the device manufacturing process, if the BMD size is small, the gettering effect is insufficient, so in order to obtain a sufficient gettering effect, it is preferable for the BMD size to be larger for the same BMD density. However, if the BMD size becomes large, there is a risk that the BMDs will become a source of slip dislocations.

Therefore, Patent Document 1 discloses a method of forming oxygen precipitation nuclei having a size of 20 nm or less in a silicon wafer at a high density of 1×10 ¹⁰ /cm ³ or more to suppress slip extension.
However, in the silicon wafer obtained by the method disclosed in Patent Document 1, the BMD size in the depth direction does not change and the amount of oxygen precipitated in the deep layer is large, which causes a problem of reduced mechanical strength.

To address this issue, Patent Document 2 (JP Patent Publication No. 11-135510) proposes a silicon wafer in which the BMD size decreases with increasing depth from just below the DZ layer.
This reduces the amount of oxygen precipitated in the deep layers, ensuring the mechanical strength of the silicon wafer while maintaining the gettering capability against metal impurities.

JP 2006-40980 A Japanese Patent Application Publication No. 11-135510

However, the silicon wafer disclosed in Patent Document 2 has a problem in that the BMD density in the deep layer of the wafer may not be able to maintain a density (1×10 ⁹ /cm ³ or more) required to suppress the extension of slip dislocations.

The object of the present invention is to provide a silicon wafer that can suppress deformation due to slip dislocations while maintaining the gettering ability for metal impurities after the device manufacturing process, and a method for manufacturing the same.

The silicon wafer according to the present invention, which has been made to solve the above problems, is a silicon wafer in which oxygen precipitates are formed by heat treatment, and is characterized in that, in each layer divided every 50 μm from the wafer surface, the average size of oxygen precipitates in a first layer from the surface including a defect-free layer to a depth of 50 μm is smaller than the average size of a second layer immediately below the first layer, the average size of oxygen precipitates decreases in layers deeper than the second layer, the density of oxygen precipitates is 1×10 ⁹ /cm ³ or more in all layers, the average size of oxygen precipitates in the second layer is 70 to 90 nm, and the average size of oxygen precipitates in a sixth layer at a depth of 250 to 300 μm is 60 nm or less .

In the silicon wafer thus constructed, the size of oxygen precipitates in the first layer extending from the wafer surface including the defect-free layer to a predetermined depth can be made small, thereby making it possible to prevent the oxygen precipitates from becoming the starting point of slip and spreading to the device active layer.
Furthermore, by forming the size of the oxygen precipitates in the bulk portion (second layer) below it to be large, it is possible to maintain the gettering ability so that impurities in the device active layer can be captured in a layer close to the defect-free layer.
In addition, by maintaining the size of oxygen precipitates small in the deeper bulk portion (the third to sixth layers) and by making the density of oxygen precipitates 1×10 ⁹ /cm ³ or more in all layers, slip extension can be suppressed and overlay errors due to wafer deformation can be prevented.

Further, a method for producing a silicon wafer according to the present invention, which has been made to solve the above-mentioned problems, is a method for producing a silicon wafer containing oxygen precipitation nuclei, and is characterized by comprising: a step of growing a silicon single crystal having an oxygen concentration of 0.8× ¹⁰ atoms/cm ^or more and 1.4× ¹⁰ atoms/cm ^or less and a nitrogen concentration of 0.2× ¹⁰ atoms/cm ^or more and 5.0× ¹⁰ atoms/cm or ^less by the Czochralski method; and a step of subjecting a silicon wafer obtained by slicing the silicon single crystal to a heat treatment in a rapid temperature increase and decrease heat treatment by setting the oxygen partial pressure in a furnace to 5% and the argon partial pressure to 95%, and maintaining the maximum temperature at 1350° C. for 10 sec.
By this method, it is possible to manufacture silicon wafers having the above characteristics.

The present invention provides a silicon wafer that can suppress deformation due to slip dislocations while maintaining gettering capability against metal impurities after the device manufacturing process, and a method for manufacturing the same.

FIG. 1 is a schematic diagram showing an enlarged partial cross section of a silicon wafer according to the present invention. FIG. 2 is a cross-sectional view of a single crystal pulling apparatus used for growing a silicon single crystal in the silicon wafer manufacturing method of FIG. FIG. 3 is a cross-sectional view showing one embodiment of a rapid temperature increase/decrease heat treatment apparatus (RTP apparatus) to which the method for producing a silicon wafer of the present invention is applied. FIG. 4 is a graph showing the results of the examples. FIG. 5 is a graph showing other results of the examples.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing an enlarged cross section of a silicon wafer W according to an embodiment of the present invention.
The silicon wafer W shown in FIG. 1 is characterized by the average size of oxygen precipitates (called BMDs) formed after heat treatment in the device process. Specifically, when the wafer is divided into sections of 50 μm in depth in the thickness direction, the average size of the surface layer (first layer) from the wafer surface to a depth of 50 μm including the defect-free zone (called the DZ layer) is smaller than the average size of the second layer immediately below it from a depth of 50 μm to 100 μm, and the average size of the bulk portion (second to sixth layers) deeper than 50 μm becomes smaller the deeper it is. The average size of the oxygen precipitates in the first layer is 67 nm, the average size of the oxygen precipitates in the second layer is 70 to 90 nm, and the average size of the oxygen precipitates in the sixth layer at a depth of 250 to 300 μm is 60 nm or less. In all layers, the BMD density is 1×10 ⁹ /cm ³ or more.

In this way, by reducing the BMD size in the first layer up to 50 μm from the wafer surface, including the DZ layer, it is possible to prevent the BMDs from becoming the starting point for slip and spreading to the device active layer. Furthermore, by increasing the BMD size in the bulk portion (second layer) below, it is possible to maintain the gettering ability so that impurities in the device active layer can be captured in a layer closer to the DZ layer.

In addition, the BMD size in the deeper bulk portion (third to sixth layers) is kept small to suppress slip extension and to prevent overlay errors due to wafer deformation. In this way, the BMD size in the bulk portion in the second to sixth layers becomes smaller the deeper, and the BMD density is maintained at 1×10 ⁹ /cm ³ or more, similar to the first layer, to suppress the extension of slip dislocations.

The BMD density and size can be measured using IR tomography (e.g. MO-441 manufactured by System Seiko). They may also be obtained from actual image observation using a TEM. The BMD size is a value calculated by creating a correlation equation between the average side length of octahedrons observed with a TEM and the average infrared scattering intensity.

Next, a method for manufacturing such a silicon wafer W will be described.
First, a silicon single crystal is grown and manufactured by the Czochralski method (CZ method).
In growing silicon single crystals by the CZ method, a quartz crucible 51 installed in a chamber 50 as shown in FIG. 2 is filled with polysilicon as a raw material, and the polysilicon is heated and melted by a heater 52 provided around the quartz crucible 51 to obtain a silicon melt M.

At this time, the oxygen concentration and nitrogen concentration in the silicon melt M are adjusted so that the silicon single crystal to be grown has an oxygen concentration of 0.8×10 ¹⁸ atoms/cm ³ or more ^and 1.4×10 ¹⁸ atoms/cm ³ or less, and a nitrogen concentration of 0.2×10 ¹⁵ atoms/cm ³ or more and 5.0×10 ¹⁵ atoms/cm 3 or less.
Incidentally, if the oxygen concentration of the silicon single crystal to be grown is 0.8×10 ¹⁸ atoms/cm ³ or less, the strength will be insufficient and the slip resistance will be poor, which is undesirable, whereas if the oxygen concentration is 1.4×10 ¹⁸ atoms/cm ³ or more, excessive BMD precipitation will occur, which is undesirable.
Furthermore, if the nitrogen concentration of the silicon single crystal to be grown is 0.2× ¹⁰¹⁵ atoms/ ^cm3 or less, the effect of eliminating void defects by the RTP treatment becomes weak, and there is a risk that void defects will remain after the RTP, which is undesirable. On the other hand, if the nitrogen concentration is 5.0× ¹⁰¹⁵ atoms/ ^cm3 or more, single crystallization is hindered during crystal growth, which is undesirable.
After the silicon melt M is formed, a seed crystal (seed) P attached to a seed chuck is immersed in the silicon melt M, and the seed chuck is pulled up while rotating the seed chuck and the quartz crucible 51 in the same or opposite directions.

Prior to the start of pulling, after the temperature of the silicon melt M has stabilized, a seed crystal P is brought into contact with the silicon melt M to perform necking, which melts the tip of the seed crystal P. The necking is an essential process for removing dislocations that occur in the silicon single crystal due to thermal shock caused by the contact between the seed crystal P and the silicon melt M.
This necking forms a neck portion P1, which must have a diameter of 3 to 4 mm and a length of at least 30 mm.

In addition, after the start of pulling, the following processes are carried out: after necking, a shoulder portion C1 is formed to expand the crystal to the diameter of the straight body portion (e.g., a diameter of 300 mm), a straight body portion C2 is formed to grow the single crystal that will become the product, and a tail portion (not shown) is formed to gradually reduce the diameter of the single crystal after the straight body portion formation process.

After the silicon single crystal is grown and produced in this manner, the silicon single crystal is sliced to obtain a plurality of silicon wafers each having a diameter of 300 mm.
These silicon wafers are subjected to a predetermined heat treatment using, for example, a rapid temperature change (RTP) apparatus shown in FIG.
3, the RTP apparatus 1 includes a chamber (reaction tube) 20 having an atmospheric gas inlet 20a and an atmospheric gas outlet 20b, a plurality of lamps 30 spaced apart from one another in the upper portion of the chamber 20, and a substrate support 40 that supports a silicon wafer W in a reaction space 25 within the chamber 20. In addition, although not shown, the apparatus includes a rotating means for rotating the silicon wafer W around its central axis at a predetermined speed.

The substrate support 40 comprises a ring 10 that supports the outer periphery of the silicon wafer W, and a stage 40a that supports the ring 10. The chamber 20 is made of, for example, quartz. The lamps 30 are made of, for example, halogen lamps. The stage 40a is made of, for example, quartz. This RTP apparatus 1 can uniformly heat and process the entire silicon wafer W with a temperature rise/fall gradient of 10 to 300°C/sec.

The temperature in the reaction space 25 in this RTP device 1 is controlled by measuring the average temperature at multiple points (e.g., nine points) in the radial direction of the lower part of the silicon wafer W using multiple radiation thermometers embedded in the stage 40a of the substrate support part 40, and controlling the multiple halogen lamps 30 (individual ON-OFF control of each lamp, control of the emission intensity of the emitted light, etc.) based on the measured temperature.

In the RTP apparatus 1 configured in this manner, first, the silicon wafer W is placed and fixed on the ring 10. This ring 10 is then fixed to the top of the stage 40a installed in the reaction space 25 under an oxidizing atmosphere so that the top surface of the silicon wafer W is approximately parallel to the top of the stage 40a.

A process gas is introduced from the atmospheric gas inlet 20a, and the gas in the reaction space 25 is exhausted from the atmospheric gas outlet 20b, forming a predetermined air flow above the silicon wafer W. The reaction space 25 preferably has an oxygen partial pressure of 5% and an argon gas partial pressure of 95%.
Next, the halogen lamps 30 arranged in an equal arrangement are individually controlled by feedback from the surface temperature of the silicon wafer W to rapidly heat the silicon wafer W while controlling the surface temperature of the silicon wafer W, thereby carrying out a heat treatment of the silicon wafer W.

Specifically, the wafer surface temperature is raised to 1250° C. within 60 seconds after the start of heating, and then raised to 1350° C. within 62 to 70 seconds after the start of heating, and this state is maintained for 10 seconds.
Thereafter, the inside of the furnace is rapidly cooled, completing the rapid temperature increase and decrease heat treatment.

Silicon wafers W that have been subjected to this rapid temperature increase and decrease heat treatment have the following characteristics: no void defects are present on the wafer surface, and oxygen precipitation nuclei that are the source of BMDs are present at the desired depth and density inside the wafer, allowing any BMD structure to be formed during the device manufacturing process.

Therefore, in the heat treatment in the device manufacturing process, for example, when a heat treatment is performed at 780° C. for 3 hours in an argon (Ar) atmosphere and then at 1000° C. for 16 hours, a BMD structure having the size and density shown in FIG. 1 is formed in the wafer.
At this time, the BMD size of the first layer from the wafer surface including the DZ layer to 50 μm is made small, which prevents the BMD from becoming the starting point of slip and spreading to the device active layer. Furthermore, the BMD size of the bulk part (second layer) below is made large, so the gettering ability that can capture impurities in the device active layer in the layer close to the DZ layer is maintained.
Furthermore, since the BMD size in the deeper bulk portion (third to sixth layers) is small, slip extension is suppressed, and the effect of preventing overlay errors due to wafer deformation is exerted.

As described above, according to the embodiment of the present invention, by forming the BMD size small in the first layer up to 50 μm from the wafer surface including the DZ layer, it is possible to prevent the BMDs from becoming the starting point of slip and spreading to the device active layer.
Furthermore, by forming the BMD size of the bulk portion (second layer) below it to be large, it is possible to maintain the gettering ability so that impurities in the device active layer can be captured in a layer close to the DZ layer.
In addition, by maintaining the BMD size small in the deeper bulk portion (the third to sixth layers) and keeping the BMD density at 1×10 ⁹ /cm ³ or more in all layers, slip extension can be suppressed and overlay errors due to wafer deformation can be prevented.

In the above embodiment, the wafer is divided into sections of 50 μm in depth in the thickness direction, and the BMD sizes for the first through sixth layers are specified, but the present invention is not limited to this configuration, and each layer may be divided at a specified depth.

The silicon wafer and manufacturing method thereof according to the present invention will be further described with reference to an example. In this example, the following experiment was carried out based on the above embodiment.

Example 1
In Example 1, first, a silicon single crystal having a diameter of 300 mm was grown by the Czochralski method so as to include a portion in which the oxygen concentration of the pulled silicon single crystal was 1.2×10 ¹⁸ atoms/cm ³ and the nitrogen concentration was 5.0×10 ¹⁴ atoms/cm ³ .
The silicon single crystal thus obtained was then sliced into silicon wafers, which were then heat-treated in a rapid temperature change (RTP) apparatus, in which the oxygen partial pressure in the furnace was set to 5% and the argon partial pressure was set to 95%, and the maximum temperature was maintained at 1350° C. for 10 seconds.

Thereafter, to simulate the heat treatment of the device process, the wafer was successively heat-treated in an argon (Ar) atmosphere at 780°C for 3 hours and then at 1000°C for 16 hours, and the BMD size and BMD density of the wafer cross section were measured by IR tomography (MO441 manufactured by System Seiko Co., Ltd.). The results of the BMD size are shown in the graph of FIG. 4, and the results of the BMD density are shown in the graph of FIG. 5. The vertical axis of the graph of FIG. 4 indicates the average BMD size (nm), and the horizontal axis indicates the depth (μm) from the wafer surface. The vertical axis of the graph of FIG. 5 indicates the average BMD density (cm ^-3 ), and the horizontal axis indicates the depth (μm) from the wafer surface. The BMD size is a value obtained by converting the scattering intensity of the IR tomography based on the BMD size obtained by TEM observation.

As shown in the graph of FIG. 4, the average BMD size is smaller than 70 nm up to a depth of 49 μm, and the average size is close to 80 nm from a depth of 50 to 99 μm, and it can be seen that the deeper the BMD size becomes, the smaller the BMD size becomes.
Furthermore, as shown in the graph of FIG. 5, the BMD density remains at 1×10 ⁹ /cm ³ or more at any depth.
In addition, the same silicon wafer was evaluated by X-ray topography (XRT300 manufactured by Rigaku Corporation) to confirm the presence or absence of dislocations. As a result, the total length of dislocations extending from the wafer boat position was 2 mm.

In addition, a solution containing Ni was applied to the silicon wafer after heat treatment by spin coating to a concentration of 1×10 ¹² atoms/cm ² , and then a diffusion treatment was performed at 900° C. for 0.5 hours, followed by etching to visually check whether shallow pits had occurred on the wafer surface. This is because if Ni is present on the surface upon cooling, Ni silicide is formed on the surface and can be detected as shallow pits. As a result, it was determined that no shallow pits had occurred in this sample, and most of the Ni that had contaminated the surface had been gettered into the internal BMDs.

(Comparative Example 1)
In Comparative Example 1, a silicon wafer obtained from the same silicon single crystal as in the Example was heat-treated in a rapid temperature change thermal processing apparatus (RTP apparatus) with an oxygen partial pressure of 75% and an argon partial pressure of 25% in a furnace, and maintained at a maximum temperature of 1350° C. for 10 seconds.
Thereafter, simulating the heat treatment in the device process, the wafer was heat-treated in an argon (Ar) atmosphere at 780° C. for 3 hours and then at 1000° C. for 16 hours in succession, and the BMD size and BMD density of the wafer cross section were measured by IR tomography (MO441 manufactured by System Seiko Co., Ltd.) The results of the BMD size are shown in the graph of FIG. 4 as in Example 1, and the results of the BMD density are shown in the graph of FIG.
In Comparative Example 1, the total length of dislocations was 74 mm, and the effect of suppressing dislocations was small. Furthermore, when Ni contamination was performed in the same manner as in Example 1, no shallow pits were generated.

(Comparative Example 2)
In Comparative Example 2, a silicon single crystal having a diameter of 300 mm was grown by the Czochralski method so as to include a portion in which the pulled silicon single crystal had an oxygen concentration of 1.2×10 ¹⁸ atoms/cm ³ and a nitrogen concentration of 1.0×10 ¹⁴ atoms/cm ³ .
Next, in a rapid temperature change (RTP) processing apparatus, the oxygen partial pressure in the furnace was set to 75%, the argon partial pressure was set to 25%, and the maximum temperature was maintained at 1350° C. for 10 seconds for heat treatment.

Thereafter, simulating the heat treatment in the device process, the wafer was heat-treated in an argon (Ar) atmosphere at 780° C. for 3 hours and then at 1000° C. for 16 hours in succession, and the BMD size and BMD density of the wafer cross section were measured by IR tomography (MO441 manufactured by System Seiko Co., Ltd.) The results of the BMD size are shown in the graph of FIG. 4 as in Example 1, and the results of the BMD density are shown in the graph of FIG.
The total dislocation length was 5 mm in Comparative Example 2. When Ni was contaminated in the same manner as in Example 1, shallow pits were observed, and it was determined that the gettering ability was insufficient.

The results of the above examples confirm that the configuration of the present invention can suppress deformation due to slip dislocations while maintaining gettering capability for metal impurities after the device manufacturing process.

1 RTP device 20 chamber (furnace)
25 Reaction space 30 Halogen lamp 40 Substrate support 40a Stage 50 Chamber C Silicon single crystal M Silicon melt W Silicon wafer

Claims (2)

A silicon wafer in which oxygen precipitates are formed by heat treatment,
In each layer divided every 50 μm from the wafer surface, the average size of oxygen precipitates in a first layer from the surface including a defect-free layer to a depth of 50 μm is smaller than the average size of a second layer immediately below the first layer, and the average size of oxygen precipitates becomes smaller in layers deeper than the second layer;
and the density of oxygen precipitates is 1×10 ⁹ /cm ³ or more in all layers;
A silicon wafer, characterized in that the average size of oxygen precipitates in the second layer is 70 to 90 nm, and the average size of oxygen precipitates in a sixth layer having a depth of 250 to 300 μm is 60 nm or less . A method for producing a silicon wafer containing oxygen precipitation nuclei, comprising the steps of:
growing a silicon single crystal having an oxygen concentration of 0.8×10 ¹⁸ atoms/cm ³ or more and 1.4×10 ¹⁸ atoms/cm ³ or less and a nitrogen concentration of 0.2×10 ¹⁵ atoms/cm ³ or more and 5.0×10 ¹⁵ atoms/cm ³ or less by the Czochralski method;
A step of heat-treating the silicon wafer obtained by slicing the silicon single crystal by rapid temperature increase and decrease heat treatment in a furnace with an oxygen partial pressure of 5% and an argon partial pressure of 95%, and maintaining the maximum temperature at 1350° C. for 10 seconds;
A method for producing a silicon wafer, comprising:

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