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JP7636855B2 - Receiver - Google Patents
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JP7636855B2 - Receiver - Google Patents

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JP7636855B2
JP7636855B2 JP2020113096A JP2020113096A JP7636855B2 JP 7636855 B2 JP7636855 B2 JP 7636855B2 JP 2020113096 A JP2020113096 A JP 2020113096A JP 2020113096 A JP2020113096 A JP 2020113096A JP 7636855 B2 JP7636855 B2 JP 7636855B2
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received signal
attenuation
control circuit
gain control
automatic gain
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康二郎 今里
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Japan Radio Co Ltd
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Description

この発明は、受信した信号から所望の音声周波数信号を抽出して音声を再生する受信機に関する。 This invention relates to a receiver that extracts a desired audio frequency signal from a received signal and reproduces the audio.

音声を再生する受信機には従来から、受信信号レベルに応じて利得・出力音声を適切な範囲に調整する自動利得制御回路(内部AGC)が設けられている。一方、受信機のアンテナ入力に過入力があった場合、電力増幅部などのデバイスが損傷、あるいは、飽和するおそれがある。このため、入力側において受信電力を監視して受信信号を減衰させる機能として、別の自動利得制御回路(外部AGC)が必要となる。この場合、例えば、図2に示すように、デジタル部で受信電力を監視し、デジタル部の前段で受信信号を減衰させる構成が考えられる。 Receivers that play back audio have traditionally been equipped with an automatic gain control circuit (internal AGC) that adjusts the gain and output audio to an appropriate range depending on the received signal level. However, if there is an excessive input to the receiver's antenna input, devices such as the power amplifier section may be damaged or saturated. For this reason, a separate automatic gain control circuit (external AGC) is required to monitor the received power on the input side and attenuate the received signal. In this case, for example, as shown in Figure 2, a possible configuration is to monitor the received power in the digital section and attenuate the received signal in the stage before the digital section.

しかしながら、2つの自動利得制御回路を備え、前段の外部AGCの収束後に後段の内部AGCが収束する、という動作、挙動を示すため、収束に時間を要し、応答性能が低下・劣化してしまう。特に上記の構成の場合、瞬間的に受信電力が大きくなった際に、外部AGCの収束前にRF_ADC(アナログ/デジタル変換器)で取り込む信号が飽和・オバーフローして、外部AGCにおける電力検出値が低く見積もられてしまい、受信信号が徐々に減衰することになる。この結果、後段の内部AGCにおける収束、応答が遅くなり、応答性が低下する。 However, because it has two automatic gain control circuits and exhibits an operation and behavior in which the subsequent internal AGC converges after the previous external AGC converges, it takes time for convergence, resulting in a decrease and deterioration of response performance. In particular, with the above configuration, when the received power increases instantaneously, the signal captured by the RF_ADC (analog/digital converter) saturates and overflows before the external AGC converges, causing the power detection value in the external AGC to be estimated too low, resulting in gradual attenuation of the received signal. As a result, the convergence and response of the subsequent internal AGC slows down, and responsiveness deteriorates.

このような問題を解決するために、内部AGCと外部AGCとの時定数を別の値に設定する、という技術が知られている(例えば、特許文献1参照。)。例えば、内部AGCの時定数を大きく設定し、外部AGCの時定数を小さく設定することで、出力信号のオーバーシュートやアンダーシュートを抑制するものである。 To solve this problem, a technique is known in which the time constants of the internal AGC and the external AGC are set to different values (see, for example, Patent Document 1). For example, by setting the time constant of the internal AGC large and the time constant of the external AGC small, overshoot and undershoot of the output signal are suppressed.

特開昭53-72441号公報Japanese Unexamined Patent Publication No. 53-72441

しかしながら、特許文献1の技術では、内部AGCと外部AGCとの時定数を別の値に設定するだけであるため、前段の外部AGCが後段の内部AGCに与える影響を抑制するには不十分で、応答性が低下する場合がある。 However, the technology in Patent Document 1 only sets the time constants of the internal AGC and the external AGC to different values, which is insufficient to suppress the effect of the external AGC in the previous stage on the internal AGC in the subsequent stage, and this may result in reduced responsiveness.

そこで本発明は、過入力によるデバイスの損傷を防止可能で、かつ、応答性が良好な受信機を提供することを目的とする。 The present invention aims to provide a receiver that can prevent damage to devices caused by excessive input and has good responsiveness.

前記の課題を解決するために、請求項1の発明は、デジタル変換された受信信号の信号レベルに応じてデジタル変換前の受信信号の利得を減衰させる第1の自動利得制御回路と、前記減衰を打ち消すタイミングで、前記第1の自動利得制御回路による減衰量の逆数を前記減衰されデジタル変換された受信信号に乗算することで、該受信信号の利得を減衰前の値に補正する利得補正部と、前記補正された受信信号の不要周波数成分を除去するチャネルフィルタと、前記チャネルフィルタを通過した受信信号の利得を所定範囲に調整する第2の自動利得制御回路と、を備え、前記利得補正部は、前記第2の自動利得制御回路において前記第1の自動利得制御回路による影響が抑制されるように、遅延を調整して前記逆数を乗算することで前記減衰を打ち消す、ことを特徴とする受信機である。
In order to solve the above problem, the invention of claim 1 is a receiver comprising: a first automatic gain control circuit that attenuates a gain of a received signal before digital conversion in accordance with a signal level of the digitally converted received signal; a gain correction unit that corrects the gain of the received signal to a value before attenuation by multiplying the attenuated and digitally converted received signal by the reciprocal of the amount of attenuation by the first automatic gain control circuit at a timing to cancel out the attenuation; a channel filter that removes unnecessary frequency components of the corrected received signal; and a second automatic gain control circuit that adjusts the gain of the received signal that has passed through the channel filter within a predetermined range, wherein the gain correction unit cancels out the attenuation by adjusting a delay and multiplying the reciprocal so that the influence of the first automatic gain control circuit is suppressed in the second automatic gain control circuit.

請求項1の発明によれば、第1の自動利得制御回路によって受信信号の利得が減衰されるため、過入力があってもデバイスの損傷を防止することが可能となる。また、前段の第1の自動利得制御回路で減衰された受信信号の利得が、利得補正部によって減衰前の利得に補正されるため、後段の第2の自動利得制御回路において第1の自動利得制御回路による影響が抑制、削減される。しかも、減衰を打ち消すタイミングで補正されるため、第1の自動利得制御回路による影響をより抑制、削減することが可能となる。この結果、第2の自動利得制御回路における収束時間が第1の自動利得制御回路に依存することなく独立して速くなり、応答性が向上する。 According to the invention of claim 1, since the gain of the received signal is attenuated by the first automatic gain control circuit, it is possible to prevent damage to the device even if there is an excessive input. In addition, since the gain of the received signal attenuated by the first automatic gain control circuit in the preceding stage is corrected to the gain before attenuation by the gain correction unit, the influence of the first automatic gain control circuit in the subsequent stage is suppressed and reduced. Moreover, since the correction is performed at a timing that cancels the attenuation, it is possible to further suppress and reduce the influence of the first automatic gain control circuit. As a result, the convergence time in the second automatic gain control circuit becomes faster independently without depending on the first automatic gain control circuit, and responsiveness is improved.

また、利得補正部において、第1の自動利得制御回路による減衰量の逆数を減衰された受信信号に乗算するため、受信信号の減衰を補正することが可能になる。しかも、減衰量の逆数を乗算するだけであるため、簡易に構成することが可能となる。 In addition, the gain correction unit multiplies the attenuated received signal by the inverse of the amount of attenuation by the first automatic gain control circuit, making it possible to correct the attenuation of the received signal. Moreover, since it only requires multiplication by the inverse of the amount of attenuation, it can be configured simply.

請求項2の発明によれば、遅延を調整して逆数を乗算するため、より適正に減衰を打ち消すことが可能となる。 According to the invention of claim 2, the delay is adjusted and the reciprocal is multiplied, making it possible to more appropriately cancel out attenuation.

この発明の実施の形態に係る受信機を示す概略構成ブロック図である。1 is a schematic block diagram showing a receiver according to an embodiment of the present invention; 内部AGCと外部AGCを備えた従来の受信機を示す概略構成ブロック図である。FIG. 1 is a schematic block diagram showing a conventional receiver equipped with an internal AGC and an external AGC.

以下、この発明を図示の実施の形態に基づいて説明する。 The present invention will be described below based on the illustrated embodiment.

図1は、この発明の実施の形態に係る受信機1を示す概略構成ブロック図である。この受信機1は、受信した信号から所望の音声周波数信号を抽出して音声を再生する装置であり、主として、A/D変換部(RF_ADC)2と、外部AGC(第1の自動利得制御回路)3と、デジタルダウンコンバータ(DDC)4と、外部AGC補正部(利得補正部)5と、チャネルフィルタ6と、内部AGC(第2の自動利得制御回路)7と、復調部8と、を備える。 Figure 1 is a schematic block diagram showing a receiver 1 according to an embodiment of the present invention. This receiver 1 is a device that extracts a desired audio frequency signal from a received signal and reproduces audio, and mainly comprises an A/D conversion unit (RF_ADC) 2, an external AGC (first automatic gain control circuit) 3, a digital down-converter (DDC) 4, an external AGC correction unit (gain correction unit) 5, a channel filter 6, an internal AGC (second automatic gain control circuit) 7, and a demodulation unit 8.

A/D変換部2は、アンテナで受信して入力されたアナログの受信信号をデジタル信号に変換するアナログ/デジタル変換器である。 The A/D conversion unit 2 is an analog/digital converter that converts the analog received signal received by the antenna and input into a digital signal.

外部AGC3は、A/D変換部2でデジタル変換された受信信号の信号レベルに応じて、デジタル変換前の受信信号の利得を減衰させる自動利得制御回路であり、A/D変換部2の上流側に配設されたアナログの可変アッテネータ31を備える。すなわち、A/D変換部2から出力された受信信号の信号レベル・強度を検出し、この信号レベルに応じた減衰量を可変アッテネータ31に出力する。そして、アンテナで受信した受信信号を可変アッテネータ31でこの減衰量だけ減衰させてA/D変換部2に入力することで、出力信号が飽和するのを防止する。ここで、外部AGC3から可変アッテネータ31に出力される減衰量は、後述する外部AGC補正部5にも出力される。 The external AGC 3 is an automatic gain control circuit that attenuates the gain of the received signal before digital conversion according to the signal level of the received signal digitally converted by the A/D conversion unit 2, and is equipped with an analog variable attenuator 31 arranged upstream of the A/D conversion unit 2. That is, it detects the signal level and strength of the received signal output from the A/D conversion unit 2, and outputs an attenuation amount according to this signal level to the variable attenuator 31. The received signal received by the antenna is then attenuated by this attenuation amount by the variable attenuator 31 and input to the A/D conversion unit 2, thereby preventing the output signal from becoming saturated. Here, the attenuation amount output from the external AGC 3 to the variable attenuator 31 is also output to the external AGC correction unit 5, which will be described later.

デジタルダウンコンバータ4は、A/D変換部2から出力された受信信号の周波数・サンプリングレートを下げるコンバータであり、これにより、チャネルフィルタ6などにおける処理時間を確保するものである。 The digital downconverter 4 is a converter that reduces the frequency and sampling rate of the received signal output from the A/D conversion unit 2, thereby ensuring processing time in the channel filter 6, etc.

外部AGC補正部5は、外部AGC3による減衰を打ち消すタイミングで、外部AGC3による減衰量の逆数を減衰された受信信号に乗算することで、該受信信号の利得を減衰前の値に補正する回路部である。すなわち、外部AGC3から伝送された減衰量の逆数となる補正値を時系列・伝送順に逆テーブル51から参照する。例えば、外部AGC3からの減衰量が-1dBの場合、+1dBに相当する振幅補正値1.122を逆テーブル51から出力する。 The external AGC correction unit 5 is a circuit unit that corrects the gain of the received signal to the value before attenuation by multiplying the attenuated received signal by the reciprocal of the amount of attenuation by the external AGC 3 at the timing to cancel out the attenuation by the external AGC 3. In other words, it references a correction value that is the reciprocal of the amount of attenuation transmitted from the external AGC 3 from the inverse table 51 in chronological order and transmission order. For example, if the amount of attenuation from the external AGC 3 is -1 dB, it outputs an amplitude correction value of 1.122, which corresponds to +1 dB, from the inverse table 51.

そして、逆テーブル51から出力された補正値を順次、デジタルダウンコンバータ4から出力された受信信号に乗算器53で乗算することで、デジタルダウンコンバータ4からの受信信号のレベルを増幅させて、減衰を補正する。この際、外部AGC3による減衰を打ち消すタイミングで増幅するように、遅延回路52で遅延させながら補正値を乗算する。すなわち、可変アッテネータ31の制御遅延、および、A/D変換部2、デジタルダウンコンバータ4による信号遅延だけ、遅延回路52で遅延、調整しながら、外部AGC3で減衰されたタイミング・信号部を増幅、補正するように補正値を乗算する。このようにして、外部AGC3による減衰を打ち消すタイミングでその減衰量の逆数を乗算することで、受信信号の利得を減衰前の状態に戻す。 Then, the received signal output from the digital down-converter 4 is sequentially multiplied by the correction value output from the inverse table 51 by the multiplier 53, thereby amplifying the level of the received signal from the digital down-converter 4 and correcting the attenuation. At this time, the correction value is multiplied while delaying by the delay circuit 52 so that the signal is amplified at a timing that cancels out the attenuation caused by the external AGC 3. In other words, the correction value is multiplied so that the timing and signal part attenuated by the external AGC 3 is amplified and corrected while delaying and adjusting only the control delay of the variable attenuator 31 and the signal delay caused by the A/D conversion unit 2 and the digital down-converter 4. In this way, the reciprocal of the attenuation amount is multiplied at a timing that cancels out the attenuation caused by the external AGC 3, thereby returning the gain of the received signal to the state before attenuation.

チャネルフィルタ6は、外部AGC補正部5で補正された受信信号の不要周波数成分を除去するフィルタである。例えば、高周波数帯域および低周波数帯域において利得が急激に低下する特性を備えたフィルタで構成することで、受信信号から不要な周波数成分を除去して受信に必要な周波数成分のみを残す。 The channel filter 6 is a filter that removes unnecessary frequency components of the received signal that has been corrected by the external AGC correction unit 5. For example, by configuring it with a filter that has a characteristic in which the gain drops sharply in the high and low frequency bands, unnecessary frequency components are removed from the received signal, leaving only the frequency components necessary for reception.

内部AGC7は、チャネルフィルタ6を通過した受信信号の利得を所定範囲に調整する自動利得制御回路である。すなわち、スピーカ(図示せず)から再生される音声レベルを安定化させるために、チャネルフィルタ6からの信号レベルに応じてその出力レベルを上げ下げする。具体的には、従来の自動利得制御回路と同様に、チャネルフィルタ6から出力された受信信号の信号レベル・強度を検出し、この信号レベルに応じて減衰器(乗算器)でチャネルフィルタ6からの受信信号のレベルを調整する。 The internal AGC 7 is an automatic gain control circuit that adjusts the gain of the received signal that has passed through the channel filter 6 to a predetermined range. That is, in order to stabilize the level of the sound reproduced from the speaker (not shown), the output level is increased or decreased according to the signal level from the channel filter 6. Specifically, like a conventional automatic gain control circuit, the signal level and strength of the received signal output from the channel filter 6 is detected, and the level of the received signal from the channel filter 6 is adjusted by an attenuator (multiplier) according to this signal level.

復調部8は、内部AGC7から出力された受信信号を音声信号に復調する復調器であり、この復調部8で復調された音声信号が、デジタル/アナログ変換器(図示せず)などを介してスピーカから出力、再生される。 The demodulation unit 8 is a demodulator that demodulates the received signal output from the internal AGC 7 into an audio signal, and the audio signal demodulated by this demodulation unit 8 is output and played from a speaker via a digital/analog converter (not shown) or the like.

このような構成の受信機1によれば、外部AGC3によって受信信号の利得が減衰されるため、過入力があってもデバイスの損傷を防止することが可能となる。また、前段の外部AGC3で減衰された受信信号のレベルが、外部AGC補正部5によって減衰を打ち消すように補正されるため、後段の内部AGC7において外部AGC3による影響が抑制、削減される。しかも、補正するタイミングを調整することで、外部AGC3による影響をより抑制、削減することが可能となる。この結果、内部AGC7における収束時間が外部AGC3に依存することなく独立して速くなり、応答性が向上する。 With a receiver 1 configured in this way, the gain of the received signal is attenuated by the external AGC 3, making it possible to prevent damage to the device even if there is excessive input. In addition, the level of the received signal attenuated by the external AGC 3 in the previous stage is corrected by the external AGC correction unit 5 to cancel out the attenuation, so that the influence of the external AGC 3 in the subsequent internal AGC 7 is suppressed and reduced. Moreover, by adjusting the timing of the correction, it is possible to further suppress and reduce the influence of the external AGC 3. As a result, the convergence time of the internal AGC 7 becomes faster independently without depending on the external AGC 3, improving responsiveness.

また、外部AGC補正部5において、外部AGC3により減衰された受信信号に減衰量の逆数を乗算することで、受信信号のレベルを補正することが可能になる。減衰量の逆数を乗算するだけであるため、簡易に構成することが可能となる。 In addition, in the external AGC correction unit 5, the level of the received signal can be corrected by multiplying the received signal attenuated by the external AGC 3 by the inverse of the attenuation amount. Since it only requires multiplication by the inverse of the attenuation amount, it can be configured simply.

以上、この発明の実施の形態について説明したが、具体的な構成は、上記の実施の形態に限られるものではなく、この発明の要旨を逸脱しない範囲の設計の変更等があっても、この発明に含まれる。 Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above embodiment, and even if there are design changes within the scope of the invention that do not deviate from the gist of the invention, they are included in the invention.

1 受信機
2 A/D変換部
3 外部AGC(第1の自動利得制御回路)
4 デジタルダウンコンバータ
5 外部AGC補正部(利得補正部)
51 逆テーブル
52 遅延回路
6 チャネルフィルタ
7 内部AGC(第2の自動利得制御回路)
8 復調部
1 Receiver 2 A/D conversion section 3 External AGC (first automatic gain control circuit)
4 Digital down converter 5 External AGC correction section (gain correction section)
51 Inverse table 52 Delay circuit 6 Channel filter 7 Internal AGC (second automatic gain control circuit)
8 Demodulation section

Claims (1)

デジタル変換された受信信号の信号レベルに応じてデジタル変換前の受信信号の利得を減衰させる第1の自動利得制御回路と、
前記減衰を打ち消すタイミングで、前記第1の自動利得制御回路による減衰量の逆数を前記減衰されデジタル変換された受信信号に乗算することで、該受信信号の利得を減衰前の値に補正する利得補正部と、
前記補正された受信信号の不要周波数成分を除去するチャネルフィルタと、
前記チャネルフィルタを通過した受信信号の利得を所定範囲に調整する第2の自動利得制御回路と、
を備え
前記利得補正部は、前記第2の自動利得制御回路において前記第1の自動利得制御回路による影響が抑制されるように、遅延を調整して前記逆数を乗算することで前記減衰を打ち消す、
ことを特徴とする受信機。
a first automatic gain control circuit for attenuating a gain of a received signal before digital conversion in accordance with a signal level of the digitally converted received signal;
a gain correction unit that corrects the gain of the received signal to a value before attenuation by multiplying the attenuated and digitally converted received signal by the reciprocal of the amount of attenuation by the first automatic gain control circuit at a timing to cancel the attenuation;
a channel filter for removing unnecessary frequency components of the corrected received signal;
a second automatic gain control circuit that adjusts the gain of the received signal that has passed through the channel filter within a predetermined range;
Equipped with
the gain correction unit cancels the attenuation by adjusting a delay and multiplying the reciprocal so that an effect of the first automatic gain control circuit is suppressed in the second automatic gain control circuit;
23. A receiver comprising:
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252868A (en) 1999-03-01 2000-09-14 Toshiba Corp CDMA communication device and automatic gain control circuit therefor
JP2005348440A (en) 1998-11-12 2005-12-15 Nokia Corp Automatic gain control method and apparatus
JP2005539412A (en) 2002-04-10 2005-12-22 ノキア コーポレイション CDMA signal power estimation apparatus and method
JP2007281633A (en) 2006-04-04 2007-10-25 Niigata Seimitsu Kk Receiving machine

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005348440A (en) 1998-11-12 2005-12-15 Nokia Corp Automatic gain control method and apparatus
JP2000252868A (en) 1999-03-01 2000-09-14 Toshiba Corp CDMA communication device and automatic gain control circuit therefor
JP2005539412A (en) 2002-04-10 2005-12-22 ノキア コーポレイション CDMA signal power estimation apparatus and method
JP2007281633A (en) 2006-04-04 2007-10-25 Niigata Seimitsu Kk Receiving machine

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