JP7638643B2 - Semiconductor device and electronic device - Google Patents

Description

The present invention relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In addition, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. In particular, one aspect of the present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor.

In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Display devices, electro-optical devices, semiconductor circuits, and electronic devices may include semiconductor devices.

Technology for constructing transistors using semiconductor materials has been attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor materials that can be used for transistors, but oxide semiconductors are also attracting attention as other materials.

Patent Document 1 discloses an example in which a transistor having an oxide semiconductor in a channel formation region (hereinafter referred to as an "oxide semiconductor transistor") is used in a dynamic random access memory (DRAM). Since oxide semiconductor transistors have a very small leakage current (off current) in the off state, it is possible to fabricate a DRAM with a long refresh period and low power consumption.

Patent document 2 also discloses a nonvolatile memory using oxide semiconductor transistors. Unlike flash memory, these nonvolatile memories have no limit to the number of times they can be rewritten, can easily achieve high-speed operation, and consume little power.

Patent Document 2 also discloses an example in which a second gate is provided in an oxide semiconductor transistor to control the threshold voltage of the transistor and reduce the off-state current of the transistor.

Patent Documents 2 and 3 also disclose examples of circuit configurations for driving the second gate described above.

JP 2013-168631 A JP 2012-069932 A JP 2012-146965 A

One embodiment of the present invention has an object to provide a memory device capable of retaining data for a long period of time. One embodiment of the present invention has an object to provide a memory device capable of suppressing power consumption. One embodiment of the present invention has an object to provide a semiconductor device capable of retaining data for a long period of time. One embodiment of the present invention has an object to provide a semiconductor device capable of suppressing power consumption. One embodiment of the present invention has an object to provide a novel semiconductor device.

Note that the description of multiple problems does not preclude the existence of each problem. Note that one embodiment of the present invention does not need to solve all of these problems. Furthermore, problems other than those listed will become apparent from the description in the specification, drawings, claims, etc., and these problems may also be problems of one embodiment of the present invention.

One aspect of the present invention is a semiconductor device having a memory circuit having a first transistor and a voltage holding circuit having a second transistor and a capacitor, the first transistor having a gate and a backgate, the capacitor having a first electrode, a second electrode, and a ferroelectric layer, the ferroelectric layer being provided between the first electrode and the second electrode, one of the first electrode or the second electrode being electrically connected to the gate of the second transistor, the other of the first electrode or the second electrode being electrically connected to a terminal that applies a voltage that inverts the polarization of the ferroelectric layer, and one of the source or drain of the second transistor being electrically connected to the backgate of the first transistor.

One aspect of the present invention is a semiconductor device having a memory circuit with a first transistor, a voltage holding circuit with a second transistor and a capacitor, and a negative voltage generating circuit, the first transistor having a gate and a backgate, the capacitor having a first electrode, a second electrode, and a ferroelectric layer, the ferroelectric layer being provided between the first electrode and the second electrode, one of the first electrode or the second electrode being electrically connected to the gate of the second transistor, the other of the first electrode or the second electrode being electrically connected to a terminal that applies a voltage that inverts the polarization of the ferroelectric layer, one of the source or drain of the second transistor being electrically connected to the backgate of the first transistor, and the other of the source or drain of the second transistor being electrically connected to the negative voltage generating circuit.

In one aspect of the present invention, the first transistor and the second transistor are preferably transistors having an oxide semiconductor in the channel.

In one aspect of the present invention, the ferroelectric layer of the semiconductor device preferably has hafnium oxide and/or zirconium oxide.

One aspect of the present invention is an electronic device having the semiconductor device described above.

Other aspects of the present invention are described in the "Description of Embodiments" and "Drawings" below.

According to one embodiment of the present invention, it is possible to provide a storage device capable of retaining data for a long period of time. According to one embodiment of the present invention, it is possible to provide a storage device capable of suppressing power consumption. According to one embodiment of the present invention, it is possible to provide a semiconductor device capable of retaining data for a long period of time. According to one embodiment of the present invention, it is possible to provide a semiconductor device capable of suppressing power consumption. According to one embodiment of the present invention, it is possible to provide a novel semiconductor device.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc.

1A and 1B are circuit diagrams illustrating examples of circuits according to one embodiment of the present invention. FIG. 2 is a circuit diagram illustrating an example of a circuit according to one embodiment of the present invention. Fig. 3A is a diagram showing a configuration example of a memory cell, and Fig. 3B is a diagram showing a configuration example of a memory device. 4A is a diagram showing an example of the configuration of a memory cell, and FIG 4B is a diagram showing an example of the configuration of a memory device. FIG. 5 is a diagram illustrating an example of a register configuration. 6A to 6C are diagrams illustrating examples of the structure of transistors. FIG. 7 is a diagram illustrating an example of the configuration of a CPU. FIG. 8 is a diagram illustrating an example of an electronic device. Fig. 9A is a diagram for explaining a cross-sectional structure of a sample according to an embodiment, Fig. 9B is a diagram showing an input voltage waveform, and Fig. 9C is a diagram showing a measurement result of the sample according to an embodiment.

The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that the form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations are omitted. Also, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be used.

Note that in each figure described in this specification, the size of each component, the thickness of a layer, or the area may be exaggerated for clarity. Therefore, they are not necessarily limited to the scale.

(Embodiment 1)
In this embodiment, a circuit configuration of a semiconductor device which is one embodiment of the present invention will be described.

The circuit 100 shown in FIG. 1 shows the circuit configuration of a semiconductor device for driving the second gate of the transistor ME. The semiconductor device shown in FIG. 1 has an input terminal VBG, an input terminal VLS, a memory cell array MCA, a circuit 100 electrically connected to the memory cell array MCA, a negative voltage generating circuit NBG, and a circuit CP. The memory cell array MCA has a plurality of memory cells MC, and each memory cell MC has a transistor M0 having a first and second gate. The transistor M0 can be, for example, a write transistor in the memory cell MC (or a write/read transistor depending on the configuration of the memory cell MC).

The circuit 100 has a transistor M1, a capacitance element C1, and a capacitance element FEC.

The second gate of transistor M0 has a function of controlling the threshold voltage (Vth) of transistor M0. For example, if transistor M0 is an n-channel transistor, applying a potential lower than the source potential to the second gate of transistor M0 can shift the Vth of transistor M0 in the positive direction and reduce the off-current at Vgs = 0V (can be set to a normally-off state). On the other hand, applying a potential higher than the source potential to the second gate of transistor M0 can shift the Vth of transistor M0 in the negative direction and allow an on-current to flow at Vgs = 0V (can be set to a normally-on state).

The first gate of transistor M0 and the second gate of transistor M0 have an overlapping region with a semiconductor layer therebetween.

The first gate of transistor M1 is electrically connected to the first terminal (also called electrode) of the capacitive element FEC. One of the source and drain of transistor M1 is electrically connected to the input terminal VBG. The other of the source and drain of transistor M1 is electrically connected to the wiring BGL. The input terminal VBG is electrically connected to the negative voltage generation circuit NBG.

The wiring BGL is electrically connected to the second gates of each of the multiple transistors M0.

The first terminal of the capacitance element C1 is electrically connected to the other of the source and drain of the transistor M1 and the wiring BGL. The second terminal of the capacitance element C1 is electrically connected to the wiring GNL. Note that a constant potential is applied to the wiring GNL. The constant potential may be a ground potential.

The input terminal VLS is electrically connected to the second terminal (also called electrode) of the capacitive element FEC. In addition, the input terminal VLS is electrically connected to the circuit CP.

The transistor M1 is preferably a transistor with low off-state current. For example, the off-state current of the transistor M1 is preferably 10 ⁻¹⁸ A/μm or less, more preferably 10 ⁻²¹ A/μm or less, further preferably 10 ⁻²⁴ A/μm or less. An example of a transistor with low off-state current is an oxide semiconductor transistor.

Note that in this specification, unless otherwise specified, the off-state refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which a voltage (Vgs) between a gate and a source is lower than Vth in an n-channel transistor, and a state in which Vgs is higher than Vth in a p-channel transistor. For example, the off-state current of an n-channel transistor may refer to a drain current when Vgs is lower than Vth. The off-state current of a transistor may depend on Vgs. Therefore, the off-state current of a transistor being 10 ⁻²¹ A or less may refer to the presence of a Vgs value at which the off-state current of the transistor is 10 ⁻²¹ A or less. The off-state current of a transistor may refer to an off-state at a predetermined Vgs, an off-state at a Vgs within a predetermined range, an off-state at a Vgs at which a sufficiently reduced off-state current is obtained, or the like.

In addition, in this specification, the off-current of a transistor having a channel width (W) may be expressed as a current value flowing per channel width. It may also be expressed as a current value flowing per a given channel width (e.g., 1 μm). In the latter case, the unit of the off-current may be expressed in a unit having the dimension of current/length (e.g., A/μm).

The off-current of a transistor may also depend on temperature. In this specification, unless otherwise specified, the off-current may refer to the off-current at room temperature, 60°C, 85°C, 95°C, or 125°C. Alternatively, it may refer to the off-current at a temperature at which the reliability of a semiconductor device or the like including the transistor is guaranteed, or at a temperature at which a semiconductor device or the like including the transistor is used (e.g., any one of temperatures from 5°C to 35°C).

The off-current of a transistor may depend on the voltage (Vds) between the drain and source. In this specification, unless otherwise specified, the off-current may refer to the off-current at an absolute value of Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, it may refer to the Vds at which the reliability of a semiconductor device or the like including the transistor is guaranteed, or the off-current at the Vds used in a semiconductor device or the like including the transistor.

In addition, in FIG. 1A, transistor M1 is illustrated with not only a first gate but also a second gate, and although the electrical connection destination of the second gate is not specified, the electrical connection destination of the second gate can be determined at the design stage. For example, in a transistor having a second gate, the first gate and the second gate may be electrically connected to increase the on-current of the transistor. Also, for example, in a transistor having a second gate, wiring electrically connected to an external circuit or the like may be provided to vary the threshold voltage of the transistor or reduce the off-current of the transistor, and a fixed potential or a variable potential may be applied to the second gate of the transistor by the external circuit or the like.

The capacitive element FEC is a capacitive element that has a material that can have ferroelectricity as a dielectric between two electrodes. In this specification, a capacitor that uses a material that can have ferroelectricity as a dielectric is called a ferroelectric capacitor.

Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, HfZrO _x (X is a real number greater than 0), materials in which element J (here, element J is silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added to hafnium oxide, yttria-stabilized zirconia (YSZ), PbTiO _x , barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium tantalate bismuthate (SBT), bismuth ferrite (BFO), barium titanate, etc. Also, as the material, a piezoelectric ceramic having a perovskite structure may be used. Also, as the material, for example, a plurality of materials selected from the materials listed above, or a laminate structure consisting of a plurality of materials selected from the materials listed above, may be used. Incidentally, the crystal structure (characteristics) of hafnium oxide can change not only depending on the film formation conditions but also on the composition of the upper and lower films or the process, and therefore in this specification and the like, ferroelectrics are not used to refer to only materials that exhibit ferroelectricity, but rather to materials that can have ferroelectricity or that are made to have ferroelectricity.

Among these, hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferred as a material that can have ferroelectricity, since it can be processed into a thin film of a few nm. By making it into a ferroelectric layer that can be thinned, it can be made into a semiconductor device that is combined with miniaturized transistors.

A material that can have ferroelectricity is an insulator that is polarized internally when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero, so it can be used as a non-volatile memory element. Therefore, by using this material as a dielectric sandwiched between a pair of electrodes of a capacitance, the capacitance can be made into a "capacitor that can have ferroelectricity" or a "ferroelectric capacitor." In addition, in this specification, etc., the material that can have ferroelectricity may be said to be between the first terminal and the second terminal of the capacitor. Note that a memory circuit using a capacitor that can have ferroelectricity may be called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc.

The circuit CP functions as a voltage generating circuit. For example, the voltage generated by the circuit CP can be a low-level potential, a negative voltage, etc. The voltage generated by the circuit CP is input to the terminal VSL of the circuit 100.

Here, when a voltage generated by the circuit CP, for example a low-level potential, is input to the terminal VSL, the low-level potential is applied to the second terminal of the capacitance element FEC. At this time, the potential of the first gate of the transistor M1 drops due to the capacitive coupling of the capacitance element FEC. Also, when the potential difference between the first terminal and the second terminal of the capacitance element FEC reaches a specific potential difference, polarization occurs in the dielectric of the capacitance element FEC, which may have ferroelectricity. By causing polarization in the dielectric of the capacitance element FEC, which may have ferroelectricity, the potential applied to the first gate of the transistor M1 can be maintained by the capacitance element FEC even if the supply of the low-level potential from the circuit CP to the terminal VSL is stopped.

The negative voltage generation circuit NBG has a function of generating a negative voltage. The negative voltage generation circuit NBG generates a negative voltage and supplies the negative voltage to the input terminal VBG of the circuit 100.

Note that the semiconductor device of one embodiment of the present invention is not limited to the circuit configuration in FIG. 1(A). The semiconductor device of one embodiment of the present invention may have a configuration in which the circuit configuration in FIG. 1(A) is changed depending on the situation. For example, the semiconductor device of one embodiment of the present invention may have a configuration in which the capacitor C1 is not provided in the circuit 100 as shown in FIG. 1(B).

In addition, in FIG. 1A, the memory cell MC electrically connected to the wiring BGL is a memory cell MC located in one row of the memory cell array MCA, but one embodiment of the present invention is not limited to this. For example, as shown in FIG. 2, the wiring BGL may be extended to divide the memory cell array MCA into multiple rows, and the wiring BGL may be electrically connected to the second gate of each of the transistors M0 of the multiple memory cells MC arranged in a matrix. With this configuration, it is not necessary to provide a circuit 100 for each row, and therefore the circuit area of the semiconductor device can be reduced.

Next, an example of the operation of the semiconductor device shown in FIG. 1(A) will be described.

In the initial state, the negative voltage generating circuit NBG does not supply a negative voltage to the input terminal VBG. Also, for example, at this time, the negative voltage generating circuit NBG may supply a ground potential to the input terminal VBG.

Also, a low-level potential (which may be a negative voltage) is supplied from the circuit CP to the input terminal VLS. The low-level potential at this time is designated as _VL . This causes polarization in the dielectric of the capacitance element FEC, which may have ferroelectricity, and an electric field is generated in the direction from the second terminal to the first terminal of the capacitance element FEC. Also, due to the capacitive coupling of the capacitance FEC, the first gate of the transistor M1 drops from its original potential. The dropped potential of the first gate of the transistor M1 is designated as _VG .

After the potential of the first gate of the transistor M1 is set to _VG , the supply of the low-level potential from the circuit CP to the input terminal VLS may be stopped.

Here, a negative voltage is supplied from the negative voltage generating circuit NBG to the input terminal VBG. The negative voltage is denoted as _VBG . Here, in the transistor M1, when _VG - _VBG is larger than the threshold voltage of the transistor M1, the transistor M1 is turned on and the negative voltage _VBG is supplied to the wiring BGL. Note that even when _VG - _VBG is smaller than the threshold voltage of the transistor M1 and the transistor M1 operates in the subthreshold region, the negative voltage _VBG can be supplied to the wiring BGL.

As a result, the negative voltage VBG is supplied from the negative voltage generation circuit NBG to the wiring _BGL through the transistor M1. After the voltage of the wiring BGL reaches the negative voltage _VBG , a potential ( _VLL ) lower than _VL is supplied from the circuit CP to the input terminal VLS. This allows the potential _VG of the first gate of the transistor M1 to be lowered by capacitive coupling of the capacitor FEC. At this time, even if the supply of _VLL from the circuit CP is stopped, the potential of the first gate of the transistor M1 can be held by the capacitor FEC. This allows the transistor M1 to be turned off, and as a result, the voltage of the wiring BGL can be held at the negative voltage _VBG .

By holding the negative voltage _VBG on the wiring BGL, the threshold voltage of the transistor M0 can be lowered. Since the transistor M0 functions as a write transistor for the memory cell MC, the off-leak current of the transistor M0 can be reduced by lowering the threshold voltage of the transistor M0. As a result, data written to the memory cell MC can be held for a long time.

The configuration shown in this embodiment can be combined as appropriate with the configurations shown in other embodiments or examples.

(Embodiment 2)
In this embodiment mode, an application example of a semiconductor device including the circuit 100 described in Embodiment 1 will be described.

<Non-volatile memory>
FIG. 3A shows a circuit configuration of a memory cell MC having a function as a memory element.

The memory cell MC in FIG. 3A includes a transistor M0 having a first gate and a second gate, a transistor 112, a capacitor 114, a node FN, a wiring BL, a wiring SL, a wiring WL, a wiring RL, and a wiring BGL.

In the memory cell MC in FIG. 3A, the first gate of the transistor M0 is electrically connected to the wiring WL, the second gate of the transistor M0 is electrically connected to the wiring BGL, one of the source and drain of the transistor M0 is electrically connected to the wiring BL, and the other of the source and drain of the transistor M0 is electrically connected to the node FN.

In the memory cell MC in FIG. 3A, the gate of the transistor 112 is electrically connected to the node FN, one of the source and drain of the transistor 112 is electrically connected to the wiring BL, and the other of the source and drain of the transistor 112 is electrically connected to the wiring SL.

In the memory cell MC in FIG. 3A, the first terminal of the capacitor 114 is electrically connected to the wiring RL, and the second terminal of the capacitor 114 is electrically connected to the node FN.

The transistor M0 is preferably a transistor with low off-state current. For example, the off-state current of the transistor M0 is preferably 10 ⁻¹⁸ A/μm or less, more preferably 10 ⁻²¹ A/μm or less, further preferably 10 ⁻²⁴ A/μm or less. An example of a transistor with low off-state current is an oxide semiconductor transistor.

It is preferable that a transistor with small threshold voltage variation is used as the transistor 112. Here, a transistor with small threshold voltage variation refers to a transistor that can be formed with an allowable threshold voltage difference of 100 mV or less when the transistors are manufactured in the same process. Specifically, an example of such a transistor is one in which the channel is formed of single crystal silicon.

By taking advantage of the feature of node FN being able to retain an electric charge, memory cell MC is able to write, retain, and read information as follows.

The writing and retention of information will be described. First, a potential is applied to the wiring WL so that the transistor M0 is turned on. As a result, the potential of the wiring BL is applied to the node FN. That is, a predetermined charge is applied to the node FN (writing). Here, one of two charges that provide different potential levels (hereinafter referred to as a low level and a high level) is applied. After that, the charge applied to the node FN is retained (retained) by turning off the transistor M0.

Because the off-state current of transistor M0 is extremely small, the charge on the gate of transistor M0 is retained for a long time.

Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the wiring SL and an appropriate potential (read potential) is applied to the wiring RL, the potential of the wiring BL fluctuates according to the amount of charge held in the gate of the transistor 112. In general, if the transistor 112 is a p-channel type, the apparent threshold value Vth_H when a high level is applied to the node FN is lower than the apparent threshold value Vth_L when a low level is applied to the node FN. Here, the apparent threshold voltage refers to the potential of the wiring RL required to make the transistor 112 "on". Therefore, the charge applied to the gate of the transistor 112 can be determined by setting the potential of the wiring RL to a potential V0 between Vth_H and Vth_L. For example, when a low level is applied in writing, if the potential of the node FN becomes V0 (<Vth_L), the transistor 112 becomes "on". When a high level is applied, even if the potential of the node FN becomes V0 (>Vth_H), the transistor 112 remains in the "off state." Therefore, by determining the potential of the wiring BL, the stored data can be read.

In the above description, transistor 112 is a p-channel transistor, but this is not limited thereto, and transistor 112 may also be an n-channel transistor.

Figure 3 (B) shows the circuit configuration of a memory device 120 that has memory cells MC arranged in a matrix and the circuit 100 shown in embodiment 1. The memory device 120 functions as a non-volatile memory.

The memory device 120 has memory cells MC arranged in a matrix of m rows and n columns. Here, m and n represent natural numbers of 2 or more. The memory cell MC arranged in the mth row is electrically connected to the wiring WL[m] and wiring RL[m], and the memory cell MC arranged in the nth column is electrically connected to the wiring BL[n] and wiring SL.

The second gate of the transistor M0 included in each memory cell MC is electrically connected to the circuit 100 via the wiring BGL. That is, the circuit 100 has a function of supplying a signal that controls the second gate of the transistor M0 included in all memory cells.

By controlling the second gate of transistor M0, the circuit 100 allows transistor M0 to have an appropriate Vth, and can prevent transistor M0 from being normally on. As a result, the off-state current of transistor M0 can be reduced, and the charge written to node FN can be retained.

By configuring the storage device 120 as described above, it is possible to provide a storage device that can retain data for a long period of time even when the power is turned off.

DRAM
FIG. 4A shows a circuit configuration of a memory cell MC having a function as a memory element.

The memory cell MC in FIG. 4A includes a transistor M0 having a first gate and a second gate, a capacitor 131, a wiring BL, a wiring WL, a wiring CL, and a wiring BGL.

In the memory cell MC in FIG. 4A, the first gate of the transistor M0 is electrically connected to the wiring WL, the second gate of the transistor M0 is electrically connected to the wiring BGL, one of the source and drain of the transistor M0 is electrically connected to the wiring BL, and the other of the source and drain of the transistor M0 is electrically connected to the first terminal of the capacitor 131. The second terminal of the capacitor 131 is electrically connected to the wiring CL.

The transistor M0 is preferably a transistor with low off-state current. For example, the off-state current of the transistor M0 is preferably 10 ⁻¹⁸ A/μm or less, more preferably 10 ⁻²¹ A/μm or less, further preferably 10 ⁻²⁴ A/μm or less. An example of a transistor with low off-state current is an oxide semiconductor transistor.

The wiring WL has a function of supplying a signal that controls the on/off state of the transistor M0, and the wiring BL has a function of writing charge to the capacitor 131 through the transistor M0. After writing charge to the capacitor 131, the charge written to the capacitor 131 can be retained by turning off the transistor M0.

The charge written to the capacitor 131 flows out through the transistor M0, so it is necessary to periodically rewrite (refresh) the charge written to the capacitor 131. However, since the off-current of the transistor M0 is extremely low and only a small amount of charge flows out of the capacitor 131, the frequency of refreshing is low.

Figure 4 (B) shows the circuit configuration of a memory device 140 that has the memory cells MC shown in Figure 2 (A) arranged in a matrix and the circuit 100 shown in embodiment 1. The memory device 140 functions as a DRAM.

The memory device 140 has memory cells MC arranged in a matrix of m rows and n columns. The memory cell MC arranged in the mth row is electrically connected to a wiring WL[m], and the memory cell MC arranged in the nth column is electrically connected to a wiring BL[n]. The wiring CL is electrically connected to a terminal VC that provides a constant low potential.

The second gate of the transistor M0 included in each memory cell MC is electrically connected to the circuit 100 via the wiring BGL. That is, the circuit 100 has a function of supplying a signal that controls the second gate of the transistor M0 included in all memory cells.

By controlling the second gate of transistor M0, the circuit 100 allows transistor M0 to have an appropriate Vth, and can prevent transistor M0 from being normally on. As a result, the off-current of transistor M0 can be reduced, and the charge written to the capacitor 131 can be retained.

By configuring the memory device 140 as described above, it is possible to provide a memory device that requires less frequent refreshing and can operate with low power consumption.

Register
FIG. 5 shows an example of the configuration of the 1-bit register circuit 150. As shown in FIG.

The register circuit 150 includes a transistor M0 having a first gate and a second gate, a capacitance element 154, a node N5, and a flip-flop circuit 153.

The flip-flop circuit 153 has an inverter 151 and an inverter 152. The inverter 151 is connected in parallel and in the opposite direction to the inverter 152, and the node to which the output side of the inverter 151 is connected corresponds to the output terminal OUT of the register circuit 150.

The second gate of transistor M0 is electrically connected to circuit 100, the first gate of transistor M0 is electrically connected to input terminal Sig1, one of the source and drain of transistor M0 is electrically connected to input terminal Sig2, and the other of the source and drain of transistor M0 is electrically connected to node N5.

The first terminal of the capacitance element 154 is electrically connected to the node N5, and a constant low potential is applied to the second terminal of the capacitance element 154. This low potential may be the ground potential. In addition, the node N5 is electrically connected to the flip-flop circuit 153.

The transistor M0 is preferably a transistor with low off-state current. For example, the off-state current of the transistor M0 is preferably 10 ⁻¹⁸ A/μm or less, more preferably 10 ⁻²¹ A/μm or less, further preferably 10 ⁻²⁴ A/μm or less. An example of a transistor with low off-state current is an oxide semiconductor transistor.

The register circuit 150 stores and outputs data according to input signals from the input terminals Sig1 and Sig2. For example, when a high-level voltage is supplied to the input terminals Sig1 and Sig2, the transistor M0 turns on and a high-level voltage is input to the node N5. As a result, a low-level voltage inverted by the inverter 151 is output from the output terminal OUT of the register circuit 150, and at the same time, low-level voltage data is stored in the flip-flop circuit 153. On the other hand, when a low-level voltage is input from the input terminal Sig2, a high-level voltage is similarly output from the output terminal OUT and the high-level voltage data is stored in the flip-flop circuit 153.

Capacitive element 154 has the function of holding the voltage of node N5.

After writing a potential from the input terminal Sig2 to the node N5, the register circuit 150 turns off the transistor M0, so that the potential of the node N5 can be maintained even when the supply of the power supply voltage is stopped. This is because the off-current of the transistor M0 is extremely small. In other words, by using the register circuit 150, it is possible to provide a memory device that can retain data even when the supply of the power supply voltage is stopped.

The circuit 100 also has a function of supplying a signal that controls the second gate of the transistor M0. By the circuit 100 controlling the second gate of the transistor M0, the transistor M0 can have an appropriate Vth, and the transistor M0 can be prevented from being normally on. As a result, the off-current of the transistor M0 can be reduced, and the charge written to the node N5 can be retained.

In this embodiment, a simple configuration using two inverter circuits is shown as an example of the flip-flop circuit 153, but the present invention is not limited to this, and a configuration using a clocked inverter capable of clock operation, or a configuration combining a NAND circuit and an inverter can be used as appropriate. For example, known flip-flop circuits such as RS type, JK type, D type, and T type can be used as appropriate.

The configuration shown in this embodiment can be combined as appropriate with the configurations shown in other embodiments or examples.

(Embodiment 3)
In this embodiment, a structural example of a transistor that can be applied to the semiconductor device described in the above embodiment will be described.

Figure 6(A) is a top view of transistor 500, which is a transistor that can be used in the semiconductor device described in the above embodiment. Figure 6(B) is a cross-sectional view of the portion L1-L2 indicated by the dashed line in Figure 6(A), which is a cross-sectional view in the channel length direction of transistor 500. Figure 6(C) is a cross-sectional view of the portion W1-W2 indicated by the dashed line in Figure 6(A), which is a cross-sectional view in the channel width direction of transistor 500. Transistor 500 can be used as an OS transistor, for example, transistor M0, included in the semiconductor device described in the above embodiment.

As shown in FIG. 6A to FIG. 6C, the transistor 500 can be provided in the insulator 512. The transistor 500 has a conductor 503 disposed so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed therebetween overlapping with the conductors 542a and 542b, an insulator 545 disposed on the bottom and side surfaces of the opening, and a conductor 560 disposed on the formation surface of the insulator 545.

As shown in FIGS. 6A to 6C, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. As shown in FIGS. 6A to 6C, it is preferable that the conductor 560 has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. As shown in FIGS. 6A to 6C, it is preferable that an insulator 574 is disposed over the insulator 580, the conductor 560, and the insulator 545.

Note that in this specification, oxide 530a and oxide 530b may be collectively referred to as oxide 530.

Note that, in the transistor 500, a structure in which two layers of oxide 530a and oxide 530b are stacked in the region where the channel is formed and in the vicinity thereof is shown, but the present invention is not limited to this. For example, a single layer of oxide 530b or a stacked structure of three or more layers may be provided.

In addition, in the transistor 500, the conductor 560 is shown as having a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. In addition, the transistor 500 shown in Figures 6(A) to 6(C) is one example, and is not limited to this structure, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc.

Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode and drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and the conductor 542b. This makes it possible to improve the switching speed of the transistor 500 and provide it with high frequency characteristics.

The conductor 560 may function as a first gate (also referred to as a gate or a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a back gate or a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 and reduce the off-current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V, compared to when a negative potential is not applied.

The conductor 503 is arranged so as to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered.

In this specification, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. The S-channel configuration disclosed in this specification is different from the fin type configuration and the planar type configuration. By adopting the S-channel configuration, it is possible to increase the resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is less likely to occur.

The conductor 503 is formed such that the conductor 503a is in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is formed further inward. Note that, although the transistor 500 shows a structure in which the conductor 503a and the conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or a stacked structure of three or more layers.

Here, the conductor 503a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms, etc. (the impurities are less likely to permeate). Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or oxygen.

For example, conductor 503a has the function of suppressing the diffusion of oxygen, which can prevent conductor 503b from being oxidized and causing a decrease in conductivity.

When the conductor 503 also functions as a wiring, it is preferable that the conductor 503b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that in this embodiment, the conductor 503 is illustrated as a stack of conductors 503a and 503b, but the conductor 503 may have a single layer structure.

Insulator 520, insulator 522, and insulator 524 function as a second gate insulating film.

Here, the insulator 524 in contact with the oxide 530 is preferably an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating may be referred to as "excess oxygen". That is, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (also referred to as V _O ) in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved. Note that when hydrogen enters the oxygen vacancies in the oxide 530, the vacancies (hereinafter sometimes referred to as V _O H) may function as donors and generate electrons that are carriers. In addition, some of the hydrogen may bond to oxygen that is bonded to a metal atom and generate electrons that are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. In addition, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field, and therefore, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, it is preferable to reduce _VOH in the oxide 530 as much as possible to make it highly pure and intrinsic or substantially highly pure and intrinsic. In order to obtain an oxide semiconductor with sufficiently reduced _VOH , it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygenation treatment"). By using an oxide semiconductor with sufficiently reduced impurities such as _VOH for a channel formation region of a transistor, stable electrical characteristics can be imparted.

Specifically, it is preferable to use an oxide material from which part of oxygen is released by heating as an insulator having an excess oxygen region. The oxide from which oxygen is released by heating is an oxide film from which the amount of oxygen released, calculated as oxygen atoms, is 1.0×10 ¹⁸ atoms/cm ³ or more, preferably 1.0×10 ¹⁹ atoms/cm ³ or more, more preferably 2.0×10 ¹⁹ atoms/cm ³ or more, or 3.0×10 ²⁰ atoms/cm ³ or more, in TDS (Thermal Desorption Spectroscopy) analysis. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

The insulator having the excess oxygen region may be brought into contact with the oxide 530 and one or more of heat treatment, microwave treatment, and RF treatment may be performed. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 in which the bond of VoH is broken, in other words, a reaction of " _VOH →Vo+H" occurs, and dehydrogenation can be performed. At this time, some of the generated hydrogen may be combined with oxygen to become H ₂ O and removed from the oxide 530 or an insulator near the oxide 530. Some of the hydrogen may be gettered to the conductor 542a and the conductor 542b.

In addition, the microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530. In addition, the pressure of the microwave treatment may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, for example, oxygen and argon are used as gases to be introduced into the apparatus for performing the microwave treatment, and the oxygen flow ratio (O ₂ /(O ₂ +Ar)) is 50% or less, preferably 10% or more and 30% or less.

In addition, in a manufacturing process of the transistor 500, it is preferable to perform heat treatment in a state where the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This makes it possible to supply oxygen to the oxide 530 and reduce oxygen vacancies (V _O ). The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher in order to compensate for desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, a heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, and then a heat treatment may be performed successively in a nitrogen gas or inert gas atmosphere.

Note that by performing oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo+O→null" can be promoted. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 530, so that the hydrogen can be removed as _H2O (dehydrated). This can prevent hydrogen remaining in the oxide 530 from recombining with the oxygen vacancies to form _VOH .

In addition, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

The insulator 522 has a function of suppressing the diffusion of oxygen or impurities, so that the oxygen contained in the oxide 530 does not diffuse toward the insulator 520, which is preferable. In addition, the conductor 503 can be suppressed from reacting with the oxygen contained in the insulator 524 or the oxide 530.

The insulator 522 is preferably a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba,Sr)TiO ₃ (BST). As transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials that have the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to permeate). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 or the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulators.

The insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. In addition, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain an insulator 520 having a layered structure that is thermally stable and has a high dielectric constant.

Note that in the transistor 500 in FIG. 6(A) to FIG. 6(C), the insulator 520, the insulator 522, and the insulator 524 are illustrated as the second gate insulating film having a three-layer stack structure, but the second gate insulating film may have a single layer, two layers, or a stack structure of four or more layers. In that case, it is not limited to a stack structure made of the same material, and may be a stack structure made of different materials.

The transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as the oxide 530.

The metal oxide functioning as an oxide semiconductor may be formed by sputtering or atomic layer deposition (ALD). The metal oxide functioning as an oxide semiconductor will be described in detail in other embodiments.

In addition, the metal oxide that functions as the channel formation region in oxide 530 is preferably a metal oxide having a band gap of preferably 2 eV or more, more preferably 2.5 eV or more. In this way, by using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

By having oxide 530a below oxide 530b, oxide 530 can suppress the diffusion of impurities from components formed below oxide 530a to oxide 530b.

The oxide 530 preferably has a laminated structure of multiple oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of element M among the constituent elements is preferably greater than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, in the metal oxide used for the oxide 530b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

It is also preferable that the energy of the conduction band minimum of oxide 530a is higher than the energy of the conduction band minimum of oxide 530b. In other words, it is also preferable that the electron affinity of oxide 530a is smaller than the electron affinity of oxide 530b.

Here, at the junction between oxide 530a and oxide 530b, the energy level of the conduction band minimum changes gradually. In other words, the energy level of the conduction band minimum at the junction between oxide 530a and oxide 530b changes continuously or can be said to be a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

Specifically, by having oxide 530a and oxide 530b have a common element other than oxygen (as a main component), a mixed layer with a low defect level density can be formed. For example, when oxide 530b is In-Ga-Zn oxide, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like as oxide 530a.

At this time, the main carrier path is oxide 530b. By configuring oxide 530a as described above, the defect state density at the interface between oxide 530a and oxide 530b can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable. Furthermore, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen and oxygen.

Although FIG. 6B shows the conductor 542a and the conductor 542b as a single layer structure, they may be stacked with two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. A titanium film and an aluminum film may be stacked. A two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

There are also three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed on the above, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed on the above. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

Also, as shown in FIG. 6B, regions 543a and 543b may be formed as low-resistance regions at and near the interface of oxide 530 with conductor 542a (conductor 542b). In this case, region 543a functions as one of the source region and drain region, and region 543b functions as the other of the source region and drain region. In addition, a channel formation region is formed in the region sandwiched between regions 543a and 543b.

By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. In addition, silicon nitride oxide or silicon nitride, etc. can also be used as the insulator 544.

In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in the heat treatment in the subsequent process. Note that, if the conductors 542a and 542b are made of a material that is resistant to oxidation or a material whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.

The presence of the insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. In addition, the excess oxygen contained in the insulator 580 can prevent the conductors 542a and 542b from being oxidized.

The insulator 545 functions as a first gate insulating film. As with the insulator 524 described above, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen when heated.

Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. As with the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 545 is reduced. The film thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. The microwave treatment described above may be performed before and/or after the formation of the insulator 545.

In addition, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

The insulator 545 may have a layered structure, like the second gate insulating film. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulating films. Therefore, by making the insulator that functions as the gate insulating film a layered structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a layered structure that is thermally stable and has a high relative dielectric constant can be achieved.

The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in Figures 6(B) and 6(C), but it may have a single-layer structure or a stacked structure of three or more layers.

The conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ , etc.), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 545 and its conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. In addition, an oxide semiconductor that can be applied to the oxide 530 can be used as the conductor 560a. In that case, the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, or resin. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, silicon oxide and silicon oxide with voids are preferred because they allow for easy formation of an excess oxygen region in a later process.

It is preferable that the insulator 580 has an excess oxygen region. By providing the insulator 580 from which oxygen is released when heated, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. It is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

The opening of the insulator 580 is formed so as to overlap the region between the conductors 542a and 542b. This allows the conductor 560 to be formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b.

When miniaturizing a semiconductor device, it is necessary to shorten the gate length, but it is also necessary to ensure that the conductivity of the conductor 560 does not decrease. If the thickness of the conductor 560 is increased for this purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.

For example, the insulator 574 can be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc.

In particular, aluminum oxide has high barrier properties, and even a thin film of 0.5 nm to 3.0 nm can suppress the diffusion of hydrogen and nitrogen. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

It is also preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. As with the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 581 is reduced.

Conductor 540a and conductor 540b are arranged in the openings formed in insulators 581, 574, 580, and 544. Conductor 540a and conductor 540b are arranged opposite each other with conductor 560 in between.

The configuration shown in this embodiment can be combined as appropriate with the configurations shown in other embodiments or examples.

(Embodiment 4)
In this embodiment, a CPU including the memory device described in Embodiment 2, which can use the transistor described in Embodiment 1, will be described.

Figure 7 is a block diagram showing the configuration of an example of a CPU that uses at least a portion of the transistors described in the previous embodiment.

The CPU shown in FIG. 7 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I/F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I/F) on a substrate 1190. The substrate 1190 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 7 is merely an example showing a simplified configuration, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 7 may be one core, and multiple such cores may be included, with each core operating in parallel. Also, the number of bits that the CPU can handle in the internal arithmetic circuit or data bus may be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Furthermore, while the CPU is executing a program, the interrupt controller 1194 determines and processes interrupt requests from external input/output devices or peripheral circuits based on their priority or mask state. The register controller 1197 generates an address for the register 1196, and reads or writes to the register 1196 depending on the state of the CPU.

The timing controller 1195 also generates signals that control the timing of the operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

In the CPU shown in FIG. 7, a memory cell is provided in the register 1196. The transistor described in embodiment 1 or the memory device described in embodiment 2 can be used as the memory cell of the register 1196.

In the CPU shown in FIG. 7, the register controller 1197 selects the holding operation in the register 1196 according to instructions from the ALU 1191. That is, it selects whether the memory cells in the register 1196 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 1196. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 1196 can be stopped.

The configuration shown in this embodiment can be combined as appropriate with the configurations shown in other embodiments or examples.

(Embodiment 5)
In this embodiment, application examples of a semiconductor device according to one embodiment of the present invention will be described.

The semiconductor device according to one embodiment of the present invention can be applied to, for example, memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare, etc. Note that here, the term "computer" includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[PC expansion device]
The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

Figure 8 (A) shows an example of such an expansion device, an expansion device 6100 that is portable and has a chip capable of storing information mounted on it and that is external to a PC. The expansion device 6100 can store information using the chip by connecting it to a PC, for example, via a USB (Universal Serial Bus) or the like. Note that while Figure 8 (A) shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with a circuit for driving the semiconductor device and the like described in the above embodiment. For example, the electronic component 4700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[SD card]
The semiconductor device described in the above embodiment can be applied to an SD card which can be attached to electronic devices such as an information terminal or a digital camera.

Figure 8 (B) is a schematic diagram of the external appearance of an SD card, and Figure 8 (C) is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a board 5113. The connector 5112 functions as an interface for connecting to an external device. The board 5113 is housed in the housing 5111. The board 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the board 5113 is provided with an electronic component 4700 and a controller chip 5115. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, etc. provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.

By providing the electronic component 4700 on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. A wireless chip with wireless communication capabilities may also be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, making it possible to read and write data from and to the electronic component 4700.

[SSD]
The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

Figure 8 (D) is a schematic diagram of the appearance of an SSD, and Figure 8 (E) is a schematic diagram of the internal structure of an SSD. The SSD 5150 has a housing 5151, a connector 5152, and a board 5153. The connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. The board 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the board 5153 is provided with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing the electronic component 4700 on the back side of the board 5153 as well. A work memory is built into the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 is built with a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

The configuration shown in this embodiment can be combined as appropriate with the configurations shown in other embodiments or examples.

A film of an insulator exhibiting ferroelectricity was formed, and the change in spontaneous polarization was measured. Figure 9 (A) shows a schematic diagram of the cross-sectional structure of sample 800 used in the measurement.

<Document structure>
The sample 800 was formed by using single crystal silicon as the substrate 801. Specifically, a thermal oxide film having a thickness of 100 nm was formed as the insulator 802 on the substrate 801, tungsten (W) having a thickness of 30 nm was formed as the conductor 803a on the insulator 802, and titanium nitride (TiNx) having a thickness of 10 nm was formed as the conductor 803b on the conductor 803a. In addition, hafnium zirconium oxide (HfZrOx) having a thickness of 10 nm was formed as the insulator 804 covering the conductor 803 (the conductor 803a and the conductor 803b).

In addition, titanium nitride (TiNx) was formed to a thickness of 10 nm as conductor 805a in a portion of the region on insulator 804 that overlaps with conductor 803, and tungsten (W) was formed to a thickness of 20 nm as conductor 805b on conductor 805a. Silicon oxynitride (SiON) was also formed as insulator 806, which covers insulator 804 and conductor 805 (conductor 805a and conductor 805b).

In addition, an electrode 807 electrically connected to the conductor 805 and an electrode 808 electrically connected to the conductor 803 were formed on the insulator 806.

<Measurement>
A triangular wave with an amplitude of 3 V and a frequency of 100 Hz was applied between the electrode 807 and the conductor 803, and the change in the spontaneous polarization of the insulator 804 was measured. The input voltage waveform is shown in FIG.

The measurement results are shown in Figure 9 (C). The horizontal axis of Figure 9 (C) indicates the voltage applied between electrode 807 and conductor 803, and the vertical axis indicates the polarization amount of insulator 804. In Figure 9 (C), when the polarization amount is positive, it indicates that positive charges are biased toward one electrode (one of conductor 803 or conductor 805) and negative charges are biased toward the other electrode (the other of conductor 803 or conductor 805). Also, when the polarization amount is negative, it indicates that negative charges are biased toward one electrode and positive charges are biased toward the other electrode.

After applying voltage VPI1 between electrode 807 and conductor 803, if the applied voltage is increased, the amount of polarization increases according to curve 851. On the other hand, after applying voltage VPI2, if the applied voltage is decreased, the amount of polarization decreases according to curve 852. In other words, it can be seen that when voltage VPI1 or voltage VPI2 is applied to insulator 804, polarization reversal occurs in insulator 804, resulting in hysteresis characteristics.

Figure 9 (C) shows that the insulator 804 has hysteresis characteristics and functions as a ferroelectric.

(Additional notes regarding the present specification, etc.)
The above embodiment and each configuration in the embodiment will be described below with additional notes.

The configurations shown in each embodiment can be combined as appropriate with configurations shown in other embodiments or examples to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

In addition, the content (or a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or a part of the content) described in that embodiment and/or the content (or a part of the content) described in one or more other embodiments.

The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

In addition, a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and/or with one or more figures (or a part of it) described in another embodiment to form even more figures.

In the present specification and elsewhere, the components are classified by function in the block diagrams, which are shown as independent blocks. However, in actual circuits and the like, it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. For this reason, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately according to the situation.

In the drawings, the size, layer thickness, or area is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

In addition, the positional relationships of the components shown in the drawings are relative. Therefore, when describing the components with reference to the drawings, terms such as "above" and "below" that indicate the positional relationships may be used for convenience. The positional relationships of the components are not limited to the contents described in this specification, and may be rephrased appropriately depending on the situation.

In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is referred to as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, etc. depending on the situation.

In addition, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wirings" are formed as a single unit.

In addition, in this specification, a node can be referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, wiring, etc. can be referred to as a node.

In addition, in this specification, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

In addition, in this specification, the terms "high-level potential" and "low-level potential" do not mean any specific potential. For example, if two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, if two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

"Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positively charged carriers move, and is described as a positive current. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of current, and is expressed as a negative current. Therefore, in this specification, etc., unless otherwise specified regarding the positive/negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Additionally, statements such as "current is input to element A" can be rephrased as "current is output from element A" etc.

In this specification, A and B are connected means that A and B are electrically connected. Here, A and B are electrically connected means a connection that allows transmission of an electrical signal between A and B when an object (an element such as a switch, transistor element, or diode, or a circuit including the element and wiring) exists between A and B. Note that A and B being electrically connected includes a case where A and B are directly connected. Here, A and B being directly connected means a connection that allows transmission of an electrical signal between A and B via wiring (or electrodes) between A and B without going through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when expressed as an equivalent circuit.

In this specification, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which a current flows.

In this specification, the channel length refers to, for example, the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is on) and the gate overlap in a top view of the transistor, or in the region where the channel is formed.

In this specification, the channel width refers to, for example, the length of the area where the semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the part where the source and drain face each other in the area where the channel is formed.

In this specification, the terms "film" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer."

C1 Capacitive element L1-L2 Location M0 Transistor M1 Transistor N5 Node Sig1 Input terminal Sig2 Input terminal V0 Potential W1-W2 Location 3V Amplitude 100 Circuit 112 Transistor 114 Capacitive element 120 Memory device 131 Capacitive element 140 Memory device 150 Register circuit 151 Inverter 152 Inverter 153 Flip-flop circuit 154 Capacitive element 500 Transistor 503 Conductor 503a Conductor 503b Conductor 512 Insulator 514 Insulator 516 Insulator 520 Insulator 522 Insulator 524 Insulator 530 Oxide 530a Oxide 530b Oxide 540a Conductor 540b Conductor 542a Conductor 542b Conductor 543a Region 543b Region 544 Insulator 545 Insulator 560 Conductor 560a Conductor 560b Conductor 574 Insulator 580 Insulator 581 Insulator 800 Sample 801 Substrate 802 Insulator 803 Conductor 803a Conductor 803b Conductor 804 Insulator 805 Conductor 805a Conductor 805b Conductor 806 Insulator 807 Electrode 808 Electrode 851 Curve 852 Curve 1189 ROM interface 1190 Substrate 1191 ALU
1192 ALU controller 1193 instruction decoder 1194 interrupt controller 1195 timing controller 1196 register 1197 register controller 1198 bus interface 1199 ROM
4700 Electronic component 5110 SD card 5111 Housing 5112 Connector 5113 Board 5115 Controller chip 5150 SSD
5151 housing 5152 connector 5153 substrate 5155 memory chip 5156 controller chip 6100 expansion device 6101 housing 6102 cap 6103 USB connector 6104 substrate 6106 controller chip

Claims (4)

a memory circuit having a first transistor;
a voltage holding circuit having a second transistor and a capacitance element;
A negative voltage generating circuit having a function of generating a negative voltage,
the first transistor has a gate and a back gate;
the capacitive element includes a first electrode, a second electrode, and a ferroelectric layer;
the ferroelectric layer is provided between the first electrode and the second electrode,
one of the first electrode and the second electrode is electrically connected to a gate of the second transistor;
the other of the first electrode and the second electrode is electrically connected to a terminal for applying a first negative voltage that inverts the polarization of the ferroelectric layer;
one of a source and a drain of the second transistor is electrically connected to a back gate of the first transistor;
the other of the source and the drain of the second transistor is electrically connected to the negative voltage generating circuit,
supplying the first negative voltage to the terminal to invert the polarization of the ferroelectric layer, and then supplying a second negative voltage to the other of the source or the drain of the second transistor to turn the second transistor on;
a second negative voltage supplying portion that supplies a second negative voltage to a back gate of the first transistor via the second transistor , and then the second transistor is turned off, thereby holding the second negative voltage in the back gate of the first transistor. The semiconductor device according to claim 1, wherein the first transistor and the second transistor are transistors having an oxide semiconductor in the channel. A semiconductor device according to claim 1 or claim 2, wherein the ferroelectric layer comprises hafnium oxide and/or zirconium oxide. An electronic device having a semiconductor device according to any one of claims 1 to 3.

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