JP7640066B2 - Information processing device, process execution method, program, and recording medium - Google Patents

Description

The present invention relates to an information processing device, a process execution method, a program, and a recording medium.

In systems that use the NUMA (Non-Uniform Memory Access) architecture, technology has been reported that selects combinations of I/O (Input/Output) and CPU (Central Processing Unit), and I/O and memory to minimize access time (for example, Patent Document 1, etc.)

In addition, in recent years, non-volatile memory (universal memory) such as NVDIMM (Nonvolatile Dual In Line Memory Module) is becoming more widely used.

JP 2012-146105 A

However, there is no established technology to optimize access in a NUMA architecture equipped with non-volatile memory.

The present invention aims to provide an information processing device, a process execution method, a program, and a recording medium that enable optimization of access to data in non-volatile memory.

In order to achieve the above object, the information processing device of the present invention comprises:
An operating system unit and a plurality of memory access nodes,
Each of the memory access nodes includes a central processing unit, a memory controller, and a memory unit;
The central processing unit includes a central processing unit,
the central processing unit includes a processor core and a connection controller;
the central processing unit connects to other central processing units via the connection controller;
the memory unit includes a non-volatile memory,
the memory unit is connected to the central processing unit via the memory controller;
the operating system unit includes a process analyzer, a data identifier, and an allocation unit;
The process analysis unit analyzes a process running in the operating system unit,
The data identifying unit identifies data to be accessed by the process and an executable file of the data based on the process;
At least one of the data and the executable file is data stored in the non-volatile memory of a specific memory access node,
The allocation unit is a device that allocates the central processing unit that executes the process from the multiple memory access nodes according to the time distance required to access the non-volatile memory based on the data and the executable file.

The process execution method of the present invention includes the steps of:
An operating system unit and a plurality of memory access nodes,
Each of the memory access nodes includes a central processing unit, a memory controller, and a memory unit;
The central processing unit includes a central processing unit,
the central processing unit includes a processor core and a connection controller;
the central processing unit connects to other central processing units via the connection controller;
the memory unit includes a non-volatile memory,
the memory unit is connected to the central processing unit via the memory controller;
The operating system unit executes each step including a process analysis step, a data identification step, and an allocation step.
The process analysis step includes analyzing a process running in the operating system unit,
The data identifying step identifies data to be accessed by the process and an executable file of the data, based on the process;
At least one of the data and the executable file is data stored in the non-volatile memory of a specific memory access node,
The allocation step allocates the central processing unit for executing the process from among the plurality of memory access nodes in accordance with the time distance required to access the non-volatile memory based on the data and the executable file.

The present invention makes it possible to optimize access to data in non-volatile memory.

FIG. 1 is a diagram illustrating an example of the configuration of an apparatus according to the first embodiment. FIG. 2 is a flowchart showing an example of processing in the device of the first embodiment. FIG. 3 is a diagram illustrating an example of a process performed by the allocation unit in the device of the first embodiment. FIG. 4 is a diagram illustrating an example of a process performed by the allocation unit in the device according to the second embodiment. FIG. 5 is a diagram showing an example of processing by the swap processing unit in the device of the third embodiment. FIG. 6 is a diagram showing an example of a process for creating new data in the device of the fourth embodiment.

In the information processing device of the present invention, for example,
The allocation unit may allocate a memory access node for executing the process based on at least one of the following (1) to (4).
(1) When the identified data and the executable file are present in the same memory access node, and/or when the process does not use the data but only uses the executable file present in the memory access node, the central processing unit has a short access time to the nonvolatile memory in the memory access node. (2) When the identified data and the executable file are present in different memory access nodes, the central processing unit has a short access time to the nonvolatile memory storing either the data or the executable file that satisfies a preset profile condition. (3) When the identified executable file itself has "a function of operating in accordance with at least one of the central processing unit and the memory unit that operate when executed by a plurality of memory access nodes," the central processing unit has a short access time to the nonvolatile memory storing the identified data. (4) When the identified executable file is present in a storage other than a nonvolatile memory and the data is present in a nonvolatile memory, the central processing unit has a short access time to the nonvolatile memory storing the identified data.

In the information processing device of the present invention, for example,
The allocation unit may be configured such that, when the process changes the processor core of the central processing unit, it allocates another processor core different from the processor core that was executing the process, depending on the time distance required to access the non-volatile memory.

The information processing device of the present invention includes, for example,
Further, a swap processing unit is included,
When swapping out is necessary, the swap processing unit may create a swap area for each of the non-volatile memories of each of the memory access nodes, and swap out data in the memory of each of the central processing units to the swap area of the non-volatile memory that is close in time to access from each of the central processing units.

The information processing device of the present invention includes, for example,
Further, the method includes:
The designation unit may be configured to create a new storage area for each of the non-volatile memories, and designate, as the memory for the newly created data, the new storage area of a non-volatile memory that is close in time to access from a central processing unit that executes the process.

In the information processing device of the present invention, for example,
The allocation unit may be configured such that, when a process executing on one memory access node accesses the non-volatile memory in the other memory access node to create new data, the allocation unit allocates the process to be executed by the central processing unit in the one memory access node or the other memory access node depending on the number of the processes and the number of at least one of the data and executable files in the non-volatile memory.

In the process execution method of the present invention, for example,
The allocation step may be performed in a manner that a memory access node for executing the process is allocated based on at least one of the following (1) to (4).
(1) When the identified data and the executable file are present in the same memory access node, and/or when the process does not use the data but only uses the executable file present in the memory access node, the central processing unit has a short access time to the nonvolatile memory in the memory access node. (2) When the identified data and the executable file are present in different memory access nodes, the central processing unit has a short access time to the nonvolatile memory storing either the data or the executable file that satisfies a pre-set profile condition. (3) When the identified executable file itself has "a function of operating in accordance with at least one of the central processing unit and the memory unit that operate when executed by a plurality of memory access nodes," the central processing unit has a short access time to the nonvolatile memory that stores the identified data. (4) When the identified executable file is present in a storage other than a nonvolatile memory and the data is present in a nonvolatile memory, the central processing unit has a short access time to the nonvolatile memory that stores the identified data.

In the process execution method of the present invention, for example,
The allocation step may be such that, when the process changes the processor core of the central processing unit, another processor core different from the processor core that was executing the process is allocated depending on the time distance required to access the non-volatile memory.

The process execution method of the present invention includes, for example,
Further, a swap processing step is included,
The swap processing step may be such that, when swapping out is necessary, a swap area is created for each of the non-volatile memories of each of the memory access nodes, and data in the memory of each of the central processing units is swapped out to the swap area of the non-volatile memory that is close in time to access from each of the central processing units.

The process execution method of the present invention includes, for example,
Further, the method includes a specified step,
The designation step may be a step of creating a new storage area for each of the non-volatile memories, and designating the new storage area of a non-volatile memory that is close in time to access from a central processing unit that executes the process as the memory for the newly created data.

In the process execution method of the present invention, for example,
The allocation step may be such that, when a process executing on one memory access node accesses the non-volatile memory in the other memory access node to create new data, the process is allocated to be executed by the central processing unit in the one memory access node or the other memory access node depending on the number of the processes and the number of at least one of the data and executable files in the non-volatile memory.

In at least one of the information processing device of the present invention, the process execution method of the present invention, and the program of the present invention, for example,
The non-volatile memory may be a non-volatile dual in-line memory module (NVDIMM).

The program of the present invention is a program for causing a computer to execute each step of the method of the present invention as a procedure.

The recording medium of the present invention is a computer-readable recording medium on which the program of the present invention is recorded.

In the present invention, "non-volatile memory" refers to, for example, a non-volatile memory directly connected to a memory controller, and is also called universal memory. Non-volatile memory uses, for example, a volatile memory (DRAM (Dynamic Random Access Memory) etc.) directly connected to a central processing unit such as a CPU as the memory base. Specifically, for example, NVDIMM (Nonvolatile Dual In Line Memory Module) etc. can be mentioned. NVDIMM is, for example, a form that integrates DRAM (Dynamic Random Access Memory) work memory and NAND (Not AND) storage memory.

Next, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the following embodiment. In each of the drawings, the same parts are given the same reference numerals. Furthermore, the explanations of each embodiment can be mutually incorporated unless otherwise specified, and the configurations of each embodiment can be combined unless otherwise specified.

[Embodiment 1]
FIG. 1A is a diagram showing an example of the configuration of an information processing device 1 according to the present embodiment. As shown in FIG. 1, the device 1 includes an operating system unit 10 and a plurality of memory access nodes 20 (20a and 20b). The device 1 may further include, for example, an input/output device 30 (hereinafter referred to as IO device 30) (30a and 30b). Each part of the device 1 is connected to each other via a connection unit 100 by each interface (I/F). The number of the plurality of memory access nodes 20 is not particularly limited and may be two or more. Similarly, the number of the IO device 30 is not particularly limited and may be one or two or more.

The device 1 can also be connected to an external device, which will be described later, via the communication network. The communication network is not particularly limited and may be a known network, for example, wired or wireless. Examples of the communication network include an Internet line, WWW (World Wide Web), a telephone line, LAN (Local Area Network), SAN (Storage Area Network), DTN (Delay Tolerant Networking), and a point-to-point (P2P) network. Examples of wireless communication include WiFi (Wireless Fidelity) and Bluetooth (registered trademark). The wireless communication may be either a form in which each device communicates directly (Ad Hoc communication) or an indirect communication via an access point. The device 1 may be, for example, a personal computer (PC, e.g., desktop or notebook type) or a terminal (smartphone, tablet terminal) on which the program of the present invention is installed.

The connection unit 100 can also be connected to, for example, an external device. Examples of the external device include an external storage device (external database, etc.), a printer, an external input device, an external display device, etc. The present device 1 can be connected to an external network (the communication line network) by, for example, a communication device connected to the connection unit 100, and can also be connected to other devices via the external network. Specifically, the connection unit 100 is, for example, a bus, a serial link, etc.

The IO device 30 has an interface for exchanging data with various devices, such as a network.

FIG. 1(B) is a diagram showing an example of the configuration of a memory access node 20 of this embodiment. As shown in FIG. 1, the memory access node 20 includes a central processing unit 21, a memory controller 22, and a memory unit 23. The memory access node 20 is, for example, a node that includes a memory to be accessed. The memory access node 20 is, for example, a NUMA node that constitutes a NUMA architecture. Hereinafter, the memory access node 20 is also referred to as a NUMA node 20 or a node 20.

The central processing unit 21 includes a central processing unit 211. The central processing unit 211 includes a processor core 2111 and a connection controller 2112. Specifically, the central processing unit 21 may be in the form of a multiprocessor including a plurality of central processing units 211, or in the form of a multicore processor including a plurality of processor cores 2111 in one central processing unit 211. In addition, the present device 1 may be in the form in which each part in one central processing unit 211 is allocated to a separate NUMA node. Specifically, for example, the central processing unit 211 may be divided in half and the memory in half, and each may constitute one NUMA node. Examples of the central processing unit 211 include a CPU, a GPU, and an APU. In the present device 1, the central processing unit 21 executes, for example, the program of the present invention and other programs, and also reads and writes various information. In addition, the central processing unit 211 is connected to other central processing units via the connection controller 2112. The other central processing unit may be a central processing unit 211 in another memory access node 20, or may be a central processing unit 211 in the same memory access node 20. The connection controller 2112 enables the connection between the central processing units 211, for example, using a data transmission path. The data transmission path is not particularly limited, and may be, for example, a bus-type data transmission path such as a front-side bus (FSB) or a point-to-point (one-to-one) connection interconnect such as an Ultra Path Interconnect (UPI).

The memory controller 22, for example, controls the writing and reading of data to the memory unit 23 described below.

The memory unit 23 includes a non-volatile memory 231. The non-volatile memory 231 is the same as described above. When the central processing unit 21 is in the form of a multi-core, the non-volatile memory 231 may be, for example, a memory capable of operating in response to the operation of each processor core. The memory unit 23 may also be, for example, a memory having one or more non-volatile memory areas. The memory unit 23 is connected to the central processing unit 21 via a high-speed network via the memory controller 22. The memory unit 23 may also include, for example, a volatile memory.

The operating system unit 10 (hereinafter also referred to as the OS unit 10) includes a process analysis unit 11, a data identification unit 12, and an allocation unit 13. The operating system unit 10 may also include, for example, a swap processing unit 14 and a designation unit 15 as optional components.

The OS unit 10 runs on the memory unit 23. Furthermore, processes run on the OS unit 10 as applications. The number of processes is not particularly limited, and may be one or more. The OS unit 10 controls all memory access nodes 20 within the device 1.

Next, an example of the process execution method of this embodiment will be described based on the flowchart of FIG. 2. The process execution method of this embodiment is implemented, for example, as follows using the information processing device 1 of FIG. 1. Note that the process execution method of this embodiment is not limited to use of the information processing device 1 of FIG. 1.

First, the process analysis unit 11 analyzes a process running on the OS unit 10 (S11). Next, the data identification unit 12 identifies the data and the executable file of the data to be accessed by the process based on the process (S12). The data and the executable file are, for example, files and data stored in the non-volatile memory 231 or volatile memory of a specific memory access node. Then, the allocation unit 13 allocates the central processing unit 21 that executes the process from the multiple memory access nodes 20, i.e., the central processing unit 211 and the processor core 2111, based on the data and the executable file, according to the time distance required to access the non-volatile memory 231 (S13), and ends (END). The allocation unit 13 is also called, for example, the process scheduler unit 13, and the allocation is also called, for example, scheduling. Note that scheduling means, for example, running a process, thread, etc. on the central processing unit 211.

Specifically, this embodiment will be described with reference to FIG. 3. FIG. 3 is a diagram showing an example of processing by the allocation unit 13. In the example shown in FIG. 3, two memory access nodes 20a and 20b are shown as memory access nodes 20. In FIG. 3(A), both the data and its executable file identified by the data identification unit 12 exist on the memory unit 23a (non-volatile memory 231a) of the memory access node 20a. Note that the non-volatile memory 231a is a non-volatile memory that operates in response to the operation of the processor core 2111a of the central processing unit 21a (central processing unit 211a), and the non-volatile memory 231b is a non-volatile memory that operates in response to the operation of the processor core 2111b of the central processing unit 21b (central processing unit 211b) (hereinafter the same). Then, the allocation unit 13 determines the allocation of which process should be executed by the central processing unit 21 of which memory access node 20. In the example shown in FIG. 3A, the allocation unit 13 allocates, for the analyzed process, the central processing unit 21a (the central processing unit 211a and the processor core 2111a) that is closest in time distance to the non-volatile memory 231a of the memory access node 20a that stores both the data and its executable file. Here, the time distance to access the non-volatile memory 231 is, for example, a distance based on the access time (access speed) calculated based on factors such as physical distance, the path length of the data transmission path used for access, bandwidth (parallelism), D/A (Digital/Analog) conversion efficiency (frequency, etc.), and SW protocol efficiency. Specifically, in the example shown in FIG. 3A, for example, the time distance to access the non-volatile memory 231 and the central processing unit 21 in the same memory access node 20 is closest, such as between the non-volatile memory 231a and the central processing unit 21a of the memory access node 20a, and between the non-volatile memory 231b and the central processing unit 21b of the memory access node 20b. The next closest time distance is the time distance required for access between the non-volatile memory 231 in one memory access node 20 and the central processing unit 21 in the other memory access node 20 that are directly connected via each connection controller 2112, such as between the non-volatile memory 231a of the memory access node 20a and the central processing unit 21b of the memory access node 20b, and between the non-volatile memory 231b of the memory access node 20b and the central processing unit 21a of the memory access node 20a. Note that in this example, an example is shown in which there are two memory access nodes 20, each of which has one central processing unit 211 (central processing unit 21), but this is not limited to this. The number of memory access nodes 20 and the number of central processing units 211 may be one or more, or two or more. In other words, the distance in time required for access is determined by how many connection controllers 2112 are passed through, in other words, the number of other central processing units 211 and other memory access nodes 20 that are passed through.

Although not shown, when the process does not use the data and only uses the executable file present in the memory unit 23 in the memory access node 20, the allocation unit 13 may allocate to the analyzed process the central processing unit 21 (central processing unit 211 and processor core 2111) that is closest in time distance to the non-volatile memory 231 of the node 20 storing the executable file, as in the example shown in FIG. 3(A). When the process does not use the data, it means, for example, that the data is not identified by the data identification unit 12 and only the executable file is identified.

In FIG. 3B, the data identified by the data identification unit 12 exists on the memory unit 23b (non-volatile memory 231b), and the executable file of the data exists on the memory unit 23a (non-volatile memory 231a). That is, the data and the executable file are stored in different locations. In this case, the allocation unit 13 allocates the central processing unit 21, which is close in time to access the non-volatile memory 231 that stores either the data or the executable file that satisfies the preset profile condition, to the analyzed process. The profile condition is not particularly limited and can be set arbitrarily. Specifically, there is a condition regarding the size of the data (large or small data size, etc.). In the example shown in FIG. 3B, the data on the non-volatile memory 231b has a larger data size than the executable file on the non-volatile memory 231a, and the preset profile condition is "large data size". The allocation unit 13 then allocates to the analyzed process the central processing unit 21b (central processing unit 211b and processor core 2111b) that is closest in time to access the non-volatile memory 231b that stores the data with a large data size.

In FIG. 3C, the data identified by the data identification unit 12 exists in both the non-volatile memories 231a and 231b, and the executable file of the data exists in the non-volatile memory 231a. Specifically, the example shown in FIG. 3C is an example in the form of a database corresponding to a hypervisor, a multiprocessor, a multi-core processor, etc., and an application such as Enterprise Resource Planning. That is, the identified executable file itself has a function (also called a NUMA optimization function) that "operates optimally according to at least one of the central processing unit 21 and the memory unit 23 that operate when executed by multiple memory access nodes 20." In this way, when there is a NUMA optimization mechanism, the allocation unit 13 may allocate the central processing unit 21b (central processing unit 211b and processor core 2111b) that is close in time to the non-volatile memory 231b in which the data is stored to the analyzed process, without considering the location of the executable file, because the executable file is optimized regardless of which memory access node 20 it is executed on.

Although not shown, when the identified executable file exists in storage other than the non-volatile memory 231 (e.g., HDD, cloud storage (storage on a network), etc.) and the data exists in the non-volatile memory 231, the allocation unit 13 may allocate, to the analyzed process, a central processing unit 21 (central processing unit 211 and processor core 2111) that is close in time to access the non-volatile memory 231 in which the data is stored, as in the example shown in FIG. 3B. More specifically, for example, there may be cases where the executable file is started from a HDD rather than an NVDIMM, and the data file is read from the NVDIMM.

It is known that the access speed from a central processing unit to data in memory differs depending on whether the data is in the same memory access node as the central processing unit. In other words, access from a central processing unit executing a process to a non-volatile memory in the same memory access node as the central processing unit can be processed at high speed. However, access from a central processing unit executing a process to a non-volatile memory in another memory access node is processed at a slower speed than the access speed to the same memory access node. Specifically, if the time required for one access to a hard disk (HDD) with a slow access speed is 100, and the time required to cross another memory access node is 0.04, the difference in access from the own memory access node to the other memory access node is only 0.04%. However, in the case of a high-speed universal memory such as an NVDIMM, the time required for one access is extremely short compared to the HDD (for example, if the time required for one access to a hard disk (HDD) with a slow access speed is 100, then the time required for one access is 0.01), so the impact of 0.04, which is the time required to cross the other memory access node, is large, and there is a problem that the difference in access from the own memory access node to the other memory access node is extremely high compared to the HDD. However, according to this embodiment, by allocating a processor core before the execution of a process, access to data in the nonvolatile memory can be optimized. Therefore, according to this embodiment, for example, even when accessing a nonvolatile memory connected to one central processing unit from another central processing unit, high-speed access is possible.

In the technology of Patent Document 1, a process is executed on an arbitrary processor core, and then memory close to that CPU is allocated. However, in the present invention, the processor core (i.e., central processing unit) that executes the process is allocated based on the data and the executable file before the process is executed. As a result, the present invention can operate the process faster than the technology of Patent Document 1. Furthermore, in order to operate the process faster, the present invention can reduce the number of systems (cost) required.

[Embodiment 2]
An example of processing when changing a processor core (central processing unit) that executes a process will be described below. For the information processing device 1 and the process execution method of this embodiment, the description of the first embodiment can be applied unless otherwise specified.

In this embodiment, for example, after the step (S13) shown in FIG. 2, when the process changes the processor core 2111 of the central processing unit 21, the allocation unit 13 allocates another processor core 2111 different from the processor core 2111 that executed the process according to the time distance required for accessing the non-volatile memory 231. The other processor core 2111 may be, for example, another processor core 2111 in the same memory access node 20, or may be a processor core 2111 in another memory access node 20. That is, the allocation unit 13 allocates, for example, another processor core 2111 that is next closest in time distance required for the access to the processor core 2111 that executed the process. In this way, the allocation unit 13 can be said to reschedule the execution of the process. Note that rescheduling refers to, for example, running a process, thread, or the like again on the central processing unit.

Specifically, this embodiment will be described with reference to FIG. 4. FIG. 4 is a diagram showing an example of processing by the allocation unit 13. In the example shown in FIG. 4, two memory access nodes 20a and 20b are shown as memory access nodes 20, and two processor cores 2111a1 and 2111a2 are shown in the central processing unit 21a of the memory access node 20a. In FIG. 4(A), the data identified by the data identification unit 12 exists in the non-volatile memory 231a. When changing the processor core 2111a1 that executes the process, the allocation unit 13 does not change the memory access node 20a of the assigned processor core 2111a1, but assigns another processor core 2111a2 in the memory access node 20a. Then, the allocation allows the process to continue to be executed in the same memory access node 20a before and after the change.

On the other hand, for example, as shown in FIG. 4(B), when both the identified executable file and the data are present in the non-volatile memory 231b in the memory access node 20b and the process is being executed by the central processing unit 21a in the memory access node 20a, the allocation unit 13 newly assigns the central processing unit 21b in the memory access node 20b as the central processing unit 21 that executes the process, instead of the central processing unit 21a that executes the process, depending on the time distance required to access the non-volatile memory 231b, for example.

In this way, in this embodiment, even when the processor core 2111 (central processing unit 211) that executes a process is changed, rescheduling is performed according to the time distance required for access to the non-volatile memory 231, that is, taking into account the positions of the data and the executable file. Therefore, according to this embodiment, as in the first embodiment, access to data in the non-volatile memory can be optimized. Note that a case in which the processor core 2111 (central processing unit 211) that executes a process is changed includes, for example, a case in which, in an environment in which scheduling is performed among a plurality of processor cores 2111 and processes, the execution of the process is controlled so that the processor cores 2111 are used in sequence.

In related technologies, when caching, a process is required to move the data to be accessed closer to a central processing unit such as a CPU. In addition, when caching, intermediate processes such as writing back the original data when data is written and validating other cached information are generated. However, according to this embodiment, the data can be used directly, so there is no need to perform the above-mentioned processes, and a function equivalent to caching can be efficiently implemented.

[Embodiment 3]
An example of processing when swapping out will be described below. Unless otherwise specified, the information processing device 1 and the process execution method of this embodiment can use the descriptions of the first and second embodiments.

In this embodiment, the device 1 further includes a swap processing unit 14. FIG. 5 shows an example of processing by the swap processing unit 14. As shown in FIG. 5, the swap processing unit 14 creates a swap area, which is a memory area for swapping out, for each non-volatile memory 231 (231a and 231b) of each memory access node 20 (20a and 20b), and swaps out data in the memory of each central processing unit 21 (21a and 21b) to the swap area of the non-volatile memory 231 that is close to the time distance required for access to each central processing unit 21 (21a and 21b). "Creating a swap area for each non-volatile memory 231" can also be said to create a swap area on the non-volatile memory 231 for each processor core 2111 corresponding to the non-volatile memory 231. The swap processing unit 14 may, for example, execute the swap-out on the swap area of the non-volatile memory 231 that is closest to each central processing unit 21 in terms of the time distance required for access, or may execute the swap-out on the swap area of the non-volatile memory 231 that is next closest in terms of the time distance required for access. The memory in each processor core 2111 is, for example, a volatile memory.

Here, swapping out refers to, for example, reserving in non-volatile memory 231 an area that is the same as the memory area reserved in the memory of processor core 2111, writing the same data as that written in the memory area to the swap area (memory area) reserved in non-volatile memory 231, and releasing the memory area of the memory. Note that "cases where swapping out is necessary" include, for example, cases where the function of virtual memory is to be realized. Specifically, for example, in a server equipped with a disk with an area larger than the memory capacity, data in the unused memory area may be temporarily evacuated to the disk, and a memory capacity larger than that actually installed may be executed.

In this way, this embodiment executes swap-out in units of memory access nodes 20. According to this embodiment, like the first and second embodiments, access to data in non-volatile memory can be optimized.

[Embodiment 4]
An example of processing for creating new data will be described below. The information processing device 1 and the process execution method of this embodiment can be applied to the descriptions of the first to third embodiments, unless otherwise specified.

In this embodiment, the new data is not particularly limited, and may be, for example, newly created data or overwritten data. Specifically, for example, there is data for which the file path indicating the location where the data is to be stored is not determined, data for which the file path is already determined and which is not stored in the same memory access node, and data for which the file path is already determined and which is shared with other processes. Figure 6 shows an example of processing when creating new data. Figure 6(A) shows an example of processing for data for which the file path is not determined, and Figure 6(B) shows an example of processing for data for which the file path is already determined.

First, an example of processing in the case where the new data is data with no determined file path, such as an intermediate file, temporary file, or cache file, will be described. In this case, the device 1 may further include, for example, a designation unit 15. As shown in FIG. 6A, the designation unit 15 creates a new storage area for each non-volatile memory 231 (231a and 231b), and designates the new storage area of the non-volatile memory 231 that is close to the central processing unit 21 that executes the process as the memory for the newly created data. More specifically, as shown in FIG. 6A, for example, the process or OS unit 10 designated by the designation unit 15 creates new data (such as a temporary file) in the volatile memory 231a that is close to the central processing unit 21a that executes the process in terms of access time.

Until now, temporary files have been stored in a location specified by the temp variable, etc. Disk caches and intermediate files have been stored in temporary folders or specific SSDs. However, according to this embodiment, when creating new data, a storage location is created for each non-volatile memory 231, and the data is stored in a storage area close to the processor core 2111 that executes the process. Therefore, as in the first to third embodiments, access to data in non-volatile memory can be optimized.

Next, an example of processing in the case of data whose file path has already been determined as the new data will be described. Specifically, this example is an example of processing in the case of data whose file path has already been determined and is not stored in the same memory access node, and data whose file path has already been determined and is shared with other processes. As shown in FIG. 6B, when a process (application) A executed on a memory access node 20a accesses a non-volatile memory 231b in a memory access node 20b to create new data, the allocation unit 13 reschedules the process A to be executed by the central processing unit 21b in the memory access node 20b according to the number of the processes and the number of at least one of the data and executable files on the non-volatile memory 231b. Note that the process B is a process (application) executed on the memory access node 20b. In this way, the allocation unit 13 reschedules, for example, each process so that it is gathered in one memory access node 20 as much as possible. The allocation unit 13 may further perform the rescheduling based on, for example, the profile of at least one of the data and the executable file corresponding to the data. The profile is not particularly limited, and for example, the profile of the executable file may be the data size, working set size, image segment size, data segment size, etc., and the profile of the data may be the size of the data, etc. In this example, the number of processes is 2, and the number of data in the non-volatile memory 231 is 1, but this is not limited to this. For example, when M processes share at least one of N pieces of data and executable files, the allocation unit 13 identifies which non-volatile memory 231 stores at least one of the N pieces of data and executable files accessed by one of the M processes, and reschedules the process to be executed by the central processing unit 21 in the memory access node 20 with the largest number of identified non-volatile memories 231. The same process is performed for processes other than the one process. In this way, rescheduling is performed according to the number of accesses of the process to at least one of the data and executable files.

In this way, in this embodiment, when a process executed on one memory access node accesses the non-volatile memory on the other memory access node to create new data, the central processing unit 21 that executes the process is changed to a central processing unit 21 that is close in time to the non-volatile memory 231, thereby optimizing access to data in the non-volatile memory.

[Embodiment 5]
The program of the present embodiment is a program for causing a computer to execute each step of the method of the present invention as a procedure. In the present invention, the "procedure" may be read as "processing." The program of the present embodiment may be recorded, for example, in a computer-readable recording medium. The recording medium is not particularly limited, and examples thereof include a read-only memory (ROM), a hard disk (HD), and an optical disk.

The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various modifications that can be understood by a person skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

<Additional Notes>
Some or all of the above embodiments may be described as follows, but are not limited to the following:
(Appendix 1)
An operating system unit and a plurality of memory access nodes,
Each of the memory access nodes includes a central processing unit, a memory controller, and a memory unit;
The central processing unit includes a central processing unit,
the central processing unit includes a processor core and a connection controller;
the central processing unit connects to other central processing units via the connection controller;
the memory unit includes a non-volatile memory,
the memory unit is connected to the central processing unit via the memory controller;
the operating system unit includes a process analyzer, a data identifier, and an allocation unit;
The process analysis unit analyzes a process running in the operating system unit,
The data identifying unit identifies data to be accessed by the process and an executable file of the data based on the process;
At least one of the data and the executable file is data stored in the non-volatile memory of a specific memory access node,
The allocation unit allocates the central processing unit that executes the process from the multiple memory access nodes according to a time distance required to access the non-volatile memory based on the data and the executable file.
(Appendix 2)
The information processing device according to claim 1, wherein the allocation unit allocates a memory access node for executing the process based on at least one of the following (1) to (4):
(1) When the identified data and the executable file are present in the same memory access node, and/or when the process does not use the data and only uses the executable file present in the memory access node, the central processing unit has a short access time to the nonvolatile memory in the memory access node. (2) When the identified data and the executable file are present in different memory access nodes, the central processing unit has a short access time to the nonvolatile memory storing either the data or the executable file that satisfies a preset profile condition. (3) When the identified executable file itself has a function of operating according to at least one of the central processing unit and the memory unit that operate when executed by multiple memory access nodes, the central processing unit has a short access time to the nonvolatile memory that stores the identified data. (4) When the identified executable file is present in a storage other than a nonvolatile memory and the data is present in a nonvolatile memory, the central processing unit has a short access time to the nonvolatile memory that stores the identified data. (Appendix 3)
The information processing device according to claim 1 or 2, wherein when the process changes the processor core of the central processing unit, the allocation unit allocates another processor core other than the processor core that was executing the process depending on the time distance required to access the non-volatile memory.
(Appendix 4)
Further, a swap processing unit is included,
The information processing device according to any one of appendices 1 to 3, wherein, when swapping out is necessary, the swap processing unit creates a swap area for each non-volatile memory of each memory access node, and swaps out data in the memory of each central processing unit to the swap area of the non-volatile memory that is close in time to access from each central processing unit.
(Appendix 5)
Further, the method includes:
5. An information processing device as described in any one of appendixes 1 to 4, wherein the designation unit creates a new storage area for each of the non-volatile memories, and designates the new storage area of a non-volatile memory that is close in time to access from a central processing unit that executes the process as the memory for the newly created data.
(Appendix 6)
An information processing device as described in any of Appendix 1 to 5, wherein when a process executing on one memory access node accesses the non-volatile memory in the other memory access node to create new data, the allocation unit allocates the process to be executed by the central processing unit in the one memory access node or the other memory access node depending on the number of the processes and the number of at least one of the data and executable files in the non-volatile memory.
(Appendix 7)
7. The information processing device according to claim 1, wherein the non-volatile memory is a Non-Volatile Dual In-Line Memory Module (NVDIMM).
(Appendix 8)
An operating system unit and a plurality of memory access nodes,
Each of the memory access nodes includes a central processing unit, a memory controller, and a memory unit;
The central processing unit includes a central processing unit,
the central processing unit includes a processor core and a connection controller;
the central processing unit connects to other central processing units via the connection controller;
the memory unit includes a non-volatile memory,
the memory unit is connected to the central processing unit via the memory controller;
The operating system unit executes each step including a process analysis step, a data identification step, and an allocation step.
The process analysis step analyzes a process running in the operating system unit,
The data identifying step identifies data to be accessed by the process and an executable file of the data, based on the process;
At least one of the data and the executable file is data stored in the non-volatile memory of a specific memory access node,
The allocation step allocates the central processing unit for executing the process from among the plurality of memory access nodes in accordance with the time distance required to access the non-volatile memory based on the data and the executable file.
(Appendix 9)
The process execution method according to claim 8, wherein the allocation step allocates a memory access node for executing the process based on at least one of the following (1) to (4):
(1) When the identified data and the executable file are present in the same memory access node, and/or when the process does not use the data and only uses the executable file present in the memory access node, the central processing unit has a short access time to the nonvolatile memory in the memory access node. (2) When the identified data and the executable file are present in different memory access nodes, the central processing unit has a short access time to the nonvolatile memory storing either the data or the executable file that satisfies a preset profile condition. (3) When the identified executable file itself has a function of operating according to at least one of the central processing unit and the memory unit that operate when executed by multiple memory access nodes, the central processing unit has a short access time to the nonvolatile memory storing the identified data. (4) When the identified executable file is present in a storage other than a nonvolatile memory and the data is present in a nonvolatile memory, the central processing unit has a short access time to the nonvolatile memory storing the identified data. (Appendix 10)
The process execution method described in Appendix 8 or 9, wherein the allocation step, when the process changes the processor core of the central processing unit, allocates another processor core different from the processor core that was executing the process depending on the time distance required to access the non-volatile memory.
(Appendix 11)
Further, a swap processing step is included,
The process execution method according to any one of appendices 8 to 10, wherein the swap processing step, when a swap-out is required, creates a swap area for each non-volatile memory of each memory access node, and swaps out data in the memory of each central processing unit to the swap area of the non-volatile memory that is close in time to access from each central processing unit.
(Appendix 12)
Further, the method includes a specified step,
12. A process execution method according to any one of appendices 8 to 11, wherein the designation step creates a new storage area for each of the non-volatile memories, and designates, as the memory for the newly created data, the new storage area of a non-volatile memory that is close in time to access from a central processing unit that executes the process.
(Appendix 13)
The process execution method described in any one of Appendix 8 to 12, wherein the allocation step, when a process executed on one memory access node accesses the non-volatile memory in the other memory access node to create new data, allocates the process to be executed by the central processing unit in the one memory access node or the other memory access node depending on the number of the processes and the number of at least one of the data and executable files in the non-volatile memory.
(Appendix 14)
14. The process execution method according to any one of appendixes 8 to 13, wherein the non-volatile memory is a Non-Volatile Dual In-Line Memory Module (NVDIMM).
(Appendix 15)
An operating system unit and a plurality of memory access nodes,
Each of the NUMA nodes includes a central processing unit, a memory controller, and a memory unit;
The central processing unit includes a central processing unit,
the central processing unit includes a processor core and a connection controller;
the central processing unit connects to other central processing units via the connection controller;
the memory unit includes a non-volatile memory,
the memory unit is connected to the central processing unit via the memory controller;
A program for causing the operating system unit to execute procedures including a process analysis procedure, a data identification procedure, and an allocation procedure:
The process analysis step includes analyzing a process running in the operating system portion;
the data identification step includes identifying data to be accessed by the process and an executable file of the data based on the process;
At least one of the data and the executable file is data stored in the non-volatile memory of a specific memory access node,
The allocation step allocates the central processing unit for executing the process from among the plurality of memory access nodes according to a time distance required for accessing the non-volatile memory based on the data and the executable file.
(Appendix 16)
The program according to claim 15, wherein the allocation procedure allocates a memory access node that executes the process based on at least one of the following (1) to (4):
(1) When the identified data and the executable file are present in the same memory access node, and/or when the process does not use the data and only uses the executable file present in the memory access node, the central processing unit has a short access time to the nonvolatile memory in the memory access node. (2) When the identified data and the executable file are present in different memory access nodes, the central processing unit has a short access time to the nonvolatile memory storing either the data or the executable file that satisfies a preset profile condition. (3) When the identified executable file itself has a function of operating according to at least one of the central processing unit and the memory unit that operate when executed by multiple memory access nodes, the central processing unit has a short access time to the nonvolatile memory that stores the identified data. (4) When the identified executable file is present in a storage other than a nonvolatile memory and the data is present in a nonvolatile memory, the central processing unit has a short access time to the nonvolatile memory that stores the identified data. (Appendix 17)
The program according to claim 15 or 16, wherein the allocation procedure, when the process changes the processor core of the central processing unit, allocates another processor core different from the processor core that was executing the process depending on the time distance required to access the non-volatile memory.
(Appendix 18)
Further, a swap processing step is included,
The program according to any one of appendices 15 to 17, wherein the swap processing procedure, when a swap-out is necessary, creates a swap area for each of the non-volatile memories of each of the memory access nodes, and swaps out data in the memory of each of the central processing units to the swap area of the non-volatile memory that is close in time to access from each of the central processing units.
(Appendix 19)
Further, including a specification procedure,
The program described in any one of Appendices 15 to 18, wherein the designation procedure creates a new storage area for each of the non-volatile memories, and designates the new storage area of a non-volatile memory that is close in time to access from a central processing unit that executes the process as the memory for the newly created data.
(Appendix 20)
The program described in any of Appendix 15 to 19, wherein the allocation procedure, when a process executing on one memory access node accesses the non-volatile memory in the other memory access node to create new data, reschedules the process to be executed by the central processing unit in the one memory access node or the other memory access node depending on the number of the processes and the number of at least one of the data and executable files in the non-volatile memory.
(Appendix 21)
21. The program according to any one of appendixes 15 to 20, wherein the non-volatile memory is a Non-Volatile Dual In-Line Memory Module (NVDIMM).
(Appendix 22)
A computer-readable recording medium having a program according to any one of appendices 15 to 21 recorded thereon.

According to the present invention, it is possible to optimize access to data in non-volatile memory. Therefore, the present invention is useful in a NUMA architecture equipped with non-volatile memory.

REFERENCE SIGNS LIST 1 Information processing device 10 Operating system unit 11 Process analysis unit 12 Data identification unit 13 Allocation unit 14 Swap processing unit 15 Designation unit 20 Memory access node 21 Central processing unit 211 Central processing unit 2111 Processor core 2112 Connection controller 22 Remote controller 23 Memory unit 231 Non-volatile memory 30 IO device 100 Connection unit

Claims (10)

An operating system unit and a plurality of memory access nodes,
Each of the memory access nodes includes a central processing unit, a memory controller, and a memory unit;
The central processing unit includes a central processing unit,
the central processing unit includes a processor core and a connection controller;
the central processing unit connects to other central processing units via the connection controller;
the memory unit includes a non-volatile memory,
the memory unit is connected to the central processing unit via the memory controller;
the operating system portion is executed by the central processing unit;
the operating system unit includes a process analyzer, a data identifier, and an allocation unit;
The process analysis unit analyzes a process running in the operating system unit,
The data identifying unit identifies data to be accessed by the process and an executable file of the data based on the process;
At least one of the data and the executable file is data stored in the non-volatile memory of a specific memory access node,
the allocation unit allocates at least one of the central processing units (1) to (2) below that executes the process from the plurality of memory access nodes in accordance with a time distance required for accessing the non-volatile memory based on the data and the executable file,
Information processing device.
(1) When the identified executable file itself has "a function of operating in response to at least one of the central processing unit and the memory unit operating when executed by a plurality of memory access nodes," the central processing unit is close in time to the non-volatile memory storing the data to be accessed by the identified process. (2) When the identified executable file exists in a storage other than the non-volatile memory and the data exists in the non-volatile memory, the central processing unit is close in time to the non-volatile memory storing the identified data. The information processing device of claim 1, wherein the allocation unit allocates at least one of the central processing units (3) to (4) below to execute the process from the multiple memory access nodes instead of at least one of the central processing units (1) to (2 ) allocated, depending on the time distance required to access the non-volatile memory based on the data and the executable file.
(3) When the identified data and the executable file are present in the same memory access node, and/or when the process does not use the data but only uses the executable file present in the memory access node, the central processing unit is close in time to the non-volatile memory in the memory access node. (4) When the identified data and the executable file are present in different memory access nodes, the central processing unit is close in time to the non-volatile memory storing either the data or the executable file that satisfies a preset profile condition. The information processing device according to claim 1 or 2, wherein the allocation unit, when the process changes the processor core of the central processing unit, allocates another processor core different from the processor core that has been executing the process, depending on the time distance required to access the non-volatile memory. Further, a swap processing unit is included,
4. The information processing device according to claim 1, wherein when swapping out is required, the swap processing unit creates a swap area for each non-volatile memory of each memory access node, and swaps out data in the memory of each central processing unit to the swap area of the non-volatile memory that is close to the time distance required to access each central processing unit. Further, the method includes a designation portion,
5. The information processing device according to claim 1, wherein the designation unit creates a new storage area for each of the non-volatile memories, and designates the new storage area of a non-volatile memory that is close in time to access from a central processing unit that executes the process as the memory for the newly created data. The information processing device according to any one of claims 1 to 5, wherein when a process executed on one memory access node accesses the non-volatile memory in the other memory access node to create new data, the allocation unit allocates the process to be executed by the central processing unit in the one memory access node or the other memory access node according to the number of the processes and the number of at least one of the data and executable files in the non-volatile memory. The information processing device according to any one of claims 1 to 6, wherein the non-volatile memory is a non-volatile dual in-line memory module (NVDIMM). An operating system unit and a plurality of memory access nodes,
Each of the memory access nodes includes a central processing unit, a memory controller, and a memory unit;
The central processing unit includes a central processing unit,
the central processing unit includes a processor core and a connection controller;
the central processing unit connects to other central processing units via the connection controller;
the memory unit includes a non-volatile memory,
the memory unit is connected to the central processing unit via the memory controller;
The operating system portion is executed by the central processing unit.
Using an information processing device,
The operating system unit executes each step including a process analysis step, a data identification step, and an allocation step.
The process analysis step includes analyzing a process running in the operating system unit,
The data identifying step identifies data to be accessed by the process and an executable file of the data, based on the process;
At least one of the data and the executable file is data stored in the non-volatile memory of a specific memory access node,
The allocation step allocates at least one of the central processing units (1) to (2) below that executes the process from the multiple memory access nodes based on the data and the executable file, and in accordance with the time distance required to access the non-volatile memory.
(1) When the identified executable file itself has "a function of operating in response to at least one of the central processing unit and the memory unit operating when executed by a plurality of memory access nodes," the central processing unit is close in time to the non-volatile memory storing the data to be accessed by the identified process. (2) When the identified executable file exists in a storage other than the non-volatile memory and the data exists in the non-volatile memory, the central processing unit is close in time to the non-volatile memory storing the identified data. The process execution method according to claim 8, wherein the allocation step allocates at least one of the central processing units (3) to (4) below that executes the process from the multiple memory access nodes in accordance with a time distance required to access the non-volatile memory based on the data and the executable file, instead of the at least one of the central processing units (1) to (2) that have been allocated .
(3) When the identified data and the executable file are present in the same memory access node, and/or when the process does not use the data but only uses the executable file present in the memory access node, the central processing unit is close in time to the non-volatile memory in the memory access node. (4) When the identified data and the executable file are present in different memory access nodes, the central processing unit is close in time to the non-volatile memory storing either the data or the executable file that satisfies a preset profile condition. An operating system unit and a plurality of memory access nodes,
Each of the memory access nodes includes a central processing unit, a memory controller, and a memory unit;
The central processing unit includes a central processing unit,
the central processing unit includes a processor core and a connection controller;
the central processing unit connects to other central processing units via the connection controller;
the memory unit includes a non-volatile memory,
the memory unit is connected to the central processing unit via the memory controller;
The operating system unit is executed by the central processing unit.
Using an information processing device,
A program for causing the operating system unit to execute procedures including a process analysis procedure, a data identification procedure, and an allocation procedure:
The process analysis step includes analyzing a process running in the operating system portion;
the data identification step includes identifying data to be accessed by the process and an executable file of the data based on the process;
At least one of the data and the executable file is data stored in the non-volatile memory of a specific memory access node,
The allocation procedure assigns at least one of the central processing units (1) to (2) below that executes the process from the multiple memory access nodes based on the data and the executable file, depending on the time distance required to access the non-volatile memory.
(1) When the identified executable file itself has "a function of operating in response to at least one of the central processing unit and the memory unit operating when executed by a plurality of memory access nodes," the central processing unit is close in time to the non-volatile memory storing the data to be accessed by the identified process. (2) When the identified executable file exists in a storage other than the non-volatile memory and the data exists in the non-volatile memory, the central processing unit is close in time to the non-volatile memory storing the identified data.

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