JP7640422B2 - Inkjet head and inkjet recording device - Google Patents

Description

Embodiments of the present invention relate to an inkjet head and an inkjet recording device.

Some inkjet heads apply ejection pulses to an actuator that contracts and expands a pressure chamber, ejecting ink droplets from a nozzle connected to the pressure chamber onto a medium such as paper. Such inkjet heads send parameters such as the pressure of the pressure chamber, the temperature of the ink, and the drive voltage to a higher-level controller.

The higher-level controller detects errors in the inkjet head based on the parameters. If the higher-level controller detects an error, it stops the inkjet head.

Conventionally, inkjet heads have the problem of being unable to autonomously detect errors and shut down.

JP 2013-220544 A

To solve the above problem, we provide an inkjet head and inkjet recording device that can detect and stop errors.

According to an embodiment, the inkjet head includes a drive circuit, an interface, a determination circuit, and a switch. The drive circuit supplies a drive voltage to an ejection section that ejects ink. The interface acquires a state parameter that indicates the state of the ejection section. The determination circuit determines whether an error condition is satisfied based on the state parameter. The switch turns off the drive circuit when the determination circuit determines that the error condition is satisfied.

FIG. 1 is a diagram illustrating an example of the configuration of an inkjet recording apparatus according to an embodiment. FIG. 2 is a block diagram showing an example of the configuration of a control system of the inkjet printing apparatus according to the embodiment. FIG. 3 is a block diagram showing an example of the configuration of a head driving circuit according to the embodiment. FIG. 4 is a flowchart showing an example of the operation of the inkjet head according to the embodiment. FIG. 5 is a flowchart showing an example of the operation of the inkjet head according to the embodiment.

Hereinafter, an inkjet recording apparatus according to an embodiment will be described with reference to the drawings.
The inkjet recording device according to the embodiment forms an image on a medium such as paper using an inkjet head. The inkjet recording device ejects ink droplets from a pressure chamber in the inkjet head onto the medium, and prints an image on the medium. Examples of the inkjet recording device include an office inkjet recording device, a barcode inkjet recording device, a POS inkjet recording device, an industrial inkjet recording device, and a 3D inkjet recording device. Note that the medium on which the inkjet recording device forms an image is not limited to a specific configuration. The inkjet head included in the printer according to the embodiment is an example of a liquid ejection head, and ink is an example of a liquid.

Figure 1 is a schematic diagram showing an example of the configuration of an inkjet recording device 1 according to an embodiment. The inkjet recording device 1 forms an image on an image forming medium S or the like using a recording material such as ink. As an example, the inkjet recording device 1 includes a plurality of liquid ejection units 2, a head support mechanism 3 that movably supports the liquid ejection units 2, and a medium support mechanism 4 (support unit) that movably supports the image forming medium S. The image forming medium S is, for example, a sheet made of a material such as paper, cloth, or resin.

As shown in FIG. 1, a plurality of liquid ejection units 2 are supported by a head support mechanism 3 in a state in which they are arranged in parallel in a predetermined direction. The head support mechanism 3 is attached to an endless belt 3b that is stretched around a roller 3a. The inkjet recording device 1 is capable of moving the head support mechanism 3 in a main scanning direction A that is perpendicular to the transport direction of the image forming medium S by rotating the roller 3a.

The liquid ejection unit 2 integrally includes an inkjet head 10 and a circulation device 20 .
The inkjet head 10 ejects ink droplets made of ink I onto an image forming medium S.
In addition, the circulation device 20 supplies the ink I to the inkjet head 10 and collects the ink I from the inkjet head 10 .

The liquid ejection unit 2 performs an ejection operation to eject, as a liquid, for example, ink I from the inkjet head 10. As an example, the inkjet recording device 1 is a scan type that performs an ink ejection operation while moving the head support mechanism 3 back and forth in the main scanning direction A to form a desired image on an image forming medium S arranged opposite to it. Alternatively, the inkjet recording device 1 may be a single pass type that performs an ink ejection operation without moving the head support mechanism 3. In this case, the roller 3a and endless belt 3b do not need to be provided. Also in this case, the head support mechanism 3 is fixed to, for example, the housing of the inkjet recording device 1.

The multiple liquid ejection units 2 eject, for example, four colors of ink corresponding to CMYK (cyan, magenta, yellow, and key (black)), i.e., cyan ink, magenta ink, yellow ink, and black ink.

Next, the control system of the inkjet recording apparatus 1 will be described.
FIG. 2 is a block diagram showing an example of the configuration of a control system of the inkjet recording apparatus 1. As shown in FIG.
2, the inkjet recording apparatus 1 includes a processor 201, a ROM 202, a RAM 203, an operation panel 204, a communication interface 205, a transport motor 206, a motor drive circuit 207, a pump 208, a pump drive circuit 209, and an inkjet head 10. The inkjet head 10 includes a head drive circuit 11 and an ejection unit 12 that ejects ink.

The inkjet recording device 1 also includes bus lines 211 such as an address bus and a data bus. The processor 201 is connected to the ROM 202, RAM 203, operation panel 204, communication interface 205, motor drive circuit 207, pump drive circuit 209, and head drive circuit 11 via the bus lines 211, either directly or via an input/output circuit. The motor drive circuit 207 is connected to the transport motor 206. The pump drive circuit 209 is connected to the pump 208. The head drive circuit 11 is connected to the ejection unit 12.

The processor 201 has a function of controlling the operation of the entire inkjet recording device 1. The processor 201 may include an internal cache and various interfaces. The processor 201 realizes various processes by executing programs stored in advance in the internal cache or the ROM 202. The processor 201 realizes various functions of the inkjet recording device 1 in accordance with the operating system, application programs, etc.

Some of the various functions realized by the processor 201 executing the programs may be realized by a hardware circuit. In this case, the processor 201 controls the functions executed by the hardware circuit.
The processor 201 also functions as a host controller for the inkjet head 10 .

ROM 202 is a non-volatile memory in which control programs, control data, etc. are pre-stored. The control programs and control data stored in ROM 202 are pre-installed according to the specifications of the inkjet recording device 1. For example, ROM 202 stores an operating system, application programs, etc.

RAM 203 is a volatile memory. RAM 203 temporarily stores data being processed by processor 201. RAM 203 stores various application programs based on instructions from processor 201. RAM 203 may also store data required for executing application programs and execution results of application programs. RAM 203 may also function as an image memory into which print data is expanded.

The operation panel 204 is an interface that accepts input of instructions from an operator and displays various information to the operator. The operation panel 204 is composed of an operation section that accepts input of instructions and a display section that displays information.

The operation panel 204 transmits signals indicating operations received from an operator to the processor 201 as the operation of the operation unit. For example, the operation unit has function keys such as a power key, a paper feed key, and an error reset key.

The operation panel 204, as an operation of a display unit, displays various information under the control of the processor 201. For example, the operation panel 204 displays the status of the inkjet recording apparatus 1. For example, the display unit is configured with a liquid crystal monitor.
The operation unit may be configured with a touch panel. In this case, the display unit may be formed integrally with the touch panel serving as the operation unit.

The communication interface 205 is an interface for transmitting and receiving data to and from an external device via a network such as a LAN (Local Area Network). For example, the communication interface 205 is an interface that supports LAN connections. For example, the communication interface 205 receives print data from a client terminal via the network. For example, when an error occurs in the inkjet recording device 1, the communication interface 205 transmits a signal notifying the client terminal of the error.

The motor drive circuit 207 controls the drive of the conveying motor 206 according to a signal from the processor 201. For example, the motor drive circuit 207 transmits power or a control signal to the conveying motor 206.

The transport motor 206 is driven under the control of the motor drive circuit 207. The transport motor 206 functions as a drive source for the head support mechanism 3 and the medium support mechanism 4. For example, when the transport motor 206 is driven, the medium support mechanism 4 transports the medium. Also, when the transport motor 206 is driven, the head support mechanism 3 transports the inkjet head 10.

The pump drive circuit 209 controls the operation of the pump 208 according to a signal from the processor 201. For example, the pump drive circuit 209 transmits power or a control signal to the pump 208.

The pump 208 is driven under the control of the pump drive circuit 209. The pump 208 is a pump for circulating the ink I in the circulation device 20. When the pump 208 is driven, the ink I is supplied from the circulation device 20 to the inkjet head 10, and the ink I is collected from the inkjet head 10.

The inkjet head 10 includes a head driving circuit 11 and an ejection unit 12 .
The head drive circuit 11 supplies a drive voltage and the like to the ejection unit 12. For example, the head drive circuit 11 supplies an ejection pulse that causes the ejection unit 12 to eject ink droplets. The head drive circuit 11 also acquires parameters (state parameters) that indicate the state of the ejection unit 12. The head drive circuit 11 will be described in detail later.

The ejection unit 12 ejects ink droplets according to control from the head drive circuit 11. The ejection unit 12 is composed of multiple channels including pressure chambers, actuators, electrodes, and nozzles. The ejection unit 12 expands and contracts the actuators based on control signals from the head drive circuit 11, and ejects ink droplets from each pressure chamber.

The ejection unit 12 also includes a sensor for measuring state parameters. For example, the sensor measures the pressure in the pressure chamber, the temperature of the ink I, and the like as state parameters. The ejection unit 12 transmits the measured state parameters (analog signals) to the head drive circuit 11.

In addition, the inkjet recording device 1 may include additional components as necessary in addition to the components shown in Figures 1 and 2, and certain components may be excluded from the inkjet recording device 1.

Next, an example of the configuration of the head driving circuit 11 will be described.
Fig. 3 is a block diagram showing an example of the configuration of the head driving circuit 11. As shown in Fig. 3, the head driving circuit 11 includes an ADC-embedded FPGA 100, a driver IC 120, and a FET 130. The ADC-embedded FPGA 100 is connected to the ejection unit 12, the driver IC 120, and the FET 130. The driver IC 120 is connected to the ejection unit 12 and the FET 130.

The ADC built-in FPGA 100 outputs setting data to the driver IC 120 and outputs an ejection pulse or the like to the ejection unit 12 under the control of the processor 201. The ADC built-in FPGA 100 also acquires state parameters and detects errors based on the state parameters.
The ADC-embedded FPGA 100 will be described in detail later.

The driver IC 120 (drive circuit) outputs an ejection pulse to the ejection unit 12 according to control from the ADC-embedded FPGA 100. The driver IC 120 also receives a drive voltage from a power source or the like via the FET 130.

Before the setting of the discharge unit 12 is completed, the driver IC 120 inputs a signal (Low) indicating that the setting is incomplete to the AND circuit unit 111 described below. In addition, when the setting is completed, the driver IC 120 inputs a signal (High, CNF_DONE) indicating that the setting is completed to the AND circuit unit 111.

The FET 130 (field effect transistor) supplies a drive voltage from a power source or the like to the driver IC 120. The FET 130 turns the supply of the drive voltage on or off based on a control signal from the ADC-embedded FPGA 100. In other words, the FET 130 functions as a switch that controls the driver IC 120 to be turned on or off.

Next, the ADC-embedded FPGA 100 will be described.
As shown in FIG. 3, the ADC-embedded FPGA 100 includes a data receiving circuit section 101, a data processing section 102, a data transfer circuit section 103, an ADC 104, a moving average circuit section 105, a FIFO 106, a non-volatile memory 107, a memory processing section 108, a comparison section 109, a serial communication section 110, and an AND circuit section 111.

The data receiving circuit unit 101 is connected to the data processing unit 102 and the comparison unit 109. The data processing unit 102 is connected to the data transfer circuit unit 103. The data transfer circuit unit 103 is connected to the driver IC 120.

The ADC 104 is connected to the discharge unit 12, the moving average circuit unit 105, the FIFO 106, the comparison unit 109, and the FET 130. The moving average circuit unit 105 is connected to the comparison unit 109. The comparison unit 109 is connected to the data transfer circuit unit 103, the memory processing unit 108, and the FET 130. The memory processing unit 108 is connected to the FIFO 106, the non-volatile memory 107, the serial communication unit 110, and the AND circuit unit 111. The AND circuit unit 111 is connected to the driver IC 120.

The data receiving circuit unit 101 receives preconfiguration data from the processor 201 or the like. The preconfiguration data includes monitoring and control parameters used for error detection and the like. The monitoring and control parameters will be described later.

The data receiving circuit unit 101 transmits monitoring control parameters, etc. to the comparison unit 109.

Furthermore, the data receiving circuit unit 101 receives data (print data) for outputting an ejection pulse from the processor 201 or the like.
The data receiving circuit unit 101 transmits the preconfiguration (or a part of the configuration data), print data, and the like to the data processing unit 102 .

The data processing unit 102 processes the configuration data, print data, etc. from the data receiving circuit unit 101. The data processing unit 102 transmits the processed configuration data, print data, etc. to the data transfer circuit unit 103.

The data transfer circuit unit 103 receives the configuration data and print data from the data processing unit 102 and transmits them to the driver IC 120 .
Furthermore, the data transfer circuit unit 103 receives a stop request to stop the driver IC 120 from the comparison unit 109. The data transfer circuit unit 103 transmits the received stop request to the driver IC 120.

The ADC 104 (Analog to Digital Converter) is an interface that acquires state parameters. The ADC 104 acquires, as state parameters, the temperature of the ink I and the pressure of the pressure chamber from the ejection unit 12. The ADC 104 also acquires, as state parameters, the drive voltage to the driver IC 120 from the FET 130. The ADC 104 converts the acquired state parameters into digital signals.

The ADC 104 transmits the state parameters converted into digital signals to the moving average circuit unit 105, the FIFO 106, and the comparison unit 109.

The moving average circuit unit 105 receives the state parameters. The moving average circuit unit 105 calculates a moving average of the state parameters over a predetermined range. The moving average circuit unit 105 transmits the calculated moving average to the comparison unit 109.

FIFO 106 (First in First out) is a volatile memory that temporarily stores state parameters from ADC 104. FIFO 106 continues to store state parameters from ADC 104. When the capacity of FIFO 106 for storing state parameters reaches its upper limit, it overwrites the oldest state parameters with new state parameters. In other words, FIFO 106 temporarily stores state parameters in a FIFO manner.

The non-volatile memory 107 non-temporarily stores the state parameters according to the control of the memory processing unit 108. The non-volatile memory 107 is a memory to which data can be written and rewritten. For example, the non-volatile memory 107 is composed of a hard disk drive (HDD), a solid state drive (SSD), a flash memory, or the like.

The comparison unit 109 (determination circuit) determines whether the conditions (write conditions) for writing the state parameters to the non-volatile memory are met based on the state parameters (or the moving average of the state parameters) and the monitoring and control parameters.

For example, the supervisory control parameters include threshold values for comparing with the state parameters with respect to the writing conditions, such as a threshold value (such as 20° C.) for comparing with the temperature of the ink I.
The monitoring control parameters may also include threshold values to be compared with the length of a period (warning period) during which the state parameter is equal to or greater than a predetermined threshold value (or equal to or less than a predetermined threshold value). For example, the monitoring control parameters may include a threshold value (e.g., 10 seconds) to be compared with the length of a period during which the temperature of the ink I is equal to or greater than a predetermined threshold value (e.g., 20° C.).

The monitoring and control parameters may also include thresholds for multiple state parameters.

The comparison unit 109 compares the threshold value included in the monitoring control parameters with the state parameters. The comparison unit 109 determines whether the write condition is satisfied based on the comparison result. For example, the comparison unit 109 may determine that the write condition is satisfied when one of the state parameters is equal to or greater than the threshold value (or equal to or less than the threshold value) (or when the length of the warning zone is equal to or greater than the threshold value). The comparison unit 109 may also determine that the write condition is satisfied when each state parameter is equal to or greater than the threshold value (or when the length of each warning zone is equal to or greater than the threshold value). The comparison unit 109 may also determine that the write condition is satisfied when a predetermined number or more of the state parameters are equal to or greater than the threshold value (or when the length of the warning zone is equal to or greater than the threshold value).
The contents of the writing conditions are not limited to a specific configuration.

When it is determined that the write condition is satisfied, the comparison unit 109 transmits a control signal (write signal) to the memory processing unit 108 to write the state parameters to the non-volatile memory 107.

The comparison unit 109 also determines whether the conditions for detecting an error (error conditions) are met based on the state parameters (or the moving average of the state parameters) and the monitoring control parameters.

For example, the monitoring control parameters include thresholds for error conditions that are compared with the state parameters. That is, the monitoring control parameters include thresholds for write conditions and thresholds for error conditions. Furthermore, the monitoring control parameters store, as the threshold for the error condition, a threshold that indicates that the state of the ejection section 12 has deteriorated more than the threshold for the write condition.

For example, the supervisory control parameters may include a threshold value (eg, 30° C.) against which the temperature of ink I is compared.
The monitoring and control parameters may also include threshold values to be compared with the length of a period (warning period) during which the state parameter is equal to or greater than a predetermined threshold value (or equal to or less than a predetermined threshold value). For example, the monitoring and control parameters may include a threshold value (e.g., 20 seconds) to be compared with a period during which the temperature of the ink I is equal to or greater than a predetermined threshold value (e.g., 30° C.).

The monitoring and control parameters may also include thresholds for multiple state parameters.

The comparison unit 109 compares the threshold value included in the monitoring control parameters with the state parameters. The comparison unit 109 determines whether the error condition is satisfied based on the comparison result. For example, the comparison unit 109 may determine that the error condition is satisfied when one of the state parameters is equal to or greater than the threshold value (or equal to or less than the threshold value) (or when the length of the warning zone is equal to or greater than the threshold value). The comparison unit 109 may also determine that the error condition is satisfied when each state parameter is equal to or greater than the threshold value (or when the length of each warning zone is equal to or greater than the threshold value). The comparison unit 109 may also determine that the error condition is satisfied when a predetermined number or more of the state parameters are equal to or greater than the threshold value (or when the length of the warning zone is equal to or greater than the threshold value).
The error condition is not limited to a particular configuration.

When it is determined that the error condition is satisfied, the comparison unit 109 stops the ejection operation of the ejection unit 12. For example, the comparison unit 109 sends a stop request to the driver IC 120 through the data transfer circuit unit 103. The comparison unit 109 also turns off the FET 130. In other words, the comparison unit 109 stops the supply of the drive voltage to the driver IC 120.

The memory processing unit 108 (memory processing circuit) stores the state parameters stored by the FIFO 106 in the non-volatile memory 107 according to the control from the comparison unit 109. For example, when the memory processing unit 108 receives a write signal from the comparison unit 109, it acquires state parameters from the FIFO 106 going back a predetermined period. When it acquires the state parameters for the predetermined period, the memory processing unit 108 stores the acquired state parameters for the predetermined period in the non-volatile memory 107.

In addition, the memory processing unit 108 may store the state parameters newly stored in the FIFO 106 in the non-volatile memory 107 until a predetermined period has elapsed since the write signal was received. That is, the memory processing unit 108 may store the state parameters for a predetermined period extending before and after the timing of receiving the write signal in the non-volatile memory 107.

When the memory processing unit 108 can write the state parameters to the non-volatile memory 107 (when there is sufficient capacity in the non-volatile memory 107), it inputs a signal (High) indicating that writing is possible to the AND circuit unit 111. When the memory processing unit 108 cannot write the state parameters to the non-volatile memory 107 (when the capacity of the non-volatile memory 107 has reached its upper limit), it sets a FULL status bit indicating that the non-volatile memory 107 is full ... can write the state parameters to the non-volatile memory 107, it inputs a signal (Low) indicating that writing is not possible to the AND circuit unit 111.

When the error condition is satisfied, the memory processing unit 108 may store the state parameters in the non-volatile memory 107 even if the capacity of the non-volatile memory 107 has reached its upper limit. That is, the memory processing unit 108 overwrites the state parameters stored in the non-volatile memory 107 (for example, the oldest state parameters) with new state parameters.

In addition, when the error condition is satisfied, the memory processing unit 108 inputs a signal (Low) indicating that an error has occurred to the AND circuit unit 111.

The AND circuit unit 111 transmits to the processor 201 a control signal that is the AND of the signal from the memory processing unit 108 and the signal from the driver IC 120. For example, when the AND circuit unit 111 receives a High signal from the memory processing unit 108 and a High signal (CNF_DONE) from the driver IC 120, it transmits to the processor 201 a signal (High, CFG_DONE) indicating that the inkjet head 10 is operable. In addition, when either of these signals is Low, the AND circuit unit 111 transmits to the processor 201 a signal (Low) indicating that the inkjet head 10 is not operable.

The serial communication unit 110 is an interface that transmits and receives data to and from the processor 201. For example, the serial communication unit 110 transmits state parameters stored in the non-volatile memory 107 to the processor 201 under control of the processor 201. The serial communication unit 110 also receives from the processor 201 a release signal that releases an error state, a reset signal that resets a FULL status bit, and the like.

Next, an example of the operation of the ADC-embedded FPGA 100 will be described.
4 and 5 are flowcharts for explaining an example of the operation of the ADC-embedded FPGA 100. FIG.

First, the ADC-embedded FPGA 100 causes the data receiving circuit unit 101 to receive pre-configuration data (ACT 11). After receiving the pre-configuration data, the ADC-embedded FPGA 100 sets the monitoring and control parameters included in the pre-configuration data in the comparison unit 109 (ACT 12). Here, when the ADC-embedded FPGA 100 receives the configuration data in the data receiving circuit unit 101, it transmits the setting data to the driver IC 120.

When the monitoring and control parameters are set in the comparison unit 109, the ADC built-in FPGA 100 determines whether the driver IC 120 has output CNF_DONE (ACT 13). If it is determined that the driver IC 120 has not output CNF_DONE (ACT 13, NO), the ADC built-in FPGA 100 returns to ACT 13.

When it is determined that the driver IC 120 has output CNF_DONE (ACT 13, YES), the ADC-embedded FPGA 100 starts the ADC 104 and the comparison unit 109, etc. (ACT 14).

Here, when the data receiving circuit unit 101 receives print data, the print data is transferred to the driver IC 120, and the driver IC 120 supplies an ejection pulse or the like to the ejection unit 12, causing the ejection unit 12 to start ejecting ink droplets.

When the ADC 104 and the comparison unit 109 are started, the ADC built-in FPGA 100 stores the state parameters from the ADC 104 in the FIFO 106 (ACT 15). After storing the state parameters, the ADC built-in FPGA 100 causes the comparison unit 109 to determine whether the write conditions are met (ACT 17).

If the comparison unit 109 determines that the write condition is not satisfied (ACT 17, NO), the ADC-embedded FPGA 100 returns to ACT 15.

When the comparison unit 109 determines that the write condition is satisfied (ACT 17, YES), the ADC built-in FPGA 100 causes the comparison unit 109 to determine whether the error condition is satisfied (ACT 18). When the comparison unit 109 determines that the error condition is satisfied (ACT 18, YES), the ADC built-in FPGA 100 causes the comparison unit 109 to stop the ejection operation (ACT 19).

When the ejection operation is stopped, the ADC built-in FPGA 100 causes the memory processing unit 108 to send a signal indicating that an error has occurred to the processor 201 (ACT 20). When the processor 201 is caused to send a signal indicating that an error has occurred, the ADC built-in FPGA 100 causes the memory processing unit 108 to store the state parameters stored in the FIFO 106 in the non-volatile memory 107 (ACT 21).

After storing the state parameters in the non-volatile memory 107, the ADC-embedded FPGA 100 determines whether the error state has been released (ACT 22). For example, the ADC-embedded FPGA 100 determines whether a release signal has been received from the processor 201 or the like.

When it is determined that the error state has not been removed (ACT 22, NO), the FPGA with built-in ADC 100 returns to ACT 22.
When it is determined that the error state has been released (ACT 22, YES), the FPGA with built-in ADC 100 returns to ACT 13.

When the comparison unit 109 determines that the error condition is not satisfied (ACT 18, NO), the ADC-embedded FPGA 100 causes the memory processing unit 108 to store the state parameters stored in the FIFO 106 in the non-volatile memory 107 (ACT 23).

After storing the state parameters in the non-volatile memory 107, the ADC-embedded FPGA 100 manages the capacity of the non-volatile memory 107 (ACT 24) and causes the memory processing unit 108 to determine whether the capacity of the non-volatile memory 107 has reached its upper limit (ACT 25).

When the memory processing unit 108 determines that the capacity of the non-volatile memory 107 has not reached its upper limit (ACT 25, NO), the ADC-embedded FPGA 100 returns to ACT 15.

When the memory processing unit 108 determines that the capacity of the non-volatile memory 107 has reached its upper limit (ACT 25, YES), the ADC-embedded FPGA 100 causes the memory processing unit 108 to set a FULL status bit and send a signal indicating that writing is not possible to the processor 201 (ACT 26).

When the signal indicating that writing is not possible is sent to the processor 201, the ADC built-in FPGA 100 stops the ADC 104 (ACT 27). When the ADC 104 is stopped, the ADC built-in FPGA 100 determines whether the FULL status bit has been reset (ACT 28). For example, the ADC built-in FPGA 100 determines whether a reset signal has been received from the processor 201 or the like.

When it is determined that the FULL status bit is not reset (ACT 28, NO), the FPGA with built-in ADC 100 returns to ACT 28.
When it is determined that the FULL status bit is reset (ACT 28, YES), the ADC built-in FPGA 100 returns to ACT 14.

After ACT25, YES, the ADC-embedded FPGA 100 may stop or continue the ejection operation.

Furthermore, after ACT21 and ACT23, the memory processing unit 108 may continue to store the state parameters stored in the FIFO 106 in the non-volatile memory 107 for a predetermined period of time.

Further, the ADC-embedded FPGA 100 may transmit state parameters stored in the non-volatile memory 107 to the processor 201 or the like in accordance with control from the processor 201. Furthermore, the ADC-embedded FPGA 100 may delete data stored in the non-volatile memory 107 in accordance with control from the processor 201.

The ADC-embedded FPGA 100 may also notify the processor 201, etc., via the serial communication unit 110, etc., of the reason why CFG_DONE became Low (satisfaction of an error condition or setting of the FULL status bit).

The inkjet head configured as described above acquires state parameters related to the state of the ejection section. The inkjet head detects errors based on the state parameters. When the inkjet head detects an error, it stops the ejection operation. Thus, the inkjet head can autonomously detect errors and stop.

In addition, when the inkjet head detects an error, it stores the status parameters before and after the error was detected in non-volatile memory. Therefore, the inkjet head can store necessary data in non-volatile memory while saving on the capacity of the non-volatile memory.

In addition, when the inkjet head detects a state that is not an error but is likely to cause an error, it stores in non-volatile memory the state parameters before and after the detection of the state that is likely to cause an error. Therefore, the inkjet head can store in non-volatile memory the state parameters in a state where an error is likely to occur.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.

1...inkjet recording device, 2...liquid ejection unit, 3...head support mechanism, 3a...roller, 3b...endless belt, 4...medium support mechanism, 10...inkjet head, 11...head drive circuit, 12...ejection unit, 20...circulation device, 101...data receiving circuit, 102...data processing unit, 103...data transfer circuit, 104...ADC, 105...moving average circuit, 106...FIFO, 107...non-volatile memory, 108...memory processing unit, 109...comparison unit, 110...serial communication unit, 111...AND circuit, 120...driver IC, 130...FET, 201...processor, 202...ROM, 203...RAM, 204...operation panel, 205...communication interface, 206...conveyor motor, 207...motor drive circuit, 208...pump, 209...pump drive circuit, 211...bus line.

Claims (5)

A drive circuit that supplies a drive voltage to an ejection unit that ejects ink;
an interface for acquiring a status parameter indicating a status of the ejection unit;
a decision circuit that decides whether an error condition is met based on the state parameters;
a switch that turns off the drive circuit when the determination circuit determines that the error condition is satisfied;
An inkjet head comprising: The determination circuit determines whether a write condition is satisfied based on the state parameter;
a volatile memory for temporarily storing the state parameters acquired by the interface;
A non-volatile memory for storing data;
a memory processing circuit that stores the state parameters stored in the volatile memory in the non-volatile memory when the determination circuit determines whether a write condition is satisfied;
Equipped with
2. The ink-jet head according to claim 1. when it is determined that the write condition is satisfied, the determination circuit determines whether the error condition is satisfied.
3. The ink-jet head according to claim 2. a receiving circuit for receiving a supervisory control parameter;
the determination circuit determines whether the error condition is satisfied based on the supervisory control parameters;
The ink-jet head according to claim 1 . An inkjet recording apparatus that ejects ink droplets onto a medium,
A support portion that supports the medium;
An inkjet head according to any one of claims 1 to 4;
An inkjet recording apparatus comprising: