JP7647871B2 - Metal plate material, laminate, and insulated circuit board - Google Patents

Description

The present invention relates to a metal plate, a laminate having a structure in which a resin member and a metal plate are laminated, and an insulating circuit board.
This application claims priority based on Japanese Patent Application No. 2021-053449, filed in Japan on March 26, 2021, the contents of which are incorporated herein by reference.

In the power module, the LED module, and the thermoelectric module, a power semiconductor element, an LED element, and a thermoelectric element are bonded to an insulating circuit board having a circuit layer made of a conductive material formed on one side of an insulating layer. As the insulating layer, those using ceramics or insulating resin have been proposed.
Here, as an insulating circuit board having an insulating resin layer, for example, Patent Document 1 proposes a metal base circuit board, and Patent Document 2 proposes a multilayer wiring board.

In the metal base circuit board described in Patent Document 1, an insulating resin layer is formed on a metal substrate, and a circuit layer having a circuit pattern is formed on the insulating resin layer. Here, the insulating resin layer is made of epoxy resin, which is a thermosetting resin, and the circuit layer is made of copper foil.
In this metal-based circuit board, a semiconductor element is bonded onto the circuit layer, and a heat sink is disposed on the side of the metal board opposite the insulating resin layer, so that heat generated by the semiconductor element is transferred to the heat sink side and dissipated.

The multilayer wiring board described in Patent Document 2 is manufactured by the following method. Metal foil adhered to a resin film is etched to make the surface roughness (Ra) of the metal foil 0.2 μm or more, and is then etched into a circuit pattern to form a wiring circuit layer. The wiring circuit layer formed on the surface of the resin film is embedded in the surface of a soft insulating sheet while applying pressure, and the insulating circuit layer is transferred to the surface of the insulating sheet. Multiple insulating sheets obtained in this way are stacked and heat-cured together.

In an insulating circuit board having a structure in which a circuit layer is formed by bonding a metal plate or the like to an insulating resin layer, it is necessary to ensure adhesion between the insulating resin layer and the circuit layer (metal plate) and between the insulating resin layer and the metal substrate (metal plate) so that peeling between the insulating resin layer and the circuit layer (metal plate) and between the insulating resin layer and the metal substrate (metal plate) does not occur during use.
Here, in the metal base circuit board described in Patent Document 1, no consideration is given to improving the adhesion between the insulating resin layer and the circuit layer, or between the insulating resin layer and the metal substrate, and there is a risk of peeling between the insulating resin layer and the circuit layer (metal plate) or between the insulating resin layer and the metal substrate (metal plate) during use.

On the other hand, in the multilayer wiring board described in Patent Document 2, the surface roughness (Ra) of the wiring circuit layer is set to 0.2 μm or more and the wiring circuit layer is embedded in the insulating sheet, thereby improving the adhesion between the insulating sheet and the wiring circuit layer.
Here, even if the surface roughness (Ra) of the wiring circuit layer is set to 0.2 μm or more, if the convex portions protruding from the circuit layer side are not formed uniformly and densely, there is a risk that adhesion with the insulating sheet cannot be ensured.

JP 2015-207666 A JP 2000-077850 A

This invention has been made in consideration of the above-mentioned circumstances, and aims to provide a metal plate material that has excellent adhesion to a laminated resin member, a laminate in which this metal plate material and a resin member are laminated, and an insulated circuit board.

As a result of intensive research conducted by the present inventors to solve the above-mentioned problems, it was found that a roughened plating layer having multiple protrusions can be formed by performing pulse plating on a metal sheet. The inventors also discovered that by reducing the residual stress of the metal sheet when forming this roughened plating layer, it is possible to form uniform and dense protrusions.

The present invention has been made based on the above-mentioned findings, and a metal sheet material according to one embodiment of the present invention has a sheet body and a roughened plating layer formed on the outermost layer of the sheet body, the sheet body being a rolled sheet having a thickness in the range of 0.05 mm to 3 mm, the roughened plating layer having a convex portion protruding toward the opposite side to the sheet body, the area ratio of an area having a KAM value of 1.0 or more in a region 6 μm in the thickness direction from the outermost layer of the roughened plating layer is 10% or less, and the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer is 20% or more, or the R (developed interface line length ratio) of the outermost surface of the roughened plating layer is 40% or more.

The KAM (Kernel Average Misorientation) value is calculated by averaging the misorientation between one pixel in a crystal grain and the pixels surrounding it. Since the shape of a pixel is a regular hexagon, when the proximity order is set to 1 (1st), the average misorientation between six adjacent pixels is calculated as the KAM value. However, if there is a grain boundary between adjacent measurement points, it is not included in the calculation of the KAM value.
By using this KAM value, it is possible to visualize the local misorientation, i.e., the distribution of strain. Regions with high KAM values are regions where the strain introduced during processing is high, and where residual stress is high.

In the metal sheet material having this configuration, in a region 6 μm in the thickness direction from the outermost layer of the roughened plating layer, the area ratio of the region having a KAM value of 1.0 or more is 10% or less. Therefore, the residual stress in the surface layer is kept low, and the roughened plating layer can have uniform and dense convex portions that protrude toward the opposite side of the plate body.
Since the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer is 20% or more, or the R (developed interface line length ratio) of the outermost surface of the roughened plating layer is 40% or more, it is possible to improve adhesion to a resin member laminated on the roughened plating layer side.

Here, in the metal plate according to one aspect of the present invention, it is preferable that the protrusion has a widening portion whose width gradually increases toward the tip end in the protruding direction.
In this case, the convex portion protruding toward the opposite side to the plate body has a widening portion whose width gradually increases toward the tip side in the protruding direction, so that the resin member laminated on the roughened plating layer side is securely engaged with the convex portion, thereby making it possible to improve adhesion with the resin member.

In the metal sheet material according to one aspect of the present invention, the sheet body is preferably made of copper or a copper alloy.
In this case, since the plate body is made of copper or a copper alloy, it has excellent electrical conductivity and thermal conductivity.

The laminate according to one embodiment of the present invention is a laminate in which a resin member is laminated on the plate surface of the above-mentioned metal plate material, and is characterized in that at the joint interface between the resin member and the metal plate material, the resin member engages with the convex portion of the metal plate material.

According to a laminate of this configuration, a resin member is laminated on the sheet surface (roughened plating layer) of a metal sheet material on which a convex portion is formed, and at the joint interface between the resin member and the metal sheet material, the convex portion of the metal sheet material and the resin member are engaged with each other, thereby improving adhesion between the resin member and the metal sheet material.
It can also be said that the laminate has the above-mentioned metal sheet and a resin member laminated on the sheet surface of the metal sheet on the side of the roughened plating layer.

An insulated circuit board according to one embodiment of the present invention is an insulated circuit board comprising an insulating resin layer and a circuit layer formed on one side of the insulating resin layer, the circuit layer being formed by bonding the above-mentioned metal plate material to one side of the insulating resin layer, and characterized in that the insulating resin layer engages with the convex portion of the metal plate material at the bonding interface between the insulating resin layer and the circuit layer.

In an insulating circuit board of this configuration, a circuit layer is formed by bonding the plate surface (roughened plating layer) of a metal plate material on which a convex portion is formed to one side of an insulating resin layer, and at the bonding interface between the insulating resin layer and the circuit layer, the insulating resin layer engages with the convex portion of the circuit layer (copper member), thereby improving adhesion between the circuit layer and the insulating resin layer.

An insulated circuit board according to another aspect of the present invention is an insulated circuit board comprising an insulating resin layer, a circuit layer formed on one side of the insulating resin layer, and a metal substrate formed on the other side of the insulating resin layer, wherein either or both of the circuit layer and the metal substrate are formed by bonding the above-mentioned metal plate material to the surface of the insulating resin layer, and the insulating resin layer is engaged with the convex portion of the metal substrate at either or both of the bonding interface between the insulating resin layer and the circuit layer and the bonding interface between the insulating resin layer and the metal substrate.

In an insulating circuit board of this configuration, one or both of a circuit layer and a metal substrate are formed by bonding the plate surface (roughened plating layer) of a metal substrate on which a convex portion is formed to the surface of an insulating resin layer. At one or both of the bonding interfaces between the insulating resin layer and the circuit layer and between the insulating resin layer and the metal substrate, the insulating resin layer engages with the convex portion of the metal substrate. This makes it possible to improve adhesion between the circuit layer and the insulating resin layer or between the metal substrate and the insulating resin layer.

According to one and other aspects of the present invention, it is possible to provide a metal sheet material having excellent adhesion to a laminated resin member, a laminate in which this metal sheet material and a resin member are laminated, and an insulated circuit board.

FIG. 1 is a schematic explanatory diagram of a power module including an insulating circuit board according to an embodiment of the present invention. FIG. 2 is an explanatory diagram of a metal plate according to an embodiment of the present invention, and more specifically, an observation photograph of the vicinity of the surface. 1 is an explanatory diagram of a metal plate according to an embodiment of the present invention, and in detail is a schematic diagram of an engaging protrusion. FIG. FIG. 2 is a flow diagram showing a method for manufacturing an insulating circuit board according to an embodiment of the present invention. 4 is a schematic explanatory diagram of a method for producing the insulating circuit board shown in FIG. 3. FIG. 2 is a schematic explanatory diagram of a test device for evaluating the insulation properties (dielectric strength voltage) of an insulating circuit board in the examples.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a metal plate, a laminate, and an insulating circuit board according to embodiments of the present invention will be described with reference to the accompanying drawings.
FIG. 1 shows an insulating circuit board 10 according to an embodiment of the present invention and a power module 1 using this insulating circuit board 10.
The insulating circuit board 10 according to this embodiment includes an insulating resin layer 12, a circuit layer 13 formed on one surface of the insulating resin layer 12, and a metal substrate 11 formed on the other surface of the insulating resin layer 12. Both the circuit layer 13 and the metal substrate 11 are formed by bonding a metal plate material 30 according to this embodiment to the surface of the insulating resin layer 12.
The insulating resin layer 12 is an example of a resin member, and the insulating circuit board 10 according to the present embodiment can be said to be a laminate according to the present embodiment. The laminate according to the present embodiment has the metal plate 30 according to the present embodiment and a resin member, and the resin member is laminated on the plate surface (roughened plating layer) of the metal plate 30. In other words, the metal plate 30 is bonded to the surface of the resin member.

The power module 1 shown in Figure 1 comprises an insulating circuit board 10, a semiconductor element 3 joined to one surface (the upper surface in Figure 1) of the insulating circuit board 10 via a first solder layer 2, and a heat sink 41 joined to the other side (the lower surface in Figure 1) of the insulating circuit board 10 via a second solder layer 42.

The semiconductor element 3 is made of a semiconductor material such as Si. The first solder layer 2 that joins the insulating circuit board 10 and the semiconductor element 3 is made of, for example, a Sn-Ag-based, Sn-Cu-based, Sn-In-based, or Sn-Ag-Cu-based solder material (a so-called lead-free solder material).

The heat sink 41 is for dissipating heat on the insulating circuit board 10 side. The heat sink 41 is made of copper or a copper alloy, aluminum or an aluminum alloy, or the like, which has good thermal conductivity. In this embodiment, the heat sink 41 is a heat sink made of oxygen-free copper. The thickness of the heat sink 41 is set within a range of 3 mm to 10 mm.
Here, the insulating circuit board 10 and the heat sink 41 are joined via a second solder layer 42. This second solder layer 42 can have the same configuration as the first solder layer 2 described above.

As shown in FIG. 1, the insulating circuit board 10 of this embodiment comprises a metal substrate 11, an insulating resin layer 12 formed on one surface (the upper surface in FIG. 1) of the metal substrate 11, and a circuit layer 13 formed on one surface (the upper surface in FIG. 1) of the insulating resin layer 12.

The metal substrate 11 has the effect of improving heat dissipation characteristics by spreading heat generated in the semiconductor element 3 mounted on the insulating circuit substrate 10 in the planar direction. For this reason, the metal substrate 11 is made of a metal with excellent thermal conductivity, such as copper or a copper alloy, aluminum or an aluminum alloy. In this embodiment, it is made of a rolled sheet of oxygen-free copper. The thickness of the metal substrate 11 is set within the range of 0.05 mm to 3 mm, and in this embodiment, it is set to 2.0 mm.

The insulating resin layer 12 prevents electrical connection between the circuit layer 13 and the metal substrate 11, and is made of an insulating thermosetting resin.
In this embodiment, a thermosetting resin containing a filler is used to ensure the strength of the insulating resin layer 12 and to ensure thermal conductivity. Here, for example, alumina, boron nitride, aluminum nitride, etc. can be used as the filler. Also, epoxy resin, polyimide resin, etc. can be used as the thermosetting resin. In this embodiment, the insulating resin layer 12 is made of an epoxy resin containing boron nitride as a filler. Also, the thickness of the insulating resin layer 12 is set to a range of 20 μm to 250 μm, and is set to 150 μm in this embodiment.

As shown in Fig. 4, the circuit layer 13 has a metal plate material 30 of this embodiment bonded to one surface (upper surface in Fig. 4) of the insulating resin layer 12, and a circuit pattern is formed. In detail, one surface of the insulating resin layer 12 and a surface of the metal plate material 30 on the roughened plating layer 35 side are bonded. Note that the circuit pattern may be formed on the metal plate material 30 first, and then the metal plate material 30 on which the circuit pattern has been formed may be bonded to one surface of the insulating resin layer 12.
A circuit pattern is formed on this circuit layer 13, and one surface thereof (the upper surface in FIG. 1) serves as a mounting surface on which the semiconductor element 3 is mounted. The thickness of the circuit layer 13 is set within a range of 0.3 mm to 3 mm, and is set to 0.5 mm in this embodiment.

Here, the metal plate material 30 of this embodiment which becomes the circuit layer 13 described above will be described with reference to FIGS. 2A and 2B. FIG.
The metal plate 30 of this embodiment is made of a metal having excellent electrical conductivity and thermal conductivity, and in this embodiment, is made of copper or a copper alloy, and more specifically, is made of oxygen-free copper.
As shown in FIG. 2A , the metal plate 30 of this embodiment includes a plate body 31 and a roughened plating layer 35 formed on the outermost surface of the plate body 31 .

As shown in FIG. 2B, the roughened plating layer 35 has a protrusion 36 formed thereon, which protrudes toward the opposite side to the plate body 31 (upward in FIG. 2B).
In this embodiment, it is preferable that the convex portion 36 includes a widened portion 36a whose width gradually increases toward the tip end in the protruding direction, as shown in FIG. 2B.

In the metal sheet material 30 of this embodiment, when the area of the copper portion in a region 6 μm in the thickness direction from the outermost layer of the roughened plating layer 35 is taken as 100%, the area ratio of the region having a KAM value of 1.0 or more is 10% or less.
In addition, the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35 is 20% or more, or the R (developed interface line length ratio) of the outermost surface of the roughened plating layer 35 is 40% or more.

In the insulating circuit board 10 of this embodiment, the convex portion 36 of the circuit layer 13 (metal plate material 30) engages with the insulating resin layer 12 at the bonding interface between the insulating resin layer 12 and the circuit layer 13, and the circuit layer 13 (metal plate material 30) and the insulating resin layer 12 are interdigitated with each other.

In this embodiment, the metal substrate 11 is formed by bonding the metal plate material 30 of this embodiment to the other surface (the lower surface in FIG. 4) of the insulating resin layer 12. In detail, the other surface of the insulating resin layer 12 is bonded to the surface of the metal plate material 30 on the roughened plating layer 35 side. At the bonding interface between the insulating resin layer 12 and the metal substrate 11, the convex portion of the metal substrate 11 (metal plate material 30) and the insulating resin layer 12 are also engaged, and the metal substrate 11 (metal plate material 30) and the insulating resin layer 12 are interdigitated with each other.

The reasons for specifying the area ratio of the region having a KAM value of 1.0 or more, the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35, and the R (developed interface line length ratio) of the outermost surface of the roughened plating layer 35 in the metal sheet material 30 constituting the circuit layer 13 and metal substrate 11 of the insulated circuit board 10 of this embodiment as described above are explained below.

(Area ratio of region having KAM value of 1.0 or more)
The KAM (Kernel Average Misorientation) value measured by the EBSD method evaluates the local misorientation, i.e., the distribution of strain. Regions with high KAM values are regions where high strain was introduced during processing, and where residual stress is high.

In the metal sheet 30 of this embodiment, if the area ratio of the region having a KAM value of 1.0 or more in the region 6 μm in the thickness direction from the outermost layer of the roughened plating layer 35 is low, there are few regions with high strain and residual stress is sufficiently reduced, making it possible to form uniform and dense convex portions 36 in the roughened plating layer 35.
For this reason, in the metal sheet 30 of this embodiment, the area ratio of the region having a KAM value of 1.0 or more in a region 6 μm deep in the thickness direction from the outermost layer of the roughened plating layer 35 is limited to 10% or less.

The area ratio of the area having a KAM value of 1.0 or more in the area 6 μm from the outermost layer of the roughened plating layer 35 in the thickness direction is preferably 5% or less, and more preferably 3% or less. There is no particular restriction on the lower limit of the above-mentioned area ratio, and it is most preferably 0%.
Here, in the observation field, the top of the most protruding convex portion 36 is the "outermost layer of the roughened plating layer 35," and the area of the metal portion in a region of 6 μm from this point in the thickness direction is taken as 100%, and the area ratio of the region where the KAM value is 1.0 or more is calculated.

(Sdr of the outermost surface of the roughened plating layer 35)
Sdr (developed interface area ratio) is an index showing the increase rate of surface area due to unevenness. If the plane parallel to the metal plate 30 is the XY plane, the surface area of the contour curved surface of the unevenness is _A1 , and the surface area (projected area) when the surface is projected onto the XY plane is _A0 , Sdr is expressed by the following formula.
Sdr={(A ₁ /A ₀ )-1}×100(%)
If Sdr is large, the projections (surface shape) are dense and have large undulations.
For this reason, in the metal sheet 30 of this embodiment, the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35 is set to 20% or more.
The Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35 is preferably 40% or more, and more preferably 65% or more. There is no particular upper limit to the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35, but in view of the measurement method, it is practically 150% or less.
Sdr (developed interface area ratio) is measured by the following method. An area of 129 μm×129 μm on the surface of the roughened plating layer 35 of the metal sheet 30 is observed using a 100x objective lens of a laser microscope. Processing is performed to remove inclination and noise of the sample. The obtained image is analyzed, and Sdr (developed interface area ratio) is calculated by the above formula.
Usually, Sdr (developed interface area ratio) is measured on the metal plate material 30 before being joined to the insulating resin layer (resin member) 12 .
When the circuit layer 13 or metal substrate 11 of the insulating circuit board (laminate) 10 is a metal plate material 30 and the metal plate material 30 is bonded to the insulating resin layer (resin member) 12, the Sdr (developed interface area ratio) of the metal plate material 30 (circuit layer 13 or metal substrate 11) in the insulating circuit board (laminate) 10 is measured by the following method. The insulating resin layer (resin member) 12 is dissolved by an organic solvent or the like, or the insulating circuit board (laminate) 10 is baked to remove the insulating resin layer (resin member) 12. In this way, the bonding interface between the metal plate material 30 and the insulating resin layer (resin member) 12 (the surface of the roughened plating layer 35 of the metal plate material 30) is exposed. Then, the surface is observed using a laser microscope as described above. The obtained image is analyzed, and the Sdr (developed interface area ratio) is calculated by the above formula.

(R of the outermost surface of the roughened plating layer 35)
If the surface curve in the cross section of the roughened plating layer 35 is taken as the cross section curve, R (developed interface line length ratio) is an index showing the rate of increase in the line length of the cross section curve due to unevenness. If the line length of the cross section curve is _L1 and the length (projected length) of the cross section curve projected onto the X axis is _L0 , R is expressed by the following formula. Note that the thickness direction of the roughened plating layer in the cross section is the Y axis, and the direction perpendicular to the Y axis is the X axis.
R={(L ₁ /L ₀ )-1}×100(%)
If R is large, the convex portions (surface shape) are dense and have large undulations.
For this reason, in the metal sheet 30 of this embodiment, R (developed interface line length ratio) of the outermost surface of the roughened plating layer 35 is specified to be 40% or more. R (developed interface line length ratio) is preferably 100% or more, and more preferably 150% or more. There is no particular upper limit to R (developed interface line length ratio), but in reality it is 1000% or less.
R (developed interface line ratio) is measured by the following method. A cross section parallel to the longitudinal direction of the metal sheet material 30 and a cross section perpendicular to the longitudinal direction of the metal sheet material 30 are prepared. A range of 115 μm of the cross-sectional curve of each cross section is observed at a magnification of 1000 times using a scanning electron microscope. The obtained image is analyzed, and R (developed interface line ratio) is calculated by the above formula. The average value of R (developed interface line ratio) in the cross section parallel to the longitudinal direction of the metal sheet material 30 and R (developed interface line ratio) in the cross section perpendicular to the longitudinal direction of the metal sheet material 30 is defined as R (developed interface line ratio) of the roughened plating layer 35 of the metal sheet material 30.
When the circuit layer 13 or metal substrate 11 of the insulating circuit board (laminate) 10 is a metal plate material 30 and the metal plate material 30 is bonded to the insulating resin layer (resin member) 12, the R (developed interface line length ratio) of the metal plate material 30 (circuit layer 13 or metal substrate 11) in the insulating circuit board (laminate) 10 is measured by the following method. A cross section parallel to the longitudinal direction of the insulating circuit board (laminate) 10 and a cross section perpendicular to the longitudinal direction of the insulating circuit board (laminate) 10 are prepared. Each cross section is observed at a magnification of 1000 times using a scanning electron microscope. In the cross section, the cross section curve of the roughened plating layer 35 at the joint interface between the metal plate material 30 and the insulating resin layer (resin member) 12 is specified. A range of 115 μm of the cross section curve is observed. The obtained image is analyzed, and R (developed interface line length ratio) is calculated by the above formula. The average value of R (developed interface line ratio) in a cross section parallel to the longitudinal direction of the insulating circuit board (laminate) 10 and R (developed interface line ratio) in a cross section perpendicular to the longitudinal direction of the insulating circuit board (laminate) 10 is defined as R (developed interface line ratio) of the roughened plating layer 35 of the metal sheet 30.
In addition, the outline of a metal piece that is separate from the metal plate material 30 and exists within the insulating resin layer (resin member) 12, and the outline of a resin piece that is separate from the insulating resin layer (resin member) 12 and exists within the metal plate material 30 are not included in the line length (L ₁ ) of the cross-sectional curve.
Compared to Sdr (developed interface area ratio) of metal sheet material 30 (circuit layer 13 and metal substrate 11) in insulated circuit board (laminate) 10, R (developed interface line length ratio) of metal sheet material 30 (circuit layer 13 and metal substrate 11) in insulated circuit board (laminate) 10 can be measured more easily.

Next, a method for manufacturing the insulating circuit board 10 according to this embodiment will be described with reference to FIGS.
In addition, in Figure 4, the metal substrate 11 is not given the symbol 30 of the metal plate material, but the metal substrate 11 is a metal plate material 30 and has a plate body 31 and a roughened plating layer 35 formed on the outermost layer of the plate body 31.

(Stress reduction step S01)
First, in the metal plate material 30 that will become the circuit layer 13, the residual stress is reduced near the surface (the surface on which the roughened plating layer 35 is formed) of the plate body 31. Similarly, the residual stress is reduced near the surface (the surface on which the roughened plating layer 35 is formed) of the metal substrate 11.
There is no particular limitation on the method for reducing the residual stress, but for example, chemical polishing, heat treatment, direct current electrolytic plating, etc. can be applied.

In chemical polishing, for example, a chemical polishing liquid (for example, a mixture of sulfuric acid and hydrogen peroxide) is used to remove the surface of the plate body 31, thereby reducing residual stress near the surface of the plate body 31.
In the heat treatment, for example, the plate body 31 is held at a temperature of 400° C. or more and 600° C. or less for 1 hour or more and 2 hours or less to reduce residual stress near the surface of the plate body 31.
In DC electrolytic plating, for example, the surface of the plate body 31 is subjected to electrolytic degreasing and pickling, and then a film of 6 μm or more is formed at high temperature and low current density. Thereafter, the plate body 31 is left at room temperature for several days or is subjected to heat treatment at 150° C. for 1 hour to reduce residual stress near the surface of the plate body 31.

(Surface roughening step S02)
Next, a roughened plating layer 35 is formed on the surface of the plate body 31 with the surface residual stress reduced. In this embodiment, a roughened plating layer 35 is also formed on the metal substrate 11. This roughened plating layer 35 is formed as follows.
The joining surface of the plate body 31 (and the metal substrate 11) is subjected to electrolytic plating. In this embodiment, it is preferable to use an electrolytic solution consisting of an aqueous solution of disodium 3,3'-dithiobis(1-propanesulfonate) added to a copper sulfate bath mainly composed of copper sulfate (CuSO ₄ ) and sulfuric acid (H ₂ SO ₄ ) as the electrolytic plating solution. The temperature of the plating bath is preferably set within a range of, for example, 25°C to 35°C.

The electrolytic plating process is first performed by a direct current electrolytic plating method, and then by a PR (periodic reverse) pulse electrolytic plating method.
In the direct current electrolytic plating method, the current density is set to be within the range of 1 A/dm ² or more and 20 A/dm ² or less, and the application time is set to be within the range of 10 seconds or more and 120 seconds or less.
By carrying out this DC electrolytic plating, even if the surface crystal grains located on the surface of the plate body 31 are coarse, it is possible to sufficiently form the convex portions 36 by the PR pulse electrolytic plating described below.
In particular, when chemical polishing or heat treatment is performed in the stress reducing step S01, the surface crystal grains are likely to become coarse, so it is preferable to perform direct current electrolytic plating.

The PR pulse electrolytic plating method is a method of electrolytic plating in which the direction of the current is periodically reversed while passing it through. For example, positive electrolysis (anodic electrolysis with the plate body 31 (and metal substrate 11) as the anode) of 1 A/dm ² or more and 30 A/dm ² or less is performed for 1 ms or more and 1000 ms or less, and negative electrolysis (negative electrolysis with the plate body 31 (and metal substrate 11) as the negative electrode) of 1 A/dm ² or more and 30 A/dm ² or less is performed for 1 ms or more and 1000 ms or less, and this is repeated. As a result, dissolution of the surface of the plate body 31 (and metal substrate 11) and precipitation of copper are repeatedly performed, and the roughened plating layer 35 is formed.

Here, the number of protrusions 36 in the roughened plating layer 35 can be adjusted by the surface properties of the plate body 31 (and the metal substrate 11) on which the roughened plating layer 35 is formed, and various plating conditions (pulse application time, pulse waveform (ratio of deposition amount/dissolution amount), pulse frequency).
For example, the size of the protrusions 36 can be increased by lengthening the pulse application time or adjusting the ratio of the amount of deposition/amount of dissolution as a pulse waveform. The number of the protrusions 36 can be increased by adjusting the pulse frequency.

(Lamination step S03)
Next, a resin composition 22 containing boron nitride as a filler, an epoxy resin as a thermosetting resin, and a curing agent is disposed on one surface (the upper surface in FIG. 4) of the metal substrate 11. In this embodiment, the resin composition 22 is formed in a sheet shape.
Moreover, a metal plate 30 which will become the circuit layer 13 is disposed on one surface (the upper surface in FIG. 4) of this resin composition 22 .
The resin composition 22 is laminated so as to be in direct contact with the surfaces of the metal substrate 11 and the metal sheet material 30 on which the roughened plating layer 35 is formed.

(Thermocompression bonding process S04)
Next, the stacked metal substrate 11, resin composition 22, and metal plate material 30 are heated while being pressurized in the stacking direction to harden the resin composition 22 to form the insulating resin layer 12 and to bond the metal substrate 11 and the insulating resin layer 12, and the insulating resin layer 12 and the metal plate material 30.
The conditions for this thermocompression step S04 are preferably a heating temperature in the range of 100° C. to 400° C., a holding time at the heating temperature in the range of 30 minutes to 90 minutes, and a pressure in the stacking direction in the range of 1 MPa to 100 MPa.

(Circuit pattern forming process S05)
Next, the metal plate material 30 joined to the insulating resin layer 12 is etched to form a circuit pattern, thereby obtaining the circuit layer 13 .

In this manner, the insulated circuit board 10 of this embodiment is manufactured.

(Heat sink bonding step S06)
Next, the heat sink 41 is joined to the other surface of the metal substrate 11 of the insulating circuit board 10. In this embodiment, the metal substrate 11 and the heat sink 41 are joined via a solder material.

(Semiconductor element bonding step S07)
Then, the semiconductor element 3 is bonded to the circuit layer 13 of the insulating circuit board 10. In this embodiment, the circuit layer 13 and the semiconductor element 3 are bonded via a solder material.
Through the above steps, the power module 1 shown in FIG. 1 is manufactured.

In the metal sheet material 30 and the insulating circuit board 10 (laminate) according to the present embodiment configured as described above, in a region 6 μm in the thickness direction from the outermost layer of the roughened plating layer 35, the area ratio of the region having a KAM value of 1.0 or more is 10% or less. This keeps the residual stress in the surface layer low, and allows the convex portions 36 protruding toward the side opposite the plate body 31 to be formed uniformly and densely in the roughened plating layer 35.
Furthermore, since the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer 35 is 20% or more, or the R (developed interface line length ratio) of the outermost surface of the roughened plating layer 35 is 40% or more, the convex portions 36 are formed uniformly and densely, and the insulating resin layer 12 laminated on the roughened plating layer 35 side engages with the above-mentioned convex portions 36, thereby making it possible to improve the adhesion between the circuit layer 13 (metal sheet material 30) and the insulating resin layer 12, and the adhesion between the metal substrate 11 (metal sheet material 30) and the insulating resin layer 12.

In this embodiment, when the convex portion 36 protruding toward the opposite side to the plate body 31 includes a widening portion 36a whose width gradually increases toward the tip side in the protruding direction, the insulating resin layer 12 laminated on the roughened plating layer 35 side is securely engaged with the convex portion 36, thereby making it possible to further improve the adhesion between the circuit layer 13 (metal sheet material 30) and the insulating resin layer 12, and the adhesion between the metal substrate 11 (metal sheet material 30) and the insulating resin layer 12.

In addition, in this embodiment, since the plate body 31 is made of copper or a copper alloy, a circuit layer 13 (metal plate material 30) having excellent electrical conductivity and thermal conductivity can be formed.

Although the embodiment of the present invention has been described above, the present invention is not limited to this, and can be modified as appropriate without departing from the technical requirements of the invention.
In the present embodiment, the insulating circuit board is manufactured by the method for manufacturing the insulating circuit board shown in FIGS. 3 and 4, but the present invention is not limited to this.

In addition, in this embodiment, the metal plate material 30 forming the circuit layer 13 has been described as being made of oxygen-free copper, but is not limited thereto, and may be made of other copper or copper alloys, or may be made of other metals such as aluminum or aluminum alloys. Furthermore, it may have a structure in which multiple metals are laminated.

Furthermore, in this embodiment, the metal substrate 11 has been described as being made of oxygen-free copper, but the present invention is not limited to this, and may be made of other copper or copper alloys, or may be made of other metals such as aluminum or aluminum alloys. Furthermore, the metal substrate 11 may have a structure in which a plurality of metals are laminated.
The metal substrate 11 may be a heat sink. That is, the heat sink may be directly bonded to the other surface of the insulating resin layer 12.

In addition, in this embodiment, a power module is configured by mounting a semiconductor element on an insulating circuit board, but this is not limited to the above. For example, an LED module may be configured by mounting an LED element on a circuit layer of an insulating circuit board, or a thermoelectric module may be configured by mounting a thermoelectric element on a circuit layer of an insulating circuit board.

In this embodiment, both the circuit layer 13 and the metal substrate 11 are described as being formed by bonding the metal plate material 30 according to this embodiment to the surface of the insulating resin layer 12, but this is not limited to this. If either the circuit layer 13 or the metal substrate 11 is formed by bonding the metal plate material 30 according to this embodiment to the surface of the insulating resin layer 12, the action and effect described in this embodiment can be obtained. In particular, the action and effect described in this embodiment can be obtained more easily when the metal substrate 11 is the metal plate material 30 according to this embodiment than when the circuit layer 13 is the metal plate material 30 according to this embodiment.

Below, we explain the results of the confirmation experiments conducted to confirm the effectiveness of the present invention.

A metal substrate (40 mm x 40 mm x 2 mm thick) made of rolled oxygen-free copper and a metal sheet material (40 mm x 40 mm x 0.5 mm thick) that will become the circuit layer were prepared, and a stress reduction process was carried out on the surfaces of the metal substrate and metal sheet material that will become the bonding surfaces with the insulating resin layer as shown in Table 1. After that, a roughened plating layer was formed by the DC electrolytic plating method and the PR pulse electrolytic plating method described in the above embodiment. The plating conditions are shown in Table 1. The application time of the PR pulse electrolysis in Table 1 is the total application time of the pulse current.

Then, a sheet material (40 mm×40 mm×0.15 mm thick) of a resin composition containing an epoxy resin containing boron nitride as a filler was placed on the surface of the metal substrate on which the roughened plating layer was formed.
In addition, a metal plate material to become a circuit layer was laminated on one surface of the sheet material of the resin composition such that the surface on which the roughened plating layer was formed faced the sheet material side of the resin composition.

The metal substrate, the resin composition sheet material, and the metal plate material laminated as described above were heated while being pressed in the lamination direction, the resin composition was cured to form an insulating resin layer, and the metal substrate and the insulating resin layer, and the insulating resin layer and the metal plate material were bonded to obtain an insulating circuit substrate. The pressure in the lamination direction was 10 MPa, the heating temperature was 180° C., and the holding time at the heating temperature was 60 minutes.
The metal plates and insulating circuit boards thus obtained were evaluated for the following items.

(Area ratio of region having KAM value of 1.0 or more)
The KAM value was measured as follows using an EBSD measuring device and OIM analysis software, with the observation planes being a plane perpendicular to the rolling width direction of the metal sheet, i.e., the TD plane (transverse direction) and a plane perpendicular to the rolling direction, i.e., the RD plane (rolling direction).

The observation surface was mechanically polished using waterproof abrasive paper. Next, cross-sectional ion processing was performed using a cross-sectional ion processing device (IM-4000, Hitachi High-Tech Corporation). Then, using an EBSD detector (Hikari, TSL/EDAX Corporation) mounted on a scanning electron microscope (ULTRA55, Carl Zeiss Corporation), the EBSD pattern was measured in the observation surface in a range of 7 μm wide perpendicular to the plating surface and 30 μm wide parallel to the plating surface at a measurement interval of 0.1 μm at an electron beam acceleration voltage of 15 kV. The orientation difference of each crystal grain was analyzed using analysis software (OIM Data Analysis ver. 7, EDAX/TSL Corporation), and the boundary where the orientation difference between adjacent pixels is 5° or more was regarded as a crystal grain boundary, and the KAM value near the plating surface (width 11 μm) was calculated.

When calculating the KAM value, in order to remove non-copper plated areas resulting from the unevenness of the roughened plating layer surface from the data of the measurement range, measurement points with an IQ (Image Quality) value of 600 or less were excluded in this measurement. The IQ value is a relative index that indicates the clarity of the EBSD pattern, but it varies greatly depending on the measurement conditions, detector, material, and state of the sample observation surface, so the IQ value was adjusted by checking whether the non-copper plated areas had been removed while comparing with the scanning electron microscope image.

(Sdr of the outermost surface of the roughened plating layer)
The surface of the roughened plating layer of the metal sheet before being bonded to the insulating resin layer was observed in a measurement range of 129 μm × 129 μm using a 100x objective lens of a laser microscope (OLS5000 manufactured by Olympus Corporation). The inclination of the sample and processing to remove noise were performed, and the obtained image was analyzed, and the developed interface area ratio Sdr of the roughened plating layer of the metal sheet was calculated by the method described in the embodiment.

(R of the outermost surface of the roughened plating layer)
A cross section parallel to the longitudinal direction of the insulating circuit board and a cross section perpendicular to the longitudinal direction of the insulating circuit board were prepared. The cross sections were mechanically polished using waterproof abrasive paper. Next, cross section ion processing was performed using a cross section ion processing device (IM-4000 manufactured by Hitachi High-Tech Corporation). Each cross section was observed at a magnification of 1000 times using a scanning electron microscope. In the cross section, the cross section curve of the roughened plating layer at the joint interface between the metal sheet material and the insulating resin layer was specified. A range of 115 μm of the cross section curve was observed. Here, the outline of the metal piece independent of the metal sheet material and present in the insulating resin layer and the outline of the resin piece independent of the insulating resin layer and present in the metal sheet material were removed. The obtained image was analyzed, and the developed interface line length ratio R was calculated. The average value of the developed interface line length ratio R in the cross section parallel to the longitudinal direction of the insulating circuit board and the developed interface line length ratio R in the cross section perpendicular to the longitudinal direction of the insulating circuit board was taken as the developed interface line length ratio R of the roughened plating layer.

(Partial discharge inception voltage and dielectric strength voltage after moisture absorption and reflow)
The insulating circuit board was placed in a thermo-hygrostat (temperature 85° C., humidity 85%) and held there for 3 days, and then placed in a heating furnace and subjected to a reflow treatment at 290° C. for 10 minutes.
In the insulating circuit board after the reflow treatment, the partial discharge inception voltage and the dielectric breakdown voltage (dielectric strength voltage) of the circuit layer and the insulating resin layer were evaluated as follows.
5, the metal substrate 11 was placed on a base plate 61, and a probe 62 was brought into contact with the circuit layer 13 to evaluate partial discharge. A partial discharge tester manufactured by Mitsubishi Electric Wire Co., Ltd. was used as the measuring device. The test was carried out in a Fluorinert (tm) FC-770 manufactured by 3M Company as the test atmosphere.
The voltage was increased in a step profile of 0.5 kV (holding time 60 seconds), and the voltage at which the average discharge charge was 5 pC or more was defined as the partial discharge inception voltage. The voltage at which dielectric breakdown occurred (the voltage at which the leakage current was 10 mA or more) was defined as the dielectric breakdown voltage. The evaluation results are shown in Table 2.
A partial discharge starts due to a small peeling void, and when a voltage above a certain level is applied, it leads to dielectric breakdown. The partial discharge inception voltage is the value caused by a small peeling.

In Comparative Examples 1 to 5, DC electrolytic plating was performed without reducing the residual stress in the plate body, and then PR pulse electrolytic plating was performed to form a roughened plating layer. As a result, the area ratio of the area in which the KAM value was 1.0 or more in the area 6 μm in the thickness direction from the outermost layer of the roughened plating layer exceeded 10%, and the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer was less than 20%. In these Comparative Examples 1 to 5, the partial discharge inception voltage after moisture absorption reflow was low, and the adhesion between the circuit layer (metal substrate) and the insulating resin layer was insufficient.

In Examples 1 to 12 of the present invention, the residual stress in the plate body was reduced by chemical polishing, DC electrolytic plating was performed, and then PR pulse electrolytic plating was performed to form a roughened plating layer. As a result, the area ratio of the area having a KAM value of 1.0 or more in a region 6 μm in the thickness direction from the outermost layer of the roughened plating layer was 10% or less, and the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer was 20% or more. In these Examples 1 to 12 of the present invention, the partial discharge inception voltage after moisture absorption reflow was high, and the circuit layer (metal substrate) and the insulating resin layer were sufficiently adhered to each other.

From the above experimental results, it has been confirmed that the present invention can provide a metal plate material having excellent adhesion to a laminated resin member, a laminate in which this metal plate material is laminated with a resin member, and an insulated circuit board.

The metal plate material of this embodiment has excellent adhesion to the laminated resin member. Therefore, the laminate and the insulating circuit board in which the metal plate material of this embodiment and the resin member are laminated are suitably applied to power modules, LED modules, and thermoelectric modules.

10 Insulated circuit board (laminate)
11 Metal substrate 12 Insulating resin layer (resin member)
13 Circuit layer 30 Metal plate material 31 Plate body 35 Roughened plating layer 36 Convex portion 36a Widened portion

Claims (6)

The plate has a plate body and a roughening plating layer formed on the outermost surface of the plate body,
The plate body is a rolled plate having a thickness in the range of 0.05 mm or more and 3 mm or less,
The roughening plating layer has a convex portion protruding toward the opposite side to the plate body,
In a region of 6 μm from the outermost layer of the roughened plating layer in a thickness direction, the area ratio of a region having a KAM value of 1.0 or more is 10% or less,
A metal sheet material characterized in that the Sdr (developed interface area ratio) of the outermost surface of the roughened plating layer is 20% or more, or the R (developed interface line length ratio) of the outermost surface of the roughened plating layer is 40% or more. The metal plate material according to claim 1, characterized in that the convex portion has a widening portion whose width gradually increases toward the tip end in the protruding direction. The metal plate material according to claim 1 or 2, characterized in that the plate body is made of copper or a copper alloy. A laminate in which a resin member is laminated on a plate surface of the metal plate material according to any one of claims 1 to 3,
A laminate, characterized in that, at a joint interface between the resin member and the metal plate, the resin member engages with the protrusion of the metal plate. An insulating circuit board comprising an insulating resin layer and a circuit layer formed on one surface of the insulating resin layer,
The circuit layer is formed by bonding the metal plate material according to any one of claims 1 to 3 to one surface of the insulating resin layer,
2. An insulating circuit board, comprising: a first insulating resin layer and a second insulating resin layer, the first insulating resin layer being engaged with the protrusions of the metal plate at a bonding interface between the first insulating resin layer and the second insulating resin layer; An insulating circuit board comprising an insulating resin layer, a circuit layer formed on one surface of the insulating resin layer, and a metal substrate formed on the other surface of the insulating resin layer,
One or both of the circuit layer and the metal substrate are formed by bonding the metal plate material according to any one of claims 1 to 3 to a surface of the insulating resin layer,
An insulated circuit board, characterized in that the insulating resin layer engages with the convex portion of the metal plate material at either or both of the bonding interface between the insulating resin layer and the circuit layer and the bonding interface between the insulating resin layer and the metal plate.

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