JP7651263B2 - Multilayer ceramic capacitor and method of manufacturing same - Google Patents

Description

The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

When mounting ceramic electronic components such as multilayer ceramic capacitors on a substrate, a structure has been disclosed in which a conductive resin layer made by mixing a metal component into the resin is provided on the external electrodes for the purpose of stress relief (see, for example, Patent Document 1).

JP 2016-63008 A

When such ceramic electronic components are used in a high-temperature, high-humidity environment, the moisture adhering to the surface of the ceramic electronic components may cause the metal components contained in the conductive resin layer to diffuse, resulting in a decrease in reliability. Even if the external electrodes do not contain a conductive resin layer, the metal components contained in the external electrodes may diffuse, resulting in a decrease in reliability.

The present invention has been made in consideration of the above problems, and aims to provide a multilayer ceramic capacitor and a manufacturing method thereof that can improve reliability.

The multilayer ceramic capacitor according to the present invention is characterized in that it comprises a multilayer chip having a substantially rectangular parallelepiped shape in which a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers are laminated, and the laminated plurality of internal electrode layers are exposed on at least one of two opposing end faces, a pair of external electrodes formed on the two end faces, and a fluorine compound that adheres to areas of the surface of the multilayer chip where the external electrodes are not formed and at least a portion of the surface of the external electrodes, and is released at any temperature of 380°C or higher.

In the multilayer ceramic capacitor, the fluorine compound may be a compound with a mass-to-charge ratio of m/z=19 in GC-MS analysis.

In the multilayer ceramic capacitor, the fluorine compound may have an emission peak at any temperature of 380°C or higher.

In the multilayer ceramic capacitor, the fluorine compound may be attached between the pair of external electrodes on the surface of the multilayer chip.

In the multilayer ceramic capacitor, the external electrodes may include a conductive resin layer containing a metal component.

In the multilayer ceramic capacitor, the fluorine compound may not be released at temperatures below 380°C.

The method for manufacturing a multilayer ceramic capacitor according to the present invention is characterized by comprising the steps of: preparing a multilayer ceramic capacitor having a laminated chip having a substantially rectangular parallelepiped shape in which a plurality of dielectric layers and a plurality of internal electrode layers, each of which is mainly composed of ceramic, are laminated, and the laminated plurality of internal electrode layers are formed so as to be exposed on at least one of two opposing end faces; and a pair of external electrodes formed on the two end faces; and contacting heated fluororubber with the areas of the surface of the laminated chip where the external electrodes are not formed and at least a portion of the surface of the external electrodes, thereby adhering a fluorine compound that is released at any temperature of 380°C or higher.

In the method for manufacturing a multilayer ceramic capacitor, the multilayer ceramic capacitor before the fluorine compound is attached may be mounted on a substrate, and a heated fluororubber sheet may be pressed against the multilayer ceramic capacitor, thereby attaching the fluorine compound to areas of the surface of the laminated chip where the external electrodes are not formed and at least a portion of the surface of the external electrodes.

In the method for manufacturing the multilayer ceramic capacitor, the fluororubber heated to 150°C or higher may be brought into contact with the areas of the multilayer chip where the external electrodes are not formed and at least a portion of the surface of the external electrodes.

The present invention provides a multilayer ceramic capacitor and a manufacturing method thereof that can improve reliability.

FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. 2 is a cross-sectional view of an external electrode, taken along line AA of FIG. 1; 1 is a diagram illustrating a structure in which a fluorine compound is attached to a multilayer ceramic capacitor; 1 is a diagram illustrating a structure in which a fluorine compound is attached to a multilayer ceramic capacitor; 1 is a diagram illustrating a structure in which a fluorine compound is attached to a multilayer ceramic capacitor; 1 is a diagram illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. 1 is a diagram illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. 13 is a diagram illustrating a case where a fluorine sheet is pressed. FIG. FIG. 2A is a diagram showing the GC-MS analysis results of Example 1, and FIG. 2B is a diagram showing the GC-MS analysis results of Example 4. FIG. 1 shows the analysis results for m/z=19.

The following describes the embodiment with reference to the drawings.

(Embodiment)
First, an overview of the multilayer ceramic capacitor will be described. FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. As illustrated in FIG. 1, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a rectangular parallelepiped shape, and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the upper and lower faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the upper, lower and two side faces in the stacking direction of the laminated chip 10. However, the external electrodes 20a, 20b are spaced apart from each other.

The laminated chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately laminated. The edges of each internal electrode layer 12 are alternately exposed to the end face of the laminated chip 10 on which the external electrode 20a is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the laminated ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are laminated via the internal electrode layers 12. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged on the outermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered by the cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layer 11 and the ceramic material.

The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high, or 0.4 mm long, 0.2 mm wide, and 0.2 mm high, or 0.6 mm long, 0.3 mm wide, and 0.3 mm high, or 1.0 mm long, 0.5 mm wide, and 0.5 mm high, or 3.2 mm long, 1.6 mm wide, and 1.6 mm high, or 4.5 mm long, 3.2 mm wide, and 2.5 mm high, but is not limited to these sizes.

The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layers 12. The dielectric layers 11 are mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO _3. The perovskite structure includes ABO _3-α , which is deviated from the stoichiometric composition. For example, the ceramic material may be _BaTiO3 (barium titanate), _CaZrO3 (calcium zirconate), _CaTiO3 (calcium titanate), _SrTiO3 (strontium titanate), or Ba1 _-x- yCaxSryTi1 _{- zZrzO3} (0 _≦ x≦1, 0≦y≦1, 0≦z≦1 ₎ which forms a _perovskite structure.

Figure 2 is a cross-sectional view of the external electrode 20b, and is a partial cross-sectional view taken along line A-A in Figure 1. Note that hatching representing the cross section has been omitted in Figure 2. As illustrated in Figure 2, the external electrode 20b has a structure in which a first plating layer 22 such as Cu, a conductive resin layer 23, a second plating layer 24 such as Ni, and a third plating layer 25 such as Sn are formed on an underlayer 21. The underlayer 21, the first plating layer 22, the conductive resin layer 23, the second plating layer 24, and the third plating layer 25 extend from both end faces of the laminated chip 10 to two side faces and the upper and lower faces in the stacking direction.

The underlayer 21 is mainly composed of metals such as Cu, Ni, Al (aluminum), and Zn (zinc), and contains glass components for densifying the underlayer 21 and co-materials for controlling the sintering property of the underlayer 21. The underlayer 21, which contains a large amount of these ceramic components, has good adhesion to the cover layer 13, which is mainly composed of a ceramic material. The conductive resin layer 23 is a resin layer containing metal components such as Ag. The conductive resin layer 23 is flexible, so it relieves stress caused by the bending of the substrate on which the multilayer ceramic capacitor 100 is mounted. The first plating layer 22 is provided to increase the adhesion between the underlayer 21 and the conductive resin layer 23. The external electrode 20a also has a laminated structure similar to that of the external electrode 20b. The conductive resin layer 23 does not necessarily have to be provided.

When the external electrodes 20a, 20b have the structure shown in FIG. 2, if the multilayer ceramic capacitor 100 is used in a high-temperature and high-humidity environment, the metal components contained in the conductive resin layer 23 may dissolve and diffuse due to moisture adhering to the surface of the multilayer ceramic capacitor 100, resulting in a risk of reduced reliability. For example, there is a risk of the metal components contained in the conductive resin layer 23 diffusing between the external electrodes 20a and 20b on the surface of the laminated chip 10 (migration). Even if the external electrodes 20a, 20b do not contain the conductive resin layer 23, there is a risk of the metal components contained in the external electrodes 20a, 20b diffusing.

Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a structure in which the fluorine compound 14 is attached to at least a portion of the surface, as illustrated in FIG. 3. The fluorine compound 14 is attached to the areas of the surface of the laminated chip 10 where the external electrodes 20a, 20b are not formed, and to at least a portion of the surfaces of the external electrodes 20a, 20b. For example, as illustrated in FIG. 4, the fluorine compound 14 may be attached only to a portion of the areas of the surface of the laminated chip 10 where the external electrodes 20a, 20b are not formed. Or, as illustrated in FIG. 5, the fluorine compound 14 may be attached only to a portion of the surfaces of the external electrodes 20a, 20b.

Note that "adhering to the surface" here includes cases where the material is directly attached to the surface, and cases where the material is attached to the surface via another film, etc. The same applies to the following explanation.

In this embodiment, the fluorine compound 14 is a fluorine compound that is released from the surface of the multilayer ceramic capacitor 100 at any temperature of 380°C or higher. Since the fluorine compound 14 is released at any temperature of 380°C or higher, it tends to remain even after the multilayer ceramic capacitor 100 is soldered and mounted. Since the fluorine compound 14 has water repellency, adhesion of moisture to the surface of the multilayer ceramic capacitor 100 is suppressed even when the multilayer ceramic capacitor 100 is used in a high-temperature and high-humidity environment. As a result, the reliability of the multilayer ceramic capacitor 100 can be improved. The fluorine compound 14 contributes to improving reliability whether it is attached to the area on the surface of the laminated chip 10 where the external electrodes 20a, 20b are not formed or to the surface of the external electrodes 20a, 20b. In addition, it is preferable that the fluorine compound 14 is not released from the surface of the multilayer ceramic capacitor 100 at temperatures below 380°C.

Fluorine compound 14 is, for example, a compound with a mass-to-charge ratio of m/z = 19 in GC-MS (Gas Chromatography Mass Spectrometry) analysis. Fluorine compound 14 preferably has at least one emission peak (maximum emission amount) at any temperature of 300°C or higher.

Even if the fluorine compound 14 adheres to the surfaces of the external electrodes 20a and 20b, the decrease in the wettability of the solder is suppressed. This is because the amount of the adhered fluorine compound 14 is very small. For example, the thickness of the fluorine compound 14 is in the range of 1 nm to 80 nm. Therefore, even if the fluorine compound 14 adheres to the surfaces of the external electrodes 20a and 20b, the mountability can be maintained.

The locations where the fluorine compound 14 adheres on the surface of the multilayer ceramic capacitor 100 are not particularly limited, but it is preferable that the fluorine compound 14 adheres to at least a portion of the area between the external electrodes 20a and 20b on the top, bottom, and two side surfaces of the multilayer chip 10. This is because the adhesion of moisture between the external electrodes 20a and 20b on the surface of the multilayer chip 10 is suppressed, thereby suppressing migration.

Alternatively, it is preferable that the fluorine compound 14 covers the entire multilayer ceramic capacitor 100. This is because the adhesion of moisture to the entire multilayer ceramic capacitor 100 is suppressed.

Next, we will explain the manufacturing method of the multilayer ceramic capacitor 100. Figure 6 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.

(Raw material powder preparation process)
First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of _ABO3 particles. For example, _BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This _BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known so far as a method for synthesizing the ceramics constituting the dielectric layer 11, such as a solid-phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these methods can be adopted.

The resulting ceramic powder is added with a specific additive compound according to the purpose. Examples of additive compounds include oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) and Yb (ytterbium)), as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium) and Si (silicon).

In this embodiment, preferably, first, a compound containing an additive compound is mixed with the ceramic particles constituting the dielectric layer 11, and calcined at 820 to 1150°C. The resulting ceramic particles are then wet-mixed with the additive compound, dried, and pulverized to prepare a ceramic powder. For example, the average particle size of the ceramic powder is preferably 50 to 300 nm from the viewpoint of thinning the dielectric layer 11. For example, the ceramic powder obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size.

(Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. Using the obtained slurry, a belt-shaped dielectric green sheet having a thickness of, for example, 0.8 μm or less is applied to a substrate by, for example, a die coater method or a doctor blade method, and then dried.

Next, a metal conductive paste for forming internal electrodes containing an organic binder is printed on the surface of the dielectric green sheet by screen printing, gravure printing, or the like to arrange the pattern for the internal electrode layer. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main ceramic component of the dielectric layer 11.

After that, in a state where it is peeled off from the base material, the dielectric green sheets are alternately stacked so that the internal electrode layers 12 and the dielectric layers 11 are alternately stacked, and so that the edges of the internal electrode layers 12 are alternately exposed at both end faces in the longitudinal direction of the dielectric layers 11 and alternately drawn out to a pair of external electrodes 20a, 20b of different polarity. For example, the total number of stacked layers is 100 to 500 layers.

Then, cover sheets that become the cover layers 13 are pressed onto the top and bottom of the laminate of the laminated dielectric green sheets to obtain a ceramic laminate. Then, the obtained ceramic laminate (for example, 1.0 mm x 0.5 mm) is subjected to a binder removal process in a _N2 atmosphere at 250 to 500°C.

(Firing process)
The molded body thus obtained is fired in a reducing atmosphere with an oxygen partial pressure of 10 ⁻⁷ to 10 ⁻¹⁰ atm at 1100 to 1300° C. for 10 minutes to 2 hours.

(Reoxidation treatment process)
Thereafter, a re-oxidation treatment may be performed at 600° C. to 1000° C. in a N ₂ gas atmosphere.

(External electrode formation process)
Next, a metal paste containing a metal filler, glass frit, binder, and solvent is applied to both end surfaces of the laminated chip 10 by a dipping method, dried, and baked. This forms the underlayer 21. The binder and solvent are evaporated by baking. Cu or the like is suitable as the metal filler for this method. It is preferable to bake at 700°C to 900°C for about 3 minutes to 30 minutes, particularly at 760°C to 840°C for 5 minutes to 15 minutes. After that, the first plating layer 22 may be formed on the underlayer 21 by plating.

Next, the conductive resin layer 23 is formed. The conductive resin layer 23 is formed by dip-coating the surface of the first plating layer 22 with a thermosetting resin, such as epoxy resin or phenolic resin, kneaded with conductive fillers such as Ag, Ni, Cu, etc., and then curing it by heat treatment. There are no particular limitations on the thickness of the conductive resin layer 23, and it is, for example, about 10 to 50 μm, and is set appropriately depending on the size of the product being processed. Thereafter, the second plating layer 24 and the third plating layer 25 are formed on the conductive resin layer 23 by electrolytic plating or the like.

(Heat contact step)
Next, the fluororubber is heated to 150° C. or higher and brought into contact with the surface of the product being processed. This allows the fluorine compound 14 to adhere to areas of the surface of the laminated chip 10 where the external electrodes 20 a, 20 b are not formed and at least a portion of the surfaces of the external electrodes 20 a, 20 b. In this manner, the laminated ceramic capacitor 100 is obtained.

According to the manufacturing method of this embodiment, the fluororubber is heated to 150°C or higher and brought into contact with the surface of the multilayer ceramic capacitor 100, so that the fluorine compound released from the surface of the multilayer ceramic capacitor 100 at any temperature of 380°C or higher can be attached to the area of the surface of the laminated chip 10 where the external electrodes 20a, 20b are not formed and at least a part of the surface of the external electrodes 20a, 20b. As a result, the fluorine compound 14 tends to remain even after the multilayer ceramic capacitor 100 is soldered and mounted. Since the fluorine compound 14 is water repellent, adhesion of moisture to the surface of the multilayer ceramic capacitor 100 is suppressed even when the multilayer ceramic capacitor 100 is used in a high-temperature and high-humidity environment. As a result, the reliability of the multilayer ceramic capacitor 100 can be improved.

The underlayer 21 may be fired simultaneously with firing the laminated chip 10. In this case, as illustrated in FIG. 7, the ceramic laminate obtained in the lamination step is debindered in an N ₂ atmosphere at 250 to 500° C., and then a metal paste containing a metal filler, a common material, a binder, and a solvent is applied to both end faces of the ceramic laminate by a dip method and dried. Then, the metal paste is fired simultaneously with the ceramic laminate. The firing conditions are, for example, exemplified in the firing step described above. Then, a reoxidation treatment may be performed at 600° C. to 1000° C. in an N ₂ gas atmosphere. Then, the first plating layer 22 is formed on the underlayer 21 by plating. Next, a conductive resin layer 23 is formed on the surface of the first plating layer 22. Then, a second plating layer 24 and a third plating layer 25 are formed on the conductive resin layer 23 by electrolytic plating or the like.

As illustrated in FIG. 8, the laminated ceramic capacitor 100 before the fluorine compound 14 is attached may be mounted on the substrate 16, the fluorine rubber sheet 17 may be heated, and the heated fluorine rubber sheet 17 may be pressed against the laminated ceramic capacitor 100 to attach the fluorine compound 14 to the area on the surface of the laminated chip 10 where the external electrodes 20a, 20b are not formed and at least a part of the surface of the external electrodes 20a, 20b. In this case, the fluorine compound 14 can also be attached to the substrate 16, so that failures due to condensation occurring on the surface of the substrate 16 can be suppressed. In addition, since the laminated ceramic capacitor 100 is mounted before the fluorine rubber sheet 17 is pressed against it, mounting defects can be suppressed. The apparent density of the fluorine rubber sheet 17 is preferably 0.75 g/cm ³ or less. This is because if the apparent density of the fluorine rubber is large, the sheet 17 becomes hard, and the chip cannot be sufficiently covered when the sheet 17 is pressed against it, and if the sheet 17 with a high apparent density is pressed against the chip to cover it, excessive force may be applied, which may damage the chip. The apparent density refers to the mass of the sheet 17 relative to its volume.

In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may be used.

The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were investigated.

(Examples 1 to 4)
A reduction-resistant ceramic powder mainly composed of barium titanate was mixed with an organic binder to prepare a slurry, which was then formed into a sheet using a doctor blade or the like to produce a dielectric green sheet. A Ni metal conductive paste was applied to this dielectric green sheet in a predetermined pattern using a screen printing method to form an internal electrode pattern. The dielectric green sheet with the internal electrode pattern formed was cut into a predetermined shape, and a predetermined number of sheets were stacked together and then thermocompressed to produce a ceramic laminate.

Next, the ceramic laminate was cut and divided into chips of a specified size. A metal paste containing a common material was applied to the electrode exposed surfaces (both end surfaces) of the resulting ceramic laminate by immersion to obtain a specified electrode width (dimension E).

Then, the obtained ceramic laminate was fired at 1250°C in a nitrogen or hydrogen atmosphere and subjected to a predetermined heat treatment to produce the laminated chip 10 and the underlayer 21 covering both end faces thereof. Then, the surface of the underlayer 21 was dry-polished using "White Morundum" (registered trademark) as an abrasive, and then Cu plating was applied to form the first plating layer 22. Next, a conductive resin paste adjusted to a predetermined viscosity (10 to 30 Pa·s) was applied to the surface of the first plating layer 22 by a dipping method. For the conductive resin paste, epoxy resin kneaded with Ag filler was used. Then, the conductive resin paste was hardened by heat treatment to form the conductive resin layer 23. Then, Ni plating and Sn plating were applied in sequence on the conductive resin layer 23 to form the second plating layer 24 and the third plating layer 25. The size of the obtained laminated ceramic capacitor 100 was 3.2 mm in length, 2.5 mm in width, and 2.5 mm in height.

The fluororubber was heated together with the multilayer ceramic capacitor 100, and the fluororubber was brought into contact with the surface of the multilayer ceramic capacitor 100. This caused the fluorine compound 14 to adhere to the surface of the multilayer ceramic capacitor 100. In Example 1, the heating temperature of the fluororubber was 150°C. In Example 2, the heating temperature of the fluororubber was 170°C. In Example 3, the heating temperature of the fluororubber was 190°C. In Example 4, the heating temperature of the fluororubber was 210°C.

In the comparative example, no fluorine compound was applied (no water-repellent treatment).

The release of fluorine compounds was confirmed for the multilayer ceramic capacitors 100 of Examples 1 and 4. The capacitors were heated from 60°C to 800°C using a gas chromatography mass spectrometer: GC-MS (Frontier Labs EGA/Py-3030D/Agilent GC7980A/JEOL JMS1050GC), and the components and amount of released gas were analyzed based on the mass of the released gas.

The analysis conditions are as follows.
Thermal decomposition conditions: Thermal decomposition temperature 60°C to 800°C
：Temperature rise rate 20℃/min
Column: Column inner diameter 0.25 mm
: Column length 5m
Oven temperature conditions: Temperature range 250°C
: Retention time 37 minutes

Figure 9(a) shows the GC-MS analysis results of Example 1. Figure 9(b) shows the GC-MS analysis results of Example 4. In Figures 9(a) and 9(b), the horizontal axis indicates the mass-to-charge ratio (m/z value), and the vertical axis indicates the peak intensity. Figures 9(a) and 9(b) show the results when the heating temperature was 450°C. As shown in Figures 9(a) and 9(b), the release of fluorine with m/z = 19 was confirmed when the heating temperature was 450°C.

Figure 10 shows the GC-MS analysis results for Examples 1 and 4, focusing on m/z = 19, with temperature on the horizontal axis. As shown in Figure 10, in Examples 1 and 4, no release of fluorine compounds was confirmed at temperatures below 380°C, but release of fluorine compounds was confirmed at high temperatures of 380°C or higher. This is thought to be because the release of fluorine compounds at low temperatures was suppressed by contacting the fluororubber with heat. Note that in the results of Figure 10, a peak in the release of fluorine compounds was confirmed at 380°C or higher.

Next, a moisture resistance test was conducted on 400 other samples each for Examples 1 to 4 and the Comparative Example. In the moisture resistance test, the samples were placed in an environment with a temperature of 120°C and a relative humidity of 85%, and a voltage 1.5 times the rated voltage was applied, after which electrical measurements (insulation resistance between the mounting electrodes) were confirmed 100 hours later. If the insulation resistance value x capacitance value met 100 MΩ·μF, the sample was deemed to have passed, and if it did not, it was deemed to have failed. The ratio of samples that failed out of the 400 samples was investigated.

Next, a condensation test was conducted on the other 400 samples of Examples 1 to 4 and Comparative Example. The samples were mounted on a reliable board (CEM3) and placed in a constant temperature and humidity chamber while applying a voltage of 16 V. The occurrence of migration was confirmed after six cycles of the condensation test program of JIS 60068-2-30 (conditions for one cycle: (1) humidity 98% maintained, temperature changed from 25°C to 55°C over three hours, (2) temperature 55°C maintained, humidity changed from 98% to 93% over 15 minutes, (3) temperature 55°C, humidity 93% maintained for nine hours and 25 minutes, (4) humidity 93% maintained, temperature changed from 55°C to 25°C over three hours, (5) temperature 25°C, humidity 93% maintained for three hours, (6) temperature 25°C maintained, humidity changed from 93% to 98% over five hours and 30 minutes). Migration was determined by visually checking whether or not there were any deposits between the external electrodes using a 40x stereo microscope, and if there were any deposits, it was determined that migration had occurred. The percentage of samples in which migration had occurred was investigated out of 400 samples.

The results of the moisture resistance test and the condensation test are shown in Table 1. As shown in Table 1, the failure rate of the moisture resistance test was high in the comparative example, whereas the failure rate of the moisture resistance test was low in Examples 1 to 4. This is believed to be because water repellency was obtained by forming fluorine compound 14.

Next, the failure rate of the condensation test was high in the comparative example, whereas the failure rate of the condensation test was low in Examples 1 to 4. This is believed to be because water repellency was achieved by forming fluorine compound 14.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as described in the claims.

REFERENCE SIGNS LIST 10 laminated chip 11 dielectric layer 12 internal electrode layer 13 cover layer 14 fluorine compound 20a, 20b external electrode 100 laminated ceramic capacitor

Claims (10)

a laminated chip having a substantially rectangular parallelepiped shape, in which a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers are laminated, the laminated plurality of internal electrode layers being exposed on at least one of two opposing end faces;
A pair of external electrodes formed on the two end surfaces;
a fluorine compound that adheres to at least a portion of the surface of the external electrode and to an area of the surface of the laminated chip where the external electrode is not formed, on both an upper surface and a lower surface, which are two surfaces sandwiching the stacking direction of the plurality of internal electrode layers of the laminated chip, and is released at any temperature of 380° C. or higher ;
The multilayer ceramic capacitor is characterized in that the fluorine compound is attached to the surfaces of the external electrodes in the portions covering the two end faces . The multilayer ceramic capacitor according to claim 1, characterized in that the fluorine compound is a compound with a mass-to-charge ratio of m/z = 19 in GC-MS analysis. The multilayer ceramic capacitor according to claim 1 or 2, characterized in that the fluorine compound has an emission peak at any temperature of 380°C or higher. The multilayer ceramic capacitor according to any one of claims 1 to 3, characterized in that the fluorine compound is attached between the pair of external electrodes on the surface of the multilayer chip. The multilayer ceramic capacitor according to any one of claims 1 to 4, characterized in that the external electrodes include conductive resin layers containing a metal component. The multilayer ceramic capacitor according to any one of claims 1 to 5, characterized in that the fluorine compound is not released at temperatures below 380°C. The multilayer ceramic capacitor according to any one of claims 1 to 6, characterized in that the thickness of the fluorine compound is 1 nm to 80 nm. a step of preparing a multilayer ceramic capacitor comprising: a laminated chip having a substantially rectangular parallelepiped shape in which a plurality of dielectric layers and a plurality of internal electrode layers, each of which is mainly composed of ceramic, are laminated, the laminated plurality of internal electrode layers being exposed on at least one of two opposing end faces; and a pair of external electrodes formed on the two end faces;
and contacting heated fluororubber with areas of the surface of the laminated chip where the external electrodes are not formed and at least a portion of the surface of the external electrodes, thereby adhering a fluorine compound that is released at any temperature of 380°C or higher. 9. The method for manufacturing a multilayer ceramic capacitor according to claim 8, characterized in that the multilayer ceramic capacitor before the adhesion of the fluorine compound is mounted on a substrate, and a heated fluororubber sheet is pressed against the multilayer ceramic capacitor, thereby adhering the fluorine compound to areas of the surface of the laminated chip where the external electrodes are not formed and at least a part of the surfaces of the external electrodes. 10. The method for manufacturing a multilayer ceramic capacitor according to claim 8, wherein the fluororubber heated to 150° C. or higher is brought into contact with areas of the laminated chip where the external electrodes are not formed and at least parts of the surfaces of the external electrodes.

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