JP7652927B2 - A scheme for adjusting the adaptive resolution of motion vector differences. - Google Patents

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Nonprovisional Application No. 17/824,193, entitled "Schemes for Adjusting Adaptive Resolution for Motion Vector Difference," filed May 25, 2022, and claims the benefit of priority to U.S. Provisional Application No. 63/302,518, entitled "Further Improvement for Adaptive MVD Resolution," filed January 24, 2022. These prior applications are incorporated herein by reference in their entireties.

The present disclosure relates generally to video coding, and more particularly to methods and systems for providing a scheme for setting different values of allowable motion vectors when implementing adaptive resolution for motion vector differences.

The background art description provided herein is intended to provide a general context for the present disclosure. The inventors' work is not admitted expressly or impliedly as prior art to the present disclosure, to the extent that that work is described in this background art section, together with aspects of the description that may not otherwise be admitted as prior art at the time of filing of this application.

Video coding and decoding may be performed using inter-picture prediction with motion compensation. Uncompressed digital video may include a sequence of pictures, each with spatial dimensions of, for example, 1920x1080 luma samples and associated fully sampled or subsampled chroma samples. The sequence of pictures may have a fixed or variable picture rate (also called frame rate), for example, 60 pictures per second or 60 frames per second. Uncompressed video has specific bitrate requirements for streaming or data processing. For example, a video with a pixel resolution of 1920x1080, a frame rate of 60 frames per second, and 4:2:0 chroma subsampling with 8 bits per pixel per color channel requires a bandwidth approaching 1.5 Gbit/s. One hour of such video requires more than 600 GByte of storage space.

One goal of video coding and decoding may be the reduction of redundancy in an uncompressed input video signal through compression. Compression may help reduce the aforementioned bandwidth and/or storage space requirements, in some cases by more than one order of magnitude. Both lossless and lossy compression, as well as combinations thereof, may be employed. Lossless compression refers to techniques where an exact copy of the original signal may be reconstructed from the compressed original signal through a decoding process. Lossy compression refers to a coding/decoding process where the original video information is not fully preserved when coding and cannot be fully restored when decoding. When using lossy compression, the reconstructed signal may not be identical to the original signal, but the distortion between the original and reconstructed signals will be small enough to make the reconstructed signal useful for its intended application, even with some information loss. For video, lossy compression has been widely adopted in many applications. The amount of distortion that can be tolerated depends on the application. For example, a user of a particular consumer video streaming application may tolerate higher distortion than a user of a movie or television broadcast application. The compression ratio achievable by a particular coding algorithm may be selected or adjusted to reflect various distortion tolerances. That is, generally speaking, higher distortion tolerance allows for coding algorithms that result in higher losses and higher compression ratios.

Video encoders and decoders can utilize techniques from several broad categories and steps, including, for example, motion compensation, Fourier transform, quantization, and entropy coding.

Video codec technology can include a technique known as intra-coding. In intra-coding, sample values are represented without reference to samples or other data from previously reconstructed reference pictures. In some video codecs, a picture is spatially subdivided into blocks of samples. If all blocks of samples are coded in intra mode, the picture can be called an intra-picture. Intra-pictures and their derived pictures, such as independent decoder refresh pictures, can be used to reset the decoder state and thus can be used as the first picture in a coded video bitstream and video session or as still images. The samples of the block after intra prediction can then be transformed to the frequency domain, and the transform coefficients so produced can be quantized before entropy coding. Intra-prediction represents a technique that minimizes sample values in the pre-transform domain. In some cases, the smaller the DC value after transformation and the smaller the AC coefficients, the fewer bits are required at a given quantization step size to represent the block after entropy coding.

Conventional intra-coding, for example as known from MPEG-2 generation coding techniques, does not use intra-prediction. However, some newer video compression techniques include techniques that attempt to code/decode a block based on surrounding sample data and/or metadata that precedes in decoding order the block of data being intra-coded or intra-decoded, e.g., obtained during the encoding and/or decoding of its spatial neighbors. Such techniques are hereafter referred to as "intra-prediction" techniques. Note that in at least some cases, intra-prediction uses reference data only from the current picture being reconstructed, and not from other reference pictures.

Intra prediction may take many different forms. When more than one of such techniques is available in a given video coding technique, the technique used may be referred to as an intra prediction mode. One or more intra prediction modes may be provided in a particular codec. In certain cases, a mode may have sub-modes and/or may be associated with various parameters, and the mode/sub-mode information and intra coding parameters for a block of video may be coded individually or collectively included in the codeword of the mode. Which codeword is used for a given mode, sub-mode, and/or parameter combination may affect the coding efficiency gains via intra prediction, and therefore also the entropy coding technique used to convert the codeword into a bitstream.

Certain modes of intra prediction were introduced in H.264, improved in H.265, and further refined in newer coding techniques such as the Joint Search Model (JEM), Versatile Video Coding (VVC), and Benchmark Set (BMS). In general, in intra prediction, the predictor block may be formed using neighboring sample values as they become available. For example, the available values of a particular set of neighboring samples along a particular direction and/or line may be copied into the predictor block. The reference to the direction in use may be coded in the bitstream or may itself be predicted.

Referring to FIG. 1A, shown at the bottom right is a subset of the nine predictor directions specified in the 33 possible intra predictor directions of H.265 (corresponding to the 33 angle modes of the 35 intra modes specified in H.265). The point where the arrows converge (101) represents the sample being predicted. The arrows represent the direction from which neighboring samples are used to predict the sample at 101. For example, arrow (102) indicates that sample (101) is predicted from one or more neighboring samples to the upper right at an angle of 45 degrees from the horizontal. Similarly, arrow (103) indicates that sample (101) is predicted from one or more neighboring samples to the lower left of sample (101) at an angle of 22.5 degrees from the horizontal.

With further reference to FIG. 1A, at the top left is shown a square block (104) of 4×4 samples (indicated by the thick dashed line). The square block (104) contains 16 samples, each labeled with an “S”, its position in the Y dimension (e.g., row index), and its position in the X dimension (e.g., column index). For example, sample S21 is the second sample (from the top) in the Y dimension and the first sample (from the left) in the X dimension. Similarly, sample S44 is the fourth sample in both the Y and X dimensions in the block (104). Since the block is 4×4 samples in size, S44 is at the bottom right. An exemplary reference sample, which follows a similar numbering scheme, is further shown. The reference sample is labeled R, its Y position (e.g., row index), and X position (column index) relative to the block (104). In both H.264 and H.265, predicted samples neighboring the block being reconstructed are used.

Intra-picture prediction of block 104 may start by copying reference sample values from neighboring samples according to a signaled prediction direction. For example, assume that the coded video bitstream includes signaling for this block 104 indicating the prediction direction of the arrow (102), i.e., the sample is predicted from one or more prediction samples to the upper right, at an angle of 45 degrees from the horizontal. In such a case, samples S41, S32, S23, and S14 are predicted from the same reference sample R05. Then sample S44 is predicted from reference sample R08.

In certain cases, to calculate a reference sample, especially when the orientation is not evenly divisible by 45 degrees, the values of multiple reference samples may be combined, for example by interpolation.

The number of possible directions has increased as video coding technology continues to develop. In H.264 (2003), for example, nine different directions are available for intra prediction. This increases to 33 in H.265 (2013), and JEM/VVC/BMS can support up to 65 directions at the time of this disclosure. Experimental studies have been conducted to help identify the most suitable intra prediction directions, and those most suitable directions can be encoded with a small number of bits using certain techniques of entropy coding, accepting a certain bit penalty for the direction. Furthermore, in some cases the direction itself can be predicted from the neighboring directions used in the intra prediction of the decoded neighboring blocks.

Figure 1B shows a schematic diagram (180) showing 65 intra prediction directions according to JEM to illustrate the increasing number of prediction directions in various encoding techniques that have evolved over time.

Methods for mapping bits representing intra-prediction directions to prediction directions in a coded video bitstream can vary across video coding techniques and can range, for example, from simple direct mappings of prediction directions to intra-prediction modes to complex adaptation schemes involving codewords, most-probable modes, and similar techniques. In all cases, however, there may be certain directions of intra-prediction that are statistically less likely to occur in the video content than certain other directions. Because the goal of video compression is redundancy reduction, in a well-designed video coding technique, those less likely directions may be represented with a greater number of bits than the more likely directions.

Interpicture prediction, or inter prediction, may be based on motion compensation, in which sample data from a previously reconstructed picture or part of it (reference picture) may be used to predict a newly reconstructed picture or picture part (e.g., a block) after being spatially shifted in a direction indicated by a motion vector (hereafter MV). In some cases, the reference picture may be the same as the picture currently being reconstructed. The MV may have two dimensions X and Y, or three dimensions, with the third dimension being an indication of the reference picture in use (similar to the temporal dimension).

In some video compression techniques, a current MV applicable to a particular area of sample data may be predicted from other MVs, e.g., from other MVs related to other areas of sample data that are spatially adjacent to the area being reconstructed and that precede the current MV in decoding order. Doing so can significantly reduce the overall amount of data required to code the MV by relying on the removal of redundancy in correlated MVs, thereby increasing compression efficiency. MV prediction can work effectively because, for example, when coding an input video signal derived from a camera (known as natural video), areas larger than the area to which a single MV is applicable have a statistical likelihood to move in a similar direction in the video sequence and therefore, in some cases, can be predicted using similar motion vectors derived from MVs of neighboring areas. As a result, the actual MV of a given area is similar or identical to the MV predicted from the surrounding MVs. Such MVs may further be represented, after entropy coding, with fewer bits than would be used if the MVs were directly coded instead of predicted from neighboring MVs. In some cases, MV prediction may be an example of lossless compression of a signal (i.e., MV) derived from an original signal (i.e., a sample stream). In other cases, the MV prediction itself may be non-lossy, for example due to rounding errors when computing the predictor from several surrounding MVs.

Various MV prediction mechanisms are described in H.265/HEVC (ITU-T Recommendation H.265, "High Efficiency Video Coding", December 2016). Among the many MV prediction mechanisms specified by H.265, the one described below is a technique that we will refer to hereafter as "spatial merging".

Specifically, referring to FIG. 2, a current block (201) contains samples that were detected by the encoder during the motion search process as predictable from a spatially shifted previous block of the same size. Instead of coding its MV directly, the MV may be derived from metadata associated with one or more reference pictures, e.g., the most recent reference picture (in decoding order), using MVs associated with any one of five surrounding samples, denoted A0, A1, and B0, B1, B2 (202-206, respectively). In H.265, MV prediction may use predictors from the same reference picture that neighboring blocks use.

The present disclosure relates generally to video coding, and more particularly to methods and systems for signaling different motion vector or motion vector difference related syntax based on whether magnitude-dependent adaptive resolution for motion vector differences in inter prediction is used.

In an example implementation, a method for processing a current video block of a video stream is disclosed. The method may include receiving a video stream and determining that the current video block is inter-coded based on a predictive block and a motion vector (MV), where the MV is to be derived from a reference motion vector (RMV) and a motion vector difference (MVD) of the current video block. The method further includes, in response to determining that the MVD is coded at an adaptive MVD pixel resolution, determining a reference MVD pixel precision for the current video block, identifying a maximum allowable MVD pixel precision, determining a set of allowable MVD levels for the current video block based on the reference MVD pixel precision and the maximum allowable MVD pixel precision, and deriving the MVD from the video stream according to at least one MVD parameter signaled in the video stream for the current video block and the set of allowable MVD levels.

In the above implementations, the reference MVD pixel precision of the current video block is specified/signaled/derived at the sequence level, picture level, frame level, superblock level, or coding block level.

In any one of the above implementations, the reference MVD pixel precision of the current video block depends on the MVD class associated with the MVD of the current video block.

In any one of the above implementations, the reference MVD pixel precision of the current video block depends on the MVD magnitude of the MVD of the current video block. In any one of the above implementations, a maximum allowable MVD pixel precision is predefined.

In any one of the above implementations, the method may further include determining a current MVD class from among a predefined set of MVD classes. Determining a set of acceptable MVD levels for the MVD based on the reference MVD pixel precision and the maximum allowable MVD pixel precision may include excluding MVD levels associated with an MVD pixel precision equal to or greater than the maximum allowable MVD pixel precision from the reference MVD level set determined based on the reference MVD pixel precision and the current MVD class to determine a set of acceptable MVD levels for the current video block.

In any one of the above implementations, the maximum allowable MVD pixel precision is 1/4 pixel. In any one of the above implementations, MVD levels associated with 1/8 pixel precision or greater are excluded from the set of allowable MVD levels for the current video block.

In any one of the above implementations, the method may further include determining a current MVD class from among a predefined set of MVD classes. An MVD level associated with a fractional MVD accuracy may be included in the set of acceptable MVD levels, regardless of the reference MVD accuracy, if the current MVD class is less than or equal to a threshold MVD class.

In any one of the above implementations, the threshold MVD class may be the lowest MVD class among a predefined set of MVD classes.

In any one of the above implementations, the method may further include determining an MVD magnitude, and an MVD level associated with an MVD accuracy higher than a threshold MVD accuracy is allowed in the set of allowable MVD levels only if the MVD magnitude is less than or equal to the threshold MVD magnitude.

In any one of the above implementations, the threshold MVD magnitude is 2 pixels or less. In any one of the above implementations, the threshold MVD precision is 1 pixel. In any one of the above implementations, MVD levels associated with MVD precision of ¼ pixel or greater are only allowed if the MVD magnitude is ½ pixel or less. In any one of the above implementations, the maximum allowable MVD pixel precision may not be greater than the reference MVD pixel precision.

In another example implementation, a method for processing a current video block of a video stream is disclosed. The method may include receiving a video stream, determining that the current video block is inter-coded and associated with multiple reference frames, and determining, based on signaling in the video stream, whether adaptive motion vector difference (MVD) pixel resolution is applied to at least one of the multiple reference frames.

In the above implementation, the signaling may include a single-bit flag to indicate whether the adaptive MVD pixel resolution is applied to all or none of the multiple reference frames.

In any one of the above implementations, the signaling may include separate flags, each corresponding to one of the multiple reference frames, to indicate whether adaptive MVD pixel resolution is applied.

In any one of the above implementations, the signaling may include, for each of the multiple reference frames, an implicit indication that adaptive MVD pixel resolution is not applied when the MVD corresponding to each of the multiple reference frames is zero, and a single-bit flag to indicate whether adaptive MVD pixel resolution is applied when the MVD corresponding to each of the multiple reference frames is non-zero.

In another example implementation, a method for processing a current video block of a video stream is disclosed. The method may include receiving a video stream; determining that the current video block is inter-coded based on a predictive block and a motion vector (MV), where the MV is to be derived from a reference motion vector (RMV) and a motion vector difference (MVD) for the current video block; determining a current MVD class of the MVD from among a predefined set of MVD classes; deriving at least one context for entropy decoding at least one explicit signaling in the video stream based on the current MVD class, where the at least one explicit signaling is included in the video stream to specify an MVD pixel resolution for at least one component of the MVD; and entropy decoding the at least one explicit signaling from the video stream using the at least one context to determine the MVD pixel resolution for the at least one component of the MVD.

In the above implementation, the at least one component of the MVD may include a horizontal component and a vertical component of the MVD, and the at least one context may include two separate contexts each associated with one of the horizontal and vertical components of the MVD, the horizontal and vertical components being associated with separate MVD pixel resolutions.

Aspects of the present disclosure also provide a video encoding or decoding device or apparatus that includes circuitry configured to perform any of the implementations of the above methods.

Aspects of the present disclosure also provide a non-transitory computer-readable medium storing instructions that, when executed by a computer, cause the computer to perform a method for video decoding and/or encoding.

Further features, nature and various advantages of the disclosed subject matter will become more apparent from the following detailed description and accompanying drawings.

FIG. 13 is a schematic diagram of an example subset of intra-prediction directional modes. FIG. 2 illustrates an exemplary intra-prediction direction. FIG. 2 is a schematic diagram illustrating a current block and its surrounding spatial merge candidates for motion vector prediction in one example. 1 is a schematic diagram of a simplified block diagram of a communication system (300) according to an exemplary embodiment. 4 is a schematic diagram of a simplified block diagram of a communication system (400) according to an exemplary embodiment. 2 is a schematic diagram of a simplified block diagram of a video decoder according to an example embodiment; 1 is a schematic diagram of a simplified block diagram of a video encoder according to an example embodiment; FIG. 11 is a block diagram of a video encoder according to another example embodiment. FIG. 11 is a block diagram of a video decoder according to another example embodiment. FIG. 2 illustrates a coding block partitioning scheme according to an exemplary embodiment of the present disclosure. FIG. 13 illustrates another scheme for coding block partitioning, according to an exemplary embodiment of the present disclosure. FIG. 13 illustrates another scheme for coding block partitioning, according to an exemplary embodiment of the present disclosure. FIG. 2 illustrates an exemplary partitioning of a base block into coding blocks according to an exemplary partitioning scheme. FIG. 1 illustrates an exemplary division-of-thirds scheme. FIG. 2 illustrates an exemplary quadtree/binary tree coding block partitioning scheme. 4A-4C are diagrams illustrating a scheme for splitting a coding block into multiple transform blocks and the coding order of the transform blocks according to an exemplary embodiment of the present disclosure. 4A-4C are diagrams illustrating other schemes for splitting a coding block into multiple transform blocks and the coding order of the transform blocks according to an exemplary embodiment of the present disclosure. FIG. 13 illustrates another scheme for splitting a coding block into multiple transform blocks, according to an exemplary embodiment of the present disclosure. FIG. 2 illustrates a flowchart of a method according to an exemplary embodiment of the present disclosure. FIG. 13 illustrates another flowchart of a method according to an exemplary embodiment of the present disclosure. FIG. 2 illustrates a flowchart of a method according to an exemplary embodiment of the present disclosure. 1 is a schematic diagram of a computer system according to an exemplary embodiment of the present disclosure.

Throughout this specification and the claims, terms may have subtle meanings that are suggested or implied in the context beyond the meaning explicitly stated. The phrases "in one embodiment" or "in some embodiments" used herein do not necessarily refer to the same embodiment, and the phrases "in other embodiments" or "in other embodiments" used herein do not necessarily refer to different embodiments. Similarly, the phrases "in one implementation" or "in some implementations" used herein do not necessarily refer to the same implementation, and the phrases "in other implementations" or "in other implementations" used herein do not necessarily refer to different implementations. For example, the claimed subject matter is intended to include all or part of the exemplary embodiments/implementations.

In general, terminology may be understood at least in part from its usage in context. For example, terms such as "and", "or", or "and/or" as used herein may include various meanings that may depend at least in part on the context in which such terms are used. Typically, "or" when used to relate a list such as A, B, or C is intended to mean A, B, and C, which are used herein in an inclusive sense, as well as A, B, or C, which are used herein in an exclusive sense. In addition, the terms "one or more" or "at least one" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a", "an", or "the" may also be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context. In addition, the terms "based on" or "determined by" may be understood not to be intended to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly described, again depending at least in part on the context. FIG. 3 illustrates a simplified block diagram of a communication system (300) according to one embodiment of the present disclosure. The communication system (300) includes a plurality of terminal devices that can communicate with each other, for example, via a network (350). For example, the communication system (300) includes a first pair of terminal devices (310) and (320) interconnected via the network (350). In the example of FIG. 3, the first pair of terminal devices (310) and (320) may perform unidirectional transmission of data. For example, the terminal device (310) may code video data (e.g., of a stream of video pictures captured by the terminal device (310)) for transmission to the other terminal device (320) via the network (350). The encoded video data may be transmitted in the form of one or more coded video bitstreams. The terminal device (320) may receive coded video data from the network (350), decode the coded video data to recover a video picture, and display the video picture according to the recovered video data. The unidirectional data transmission may be implemented in a media serving application, etc.

In another example, the communication system (300) includes a second pair of terminal devices (330) and (340) performing bidirectional transmission of coded video data, which may occur, for example, during video conferencing applications. For the bidirectional transmission of data, in one example, each of the terminal devices (330) and (340) may code video data (e.g., of a stream of video pictures captured by that terminal device) for transmission to the other of the terminal devices (330) and (340) over the network (350). Each of the terminal devices (330) and (340) may also receive coded video data transmitted by the other of the terminal devices (330) and (340), decode the coded video data to recover the video pictures, and display the video pictures on an accessible display device according to the recovered video data.

In the example of FIG. 3, terminal devices (310), (320), (330), and (340) may be implemented as a server, a personal computer, and a smartphone, although application of the principles underlying the present disclosure need not be so limited. Embodiments of the present disclosure may be implemented in desktop computers, laptop computers, tablet computers, media players, wearable computers, dedicated video conferencing equipment, and the like. Network (350) represents any number or type of network that conveys coded video data between terminal devices (310), (320), (330), and (340), including, for example, wired and/or wireless communication networks. Communications network (350) may exchange data over circuit-switched channels, packet-switched channels, and/or other types of channels. Representative networks include telecommunications networks, local area networks, wide area networks, and/or the Internet. For purposes of this description, the architecture and topology of network (350) may not be important to the operation of the present disclosure unless expressly described herein.

Figure 4 illustrates the arrangement of a video encoder and a video decoder in a video streaming environment as an example of an application for the disclosed subject matter. The disclosed subject matter may be equally applicable to other video applications including, for example, video conferencing, digital television broadcasting, gaming, virtual reality, storage of compressed video on digital media including CDs, DVDs, memory sticks, etc.

A video streaming system may include a video source (401) for creating a stream of uncompressed video pictures or images (402), a video capture subsystem (413) that may include, for example, a digital camera. In one example, the stream of video pictures (402) includes samples recorded by the digital camera of the video source 401. The stream of video pictures (402), shown as a thick line to emphasize the large amount of data when compared to the encoded video data (404) (or coded video bitstream), may be processed by an electronic device (420) that includes a video encoder (403) coupled to the video source (401). The video encoder (403) may include hardware, software, or a combination thereof to enable or implement aspects of the disclosed subject matter, as described in more detail below. The encoded video data (404) (or encoded video bitstream (404)), shown with thin lines to emphasize its low amount of data compared to the stream of uncompressed video pictures (402), may be stored directly to the streaming server (405) or to a downstream video device (not shown) for future use. One or more streaming client subsystems, such as the client subsystems (406) and (408) of FIG. 4, may access the streaming server (405) to retrieve copies (407) and (409) of the encoded video data (404). The client subsystem (406) may include, for example, a video decoder (410) within the electronic device (430). The video decoder (410) decodes the input copy of the encoded video data (407) and creates an output stream of video pictures (411) that is uncompressed and can be rendered on a display (412) (e.g., a display screen) or other rendering device (not shown). The video decoder 410 may be configured to perform some or all of the various functions described in this disclosure. In some streaming systems, the encoded video data (404), (407), and (409) (e.g., a video bitstream) may be encoded according to a particular video coding/compression standard. Examples of such standards include ITU-T Recommendation H.265. In one example, a video coding standard under development is informally known as Versatile Video Coding (VVC). The disclosed subject matter may be used in the context of VVC, as well as other video coding standards.

It should be noted that electronic devices (420) and (430) may include other components (not shown). For example, electronic device (420) may include a video decoder (not shown) and electronic device (430) may also include a video encoder (not shown).

FIG. 5 illustrates a block diagram of a video decoder (510) according to any embodiment of the present disclosure below. The video decoder (510) may be included in an electronic device (530). The electronic device (530) may include a receiver (531) (e.g., receiving circuitry). The video decoder (510) may be used in place of the video decoder (410) of the example of FIG. 4.

The receiver (531) may receive one or more coded video sequences to be decoded by the video decoder (510). In the same or other embodiments, one coded video sequence at a time may be decoded, with the decoding of each coded video sequence being independent of the other coded video sequences. Each video sequence may be associated with multiple video frames or video images. The coded video sequences may be received from a channel (501), which may be a hardware/software link to a storage device that stores the encoded video data, or a streaming source that transmits the encoded video data. The receiver (531) may receive the encoded video data along with other data, such as coded audio data and/or auxiliary data streams, which may be forwarded to respective processing circuits (not shown). The receiver (531) may separate the coded video sequences from the other data. To combat network jitter, a buffer memory (515) may be placed between the receiver (531) and the entropy decoder/parser (520) (hereafter “parser (520)”). In certain applications, the buffer memory (515) may be implemented as part of the video decoder (510). In other applications, the buffer memory (515) may be separate and external to the video decoder (510) (not shown). In still other applications, there may be a buffer memory (not shown) external to the video decoder (510), for example, to combat network jitter, and there may be other additional buffer memories (515) internal to the video decoder (510), for example, to handle playback timing. When the receiver (531) is receiving data from a storage/forwarding device with sufficient bandwidth and controllability, or from an isosynchronous network, the buffer memory (515) may be unnecessary or may be small. For use with best-effort packet networks such as the Internet, a buffer memory (515) of sufficient size may be required, which may be relatively large in size. Such a buffer memory may be implemented with an adaptive size and may be implemented at least in part in an operating system or similar element (not shown) external to the video decoder (510).

The video decoder (510) may include a parser (520) to reconstruct symbols (521) from the coded video sequence. These categories of symbols include information used to manage the operation of the video decoder (510) and potentially information for controlling a rendering device such as a display (512) (e.g., a display screen) that may or may not be an integral part of the electronic device (530) but may be coupled to the electronic device (530) as shown in FIG. 5. The control information for the rendering device may be in the form of a supplemental enhancement information (SEI message) or a video usability information (VUI) parameter set fragment (not shown). The parser (520) may parse/entropy decode the coded video sequence received by the parser (520). The entropy coding of the coded video sequence may be according to a video coding technique or standard and may follow various principles including variable length coding, Huffman coding, arithmetic coding with or without context dependency, etc. The parser (520) may extract from the coded video sequence a set of subgroup parameters for at least one of the subgroups of pixels in the video decoder based on at least one parameter corresponding to the subgroup. The subgroups may include groups of pictures (GOPs), pictures, tiles, slices, macroblocks, coding units (CUs), blocks, transform units (TUs), prediction units (PUs), etc. The parser (520) may also extract information from the coded video sequence, such as transform coefficients (e.g., Fourier transform coefficients), quantization parameter values, motion vectors, etc.

The parser (520) may perform entropy decoding/parsing operations on the video sequence received from the buffer memory (515) to create symbols (521).

The reconstruction of the symbols (521) may involve a number of different processing or functional units, depending on the type of video picture or portion thereof being coded (interpicture and intrapicture, interblock and intrablock, etc.), as well as other factors. The units that are included and how the units are included may be controlled by subgroup control information parsed from the coded video sequence by the parser (520). The flow of such subgroup control information between the parser (520) and the following processing or functional units is not shown for the sake of simplicity.

Beyond the functional blocks already mentioned, the video decoder (510) may be conceptually subdivided into several functional units, as described below. In an actual implementation operating under commercial constraints, many of these functional units may closely interact with each other and may be, at least in part, integrated with each other. However, for purposes of clearly describing the various functions of the disclosed subject matter, a conceptual subdivision into functional units is adopted in the following disclosure.

The first unit may include a scalar/inverse transform unit (551), which may receive quantized transform coefficients as well as control information from the parser (520) including information indicating which type of inverse transform to use, block size, quantization coefficients/parameters, quantization scaling matrix, etc., as symbols (521). The scalar/inverse transform unit (551) may output a block containing sample values that may be input to an aggregator (555).

In some cases, the output samples of the scalar/inverse transform (551) may relate to intra-coded blocks, i.e., blocks that do not use prediction information from a previously reconstructed picture, but may use prediction information from a previously reconstructed portion of the current picture. Such prediction information may be provided by an intra-picture prediction unit (552). In some cases, the intra-picture prediction unit (552) may generate a block of the same size and shape as the block being reconstructed using information of surrounding blocks that have already been reconstructed and stored in the current picture buffer (558). The current picture buffer (558) may, for example, buffer the partially reconstructed and/or fully reconstructed current picture. The aggregator (555) may, in some implementations, add the prediction information generated by the intra-prediction unit (552) to the output sample information provided by the scalar/inverse transform unit (551) on a sample-by-sample basis.

In other cases, the output samples of the scalar/inverse transform unit (551) may relate to an inter-coded, potentially motion-compensated block. In such cases, the motion compensated prediction unit (553) may access the reference picture memory (557) to fetch samples used for inter-picture prediction. After motion compensating the fetched samples according to the symbols (521) related to the block, these samples may be added to the output of the scalar/inverse transform unit (551) by the aggregator (555) to generate output sample information (the output of unit 551 may be referred to as residual samples or residual signals). The addresses in the reference picture memory (557) from which the motion compensated prediction unit (553) fetches the prediction samples may be controlled by a motion vector, available to the motion compensated prediction unit (553) in the form of a symbol (521), which may have, for example, an X component, a Y component (shift), and a reference picture component (time). Motion compensation may also include interpolation of sample values fetched from the reference picture memory (557) when sub-sample accurate motion vectors are used, and may also be associated with motion vector prediction mechanisms, etc.

The output samples of the aggregator (555) may be subjected to various loop filtering techniques in the loop filter unit (556). Video compression techniques may include in-loop filter techniques controlled by parameters contained in the coded video sequence (also called the coded video bitstream) and made available to the loop filter unit (556) as symbols (521) from the parser (520), but may also be responsive to previously reconstructed and loop filtered sample values as well as meta-information obtained during decoding of a previous portion (in decoding order) of the coded picture or coded video sequence. As described in more detail below, several types of loop filters may be included as part of the loop filter unit 556 in various orders.

The output of the loop filter unit (556) may be a sample stream that can be output to a rendering device (512) but also stored in a reference picture memory (557) for use in future inter-picture prediction.

Once a particular coded picture has been fully reconstructed, it may be used as a reference picture for future inter-picture prediction. For example, once a coded picture corresponding to a current picture has been fully reconstructed and the coded picture has been identified (e.g., by the parser (520)) as a reference picture, the current picture buffer (558) may become part of the reference picture memory (557), and any unused current picture buffer may be reallocated prior to beginning reconstruction of the next coded picture.

The video decoder (510) may perform decoding operations according to a given video compression technique adopted in a standard, such as ITU-T Recommendation H.265. The coded video sequence may conform to the syntax specified by the video compression technique or standard used in the sense that the coded video sequence adheres to both the syntax of the video compression technique or standard and to the profile documented in the video compression technique or standard. Specifically, the profile may select certain tools from all tools available in the video compression technique or standard as the only tools that may be used under that profile. To conform to a standard, the complexity of the coded video sequence may be within a range defined by a level of the video compression technique or standard. In some cases, the level limits the maximum picture size, maximum frame rate, maximum reconstruction sample rate (e.g., measured in megasamples per second), maximum reference picture size, etc. The limits set by the level may be further limited in some cases by the specification of a hypothetical reference decoder (HRD) and metadata for HRD buffer management signaled in the coded video sequence.

In some example embodiments, the receiver (531) may receive additional (redundant) data along with the encoded video. The additional data may be included as part of the coded video sequence. The additional data may be used by the video decoder (510) to properly decode the data and/or to more accurately reconstruct the original video data. The additional data may be in the form of, for example, temporal, spatial, or signal-to-noise ratio (SNR) enhancement layers, redundant slices, redundant pictures, forward error correction codes, etc.

FIG. 6 illustrates a block diagram of a video encoder (603) according to an exemplary embodiment of the present disclosure. The video encoder (603) may be included in an electronic device (620). The electronic device (620) may further include a transmitter (640) (e.g., a transmitting circuit). The video encoder (603) may be used in place of the video encoder (403) of the example of FIG. 4.

The video encoder (603) may receive video samples from a video source (601) (which in the example of FIG. 6 is not part of the electronic device (620)) that may capture video images to be coded by the video encoder (603). In other examples, the video source (601) may be implemented as part of the electronic device (620).

The video source (601) may provide a source video sequence to be coded by the video encoder (603) in the form of a digital video sample stream that may be of any suitable bit depth (e.g., 8-bit, 10-bit, 12-bit, ...), any color space (e.g., BT.601 YCrCb, RGB, XYZ ...), and any suitable sampling structure (e.g., YCrCb 4:2:0, YCrCb 4:4:4). In a media serving system, the video source (601) may be a storage device capable of storing previously prepared video. In a video conferencing system, the video source (601) may be a camera that captures local image information as a video sequence. The video data may be provided as a number of individual pictures or images that give motion when viewed in sequence. The picture itself may be organized as a spatial array of pixels, each pixel may contain one or more samples depending on the sampling structure, color space, etc. being used. Those skilled in the art can easily understand the relationship between pixels and samples. The following description focuses on samples.

According to some example embodiments, the video encoder (603) may code and compress pictures of a source video sequence into a coded video sequence (643) in real time or under any other time constraint required by the application. Enforcing an appropriate coding rate constitutes one function of the controller (650). In some embodiments, the controller (650) may be operatively coupled to and control other functional units as described below. For the sake of brevity, couplings are not shown. Parameters set by the controller (650) may include rate control related parameters (picture skip, quantizer, lambda value for rate distortion optimization techniques, etc.), picture size, group of pictures (GOP) layout, maximum motion vector search range, etc. The controller (650) may be configured to have other appropriate functions associated with the video encoder (603) optimized for a particular system design.

In some example embodiments, the video encoder (603) may be configured to operate in a coding loop. As an oversimplified explanation, in one example, the coding loop may include a source coder (630) (e.g., involved in generating symbols, such as a symbol stream, based on an input picture to be coded and a reference picture) and a (local) decoder (633) embedded in the video encoder (603). The decoder (633) reconstructs the symbols to create sample data in a similar manner as a (remote) decoder would create them (since in the video compression techniques contemplated in the disclosed subject matter, any compression between the symbols and the coded video bitstream may be lossless). The reconstructed sample stream (sample data) is input to a reference picture memory (634). Since decoding of the symbol stream yields bit-exact results regardless of the location of the decoder (local or remote), the contents of the reference picture memory (634) are also bit-exact between the local and remote encoders. In other words, the predictive part of the encoder "sees" exactly the same sample values as the reference picture samples that the decoder "sees" when using prediction during decoding. This fundamental principle of reference picture synchrony (and the resulting drift when synchrony cannot be maintained due to, for example, channel errors) is used to improve coding quality.

The operation of the "local" decoder (633) may be the same as that of a "remote" decoder, such as the video decoder (510), already described in detail above in conjunction with FIG. 5. With brief reference also to FIG. 5, however, because symbols are available and the encoding/decoding of symbols into a coded video sequence by the entropy coder (645) and parser (520) may be lossless, the entropy decoding portion of the video decoder (510), including the buffer memory (515) and parser (520), may not be fully implemented in the local decoder (633) within the encoder.

At this point, it can be said that any decoder technology, except for parsing/entropy decoding, which may only be present in the decoder, may necessarily also need to be present in a corresponding encoder in substantially the same functional form. For this reason, the disclosed subject matter may focus on the decoder operation, which is similar to the decoding portion of the encoder. Thus, a description of the encoder technology may be omitted, since it is the inverse of the decoder technology described generically. Only in certain areas or aspects is a more detailed description of the encoder provided below.

In operation, in some example implementations, the source coder (630) may perform motion-compensated predictive coding, which predictively codes an input picture with reference to one or more previously coded pictures from the video sequence designated as "reference pictures." In this manner, the coding engine (632) codes color channel differences (or residuals) between pixel blocks of the input picture and pixel blocks of reference pictures that may be selected as predictive references to the input picture. The terms "residual" and its adjective form "residual" may be used interchangeably.

The local video decoder (633) may decode the coded video data of pictures that may be designated as reference pictures based on the symbols created by the source coder (630). The operation of the coding engine (632) may advantageously be a lossy process. When the coded video data may be decoded in a video decoder (not shown in FIG. 6), the reconstructed video sequence may typically be a replica of the source video sequence with some errors. The local video decoder (633) may replicate the decoding process that may be performed by the video decoder on the reference pictures, such that the reconstructed reference pictures are stored in the reference picture cache (634). In this way, the video encoder (603) may locally store copies of reconstructed reference pictures that have common content with the reconstructed reference pictures obtained by the far-end (remote) video decoder (without transmission errors).

The predictor (635) may perform a prediction search for the coding engine (632). That is, for a new picture to be coded, the predictor (635) may search the reference picture memory (634) for sample data (as candidate reference pixel blocks) or specific metadata such as reference picture motion vectors, block shapes, etc., that may serve as suitable prediction references for the new pixels. The predictor (635) may operate on sample blocks, pixel block by pixel block, to find a suitable prediction reference. In some cases, as determined by the search results obtained by the predictor (635), the input picture may have prediction references drawn from multiple reference pictures stored in the reference picture memory (634).

The controller (650) may manage the coding operations of the source coder (630), including, for example, setting parameters and subgroup parameters used to encode the video data.

The output of all the aforementioned functional units can be subjected to entropy coding in an entropy coder (645), which converts the symbols produced by the various functional units into a coded video sequence by lossless compression of the symbols according to techniques such as Huffman coding, variable length coding, arithmetic coding, etc.

The transmitter (640) may buffer the coded video sequence created by the entropy coder (645) and prepare it for transmission over a communication channel (660), which may be a hardware/software link to a storage device that stores the encoded video data. The transmitter (640) may merge the coded video data from the video coder (603) with other data to be transmitted, such as coded audio data and/or auxiliary data streams (sources not shown).

The controller (650) may manage the operation of the video encoder (603). During coding, the controller (650) may assign a particular coded picture type to each coded picture, which may affect the coding technique that may be applied to the respective picture. For example, pictures are often assigned as one of the following picture types:

An intra picture (I-picture) may be one that can be coded and decoded without using other pictures in a sequence as a source of prediction. Some video codecs allow different types of intra pictures, including, for example, Independent Decoder Refresh ("IDR") pictures. Those skilled in the art are aware of these variations of I-pictures, as well as their respective uses and characteristics.

A predicted picture (P picture) may be a picture that can be coded and decoded using intra- or inter-prediction, which uses at most one motion vector and reference index to predict the sample values of each block.

A bidirectionally predicted picture (B-picture) may be a picture that can be coded and decoded using intra- or inter-prediction, which uses up to two motion vectors and reference indices to predict the sample values of each block. Similarly, a multi-predicted picture may use more than two reference pictures and associated metadata for the reconstruction of a single block.

A source picture may generally be spatially subdivided into multiple sample coding blocks (e.g., blocks of 4x4, 8x8, 4x8, or 16x16 samples each) and coded block by block. Blocks may be predictively coded with reference to other (already coded) blocks, as determined by the coding assignment applied to the respective picture of the block. For example, blocks of an I picture may be non-predictively coded or predictively coded with reference to already coded blocks of the same picture (spatial prediction or intra prediction). Pixel blocks of a P picture may be predictively coded via spatial prediction with reference to one previously coded reference picture or via temporal prediction. Blocks of a B picture may be predictively coded via spatial prediction with reference to one or two previously coded reference pictures or via temporal prediction. Source pictures or intermediate processed pictures may be subdivided into other types of blocks for other purposes. The division of coding blocks and other types of blocks may or may not follow the same method, as described in more detail below.

The video encoder (603) may perform coding operations in accordance with a given video coding technique or standard, such as ITU-T Recommendation H.265. In its operations, the video encoder (603) may perform various compression operations, including predictive coding operations that exploit temporal and spatial redundancies in the input video sequence. Thus, the coded video data may conform to a syntax specified by the video coding technique or standard being used.

In some example embodiments, the transmitter (640) may transmit additional data along with the encoded video. The source coder (630) may include such data as part of the coded video sequence. The additional data may include temporal/spatial/SNR enhancement layers, other forms of redundant data such as redundant pictures and slices, SEI messages, VUI parameter set fragments, etc.

Video may be captured as multiple source pictures (video pictures) in a time sequence. Intra-picture prediction (often abbreviated as intra prediction) exploits spatial correlation in a given picture, while inter-picture prediction exploits temporal or other correlation between pictures. For example, a particular picture being encoded/decoded, called the current picture, may be divided into blocks. If a block in the current picture is similar to a reference block in a previously coded, yet buffered, reference picture in the video, it may be coded by a vector, called a motion vector. A motion vector points to a reference block in the reference picture, and may have a third dimension that identifies the reference picture if multiple reference pictures are used.

In some example embodiments, bi-prediction techniques may be used for inter-picture prediction. According to such bi-prediction techniques, two reference pictures are used, such as a first reference picture and a second reference picture, both of which advance the current picture in the video in decoding order (but may be in the past or future, respectively, in display order). A block in the current picture may be coded by a first motion vector that points to a first reference block in the first reference picture and a second motion vector that points to a second reference block in the second reference picture. A block may be jointly predicted by a combination of the first and second reference blocks.

Furthermore, merge mode techniques may be used to improve coding efficiency in inter-picture prediction.

According to some exemplary embodiments of the present disclosure, predictions such as inter-picture prediction and intra-picture prediction are performed on a block-by-block basis. For example, a picture in a sequence of video pictures is divided into coding tree units (CTUs) for compression, and the CTUs in a picture may have the same size, such as 64×64 pixels, 32×32 pixels, or 16×16 pixels. In general, a CTU may include three parallel coding tree blocks (CTBs), i.e., one luma CTB and two chroma CTBs. Each CTU may be recursively quadtree partitioned into one or more coding units (CUs). For example, a CTU of 64×64 pixels may be partitioned into one CU of 64×64 pixels, or four CUs of 32×32 pixels. Each of one or more of the 32×32 blocks may be further partitioned into four CUs of 16×16 pixels. In some exemplary embodiments, each CU may be analyzed during encoding to determine a prediction type for that CU from among various prediction types, such as an inter prediction type and an intra prediction type. A CU may be divided into one or more prediction units (PUs) according to temporal and/or spatial predictability. In general, each PU includes one luma prediction block (PB) and two chroma PBs. In one embodiment, prediction operations in coding (encoding/decoding) are performed in units of prediction blocks. The division of a CU into PUs (or PBs of different color channels) may be performed in various spatial patterns. A luma PB or a chroma PB may include a matrix of sample values (e.g., luma values), for example, 8×8 pixels, 16×16 pixels, 8×16 pixels, 16×8 pixels, etc.

FIG. 7 shows a diagram of a video encoder (703) according to another example embodiment of this disclosure. The video encoder (703) is configured to receive a processed block (e.g., a predictive block) of sample values in a current video picture in a sequence of video pictures and to encode the processed block into a coded picture that is part of a coded video sequence. The example video encoder (703) may be used in place of the example video encoder (403) of FIG. 4.

For example, the video encoder (703) receives a matrix of sample values for a processing block, such as a predictive block of 8×8 samples. The video encoder (703) then determines, for example using rate-distortion optimization (RDO), whether the processing block is best coded using intra-mode, inter-mode, or bi-predictive mode. If it is determined that the processing block is coded in intra-mode, the video encoder (703) may encode the processing block into a coded picture using intra-prediction techniques, and if it is determined that the processing block is coded in inter-mode or bi-predictive mode, the video encoder (703) may encode the processing block into a coded picture using inter-prediction techniques or bi-prediction techniques, respectively. In some exemplary embodiments, a merge mode may be used as a sub-mode of inter-picture prediction, in which motion vectors are derived from one or more motion vector predictors without the benefit of coded motion vector components outside the predictors. In some other exemplary embodiments, there may be motion vector components applicable to the current block. Thus, the video encoder (703) may include components not explicitly shown in FIG. 7, such as a mode decision module, to determine the prediction mode of a processing block.

In the example of FIG. 7, the video encoder (703) includes an inter-encoder (730), an intra-encoder (722), a residual calculator (723), a switch (726), a residual encoder (724), a general controller (721), and an entropy encoder (725) coupled together as shown in the exemplary arrangement of FIG. 7.

The inter-encoder (730) is configured to receive samples of a current block (e.g., a processing block), compare the block to one or more reference blocks in a reference picture (e.g., blocks in previous and subsequent pictures in display order), generate inter-prediction information (e.g., a description of redundancy information, motion vectors, merge mode information from an inter-encoding technique), and calculate an inter-prediction result (e.g., a predicted block) based on the inter-prediction information using any suitable technique. In some examples, the reference picture is a decoded reference picture that has been decoded based on the encoded video information using a decoding unit 633 incorporated in the example encoder 620 of FIG. 6 (shown as a residual decoder 728 of FIG. 7, as described in more detail below).

The intra encoder (722) is configured to receive samples of a current block (e.g., a processing block), compare the block to previously coded blocks in the same picture, generate transformed quantized coefficients, and possibly also generate intra prediction information (e.g., intra prediction direction information according to one or more intra encoding techniques). The intra encoder (722) may calculate an intra prediction result (e.g., a prediction block) based on the intra prediction information and a reference block in the same picture.

The generic controller (721) may be configured to determine generic control data and control other components of the video encoder (703) based on the generic control data. In one example, the generic controller (721) determines a prediction mode for the block and provides a control signal to the switch (726) based on the prediction mode. For example, if the prediction mode is an intra mode, the generic controller (721) controls the switch (726) to select an intra mode result for use by the residual calculator (723) and controls the entropy encoder (725) to select intra prediction information and include the intra prediction information in the bitstream, and if the prediction mode for the block is an inter mode, the generic controller (721) controls the switch (726) to select an inter prediction result for use by the residual calculator (723) and controls the entropy encoder (725) to select inter prediction information and include the inter prediction information in the bitstream.

The residual calculator (723) may be configured to calculate a difference (residual data) between a received block and a prediction result for a block selected from the intra-encoder (722) or the inter-encoder (730). The residual encoder (724) may be configured to encode the residual data to generate transform coefficients. For example, the residual encoder (724) may be configured to transform the residual data from the spatial domain to the frequency domain to generate transform coefficients. The transform coefficients then undergo a quantization process to obtain quantized transform coefficients. In various exemplary embodiments, the video encoder (703) also includes a residual decoder (728). The residual decoder (728) is configured to perform an inverse transform and generate decoded residual data. The decoded residual data may be used by the intra-encoder (722) and the inter-encoder (730) as appropriate. For example, the inter-encoder (730) can generate decoded blocks based on the decoded residual data and the inter-prediction information, and the intra-encoder (722) can generate decoded blocks based on the decoded residual data and the intra-prediction information. The decoded blocks are appropriately processed to generate decoded pictures, which can be buffered in a memory circuit (not shown) and used as reference pictures.

The entropy encoder (725) may be configured to format a bitstream to include the encoded block and perform entropy coding. The entropy encoder (725) may be configured to include various information in the bitstream. For example, the entropy encoder (725) may be configured to include general control data, selected prediction information (e.g., intra-prediction information or inter-prediction information), residual information, and other suitable information in the bitstream. When coding a block in a merged sub-mode of either an inter mode or a bi-prediction mode, the residual information may not be present.

FIG. 8 shows a diagram of an example video decoder (810) according to another embodiment of the disclosure. The video decoder (810) is configured to receive coded pictures that are part of a coded video sequence and to decode the coded pictures to generate reconstructed pictures. In one example, the video decoder (810) may be used in place of the example video decoder (410) of FIG. 4.

In the example of FIG. 8, the video decoder (810) includes an entropy decoder (871), an inter-decoder (880), a residual decoder (873), a reconstruction module (874), and an intra-decoder (872) coupled together as shown in the example arrangement of FIG. 8.

The entropy decoder (871) may be configured to reconstruct from the coded picture certain symbols that represent syntax elements of which the coded picture is composed. Such symbols may include, for example, prediction information (e.g., intra- or inter-prediction information) that may identify the mode in which the block is coded (e.g., intra-, inter-, bi-prediction, merged or other sub-modes), certain samples or metadata used for prediction by the intra- or inter-decoder (872) or (880), residual information, for example in the form of quantized transform coefficients, etc. In one example, if the prediction mode is an inter- or bi-prediction mode, the inter-prediction information is provided to the inter-decoder (880), and if the prediction type is an intra-prediction type, the intra-prediction information is provided to the intra-decoder (872). The residual information may undergo inverse quantization and is provided to the residual decoder (873).

The inter decoder (880) may be configured to receive inter prediction information and generate inter prediction results based on the inter prediction information.

The intra decoder (872) may be configured to receive intra prediction information and generate a prediction result based on the intra prediction information.

The residual decoder (873) may be configured to perform inverse quantization to extract inverse quantized transform coefficients and process the inverse quantized transform coefficients to transform the residual from the frequency domain to the spatial domain. The residual decoder (873) may also utilize certain control information (to include quantizer parameters (QP)), which may be provided by the entropy decoder (871) (datapath not shown as this may be only a small amount of control information).

The reconstruction module (874) may be configured to combine, in the spatial domain, the residual as output by the residual decoder (873) and the prediction result (possibly as output by an inter prediction module or an intra prediction module) to form a reconstructed block that forms part of a reconstructed picture as part of the reconstructed video. It should be noted that other suitable operations, such as deblocking operations, may be performed to improve visual quality.

It should be noted that the video encoders (403), (603), and (703) and the video decoders (410), (510), and (810) may be implemented using any suitable technique. In some exemplary embodiments, the video encoders (403), (603), and (703) and the video decoders (410), (510), and (810) may be implemented using one or more integrated circuits. In other embodiments, the video encoders (403), (603), and (603) and the video decoders (410), (510), and (810) may be implemented using one or more processors executing software instructions.

Turning to block partitioning for coding and decoding, a general partitioning may start from a base block, may follow a predefined set of rules, a specific pattern, a partitioning tree, or any partitioning structure or scheme. The partitioning may be hierarchical and recursive. After isolating or dividing the base block according to any of the exemplary partitioning procedures described below or other procedures, or combinations thereof, a final set of partitions or coding blocks may be obtained. Each of these partitions may be at one of various partitioning levels in the partitioning hierarchy and may be partitions of various shapes. Each of the partitions may be referred to as a coding block (CB). In various exemplary partitioning implementations described further below, each resulting CB may be a CB of any of the allowed sizes and partitioning levels. Such partitions are referred to as coding blocks because they may form a unit for which some basic coding/decoding decisions may be made and coding/decoding parameters may be optimized, determined, and signaled in the encoded video bitstream. The highest or deepest level in the final partition represents the depth of the coding block partitioning tree structure. The coding block may be a luma coding block or a chroma coding block. The CB tree structure for each color is sometimes called the coding block tree (CBT).

The coding blocks of all color channels may be collectively referred to as a coding unit (CU). The hierarchical structure of all color channels may be collectively referred to as a coding tree unit (CTU). The partitioning pattern or structure of the various color channels within a CTU may or may not be the same.

In some implementations, the split tree scheme or structure used for the luma channel and the chroma channel may not need to be the same. In other words, the luma channel and the chroma channel may have separate coding tree structures or patterns. Furthermore, whether the luma channel and the chroma channel use the same coding split tree structure or different coding split tree structures, and the actual coding split tree structure to be used, may depend on whether the slice being coded is a P slice, a B slice, or an I slice. For example, for an I slice, the chroma channel and the luma channel may have separate coding split tree structures or coding split tree structure modes, while for a P slice or a B slice, the luma channel and the chroma channel may share the same coding split tree scheme. When separate coding split tree structures or modes are applied, the luma channel may be split into CBs by one coding split tree structure, and the chroma channel may be split into chroma CBs by the other coding split tree structure.

In some exemplary implementations, a predefined partitioning pattern may be applied to the base block. As shown in FIG. 9, an exemplary four-way partitioning tree may start at a first predefined level (e.g., 64×64 block level or other size as the base block size), and the base block may be partitioned hierarchically down to a predefined lowest level (e.g., 4×4 level). For example, the base block may follow four predefined partitioning options or patterns illustrated by 902, 904, 906, and 908, and the partition designated as R is capable of recursive partitioning in that the same partitioning option illustrated in FIG. 9 may be repeated at a lower scale down to the lowest level (e.g., 4×4 level). In some implementations, additional restrictions may be placed on the partitioning scheme of FIG. 9. In the implementation of FIG. 9, rectangular partitions (e.g., 1:2/2:1 rectangular partitions) may be allowed but not recursive, while square partitions are allowed to be recursive. Subsequent partitioning of FIG. 9 by recursion, if necessary, produces a final set of coding blocks. A coding tree depth may be further defined to indicate the division depth from the root node or root block. For example, the coding tree depth for a root node or root block of 64x64 blocks may be set to 0, and after the root block is further divided one time according to FIG. 9, the coding tree depth increases by 1. The maximum or deepest level from the 64x64 base block to the 4x4 smallest partition is 4 (starting from level 0) in the above scheme. Such a division scheme may be applied to one or more of the color channels. Each color channel may be divided independently according to the scheme of FIG. 9 (e.g., for each of the color channels at each hierarchical level, a division pattern or option in the predefined pattern may be determined independently). Alternatively, two or more color channels may share the same hierarchical pattern tree of FIG. 9 (e.g., for two or more color channels at each hierarchical level, the same division pattern or option in the predefined pattern may be selected).

FIG. 10 illustrates another exemplary predefined partitioning pattern that allows the recursive partitioning to form a partitioning tree. As shown in FIG. 10, an exemplary ten-way partitioning structure or pattern may be predefined. The root block may start from a predefined level (e.g., from a base block at a 128×128 level or a 64×64 level). The exemplary partitioning structure of FIG. 10 includes various 2:1/1:2 and 4:1/1:4 rectangular partitions. A partition type having three subpartitions, shown as 1002, 1004, 1006, and 1008 in the second column of FIG. 10, may be referred to as a “T-type” partition. The “T-type” partitions 1002, 1004, 1006, and 1008 may be referred to as a left T-type, an upper T-type, a right T-type, and a lower T-type. In some exemplary implementations, none of the rectangular partitions of FIG. 10 may be further subdivided. A coding tree depth may be further defined to indicate the partitioning depth from the root node or root block. For example, the coding tree depth for a root node or root block of a 128×128 block may be set to 0, and after the root block is further divided one time according to FIG. 10, the coding tree depth increases by 1. In some implementations, only the all-square partitions of 1010 may allow recursive division to the next level of the division tree following the pattern of FIG. 10. In other words, recursive division may not be possible for the square partitions in the T-shaped patterns 1002, 1004, 1006, and 1008. If necessary, the division procedure following FIG. 10 by recursion generates a final set of coding blocks. Such a scheme may be applied to one or more of the color channels. In some implementations, more flexibility may be added to the use of partitions less than 8×8 levels. For example, in some cases, 2×2 chroma inter prediction may be used.

In some other example implementations of coding block partitioning, a quadtree structure may be used to partition a base block or intermediate block into quadtree partitions. Such quadtree partitioning may be applied hierarchically and recursively to any square partitions. Whether a base block or intermediate block or partition is further quadtree partitioned may be adapted to various local characteristics of the base block or intermediate block/partition. The quadtree partitioning at the picture boundary may be further adapted. For example, an implicit quadtree partitioning may be done at the picture boundary such that a block continues to be quadtree partitioned until its size fits into the picture boundary.

In some other example implementations, a hierarchical bisection from the base block may be used. For such a scheme, the base block or mid-level block may be divided into two partitions. The bisection may be either horizontal or vertical. For example, a horizontal bisection may divide the base block or mid-block into equal left and right partitions. Similarly, a vertical bisection may divide the base block or mid-block into equal top and bottom partitions. Such bisection may be hierarchical and recursive. It may be determined at each of the base block or mid-block whether the bisection scheme should continue, and if the scheme continues further, whether a horizontal or vertical bisection should be used. In some implementations, further division may stop at a predefined minimum partition size (in one or both dimensions). Alternatively, further division may stop once a predefined division level or depth from the base block is reached. In some implementations, the aspect ratio of the partitions may be limited. For example, the aspect ratio of the partitions may not be smaller than 1:4 (or larger than 4:1). Therefore, a vertical strip partition with a 4:1 vertical to horizontal aspect ratio can only be further divided vertically into an upper and lower partition, each with a 2:1 vertical to horizontal aspect ratio.

In yet some other examples, a three-way splitting scheme may be used to split the base block or any intermediate blocks, as shown in FIG. 13. The ternary pattern may be implemented vertically, as shown at 1302 in FIG. 13, or horizontally, as shown at 1304 in FIG. 13. The example split ratio in FIG. 13 is shown as 1:2:1 either vertically or horizontally, but other ratios may be predefined. In some implementations, two or more different ratios may be predefined. Such a three-way splitting scheme may be used to complement a quadtree or bipartition structure, in that such a ternary tree splitting can capture objects located at block centers in one contiguous partition, while quadtrees and bipartitions always split along block centers, thus splitting objects into separate partitions. In some implementations, the width and height of the partitions of the example ternary tree are always powers of two to avoid further transformations.

The above partitioning schemes may be combined in any manner at different partitioning levels. As an example, the quadtree and bipartitioning schemes described above may be combined to partition the base block into a quadtree-binary tree (QTBT) structure. In such a scheme, the base block or intermediate blocks/partitions may be either quadtree-partitioned or bipartitioned, if specified, subject to a set of predefined conditions. A specific example is shown in FIG. 14. In the example of FIG. 14, the base block is first quadtree-partitioned into four partitions, as shown by 1402, 1404, 1406, and 1408. Each of the resulting partitions is then either quadtree-partitioned into four further partitions (such as 1408) or bipartitioned into two further partitions at the next level (e.g., either horizontally or vertically, such as 1402 or 1406, both of which are symmetric), or not partitioned (such as 1404). Bisection or quadtree partitioning may be recursively enabled for square partitions, as shown by the overall example partitioning pattern in 1410 and the corresponding tree structure/representation in 1420, where solid lines represent quadtree partitioning and dashed lines represent bisection. A flag may be used for each bisection node (non-leaf binary partition) to indicate whether the bisection is horizontal or vertical. For example, flag "0" may represent horizontal bisection and flag "1" may represent vertical bisection, as shown in 1420, which matches the partitioning structure in 1410. In the case of quadtree partitioning, there is no need to indicate the type of partitioning, since quadtree partitioning always splits a block or partition both horizontally and vertically to generate four sub-blocks/partitions of equal size. In some implementations, flag "1" may represent horizontal bisection and flag "0" may represent vertical bisection.

In some example implementations of QTBT, the quadtree and binary splitting rule sets may be represented by the following predefined parameters and their associated corresponding functions:
- CTU size: Root node size of the quadtree (size of the base block)
-MinQTSize: Minimum allowable quad tree leaf node size -MaxBTSize: Maximum allowable binary tree root node size -MaxBTDepth: Maximum allowable binary tree depth -MinBTSize: Minimum allowable binary tree leaf node size
In some exemplary implementations of the QTBT partitioning structure, the CTU size may be set as 128x128 luma samples with two corresponding 64x64 blocks of chroma samples (if exemplary chroma subsampling is considered and used), MinQTSize may be set as 16x16, MaxBTSize may be set as 64x64, MinBTSize (for both width and height) may be set as 4x4, and MaxBTDepth may be set as 4. A quadtree partition may be applied to the CTU first to generate quadtree leaf nodes. The quadtree leaf nodes may have a size from its minimum allowed size of 16x16 (i.e., MinQTSize) to 128x128 (i.e., CTU size). If a node is 128x128, it will not be split first by the binary tree because the size exceeds MaxBTSize (i.e., 64x64). Otherwise, nodes that do not exceed MaxBTSize may be split by binary tree. In the example of FIG. 14, the base block is 128×128. The base block is only capable of quadtree splitting according to a predefined set of rules. The base block has a split depth of 0. Each of the resulting four partitions is 64×64, not exceeding MaxBTSize, and may be further quadtree or binary tree split at level 1. The process continues. When the binary tree depth reaches MaxBTDepth (i.e., 4), no further splits may be considered. When the width of a binary tree node is equal to MinBTSize (i.e., 4), no further horizontal splits may be considered. Similarly, when the height of a binary tree node is equal to MinBTSize, no further vertical splits may be considered.

In some example implementations, the above QTBT scheme may be configured to support flexibility for luma and chroma to have the same QTBT structure or separate QTBT structures. For example, for P and B slices, the luma CTB and chroma CTB in one CTU may share the same QTBT structure. However, for I slices, the luma CTB may be divided into CBs by a QTBT structure, and the chroma CTB may be divided into chroma CBs by another QTBT structure. This means that CUs may be used to refer to different color channels in an I slice, e.g., an I slice may consist of a coding block of a luma component or a coding block of two chroma components, and a CU in a P or B slice may consist of coding blocks of all three color components.

In some other implementations, the QTBT scheme may be complemented with the ternary scheme described above. Such implementations may be referred to as multi-type tree (MTT) structures. For example, in addition to the bisection of the nodes, one of the trisection patterns of FIG. 13 may be selected. In some implementations, only square nodes may undergo trisection. An additional flag may be used to indicate whether the trisection is horizontal or vertical.

The design of two-level or multi-level trees, such as the QTBT implementation and the QTBT implementation complemented by trisection, may be motivated primarily by reducing complexity. In theory, the complexity of traversing a tree is T ^D , where T represents the number of partition types and D is the depth of the tree. A trade-off may be made by using multiple types (T) while reducing the depth (D).

In some implementations, the CB may be further divided. For example, the CB may be further divided into multiple prediction blocks (PBs) for the purpose of intra-frame or inter-frame prediction during the coding and decoding processes. In other words, the CB may be further divided into different sub-partitions, where individual prediction decisions/configurations may be made. In parallel, the CB may be further divided into multiple transform blocks (TBs) for the purpose of describing the level at which the transformation or inverse transformation of the video data is performed. The division scheme of the CB into PBs and TBs may or may not be the same. For example, each division scheme may be performed using a unique procedure based on, for example, various characteristics of the video data. The division scheme of the PBs and TBs may be independent in some exemplary implementations. The division schemes and boundaries of the PBs and TBs may be correlated in some other exemplary implementations. In some implementations, for example, the TBs may be divided after the PB division, and in particular, each PB may be determined following the division of the coding block and then further divided into one or more TBs. For example, in some implementations, the PB may be divided into one, two, four, or other number of TBs.

In some implementations, the luma and chroma channels may be processed differently to split the base blocks into coding blocks and further into prediction and/or transform blocks. For example, in some implementations, splitting of coding blocks into prediction and/or transform blocks may be allowed for the luma channel, but such splitting of coding blocks into prediction and/or transform blocks may not be allowed for the chroma channels. In such implementations, the transformation and/or prediction of luma blocks may thus only be performed at the coding block level. In other examples, the minimum transform block sizes of the luma and chroma channels may be different, e.g., the coding blocks of the luma channel may be allowed to be split into smaller transform and/or predictive blocks than the chroma channels. In yet other examples, the maximum depth of the splitting of coding blocks into transform and/or predictive blocks may be different between the luma and chroma channels, e.g., the coding blocks of the luma channel may be allowed to be split into deeper transform and/or predictive blocks than the chroma channels. As a specific example, a luma coding block may be divided into transform blocks of multiple sizes that can be represented by a recursive division down by up to two levels, allowing transform block shapes such as square, 2:1/1:2, and 4:1/1:4, as well as transform block sizes from 4x4 to 64x64. However, for chroma blocks, only the largest possible transform block designated for the luma block may be allowed.

In some example implementations for partitioning a coding block into PBs, the depth, shape, and/or other characteristics of the PB partition may depend on whether the PB is intra-coded or inter-coded.

The division of the coding block (or prediction block) into transform blocks may be performed in various exemplary manners, including but not limited to quadtree division and predefined pattern division, recursively or non-recursively, further considering transform blocks at the boundaries of the coding block or prediction block. In general, the resulting transform blocks may be at different division levels, may not be the same size, and need not be square in shape (e.g., they may be rectangular with some allowed size and aspect ratio). Further examples are described in more detail below in connection with Figures 15, 16, and 17.

However, in some other implementations, the CB obtained via any of the above partitioning schemes may be used as a basic or smallest coding block for prediction and/or transformation. In other words, no further partitioning is performed for the purpose of performing inter/intra prediction and/or transformation. For example, the CB obtained from the above QTBT scheme may be used as it is as a unit for performing prediction. Specifically, such a QTBT structure removes the concept of multiple partition types, i.e., removes the separation of CU, PU, and TU, and supports more flexibility on CU/CB partition shapes as described above. In such a QTBT block structure, the CU/CB can have either a square or rectangular shape. The leaf nodes of such a QTBT are used as units for prediction and transformation processing without further partitioning. This means that the CU, PU, and TU have the same block size in such an exemplary QTBT coding block structure.

The various CB division schemes described above, as well as further division of the CB into PB and/or TB (including no PB/TB division), may be combined in any manner. The following specific implementations are provided as non-limiting examples.

Specific exemplary implementations of the division of coding blocks and transform blocks are described below. In such exemplary implementations, the base block may be divided into coding blocks using a recursive quadtree division or a predefined division pattern described above (such as the division patterns of Figures 9 and 10). At each level, whether to continue further quadtree division of a particular partition may be determined by local video data characteristics. The resulting CBs may be at various quadtree division levels and of various sizes. The decision to code a picture area using inter-picture (temporal) prediction or intra-picture (spatial) prediction may be made at the CB level (or at the CU level for all three color channels). Each CB may be further divided into one, two, four, or other number of PBs according to a predefined PB division type. Within one PB, the same prediction process may be applied and related information may be transmitted to the decoder on a PB basis. After obtaining the residual blocks by applying the prediction process based on the PB division type, the CBs may be divided into TBs according to other quadtree structures similar to the coding tree for CBs. In this particular implementation, the CB or TB may not be limited to a square. Furthermore, in this particular example, the PB may be square or rectangular for inter prediction, and only square for intra prediction. A coding block may be divided, for example, into four square TBs. Each TB may be further divided recursively (using quadtree partitioning) into smaller TBs called residual quadtrees (RQTs).

Other exemplary implementations for splitting the base block into CBs, PBs, and/or TBs are described further below. For example, rather than using multiple partition unit types such as those shown in FIG. 9 or FIG. 10, a quadtree with nested multi-type trees using bipartite and tripartite segmentation structures (e.g., QTBT or QTBT with tripartites as described above) may be used. Separation of CBs, PBs, and TBs (i.e., splitting CBs into PBs and/or TBs, and splitting PBs into TBs) may be abandoned except when necessary for CBs that have a size that is too large for the maximum transform length, when such CBs require further splitting. This exemplary splitting scheme may be designed to support further flexibility on the CB splitting shape, such that prediction and transformation can both be performed at the CB level without further splitting. In such coding tree structures, the CBs may have either a square or rectangular shape. Specifically, the coding tree block (CTB) may first be split by a quadtree structure. The quadtree leaf nodes may then be further split by a nested multi-type tree structure. An example of a nested multi-type tree structure using bisection or trisection is shown in FIG. 11. Specifically, the example multi-type tree structure of FIG. 11 includes four split types called vertical bisection (SPLIT_BT_VER) (1102), horizontal bisection (SPLIT_BT_HOR) (1104), vertical trisection (SPLIT_TT_VER) (1106), and horizontal trisection (SPLIT_TT_HOR) (1108). Then, CB corresponds to a leaf of the multi-type tree. In this example implementation, as long as CB is not too large for the maximum transform length, this segmentation is used for both prediction and transform processing without further splitting. This means that in most cases, CB, PB, and TB have the same block size in a quadtree with a nested multi-type tree coding block structure. An exception occurs when the maximum supported transform length is smaller than the width or height of the color components of CB. In some implementations, in addition to bisection or trisection, the nested pattern of FIG. 11 may further include a quadtree division.

One specific example of a quadtree with nested multi-type tree coding block structure of block partitions (including quadtree partition, bipartition, and tripartition options) for one base block is shown in FIG. 12. More specifically, FIG. 12 shows that a base block 1200 is quadtree partitioned into four square partitions 1202, 1204, 1206, and 1208. A decision to further use the multi-type tree structure and quadtree of FIG. 11 for further partitioning is made for each of the quadtree partitioned partitions. In the example of FIG. 12, partition 1204 is not further partitioned. Partition 1202 and partition 1208 each adopt another quadtree partition. In partition 1202, the second level quadtree partitioned top left, top right, bottom left, and bottom right partitions adopt third level partitions of quadtree, horizontal bipartition 1104 of FIG. 11, non-partition, and horizontal tripartition 1108 of FIG. 11, respectively. Partition 1208 adopts another quadtree division, and the second level quadtree divided top left, top right, bottom left, and bottom right partitions adopt the third level division of vertical trisection 1106, unsplit, unsplit, and horizontal bisection 1104 of FIG. 11, respectively. Two of the subpartitions of the top left partition of the third level of 1208 are further divided according to horizontal bisection 1104 and horizontal trisection 1108 of FIG. 11, respectively. Partition 1206 adopts the second level division pattern into two partitions following vertical bisection 1102 of FIG. 11, and the two partitions are further divided at the third level according to horizontal trisection 1108 and vertical bisection 1102 of FIG. 11, respectively. A fourth level division is further applied to one of them according to horizontal bisection 1104 of FIG. 11.

In the above specific example, the maximum luma transform size may be 64x64, and the maximum supported chroma transform size may be different from the luma, e.g., 32x32. Even if the above example CB of FIG. 12 is not generally further divided into smaller PBs and/or TBs, when the width or height of the luma coding block or chroma coding block is larger than the maximum transform width or maximum transform height, the luma coding block or chroma coding block may be automatically divided in the horizontal and/or vertical directions to meet the transform size constraints in that direction.

In the specific example of the division of base blocks into CBs above, as described above, the coding tree scheme may support the ability for luma and chroma to have separate block tree structures. For example, for P and B slices, the luma CTB and chroma CTB in one CTU may share the same coding tree structure. For I slices, for example, luma and chroma may have separate coding block tree structures. When separate block tree structures are applied, the luma CTB may be divided into luma CBs by one coding tree structure, and the chroma CTB is divided into chroma CBs by the other coding tree structure. This means that a CU in an I slice may consist of a coding block of the luma component or a coding block of two chroma components, and a CU in a P or B slice is always composed of coding blocks of all three color components unless the video is monochrome.

When a coding block is further divided into multiple transform blocks, the transform blocks therein may be ordered in the bitstream according to various orders or scanning schemes. Exemplary implementations for dividing a coding block or a prediction block into transform blocks, and the coding order of the transform blocks, are described in further detail below. In some exemplary implementations, as described above, the transform division may support transform blocks of multiple shapes, e.g., 1:1 (square), 1:2/2:1, and 1:4/4:1, with transform block sizes ranging from, e.g., 4×4 to 64×64. In some implementations, when the coding block is smaller than or equal to 64×64, the transform block division may be applied only to the luma component, such that for chroma blocks, the transform block size is identical to the coding block size. Otherwise, if the width or height of a coding block is greater than 64, both the luma coding block and the chroma coding block may be implicitly divided into multiples of min(W,64)×min(H,64) and min(W,32)×min(H,32) transform blocks, respectively.

In some example implementations of transform block partitioning, for both intra-coded and inter-coded blocks, a coding block may be further partitioned into multiple transform blocks with a partition depth up to a predefined number of levels (e.g., two levels). The partition depth and size of the transform blocks may be related. For some example implementations, the mapping from the transform size of the current depth to the transform size of the next depth is shown below in Table 1.

Based on the example mappings in Table 1, for a 1:1 square block, the next level transform split may create four 1:1 square sub-transform blocks. The transform split may stop at, for example, 4x4. Thus, a transform size at the current depth of 4x4 corresponds to the same size of 4x4 at the next depth. In the example of Table 1, for a 1:2/2:1 non-square block, the next level transform split may create two 1:1 square sub-transform blocks, while for a 1:4/4:1 non-square block, the next level transform split may create two 1:2/2:1 sub-transform blocks.

In some example implementations, further restrictions may be applied on transform block partitioning for the luma components of intra-coded blocks. For example, for each level of transform partitioning, all sub-transform blocks may be restricted to have equal size. For example, for a 32×16 coding block, level 1 transform partitioning creates two 16×16 sub-transform blocks, and level 2 transform partitioning creates eight 8×8 sub-transform blocks. In other words, to keep the transform units equal in size, a second level partitioning must be applied to all first level sub-blocks. An example of transform block partitioning for an intra-coded square block according to Table 1 is shown in FIG. 15 with the coding order indicated by the arrows. Specifically, 1502 shows a square coding block. The first level partitioning according to Table 1 into four equal-sized transform blocks is shown in 1504 with the coding order indicated by the arrows. The second level partitioning of all first level equal-sized blocks according to Table 1 into 16 equal-sized transform blocks is shown in 1506 with the coding order indicated by the arrows.

In some example implementations, the above restrictions on intra-coding may not apply to the luma components of an inter-coded block. For example, after the first level of transform splitting, any one of the sub-transform blocks may be further split independently at another level. Thus, the resulting transform blocks may or may not be blocks of the same size. An example splitting of an inter-coded block into transform blocks according to their coding order is shown in FIG. 16. In the example of FIG. 16, an inter-coded block 1602 is split into transform blocks at two levels according to Table 1. At the first level, the inter-coded block is split into four transform blocks of equal size. Then, only one of the four transform blocks (but not all of them) is further split into four sub-transform blocks, resulting in a total of seven transform blocks having two different sizes, as indicated by 1604. An example coding order of these seven transform blocks is indicated by arrows at 1604 in FIG. 16.

In some example implementations, for chroma components, some further restrictions on the transform blocks may apply. For example, for chroma components, the transform block size may be as large as the coding block size, but cannot be smaller than a predefined size, e.g., 8x8.

In some other example implementations, for coding blocks with either width (W) or height (H) greater than 64, both luma coding blocks and chroma coding blocks may be implicitly divided into multiples of min(W, 64) x min(H, 64) and min(W, 32) x min(H, 32) transform units, respectively. Here, in this disclosure, "min(a, b)" may return the smaller value between a and b.

Figure 17 further illustrates other alternative exemplary schemes for partitioning coding blocks or predictive blocks into transform blocks. As shown in Figure 17, instead of using recursive transform partitioning, a set of predefined partition types may be applied to the coding block according to the transform type of the coding block. In the particular example shown in Figure 17, one of six exemplary partition types may be applied to partition the coding block into a varying number of transform blocks. Such a scheme for generating transform block partitioning may be applied to either the coding block or the predictive block.

More specifically, the partitioning scheme of FIG. 17 provides up to six exemplary partitioning types for any given transform type (transform type refers to the type of primary transform, e.g., ADST). In this scheme, every coding block or predictive block may be assigned a transform partitioning type based on, e.g., rate-distortion cost. In one example, the transform partitioning type assigned to a coding block or predictive block may be determined based on the transform type of the coding block or predictive block. As illustrated by the six transform partitioning types illustrated in FIG. 17, a particular transform partitioning type may correspond to the partitioning size and pattern of the transform block. The correspondence between various transform types and various transform partitioning types may be predefined. An example is shown below in which capitalized labels indicate transform partitioning types that may be assigned to a coding block or predictive block based on rate-distortion cost.

-PARTITION＿NONE: Assigns a transformation size equal to the block size.

-PARTITION＿SPLIT: Assigns a transformation size that is 1/2 the width of the block size and 1/2 the height of the block size.

-PARTITION＿HORZ: Assigns a transformation size with the same width as the block size and half the height of the block size.

-PARTITION＿VERT: Assigns a transformation size with a width half the block size and a height equal to the block size.

-PARTITION＿HORZ4: Assigns a transformation size with the same width as the block size and 1/4 of the height of the block size.

-PARTITION＿VERT4: Assigns a transformation size with a width of 1/4 of the block size and a height equal to the block size.

In the above example, the transform split types shown in FIG. 17 include uniform transform sizes for all split transform blocks. This is by way of example only and not limitation. In some other implementations, mixed transform block sizes may be used for the split transform blocks in a particular split type (or pattern).

The PBs (or CBs, also called PBs if not further divided into predictive blocks) obtained from any of the above partitioning schemes can become individual blocks for coding via either intra- or inter-prediction. For inter-prediction on the current PB, the residual between the current block and the predictive block can be generated, coded, and included in the coded bitstream.

Inter prediction may be implemented, for example, in single reference mode or mixed reference mode. In some implementations, a skip flag may be included initially in the bitstream of the current block (or at a higher level) to indicate whether the current block is inter-coded and will not be skipped. If the current block is inter-coded, another flag may be further included in the bitstream to signal whether a single or mixed reference mode is used to predict the current block. In the case of a single reference mode, one reference block may be used to generate the prediction block of the current block. In the case of a mixed reference mode, two or more reference blocks may be used to generate the prediction block, for example, by weighted averaging. A mixed reference mode may be referred to as a multiple reference mode, a two-reference mode, or a multiple reference mode. One or more reference blocks may be identified using one or more reference frame indices and further using one or more corresponding motion vectors indicating a shift between the reference block and the current block, for example, in positions in horizontal and vertical pixels. For example, the inter-predicted block of the current block may be generated from a single reference block identified by one motion vector in a reference frame as the predictive block in a single reference mode, while in the case of a mixed reference mode, the predictive block may be generated by a weighted average of two reference blocks in two reference frames indicated by two reference frame indexes and two corresponding motion vectors. The motion vectors may be coded and included in the bitstream in various ways.

In some implementations, the encoding or decoding system may maintain a decoded picture buffer (DPB). Some images/pictures may be maintained in the DPB waiting to be displayed (in the decoding system) and some images/pictures in the DPB may be used as reference frames to enable inter prediction (in the decoding system or encoding system). In some implementations, the reference frames in the DPB may be tagged as either short-term or long-term references for the current picture being encoded or decoded. For example, short-term reference frames may include frames used for inter prediction of blocks in the current frame or the predefined number (e.g., two) subsequent video frames closest to the current frame in decoding order. Long-term reference frames may include frames in the DPB that can be used to predict image blocks in frames beyond a predefined number of frames from the current frame in decoding order. Information regarding such tags for short-term and long-term reference frames may be referred to as a reference picture set (RPS) and may be added to the header of each frame in the encoded bitstream. Each frame in the encoded video stream may be identified by a picture order counter (POC), which is numbered according to the playback sequence, either in an absolute manner or relative to a group of pictures starting with, for example, an I-frame.

In some example implementations, one or more reference picture lists including identification of short-term and long-term reference frames for inter prediction may be formed based on information in the RPS. For example, a single picture reference list may be formed for unidirectional inter prediction, denoted as L0 reference (or reference list 0), and two picture reference lists may be formed for bidirectional inter prediction, denoted as L0 (or reference list 0) and L1 (or reference list 1) for each of the two prediction directions. The reference frames included in the L0 and L1 lists may be ordered in various predetermined manners. The lengths of the L0 and L1 lists may be signaled in the video bitstream. Unidirectional inter prediction may be either a single reference mode or a mixed reference mode, where multiple references for the generation of a prediction block by weighted averaging in the mixed prediction mode are on the same side of the block to be predicted. Bidirectional inter prediction may only be a mixed mode, in that bidirectional inter prediction includes at least two reference blocks.

In some implementations, a merge mode (MM) for inter prediction may be implemented. In general, for a merge mode, one or more of the motion vectors in single reference prediction or mixed reference prediction of the current PB may be derived from other motion vectors, rather than being calculated and signaled independently. For example, in an encoding system, a current motion vector of a current PB may be represented by a difference between the current motion vector and one or more other already encoded motion vectors (referred to as reference motion vectors). Such a difference of the motion vector, rather than the entire current motion vector, may be encoded and included in the bitstream and linked to the reference motion vector. Correspondingly, in a decoding system, a motion vector corresponding to the current PB may be derived based on the decoded motion vector difference and the decoded reference motion vector linked therewith. As a specific form of the general merge mode (MM) inter prediction, such inter prediction based on the motion vector difference may be referred to as a merge mode with motion vector difference (MMVD). Thus, the general MM or the MMVD in particular may be implemented to exploit the correlation between the motion vectors associated with different PBs to improve coding efficiency. For example, adjacent PBs may have similar motion vectors and therefore the MVD may be small and can be coded efficiently. In other examples, the motion vectors may be correlated temporally (between frames) for similarly located/positioned blocks in space.

In some example implementations, an MM flag may be included in the bitstream during the encoding process to indicate whether the current PB is in merge mode. Additionally or alternatively, an MMVD flag may be included and signaled in the bitstream during the encoding process to indicate whether the current PB is in MMVD mode. MM and/or MMVD flags or indicators may be provided at the PB level, CB level, CU level, CTB level, CTU level, slice level, picture level, etc. In a particular example, both an MM flag and an MMVD flag may be included for the current CU, and the MMVD flag may be signaled immediately after the skip flag and the MM flag to specify whether the MMVD mode is used for the current CU.

In some example implementations of MMVD, a list of reference motion vector (RMV) or MV predictor candidates for motion vector prediction may be formed for a predicted block. The list of RMV candidates may include a predetermined number (e.g., two) of MV predictor candidate blocks whose motion vectors may be used to predict the current motion vector. The RMV candidate blocks may include blocks selected from neighboring blocks and/or temporal blocks in the same frame (e.g., blocks that are co-located in an ongoing or subsequent frame of the current frame). These options represent blocks that are in a spatial or temporal position relative to the current block that are likely to have a similar or identical motion vector to the current block. The size of the list of MV predictor candidates may be predetermined. For example, the list may include two or more candidates. To be on the list of RMV candidates, a candidate block may, for example, need to have the same reference frame (or frames) as the current block, must exist (e.g., if the current block is near an edge of a frame, a bounds check needs to be done), must already be encoded during the encoding process, and/or must already be decoded during the decoding process. In some implementations, the list of merge candidates may be filled first with spatially adjacent blocks (scanned in a certain predefined order) if available and satisfy the above conditions, and then with temporal blocks if space is still available in the list. Neighboring RMV candidate blocks may be selected, for example, from the blocks to the left and above the current block. The list of RMV predictor candidates may be dynamically formed at various levels (sequence, picture, frame, slice, superblock, etc.) as a dynamic reference list (DRL). The DRL may be signaled in the bitstream.

In some implementations, the actual MV predictor candidate that is being used as the reference motion vector for predicting the motion vector of the current block may be signaled. If the RMV candidate list includes two candidates, a one-bit flag, called the merge candidate flag, may be used to indicate the selection of the reference merge candidate. For the current block being predicted in a mixed mode, each of the multiple motion vectors predicted using the MV predictor may be associated with a reference motion vector from the merge candidate list. The encoder may determine which RMV candidate more closely predicts the current coding block and signal the selection as an index to the DRL.

In some example implementations of MMVD, after an RMV candidate is selected and used as a base motion vector predictor for the motion vector to be predicted, a motion vector difference (MVD or delta MV representing the difference between the motion vector to be predicted and the reference candidate motion vector) may be calculated in the encoding system. Such an MVD may include information representing the magnitude of the MV difference and the direction of the MV difference, both of which may be signaled in the bitstream. The magnitude of the motion difference and the direction of the motion difference may be signaled in various ways.

In some example implementations of MMVD, a distance index may be used to specify motion vector difference magnitude information and indicate one of a set of predefined offsets representing a predefined motion vector difference from a starting point (reference motion vector). The MV offset according to the signaled index may then be added to either the horizontal or vertical component of the starting (reference) motion vector. Whether the horizontal or vertical component of the reference motion vector should be offset may be determined by the MVD's orientation information. An example predefined relationship between the distance index and the predefined offsets is specified in Table 2.

In some example implementations of MMVD, a direction index may be further signaled and used to represent the direction of the MVD relative to the reference motion vector. In some implementations, the direction may be limited to either the horizontal or vertical direction. An example 2-bit direction index is shown in Table 3. In the example of Table 3, the interpretation of the MVD may change according to the information of the start/reference MV. For example, if the start/reference MV corresponds to a uni-predictive block or a bi-predictive block with both reference frame lists pointing to the same side of the current picture (i.e., the POCs of the two reference pictures are both greater than the POC of the current picture or both less than the POC of the current picture), the sign in Table 3 may specify the sign (direction) of the MV offset added to the start/reference MV. If the start/reference MV corresponds to a bi-predictive block with two reference pictures on different sides of the current picture (i.e., the POC of one reference picture is larger than the POC of the current picture and the POC of the other reference picture is smaller than the POC of the current picture) and the difference between the reference POC in picture reference list 0 and the current frame is larger than the difference between the reference POC in picture reference list 1 and the current frame, the code in Table 3 may specify the sign of the MV offset added to the reference MV corresponding to the reference picture in picture reference list 0, and the sign of the offset of the MV corresponding to the reference picture in picture reference list 1 may have the opposite value (opposite sign of the offset). Otherwise, if the difference between the reference POC in picture reference list 1 and the current frame is larger than the difference between the reference POC in picture reference list 0 and the current frame, the code in Table 3 may specify that the sign of the MV offset added to the reference MV associated with picture reference list 1 and the sign of the offset to the reference MV associated with picture reference list 0 have opposite values.

In some example implementations, the MVD may be scaled according to the difference in POC in each direction. If the difference in POC in both lists is the same, no scaling is required. Otherwise, if the difference in POC in reference list 0 is greater than the difference in reference list 1, the MVD of reference list 1 is scaled. If the POC difference in reference list 1 is greater than list 0, the MVD of list 0 may be scaled as well. If the starting MV is uni-predicted, the MVD is added to the available or reference MV.

In some example implementations of MVD coding and signaling for bidirectional composite prediction, in addition to or instead of coding and signaling the two MVDs separately, symmetric MVD coding may be implemented such that only one MVD needs to be signaled and the other MVD may be derived from the signaled MVD. In such implementations, motion information including reference picture indexes for both list 0 and list 1 is signaled. However, for example, only the MVD associated with reference list 0 is signaled, while the MVD associated with reference list 1 is not signaled and is derived. Specifically, at the slice level, a flag called "mvd_l1_0_flag" may be included in the bitstream to indicate if reference list 1 is not signaled in the bitstream. If this flag is 1, indicating that reference list 1 is equal to zero (and thus not signaled), a bidirectional prediction flag called "BiDirPredFlag" may be set to 0, meaning there is no bidirectional prediction. Otherwise, if mvd_l1_0_flag is zero, BiDirPredFlag may be set to 1 if the closest reference picture in list 0 and the closest reference picture in list 1 form a forward and backward pair of reference pictures or a backward and forward pair of reference pictures, and the reference pictures in list 0 and list 1 are both short-term reference pictures. Otherwise, BiDirPredFlag is set to 0. A BiDirPredFlag of 1 may indicate that a symmetric mode flag is additionally signaled in the bitstream. A decoder may extract the symmetric mode flag from the bitstream if BiDirPredFlag is 1. The symmetric mode flag may be signaled, for example, at the CU level (if necessary) to indicate whether a symmetric MVD coding mode is used for the corresponding CU. When the symmetric mode flag is 1, it indicates the use of a symmetric MVD coding mode and indicates that only the reference picture indexes for both list 0 and list 1 (referred to as "mvp_l0_flag" and "mvp_l1_flag") are signaled by the MVD associated with list 0 (referred to as "MVD0"), and the other motion vector difference "MVD1" should be derived rather than signaled. For example, MVD1 may be derived as -MVD0. Thus, in the exemplary symmetric MVD mode, only one MVD is signaled. In some other exemplary implementations for MV prediction, a harmonic scheme may be used to implement a general merged mode MMVD, as well as some other types of MV prediction, for both single reference mode MV prediction and mixed reference mode MV prediction. Various syntax elements may be used to signal how the MV of the current block is predicted.

For example, for single reference mode, the following MV prediction modes may be signaled:

NEARMV - Use one of the motion vector predictors (MVPs) in the list indicated by the DRL (Dynamic Reference List) index directly without MVD.

NEWMV - Use one of the motion vector predictors (MVP) in the list signaled by the DRL index as a reference and apply the delta to the MVP (e.g., use MVD).

GLOBALMV - Use motion vectors based on frame-level global motion parameters.

Similarly, for mixed reference inter prediction modes using two reference frames corresponding to the two MVs to be predicted, the following MV prediction modes may be signaled:

NEAR_NEARMV - For each of the two MVs to predict, use one of the motion vector predictors (MVPs) in the list signaled by the DRL index without MVD.

NEAR_NEWMV - Use one of the motion vector predictors (MVP) in the list signaled by the DRL index without MVD as a reference MV to predict the first of the two motion vectors, and use one of the motion vector predictors (MVP) in the list signaled by the DRL index as a reference MV together with the additionally signaled delta MV (MVD) to predict the second of the two motion vectors.

NEW_NEARMV - Use one of the motion vector predictors (MVP) in the list signaled by the DRL index without MVD as a reference MV to predict the second of the two motion vectors, and use one of the motion vector predictors (MVP) in the list signaled by the DRL index as a reference MV together with the additionally signaled delta MV (MVD) to predict the first of the two motion vectors.

NEW_NEWMV - Use one of the motion vector predictors (MVPs) in the list signaled by the DRL index as a reference MV and use it together with the additionally signaled delta MV to predict for each of the two MVs.

GLOBAL_GLOBALMV - Use MV from each reference based on frame-level global motion parameters.

Thus, the term "NEAR" above refers to MV prediction using a reference MV without MVD as a general merge mode, whereas the term "NEW" refers to MV prediction that involves using a reference MV and offsetting it with the signaled MVD as in the MMVD mode. In the case of mixed inter prediction, both the reference-based motion vector and the above motion vector delta may generally be different or independent between the two references, even though they may be correlated and such correlation may be exploited to reduce the amount of information required to signal the two motion vector deltas. In such situations, joint signaling of the two MVDs may be implemented and indicated in the bitstream.

The dynamic reference list (DRL) described above can be used to hold a dynamically maintained set of indexed motion vectors that are considered as candidate motion vector predictors.

In some example implementations, a predefined resolution of the MVD may be allowed. For example, a motion vector accuracy (or precision) of 1/8 pixel may be allowed. The MVDs described above for various MV prediction modes may be constructed and signaled in various ways. In some implementations, various syntax elements may be used to signal the above motion vector differences in reference frame list 0 or list 1.

For example, a syntax element called "mv_joint" may specify which components of the motion vector difference associated with it are non-zero. In the case of MVD, this is signaled for all non-zero components together. For example, mv_joint has the following values:
0 can indicate no non-zero MVD along either the horizontal or vertical direction,
1 can be shown that there is non-zero MVD only along the horizontal direction,
2 can be shown that there is non-zero MVD only along the vertical direction,
3 can be shown to have non-zero MVD along both the horizontal and vertical directions.

If the "mv_joint" syntax element for MVD signals that there are no non-zero MVD components, no further MVD information may be signaled. However, if the "mv_joint" syntax signals that there are one or two non-zero components, additional syntax elements may be further signaled for each of the non-zero MVD components, as described below.

For example, a syntax element called "mv_sign" may be used to further specify whether the corresponding motion vector difference component is positive or negative.

In another example, a syntax element called "mv_class" may be used to specify the class of motion vector differences between a predefined set of classes of corresponding non-zero MVD components. The predefined classes of motion vector differences may be used, for example, to separate a continuous magnitude space of motion vector differences into non-overlapping ranges, each range corresponding to an MVD class. Thus, the signaled MVD class indicates the magnitude range of the corresponding MVD component. In the example implementation shown in Table 4 below, higher classes correspond to motion vector differences with a larger magnitude range. In Table 4, the symbol (n,m] is used to represent a range of motion vector differences greater than n pixels and less than or equal to m pixels.

In some other examples, a syntax element called "mv_bit" may be further used to specify the integer portion of the offset between a non-zero motion vector difference component and the magnitude of the start of the correspondingly signaled MV class magnitude range. Thus, mv_bit may indicate the magnitude or amplitude of the MVD. The number of bits required for "my_bit" to signal the full range of each MVD class may vary depending on the MV class. For example, MV_CLASS 0 and MV_CLASS 1 in the implementation of Table 4 may require only a single bit to indicate an integer pixel offset of 1 or 2 from a starting MVD of 0, and each higher MV_CLASS in the example implementation of Table 4 may require progressively one more bit for "mv_bit" than the previous MV_CLASS.

In some other examples, a syntax element called "mv_fr" may be further used to specify the first two fractional bits of the motion vector difference of the corresponding non-zero MVD component, and a syntax element called "mv_hp" may be used to specify the third fractional bit (high resolution bit) of the motion vector difference of the corresponding non-zero MVD component. The two bits of "mv_fr" essentially provide a 1/4 pixel MVD resolution, while the "mv_hp" bits may further provide 1/8 pixel resolution. In some other implementations, two or more "mv_hp" bits may be used to provide an MVD pixel resolution finer than 1/8 pixel. In some example implementations, additional flags may be signaled at one or more of various levels to indicate whether 1/8 pixel or finer MVD resolutions are supported. If the MVD resolution does not apply to a particular coding unit, the above syntax elements for the corresponding unsupported MVD resolutions may not be signaled.

In some example implementations above, fractional resolution may be independent of the MVD of different classes. In other words, a predefined number of "mv_fr" and "mv_hp" bits may be used to signal fractional MVD of non-zero MVD components regardless of the magnitude of the motion vector difference, providing similar options for motion vector resolution.

However, in some other example implementations, the resolution of the motion vector differences in various MVD magnitude classes may be differentiated. Specifically, a high-resolution MVD for a large MVD magnitude of a higher MVD class may not provide a statistically significant improvement in compression efficiency. Thus, the MVD may be coded at a reduced resolution (integer pixel resolution or fractional pixel resolution) for a larger MVD magnitude range corresponding to a higher MVD magnitude class. Similarly, the MVD may be coded at a reduced resolution (integer pixel resolution or fractional pixel resolution) for a generally larger MVD value. Such MVD class-dependent or MVD magnitude-dependent MVD resolution may generally be referred to as adaptive MVD resolution, amplitude-dependent adaptive MVD resolution, or magnitude-dependent MVD resolution. The term "resolution" may further be referred to as "pixel resolution". The adaptive MVD resolution may be implemented in various ways as described by the following example implementations to achieve better compression efficiency overall. In particular, the reduction in the number of signaling bits by aiming for a less accurate MVD may be greater than the additional bits required to code the inter-prediction residual as a result of such a less accurate MVD, due to the statistical observation that non-adaptively processing the MVD resolution of a large-scale or high-class MVD at a similar level as a low-scale or low-class MVD cannot significantly increase the inter-prediction residual coding efficiency of blocks with a large-scale or high-class MVD. In other words, using a higher MVD resolution for a large-scale or high-class MVD may not result in more coding gain than using a lower MVD resolution.

In some typical example implementations, the pixel resolution or precision of the MVD may or may not decrease with increasing MVD class. Reducing the pixel resolution of the MVD corresponds to a coarser MVD (or a larger step from one MVD level to the next). In some implementations, the correspondence between MVD pixel resolution and MVD class may be specified, predefined, or preconfigured, and thus does not need to be signaled in the encoded bitstream.

In some example implementations, each of the MV classes in Table 3 may be associated with a different MVD pixel resolution.

In some example implementations, each MVD class may be associated with a single allowed resolution. In some other implementations, one or more MVD classes may be associated with two or more optional MVD pixel resolutions. Thus, a signal in the bitstream of a current MVD component having such an MVD class may be followed by additional signaling to indicate which optional pixel resolution is selected for the current MVD component.

In some example implementations, the adaptively allowed MVD pixel resolutions may include, but are not limited to, (in descending order of resolution): 1/64pel (pixel), 1/32pel, 1/16pel, 1/8pel, 1-4pel, 1/2pel, 1pel, 2pel, 4pel.... Thus, each ascending MVD class may be associated with one of these resolutions in a non-ascending order. In some implementations, an MVD class may be associated with two or more of the above resolutions, where the higher resolution may be less than or equal to the lower resolution of the preceding MVD class. For example, if MV_CLASS_3 in Table 4 may be associated with optional 1pel and 2pel resolutions, then the highest resolution to which MV_CLASS_4 in Table 4 may be associated would be 2pel. In some other implementations, the highest allowed resolution of an MV class may be higher than the lowest allowed resolution of the preceding (lower) MV class. However, the average of the allowed resolutions for the ascending MV classes may only be in non-ascending order.

In some implementations, if fractional pixel resolution higher than 1/8 pel is allowed, the "mv_fr" and "mv_hp" signaling may be extended to accommodate more than 3 fractional bits in total.

In some example implementations, fractional pixel resolution may only be allowed for MVD classes that are equal to or less than the threshold MVD class. For example, fractional pixel resolution may only be allowed for MVD-CLASS 0 and not for all other MV classes in Table 4. Similarly, fractional pixel resolution may only be allowed for MVD classes that are equal to or less than any one of the other MV classes in Table 4. For other MVD classes above the threshold MVD class, only integer pixel resolution of the MVD is allowed. In this manner, fractional resolution signaling, such as one or more of the "mv-fr" and/or "mv-hp" bits, need not be signaled for MVDs that are signaled in MVD classes equal to or greater than the threshold MVD class. For MVD classes with resolution less than one pixel, the number of bits of "mv-bit" signaling may be further reduced. For example, for MV_CLASS_5 in Table 4, the range of the MVD pixel offset is (32, 64], and therefore 5 bits are required to signal the entire range at 1 pel resolution. However, if MV_CLASS_5 is associated with a 2 pel MVD resolution (a resolution lower than 1 pel resolution), then 4 bits instead of 5 bits may be required for "mv-bit", and neither "mv-fr" nor "mv-hp" would need to be signaled following the signaling of "mv_class" as MV-CLASS_5.

In some example implementations, fractional pixel resolution may be allowed only for MVDs with integer values less than a threshold integer pixel value. For example, fractional pixel resolution may be allowed only for MVDs smaller than 5 pixels. Corresponding to this example, fractional resolution may be allowed for MV_CLASS_0 and MV_CLASS_1 in Table 4, and not allowed for all other MV classes. In another example, fractional pixel resolution may be allowed only for MVDs smaller than 7 pixels. Corresponding to this example, fractional resolution may be allowed for MV_CLASS_0 and MV_CLASS_1 in Table 4 (having a range less than 5 pixels), and not allowed for MV_CLASS_3 and above (having a range greater than 5 pixels). For MVDs belonging to MV_CLASS_2, whose pixel range encompasses 5 pixels, fractional pixel resolution of the MVD may be allowed according to the "mv-bit" value. If the "m-bit" value is signaled as 1 or 2 (such that the integer part of the signaled MVD, calculated as the start of the pixel range of MV_CLASS_2 with offset 1 or 2 as indicated by "m-bit", is 5 or 6), fractional pixel resolution may be allowed. Otherwise, if the "mv-bit" value is signaled as 3 or 4 (such that the integer part of the signaled MVD is 7 or 8), fractional pixel resolution may not be allowed.

In some other implementations, only a single MVD value may be allowed for MV classes equal to or greater than the threshold MV class. For example, such a threshold MV class may be MV_CLASS 2. Thus, MV_CLASS_2 and above may only be allowed to have a single MVD value and no fractional pixel resolution. The single allowed MVD value for these MV classes may be predefined. In some examples, the single allowed value may be the upper limit of the range for each of these MV classes in Table 4. For example, MV_CLASS_2 through MV_CLASS_10 may be equal to or greater than the threshold class for MV_CLASS 2, and the single allowed MVD values for these classes may be predefined as 8, 16, 32, 64, 128, 256, 512, 1024, and 2048, respectively. In some other examples, the single allowed value may be the median of the range for each of these MV classes in Table 4. For example, MV_CLASS_2 through MV_CLASS_10 may be above the class threshold, and the single allowable MVD values for these classes may be predefined as 3, 6, 12, 24, 48, 96, 192, 384, 768, and 1536, respectively. Any other value within the range may also be defined as the single allowable resolution for the respective MVD class.

In the above implementation, if the signaled "mv_class" is greater than or equal to a predefined MVD class threshold, then the "mv_class" signaling alone is sufficient to determine the MVD value. The magnitude and direction of the MVD are then determined using "mv_class" and "mv_sign".

Thus, when an MVD is signaled for just one reference frame (either from reference frame list 0 or list 1, but not both), or for two reference frames together, the precision (or resolution) of the MVD may depend on the class of the associated motion vector difference in Table 3 and/or the magnitude of the MVD.

In some other implementations, the pixel resolution or precision of the MVD may decrease or not increase with increasing MVD magnitude. For example, the pixel resolution may depend on the integer portion of the MVD magnitude. In some implementations, fractional pixel resolution may only be allowed for MVD magnitudes below an amplitude threshold. For a decoder, the integer portion of the MVD magnitude may first be extracted from the bitstream. The pixel resolution may then be determined, and then a determination may be made as to whether any fractional MVD is present in the bitstream and needs to be parsed (e.g., if fractional pixel resolution is not allowed for the integer magnitude of a particular extracted MVD, the bitstream requiring extraction may not include fractional MVD bits). The exemplary implementations described above for MVD class-dependent adaptive MVD pixel resolution apply to MVD magnitude-dependent adaptive MVD pixel resolution. In a particular example, MVD classes above or including a magnitude threshold may be allowed to have only one predefined value.

The various exemplary implementations described above apply to single-reference modes. These implementations also apply to the exemplary NEW_NEARMV, NEAR_NEWMV, and/or NEW_NEWMV modes in composite prediction under MMVD. These implementations generally apply to any MVD adaptation resolution.

In a particular example implementation for adaptive MVD pixel resolution, the MVD pixel resolution for MVD magnitudes less than 1 may be fractional, and for MV classes MV_CLASS_1 and above, only a single MVD magnitude may be allowed equal to the end value of the corresponding MVD magnitude range in Table 4. In such an example, the allowed MVD values are shown in Table 4 for allowed fractional pixel resolutions of 1/8, 1/4, or 1/2 pixel.

For coding blocks, whether an adaptive MVD pixel resolution is used can be signaled (derived) explicitly or implicitly. If an adaptive MVD pixel resolution is not used, it indicates that different MVD classes may follow the MVD ranges shown in Table 4, and a non-adaptive MVD pixel resolution can be defined or signaled. Such a non-adaptive resolution may be fractional (e.g., 1/8, 1/4, or 1/2 pixel) or non-fractional (e.g., 1, 2, 4, ... pixels) and applies to all MVD classes. The non-adaptive resolution basically determines the number of bits required to signal mv_bit, mv_fr, and mv_hp mentioned above. If the non-adaptive resolution is fractional, it can only determine the number of bits required to signal mv_fr and mv_hp for all MVD classes (independent of the class of MVD), and the number of bits for signaling Mv_bit may depend on the MVD class.

When adaptive MVD pixel resolution is signaled as being used, the allowed MVD levels or values may be predefined or signaled in an adaptive manner, such as those shown in Table 5. For example, they may be signaled in the bitstream in various ways depending on the particular scheme for the adaptive MVD resolution. In the example of Table 5, a set of signaling syntax may be used to indicate a fractional resolution (e.g., 1/8 pixel), a magnitude threshold (e.g., MVD magnitude of 1 pixel) at which the signaled fractional resolution applies. Other sets of syntax (which may be more complex) may be used to signal other adaptive MVD resolution schemes. Such indication of an adaptive MVD pixel resolution scheme may be signaled at one of various coding levels, such as the sequence level, picture level, frame level, slice level, superblock level, or coding block level.

In some example implementations, a global adaptive MVD pixel resolution scheme, including but not limited to those shown in Table 5, may be defined or signaled at a particular coding level (e.g., sequence level, picture level, frame level, slice level, superblock level). Such an adaptive MVD pixel resolution scheme may be further modified at the same or other coding levels such that the allowable MVD pixel resolution values for various MVD classes may be adjusted or modified at the same or other coding levels. If no adjustment is made at a particular coding level, the signaled or predefined adaptive MVD pixel resolution scheme is applied without modification. For example, a global adaptive MVD pixel resolution scheme may be defined or signaled at the frame level, while adjustments may be made at one or more superblock levels or coding block levels, or vice versa.

Such an adjustment may be implemented as a limitation of the MVD precision or an extension of the MVD precision. Information related to such an adjustment may be predefined or signaled. The predefined adjustment may be applied to all coding blocks. Alternatively, the predefined adjustment may be activated at various coding levels by signaling.

In some implementations, such an adjustment may be embodied as a maximum allowed MVD precision. For a particular coding block, when an adaptive MVD resolution is applied, such maximum allowed MVD precision may differ from the MVD pixel precision of the adaptive MVD pixel resolution scheme specified/signaled/derived at the picture level, or superblock level, or coded block level, as described above. In such a situation, the allowed MVD resolution values for the various MVD classes may be determined by taking both the allowed values and the maximum allowed MVD precision specified by or derived from the adaptive MVD pixel resolution scheme.

For example, assume that the adaptive MVD pixel resolution scheme in Table 5 is predefined/signaled/derived for a particular coding level. Further assume that the maximum allowable precision is 1/4 pixel, which means that no precision greater than 1/8 pixel is allowed for any MVD class, regardless of the adaptive MVD resolution associated with Table 5. Then, by indiscriminately applying the maximum allowable pixel precision as a constraint in Table 5, the allowable MVD pixel levels or values for various MVD classes may be modified as follows:

Defining/signaling a maximum allowable MVD pixel precision of 1/4 pixel, thereby not allowing more than 1/8 pixel precision for all MVD classes, is just one example. In another example, the maximum allowable pixel precision may be defined/signaled as 1/2 pixel. The allowable MVD values corresponding to MV_CLASS_0 above could be (1/2, 1, 2) for adaptive resolution schemes with fractional pixel resolutions of 1/8 pixel, 1/4 pixel, and 1/2 pixel, and (1, 2) for pixel resolution of 1 pixel.

As illustrated in the implementation above in connection with Table 6, when using an adaptive resolution scheme defined/signaled/derived at a particular coding level and an adaptive MVD resolution is applied with an additional defined/signaled maximum allowed MVD precision at the same or a different coding level, it may be required/constrained that such maximum allowed MVD precision is not greater than the MVD resolution of the adaptive resolution scheme. In other words, the actually applied MVD precision, derived taking into account both the adaptive resolution scheme and the maximum allowed precision, is clipped by the MVD resolution in the adaptive resolution scheme (i.e., the maximum allowed precision is not effective if it is greater than the resolution defined/signaled/derived from the adaptive resolution scheme).

However, in some other implementations, such clipping may not be required, and the defined/signaled maximum allowed MVD precision may control the actual MVD resolution of at least some MVD classes. In these implementations, if adaptive MVD resolution is applied (as indicated by definition/signaling/derivation at various coding levels, as described above), the adjustment of the MVD level of at least some MVD classes may include increasing, rather than limiting, the adaptive MVD resolution defined/signaled/derived in an adaptive MVD pixel resolution scheme, such as that associated with Table 5. For example, the adjustment may be made to allow a higher precision than specified/signaled/derived from the adaptive resolution scheme of the MVD class below the defined or signaled threshold MVD class level. Such a higher precision may be defined/signaled as a maximum allowed MVD precision, as described above. Such a maximum allowed precision may be imposed below the threshold MVD class level, regardless of the specified/signaled/derived MVD resolution in the adaptive resolution scheme. Specifically, such a threshold MVD class level may be (but need not be) MV_CLASS_0 (or the lowest MVD class level of a set of MVD classes, such as the set of MVD classes in Table 5). The maximum allowable pixel precision may be predefined/signaled. The maximum allowable pixel precision may be a fraction. For a specific example, if the threshold MVD class is MV_CLASS_0 in the adaptive resolution scheme of Table 5, the MVD pixel resolution of MV_CLASS_0 is a non-fractional 1 pixel, and the maximum allowable fractional pixel precision for adjustment is 1/8, 1/4, or 1/2 pixel, the adjusted allowable MVD values are as follows:

In some exemplary alternative implementations to that of Table 7, a threshold MVD amplitude may be used instead of the threshold MVD class level. In these implementations, higher precision may be imposed by a maximum allowable MVD precision specified/signaled for MVDs with magnitudes equal to or less than the threshold MVD amplitude rather than the threshold MVD class level. In such implementations, mv_bit information may be signaled early enough in the video stream in addition to the mv_class information so that the magnitude of the MVD can be determined in time to determine the allowable MVD value. For example, by replacing the threshold MVD class with a threshold MVD magnitude of 1/2 pixel and still assuming that the adaptive MVD resolution of MV_CLASS_0 is 1 pixel in the adaptive resolution scheme, Table 7 becomes Table 8 below:

In some other example implementations, the above adjustments may include only allowing certain precisions and lower precisions (e.g., decimal precision 1/8, 1/4, or 1/2 or less) when the MVD magnitude is equal to or less than a threshold MVD magnitude. In such implementations, again, the mv_bit information in addition to the mv_class information may be signaled early enough in the video stream so that the MVD magnitude can be determined in time to determine the allowed MVD value.

In such implementations, no additional resolution may be imposed on the MVD values derived from the adaptive resolution scheme (e.g., Table 5). Instead, MVD values associated with a resolution equal to or greater than the defined/signaled precision level may not be allowed if the MVD amplitude is greater than a threshold MVD magnitude. Again, in the example of Table 5, further assume that MVD values associated with a resolution equal to or greater than the defined/signaled precision of ⅛ pixel precision are not allowed for MVD magnitudes greater than a threshold MVD magnitude of ½ pixel. Table 5 is then adjusted as follows:

In particular, as noted above, the allowed MVD values for MV_CLASS_0 and 1/8 pixel fractional resolution (1/8, 2/8, 3/8, 1/2, 5/8, 6/8, 7/8, 1, 2) are adjusted to (1/8, 2/8, 3/8, 1/2, 6/8, 1, 2), such that MVD values associated with 1/8 pixel precision are only allowed and kept below a threshold MVD magnitude of 1/2 pixel. Above the 1/2 pixel magnitude, MVD values associated with 1/8 pixel precision, such as 5/8 pixel values and 7/8 pixel values, are not allowed.

Similarly, in the example of Table 5, assume that MVD values associated with resolutions equal to or greater than the defined/signaled precision of 1/4 pixel precision are not allowed if the MVD magnitude is greater than the threshold magnitude of 1/2 pixel. Then, adjust Table 5 as follows:

In some of the above implementations, the threshold MVD magnitude may be 2 pixels or less, such as the 1/2 pixel magnitude threshold given in the example above.

The above example implementations are described with respect to a particular MVD, regardless of whether the inter prediction mode is in a single reference mode or a mixed reference mode. In some other example implementations in a mixed reference mode where the MV is predicted by multiple reference frames, a set of definitions/signaling may be used to indicate whether an adaptive MVD resolution is applied and to which of the multiple reference frames it is applied.

In some example implementations, if MVD is signaled for multiple reference frames, one (or more) flags/indexes may be signaled to indicate whether adaptive MVD resolution is applied or not.

For example, when MVD is signaled for multiple reference frames (e.g., in the NEW_NEWMV mode described above, or other mixed reference inter prediction modes), one flag/index may be signaled in the video stream to indicate whether adaptive MVD resolution is applied to the signaling of MVD for all of the multiple reference frames. If this flag/index is 1 (or 0), this indicates that adaptive MVD resolution is applied to the signaling of MVD for all of the multiple reference frames. Otherwise, if this flag/index is 0 (or 1), adaptive MVD coding is not applied to the signaling of MVD for any of the multiple reference frames. In such an implementation, adaptive MVD resolution is applied in an all-or-nothing manner with respect to the multiple inter prediction reference frames.

In some other examples, when MVD is signaled for multiple reference frames (e.g., in the NEW_NEWMV mode described above for the two-reference frame composite inter prediction mode or other composite inter prediction modes), one flag/index may be signaled separately for each reference frame to indicate whether adaptive MVD resolution is applied to each reference frame. In such implementations, whether adaptive MVD resolution is applied may be determined individually for each of the reference frames. The decision of whether to apply adaptive MVD resolution may be made at the encoder independently for each of the multiple reference frames and signaled separately in the video stream.

In some example implementations, when MVD is signaled for multiple reference frames, for each of the multiple reference frames, if the MVD of that reference frame is non-zero, one flag/index may be signaled to indicate whether adaptive MVD resolution is applied to that reference frame or not. Otherwise, no flag/index needs to be signaled. In other words, if the MVD of a particular reference frame is signaled/indicated as zero, there is no need to determine whether adaptive MVD resolution is applied or not, and therefore no corresponding signaling in the video stream is needed. However, in such implementations, an indication that the MVD is zero needs to be signaled before the time when a determination is made as to whether adaptive resolution is applied or not.

Further turning to signaling of MVD resolution, in some example implementations, a flag/index may be signaled to explicitly indicate the MVD resolution of the current coding block, and the context used to entropy code such flag/index may depend on the MVD class associated with the MVD. Such a flag/index may be either the MVD resolution used to derive an adaptive resolution scheme, such as Table 5, or the maximum allowed MVD precision described above.

In some example implementations of signaling MVD resolution, various components of the MVD may be signaled separately. The MVD may include, for example, a horizontal component and a vertical component. A flag/index may be signaled for each of the horizontal and vertical components of the MVD to indicate the MVD resolution of the horizontal and vertical components, respectively.

In some example implementations, the MVD resolution flag/index may be signaled after the MVD class information. Depending on the value of the signaled MVD class information, such as MV_CLASS_0, MV_CLASS_1, MV_CLASS_2, etc., a context value may be derived and used to signal the MVD resolution flag/index to indicate the MVD resolution. In other words, the syntax(es) for signaling the MVD resolution may be entropy coded using different contexts for different MVD classes or different MVD class groups.

FIG. 18 illustrates a flowchart 1800 of an exemplary method according to the principles underlying the above implementation for adaptive MVD resolution. The flow of the exemplary decoding method starts at S1801. At S1810, a video stream is received. At S1820, it is determined that a video block is inter-coded based on a predictive block and a motion vector (MV), and the MV should be derived from a reference motion vector (RMV) and a motion vector difference (MVD) of the video block. At S1830, in response to determining that the MVD is coded at the adaptive MVD pixel resolution, a reference MVD pixel precision of a current video block is determined, a maximum allowable MVD pixel precision is identified, a set of allowable MVD levels of the current video block is determined based on the reference MVD pixel precision and the maximum allowable MVD pixel precision, and the MVD from the video stream is derived according to at least one MVD parameter and the set of allowable MVD levels signaled in the video stream for the current video block. The exemplary method stops at S1899.

FIG. 19 shows a flowchart 1900 of an example method according to the principles underlying the above implementation for adaptive MVD resolution. The flow of the example decoding method starts at S1901. At S1910, a video stream is received. At S1920, it is determined that the current video block is inter-coded and associated with multiple reference frames. At S1930, it is further determined, based on signaling in the video stream, whether an adaptive motion vector difference (MVD) pixel resolution is applied to at least one of the multiple reference frames. The example method stops at S1999.

FIG. 20 shows a flowchart 2000 of an example method according to the principles underlying the above implementation for adaptive MVD resolution. The flow of the example decoding method starts at S2001. At S2010, a video stream is received. At S2020, it is determined that a video block is inter-coded based on a predictive block and a motion vector (MV), and the MV should be derived from a reference motion vector (RMV) and a motion vector difference (MVD) of the video block. At S2030, a current MVD class of the MVD among a predefined set of MVD classes is determined. At S2040, at least one context for entropy decoding at least one explicit signaling in the video stream is derived based on the current MVD class, and the at least one explicit signaling is included in the video stream to specify an MVD pixel resolution of at least one component of the MVD. At S2050, at least one explicit signaling from the video stream is entropy decoded using the at least one context to determine an MVD pixel resolution of at least one component of the MVD. The exemplary method stops at S2099.

In the embodiments and implementations of the present disclosure, any steps and/or operations may be combined or arranged in any quantity or order, as desired. Two or more of the steps and/or operations may be performed in parallel. The embodiments and implementations of the present disclosure may be used separately or combined in any order. Furthermore, each of the methods (or embodiments), the encoder, and the decoder may be implemented by a processing circuit (e.g., one or more processors or one or more integrated circuits). In one example, the one or more processors execute a program stored in a non-transitory computer-readable medium. The embodiments of the present disclosure may be applied to a luma block or a chroma block. The term block may be interpreted as a prediction block, a coding block, or a coding unit, i.e., a CU. The term block here may also be used to refer to a transform block. In the following items, when referring to a block size, it may refer to either the width or height of the block, or the maximum value of the width and height, or the minimum value of the width and height, or the size of the area (width * height), or the aspect ratio of the block (width: height, or height: width).

The techniques described above may be implemented as computer software using computer-readable instructions and physically stored on one or more computer-readable media. For example, FIG. 21 illustrates a computer system (2100) suitable for implementing certain embodiments of the disclosed subject matter.

Computer software may be coded using any suitable machine code or computer language that is amenable to mechanisms such as assembly, compilation, linking, etc., to create code that includes instructions that may be executed by one or more computer central processing units (CPUs), graphics processing units (GPUs), etc., directly or via interpretation, microcode execution, etc.

The instructions can be executed on various types of computers or computer components, including, for example, personal computers, tablet computers, servers, smartphones, gaming consoles, Internet of Things devices, etc.

The components illustrated in FIG. 21 for the computer system (2100) are exemplary in nature and are not intended to suggest any limitations as to the scope of use or functionality of the computer software implementing the embodiments of the present disclosure. The configuration of components should not be construed as having any dependency or requirement regarding any one or combination of components illustrated in the exemplary embodiment of the computer system (2100).

The computer system (2100) may include certain human interface input devices. Such human interface input devices may respond to input by one or more human users, for example, via tactile input (e.g., keystrokes, swipes, data glove movements), audio input (e.g., voice, clapping), visual input (e.g., gestures), or olfactory input (not depicted). Human interface devices may also be used to capture certain media not necessarily directly associated with conscious human input, such as audio (e.g., voice, music, ambient sounds), images (e.g., scanned images, photographic images obtained from still image cameras), and video (e.g., two-dimensional video, three-dimensional video including stereoscopic video).

The input human interface devices may include one or more of a keyboard (2101), a mouse (2102), a trackpad (2103), a touch screen (2110), a data glove (not shown), a joystick (2105), a microphone (2106), a scanner (2107), and a camera (2108) (only one of each is depicted).

The computer system (2100) may also include certain human interface output devices. Such human interface output devices may stimulate one or more of the human user's senses, for example, through haptic output, sound, light, and smell/taste. Such human interface output devices may include haptic output devices (e.g., haptic feedback via a touch screen (2110), data gloves (not shown), or joystick (2105), although there may be haptic feedback devices that do not function as input devices), audio output devices (such as speakers (2109), headphones (not depicted)), visual output devices (such as screens (2110), including CRT screens, LCD screens, plasma screens, OLED screens, each with or without touch screen input capability, each with or without haptic feedback capability, some of which may be capable of outputting two-dimensional visual output or three or more dimensional output via means such as stereographic output, virtual reality glasses (not depicted), holographic displays, and smoke tanks (not depicted)), and printers (not depicted).

The computer system (2100) may also include human-accessible storage devices and their associated media, such as optical media, including CD/DVD ROM/RW (2120) with CD/DVD or similar media (2121), thumb drives (2122), removable hard drives or solid state drives (2123), legacy magnetic media such as tapes and floppy disks (not depicted), and specialized ROM/ASIC/PLD-based devices (not depicted) such as security dongles.

Those skilled in the art should also understand that the term "computer-readable medium" as used in connection with the subject matter of this disclosure does not encompass transmission media, carrier waves, or other transitory signals.

The computer system (2100) may also include interfaces (2154) to one or more communication networks (2155). The networks may be, for example, wireless, wired, optical. The networks may further be local, wide area, metropolitan, vehicular and industrial, real-time, delay tolerant, etc. Examples of networks include local area networks such as Ethernet, WLAN, cellular networks including GSM, 3G, 4G, 5G, LTE, etc., television wired or wireless wide area digital networks including cable television, satellite television, and terrestrial broadcast television, vehicular and industrial including CANbus, etc. Certain networks typically require an external network interface adapter attached to a particular general-purpose data port (e.g., a USB port on the computer system (2100)) or peripheral bus (2149), while other networks are typically integrated into the core of the computer system (2100) by attachment to a system bus as described below (e.g., an Ethernet interface to a PC computer system, or a cellular network interface to a smartphone computer system). Using any of these networks, the computer system (2100) can communicate with other entities. Such communications may be one-way receive only (e.g., broadcast TV), one-way transmit only (e.g., CANbus to a particular CANbus device), or bidirectional with other computer systems using, for example, local or wide area digital networks. Specific protocols and protocol stacks may be used with each of these networks and network interfaces, as described above.

The aforementioned human interface devices, human accessible storage devices, and network interfaces may be attached to the core (2140) of the computer system (2100).

The cores (2140) may include specialized programmable processing devices in the form of one or more central processing units (CPUs) (2141), graphics processing units (GPUs) (2142), field programmable gate arrays (FPGAs) (2143), hardware accelerators for specific tasks (2144), graphics adapters (2150), and the like. These devices may be connected via a system bus (2148), along with read only memory (ROM) (2145), random access memory (2146), and internal mass storage (2147) such as an internal hard drive, SSD, etc. that is not accessible to the user. In some computer systems, the system bus (2148) may be accessible in the form of one or more physical plugs to allow expansion with additional CPUs, GPUs, etc. Peripheral devices may be attached directly to the core's system bus (2148) or via a peripheral bus (2149). In one example, a screen (2110) may be connected to a graphics adapter (2150). Architectures for peripheral buses include PCI, USB, etc.

The CPU (2141), GPU (2142), FPGA (2143), and accelerator (2144) can execute certain instructions that, in combination, may constitute the aforementioned computer code. That computer code may be stored in ROM (2145) or RAM (2146). Transient data may also be stored in RAM (2146), and persistent data may be stored, for example, in internal mass storage (2147). Rapid storage and retrieval from any of the memory devices may be enabled using cache memories that may be closely associated with one or more of the CPU (2141), GPU (2142), mass storage (2147), ROM (2145), RAM (2146), etc.

The computer-readable medium can bear computer code for performing various computer-implemented operations. The medium and computer code may be those specially designed and constructed for the purposes of the present disclosure, or they may be of the kind known and available to those skilled in the computer software arts.

As a non-limiting example, a computer system (2100) having an architecture, and specifically a core (2140), can provide functionality as a result of a processor (including a CPU, GPU, FPGA, accelerator, etc.) executing software embodied in one or more tangible computer-readable media. Such computer-readable media can be the user-accessible mass storage introduced above, as well as media associated with a particular storage of the core (2140) of a non-transitory nature, such as the core internal mass storage (2147) or ROM (2145). Software implementing various embodiments of the present disclosure can be stored in such devices and executed by the core (2140). The computer-readable media can include one or more memory devices or chips, depending on the particular needs. The software can cause the core (2140), and specifically the processor therein (including a CPU, GPU, FPGA, etc.) to perform a particular process or a particular portion of a particular process described herein, including defining data structures stored in RAM (2146) and modifying such data structures according to a process defined by the software. Additionally or alternatively, the computer system may provide functionality as a result of logic hardwired or otherwise embodied in circuitry (e.g., accelerator (2144)), which may operate in place of or in conjunction with software to perform particular processes or portions of particular processes described herein. References to software may encompass logic, and vice versa, where appropriate. References to computer-readable media may encompass circuitry (such as integrated circuits (ICs)) that stores software for execution, circuitry that embodies logic for execution, or both, where appropriate. The present disclosure encompasses any suitable combination of hardware and software.

While this disclosure describes several exemplary embodiments, there are alterations, permutations, and various substitute equivalents that fall within the scope of this disclosure. Thus, it will be appreciated that those skilled in the art can devise numerous systems and methods that, although not explicitly shown or described herein, embody the principles of the present disclosure and are therefore within the spirit and scope of the present disclosure.
Appendix A: Acronyms
JEM: Joint Exploration Model
VVC: Versatile Video Coding
BMS: Benchmark Set
MV: Motion Vector
HEVC: High Efficiency Video Coding
SEI: Supplemental Extended Information
VUI: Video Usability Information
GOPs: Group of Pictures
TUs: conversion units
PUs: Prediction Units
CTUs: Coding Tree Units
CTBs: coding tree blocks
PBs: Predicted blocks
HRD: Hypothetical Reference Decoder
SNR: Signal to Noise Ratio
CPUs: Central Processing Units
GPUs: Graphics Processing Units
CRT: Cathode ray tube
LCD: Liquid crystal display
OLED: Organic Light Emitting Diode
CD: Compact Disc
DVD: Digital Video Disc
ROM: Read-Only Memory
RAM: Random Access Memory
ASIC: Application Specific Integrated Circuit
PLD: Programmable Logic Device
LAN: Local Area Network
GSM: Global System for Mobile Communications
LTE: Long Term Evolution
CANBus: Controller Area Network Bus
USB: Universal Serial Bus
PCI: Peripheral Component Interconnect
FPGA: Field Programmable Gate Area
SSD: Solid State Drive
IC: Integrated Circuit
HDR: High Dynamic Range
SDR: Standard Dynamic Range
JVET: Joint Video Exploration Team
MPM: Most Probable Mode
WAIP: Wide-angle intra prediction
CU: coding unit
PU: Prediction Unit
TU: conversion unit
CTU: Coding Tree Unit
PDPC: Position-dependent prediction combination
ISP: Intra Subpartition
SPS: Sequence parameter settings
PPS: Picture Parameter Set
APS: Adaptive Parameter Set
VPS: Video Parameter Set
DPS: Decoding Parameter Set
ALF: Adaptive Loop Filter
SAO: Sample Adaptive Offset
CC-ALF: Cross-component adaptive loop filter
CDEF: Constrained Directional Enhancement Filter
CCSO: Cross component sample offset
LSO: Local Sample Offset
LR: Loop restoration filter
AV1: AOMedia Video 1
AV2: AOMedia Video 2
MVD: Motion Vector Difference
CfL: Chroma from Luma
SDT: Semi-Disjoint Tree
SDP: Semi-separated division
SST: Semi-separate tree
SB: Superblock
IBC (or IntraBC): Intra-block copy
CDF: Cumulative density function
SCC: Screen Content Coding
GBI: Generalized Biprediction
BCW: Bi-prediction with CU-level weights
CIIP: Combined Intra-Inter Prediction
POC: Picture Order Count
RPS: Reference Picture Set
DPB: Decoded Picture Buffer
MMVD: Merge mode with motion vector difference

101 Samples
102 Arrow
103 Arrow
104 Block
201 Current Block
202 Sample
203 Sample
204 Sample
205 Samples
206 Samples
300 Communication Systems
310 Terminal Devices
320 Terminal Devices
330 Terminal Devices
340 Terminal Devices
350 Network
400 Communication Systems
401 Video Source
402 Video Picture Stream
403 Video Encoder
404 Encoded video data
405 Streaming Server
406 Client Subsystem
407 Video Data
408 Client Subsystem
409 Video Data
410 Video Decoder
411 Video Picture Output Stream
412 Display
413 Video Capture Subsystem
420 Electronic Devices
430 Electronic Devices
501 Channel
510 Video Decoder
512 Rendering Device
515 Buffer Memory
520 Parser
521 Symbols
530 Electronic Devices
531 Receiver
551 Scaler/Inverse Conversion Unit
552 Intra Prediction Units
553 Motion Compensation Prediction Unit
555 Aggregator
556 Loop Filter
557 Reference Picture Memory
558 Current Picture Buffer
601 Video Sources
603 Video Encoder
620 Electronic Devices
630 Source Coder
632 Coding Engine
633 Decoder
634 Reference Picture Memory
635 Predictor
640 Transmitter
645 Entropy Coder
650 Controller
660 Communication Channels
703 Video Encoder
721 General-purpose controller
722 Intra Encoder
723 Residual Calculator
724 Residual Encoder
725 Entropy Encoder
726 Switch
728 Residual Decoder
730 InterEncoder
810 Video Decoder
871 Entropy Decoder
872 Intra Decoder
873 Residual Decoder
874 Reconstruction Module
880 Interdecoder
2100 Computer Systems
2101 Keyboard
2102 Mouse
2103 Trackpad
2105 Joystick
2106 Microphone
2107 Scanner
2108 Camera
2109 Speaker
2110 Touch Screen
2120 CD/DVD ROM/RW
2121 CD/DVD or similar media
2122 Thumb Drive
2123 Removable Hard Drive or Solid State Drive
2140 Core
2141 Central Processing Unit (CPU)
2142 Graphics Processing Unit (GPU)
2143 Field Programmable Gate Area (FPGA)
2144 Accelerator
2145 Read-Only Memory (ROM)
2146 Random Access Memory (RAM)
2147 Mass Storage
2148 System Bus
2149 Surrounding bus
2150 Graphics Adapter
2154 Network Interface
2155 Communication Network

Claims (22)

1. A method, executed by a video processing device, for processing a current video block of a video stream, comprising:
receiving the video stream;
determining that the current video block is inter-coded based on a predictive block and a motion vector (MV), where the MV should be derived from a reference motion vector (RMV) and a motion vector difference (MVD) of the current video block;
In response to determining that the MVD is coded at an adaptive MVD pixel resolution,
determining a reference MVD pixel precision of the current video block;
Identifying a maximum allowable MVD pixel accuracy;
determining a set of allowable MVD levels for the current video block based on the reference MVD pixel precision and the maximum allowable MVD pixel precision;
and deriving the MVD from the video stream according to at least one MVD parameter signaled within the video stream for the current video block and the set of allowable MVD levels. The method of claim 1, wherein the reference MVD pixel precision of the current video block is specified/signaled/derived at a sequence level, a picture level, a frame level, a superblock level, or a coding block level. The method of claim 2, wherein the reference MVD pixel precision of the current video block depends on an MVD class associated with the MVD of the current video block. The method of claim 2, wherein the reference MVD pixel precision of the current video block depends on the MVD magnitude of the MVD of the current video block. The method of claim 2, wherein the maximum allowable MVD pixel precision is predefined. determining a current MVD class from among a predefined set of MVD classes, and determining the set of allowable MVD levels for the MVD based on the reference MVD pixel precision and the maximum allowable MVD pixel precision comprises:
6. The method of claim 1 , further comprising: excluding MVD levels associated with MVD pixel precision equal to or greater than the maximum allowable MVD pixel precision from a reference MVD level set determined based on the reference MVD pixel precision and the current MVD class to determine the set of allowable MVD levels for the current video block. The method of claim 6, wherein the maximum allowable MVD pixel precision is 1/4 pixel. The method of any one of claims 1 to 5, wherein MVD levels associated with 1/8 pixel precision or better are excluded from the set of allowable MVD levels for the current video block. determining a current MVD class from among a predefined set of MVD classes;
6. The method of claim 1, wherein an MVD level associated with a fractional MVD precision is included in the set of allowable MVD levels regardless of the reference MVD pixel precision if the current MVD class is less than or equal to a threshold MVD class. The method of claim 9, wherein the threshold MVD class is the lowest MVD class among a predefined set of MVD classes. The method of any one of claims 1 to 5, further comprising determining a magnitude of the MVD, and an MVD level associated with an MVD accuracy higher than a threshold MVD accuracy is allowed in the set of allowable MVD levels only if the magnitude of the MVD is less than or equal to a threshold MVD magnitude. The method of claim 11, wherein the threshold MVD magnitude is 2 pixels or less. The method of claim 12, wherein the threshold MVD accuracy is 1 pixel. The method of claim 11, wherein MVD levels associated with MVD precision of 1/4 pixel or greater are allowed only if the magnitude of the MVD is 1/2 pixel or less. The method of any one of claims 1 to 5, wherein the maximum allowable MVD pixel precision is less than or equal to the reference MVD pixel precision. 1. A method, executed by a video processing device, for processing a current video block of a video stream, comprising:
receiving the video stream;
determining that the current video block is inter-coded and associated with multiple reference frames;
determining whether an adaptive motion vector difference (MVD) pixel resolution is applied to at least one of the plurality of reference frames based on signaling in the video stream ;
the signaling includes a single-bit flag to indicate whether adaptive MVD pixel resolution is applied to all or none of the multiple reference frames.
method . The video processing device processes the current video block of the video stream.
13. A method for
receiving the video stream;
The current video block is inter-coded and associated with multiple reference frames.
determining that the device is being used;
determining whether an adaptive motion vector difference (MVD) pixel resolution is applied to at least one of the plurality of reference frames based on signaling in the video stream;
the signaling includes a separate flag, each corresponding to one of the plurality of reference frames, for indicating whether an adaptive MVD pixel resolution is applied;
method . The video processing device processes the current video block of the video stream.
13. A method for
receiving the video stream;
The current video block is inter-coded and associated with multiple reference frames.
determining that the device is being used;
determining whether an adaptive motion vector difference (MVD) pixel resolution is applied to at least one of the plurality of reference frames based on signaling in the video stream;
The signaling comprises, for each of a plurality of reference frames:
an implicit indication that adaptive MVD pixel resolution is not applied when the MVD corresponding to each of the plurality of reference frames is zero; and
and a single-bit flag for indicating whether adaptive MVD pixel resolution is applied when the MVD corresponding to each of the plurality of reference frames is non-zero.
method . 1. A method, executed by a video processing device, for processing a current video block of a video stream, comprising:
receiving the video stream;
determining that the current video block is inter-coded based on a predictive block and a motion vector (MV), where the MV should be derived from a reference motion vector (RMV) and a motion vector difference (MVD) for the current video block;
determining a current MVD class of the MVD from among a predefined set of MVD classes;
deriving at least one context for entropy decoding at least one explicit signaling in the video stream based on the current MVD class, the at least one explicit signaling being included in the video stream to specify an MVD pixel resolution for at least one component of the MVD;
and entropy decoding the at least one explicit signaling from the video stream using the at least one context to determine the MVD pixel resolution for the at least one component of the MVD. 20. The method of claim 19, wherein the at least one component of the MVD includes a horizontal component and a vertical component of the MVD, and the at least one context includes two separate contexts each associated with one of the horizontal and vertical components of the MVD, the horizontal and vertical components being associated with separate MVD pixel resolutions. A video processing device comprising a memory for storing computer instructions and a processor, the processor being configured, when executing the computer instructions, to perform a method according to any one of claims 1 to 5 and 16 to 20 . A computer program product for causing a computer to carry out the method according to any one of claims 1 to 5 and 16 to 20 .

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