JP7653799B2 - Ceramic electronic component, circuit board, and method for manufacturing ceramic electronic component - Google Patents

Description

The present invention relates to ceramic electronic components, circuit boards, and methods for manufacturing ceramic electronic components.

A multilayer ceramic capacitor is formed by alternately stacking multiple internal electrode layers and ceramic layers, with the ends of each internal electrode layer exposed alternately at both end faces in the longitudinal direction, and a pair of external electrodes formed at both ends in the longitudinal direction so as to be conductive with the exposed ends of the internal electrode layers. As disclosed in Patent Document 1, these external electrodes cover not only the ends of the capacitance section, but also the top, bottom, and side surfaces in a cap-like shape.

Patent document 2 also discloses a configuration in which a ridge formed by the first and second side faces of the element body is exposed between electrode portions formed on the element body in order to improve self-alignment during solder mounting while eliminating directional constraints during mounting and improving workability during mounting.

International Publication No. 2006/098092 JP 2015-103554 A

However, there was a risk of cracks occurring near the ends of the external electrodes, particularly at the ridges of the element body, due to the difference in the linear expansion coefficient between the external electrodes and the element body, stresses and residual stresses caused by differences in shrinkage during the firing process of the base layer of the external electrodes, and stresses from the solder after mounting. Also, in a structure in which the ridges of the element body are exposed, there was a risk of cracks occurring in those areas when the ridges come into contact with external objects during handling of the component.

The present invention aims to provide a ceramic electronic component, a circuit board, and a method for manufacturing a ceramic electronic component that can relieve stress concentrated on the edges of the element body via external electrodes.

In order to solve the above problems, a ceramic electronic component according to one aspect of the present invention comprises an element body having a dielectric and an internal electrode, and a pair of external electrodes connected to the internal electrodes at end faces opposite each other in the longitudinal direction of the element body and formed contiguous with the end faces of the element body on side faces opposite each other in the width direction and on top and bottom faces opposite each other in the height direction, each external electrode having a portion covering at least one side face of the element body, each slit portion opening toward the opposite external electrode and extending from the opening toward the end face covered by the external electrode but not reaching the end face, each external electrode having no slit portion formed on the top face of the element body, the bottom face of the element body, the ridge line between the top face and the side face of the element body, the ridge line between the bottom face and the side face of the element body, and a portion covering the end face of the element body. Slit portions may not be formed on the top face and the bottom face of the element body of each external electrode.

Furthermore, in a ceramic electronic component according to one aspect of the present invention, a plurality of the slit portions are formed in the portion of each external electrode covering both side surfaces of the element body, the element body has a plurality of layers of the internal electrodes arranged at intervals from one another within the dielectric, and the uppermost slit portion formed in the portion covering each side surface overlaps in the height direction with the uppermost internal electrode, and the lowermost slit portion formed in the portion covering each side surface overlaps in the height direction with the lowermost internal electrode.

Furthermore, in a ceramic electronic component according to one aspect of the present invention, the element body is exposed from the external electrode at the position of the slit portion.

In addition, according to a ceramic electronic component according to one aspect of the present invention, when the dimension in the height direction of the side surface of the external electrode is T, the width of the slit portion is (T/30) μm or more and (T/10) μm or less.

In the ceramic electronic component according to one aspect of the present invention, when the length of the external electrode is L, the length of the slit portion is not less than (L/5) μm and not more than (L/1.5) μm.

Furthermore, in a ceramic electronic component according to one aspect of the present invention, when the height dimension of the side surface of the external electrode is T, the slit portion is spaced from the edge line of the element body that is closest to the slit portion by (T/30) μm or more and (T/3) μm or less.

In addition, in a ceramic electronic component according to one aspect of the present invention, the slit portion has a side that is formed in an oblique arc shape with respect to a ridge line of the element body that is closest to the slit portion , and is distal to the ridge line .

In the ceramic electronic component according to one aspect of the present invention, the slits are provided in parallel and at equal intervals on each side surface of the element body.

In addition, in a ceramic electronic component according to one aspect of the present invention, each of the conductive layers includes a base layer that contains a metal and is formed on multiple surfaces of the base body so as to cover the ridge lines of the base body, is connected to the internal electrodes, and has a plating layer formed on the base layer.

In addition, according to a ceramic electronic component according to one aspect of the present invention, the base layer comprises a common material mixed with the metal.

Furthermore, in a ceramic electronic component according to one aspect of the present invention, the common material is mainly composed of the dielectric material contained in the base body.

In addition, according to a ceramic electronic component according to one aspect of the present invention, the base layer is mainly composed of Ni.

In addition, according to a ceramic electronic component according to one aspect of the present invention, the base layer is mainly composed of Cu.

In addition, according to a ceramic electronic component according to one aspect of the present invention, the plating layer covers the base layer at the position of the slit portion.

In addition, according to a ceramic electronic component according to one aspect of the present invention, the internal electrode comprises a first internal electrode layer and a second internal electrode layer laminated on the first internal electrode layer via a dielectric layer containing the dielectric, and the external electrode comprises a first external electrode connected to the first internal electrode layer and a second external electrode provided separately from the first external electrode and connected to the second internal electrode layer.

Furthermore, according to a circuit board according to one aspect of the present invention, there is provided a circuit board on which any of the ceramic electronic components described above is mounted, and the ceramic electronic component is connected via a solder layer attached to the external electrode .

Moreover, a method for manufacturing a ceramic electronic component according to one aspect of the present invention is a method for manufacturing the ceramic electronic component, comprising the steps of: forming an element body having a dielectric and an internal electrode, the element body having two end faces, two side faces, a top face, and a bottom face, with the internal electrodes extended to the end faces; applying an inhibitor that inhibits adhesion of a base material of a base layer of an external electrode to an area where the slit portion is to be formed , the inhibitor extending in a slit shape to an area where the slit portion is to be formed; applying the base material to the two end faces and parts of the two side faces, the top face, and the bottom face of the element body; firing the base material to form a base layer having the slit portion; and forming a plating layer on the base layer.

According to one aspect of the present invention, stress concentrated on the edge of the element body can be alleviated via the external electrodes.

1 is a perspective view showing a configuration of a multilayer ceramic capacitor in accordance with a first embodiment. 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 cut in the longitudinal direction. 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 cut in the width direction. 2B is a cross-sectional view showing an example of a stress acting on the element body when the external electrode in FIG. 2A has a slit portion. FIG. 2B is a cross-sectional view showing an example of a stress acting on the element body when the external electrode in FIG. 2A does not have a slit portion. FIG. 4 is a flowchart showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 3A to 3C are cross-sectional views showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 3A to 3C are cross-sectional views showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 3A to 3C are cross-sectional views showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 3A to 3C are cross-sectional views showing an example of a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 2A to 2C are cross-sectional views showing a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 2A to 2C are cross-sectional views showing a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 2A to 2C are cross-sectional views showing a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 2A to 2C are cross-sectional views showing a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 2A to 2C are cross-sectional views showing a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. 11 is a cross-sectional view showing the configuration of a circuit board on which a multilayer ceramic capacitor in accordance with a second embodiment is mounted. 6B is a cross-sectional view showing the configuration of a circuit board on which a multilayer ceramic capacitor is mounted when the external electrodes of FIG. 6A do not have slits. FIG. 13 is a flowchart showing another example of the method for manufacturing the multilayer ceramic capacitor in accordance with the third embodiment. FIG. 13 is a perspective view showing a configuration of a multilayer ceramic capacitor in accordance with a fourth embodiment. FIG. 13 is a perspective view showing a configuration of a multilayer ceramic capacitor in accordance with a fifth embodiment. FIG. 13 is a perspective view showing a configuration of a ceramic electronic component according to a sixth embodiment.

Below, the embodiments of the present invention will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the present invention, and not all of the combinations of features described in the embodiments are necessarily essential to the configuration of the present invention. The configuration of the embodiments may be modified or changed as appropriate depending on the specifications of the device to which the present invention is applied and various conditions (conditions of use, environment of use, etc.). The technical scope of the present invention is determined by the claims, and is not limited by the individual embodiments below. Also, the drawings used in the following description may differ in scale and shape from the actual structure in order to make each configuration easier to understand.

First Embodiment
Fig. 1 is a perspective view showing the configuration of the multilayer ceramic capacitor according to the first embodiment, Fig. 2A is a cross-sectional view taken along the length of the multilayer ceramic capacitor in Fig. 1, and Fig. 2B is a cross-sectional view taken along the width of the multilayer ceramic capacitor in Fig. 1. Note that Fig. 2A is taken along line A1-A1 in Fig. 1, and Fig. 2B is taken along line B1-B1 in Fig. 1.

In Figures 1, 2A, and 2B, multilayer ceramic capacitor 1A includes element body 2 and external electrodes 6A, 6B. Element body 2 includes laminate 2A, lower cover layer 5A, and upper cover layer 5B. Laminate 2A includes internal electrode layers 3A, 3B, and dielectric layer 4.

A lower cover layer 5A is provided on the lower layer of the laminate 2A, and an upper cover layer 5B is provided on the upper layer of the laminate 2A. The internal electrode layers 3A, 3B are alternately drawn to either of the two end faces of the element body 2 via a dielectric layer 4 and laminated. Although an example in which a total of 11 internal electrode layers 3A, 3B are laminated is shown in Figures 1, 2A, and 2B, the number of laminated internal electrode layers 3A, 3B is not particularly limited. The shapes of the element body 2 and the laminate 2A can be approximately rectangular parallelepiped shapes.

In the following description, the direction perpendicular to the two end faces of the element body 2 may be referred to as the length direction DL, the direction perpendicular to the two side faces of the element body 2 as the width direction DW, and the direction perpendicular to the top and bottom faces of the element body 2 as the stacking direction (height direction or thickness direction) DS. The bottom surface of the element body 2 may be disposed in a position facing the mounting surface of the circuit board on which the multilayer ceramic capacitor 1A is mounted. The element body 2 may be chamfered along the ridge line LY of the element body 2. The element body 2 may have a curved surface R with its corners chamfered.

The external electrodes 6A, 6B are formed on the element body 2 while being separated from each other in the longitudinal direction DL. Each external electrode 6A, 6B is formed continuously from the lower surface side of the element body 2 via the end faces to the upper surface side of the element body 2, and is also formed continuously on a pair of opposite side surfaces perpendicular to both the lower surface and the end faces of the element body 2. In this way, the base layer 7 is formed continuously from a pair of end faces of the element body 2 over four adjacent peripheral surfaces. End edges EA of the external electrodes 6A, 6B are located on the surface of the element body 2.

Here, the external electrodes 6A, 6B have slit portions 8. The slit portions 8 open at the edge EA of the external electrode 6A or 6B toward the opposite external electrode . Also, each slit portion 8 can be located on the side surface of the external electrode 6A, 6B. The slit portions 8 can be provided at a position away from the ridge line LY of the element body 2. At the positions of the slit portions 8, the element body 2 is exposed from the external electrodes 6A, 6B, and the exposed region has a constant width in the height direction, extends from the opening of the slit portion 8 toward the end face of the external electrode on which the slit portion 8 is formed, and has a constant length.
For example, the slit portions 8 extend from the ends of the external electrodes 6A, 6B along the direction of the ridge lines LY of the element body 2. The slit portions 8 have openings KA at positions away from the ridge lines LY of the element body 2. The slit portions 8 can reduce stress acting on the closest ridge lines of the four ridge lines LY extending in the longitudinal direction DL of the element body 2 via the external electrodes 6A, 6B.

1 and 2B show an example in which the slits 8 are provided in each of the external electrodes 6A, 6B on the surface (a pair of side surfaces of the element body 2) normal to the width direction DW, but the slits 8 may also be provided in each of the external electrodes 6A, 6B on the surface (lower and upper surfaces of the element body 2) normal to the stacking direction DS. A plurality of slits 8 may be provided on one surface of the element body 2. The slits 8 may have a side far from the ridgeline LY of the element body 2 that is closest to the slits 8 and has an oblique arc shape with respect to the ridgeline LY, or may be wedge-shaped. The slits 8 may be formed in a straight line parallel to the ridgeline LY, and the tip of the slits 8 may have an acute angle.

Here, by providing the slits 8 in each of the external electrodes 6A, 6B, when the multilayer ceramic capacitor 1A is mounted, the solder that wets up through each of the external electrodes 6A, 6B can be suppressed at the position of the slits 8. In the conventional configuration, as shown in Fig. 6B, the solder 13A', 13B' wets up onto the side surfaces of the external electrodes 6A', 6B', but the stress caused by the upper solder 13A', 13B' is concentrated at a position S' where the ridgeline of the element body 2 formed by the underside and side surfaces comes into contact with the external electrodes 6A, 6B.

On the other hand, in this embodiment, as shown in FIG. 6A, the amount of solder 13A, 13B that wets upward is suppressed by the slit portion 8, so the amount of solder on the side surface is reduced, and the stress concentrated at the position S where the ridge line LY of the element body 2 and the external electrodes 6A, 6B contact can be reduced. Position S is on the ridge line LY where two surfaces are adjacent, so stress is likely to concentrate, and it is subjected to stress from the solder 13A, 13B on the lower surface and from the solder 13A, 13B on the side surface, and furthermore, since it is at the end edge in the length direction of the external electrodes 6A, 6B, it is the most stress-concentrated in the product and is likely to become the starting point of cracks. Therefore, reducing the stress at this position S contributes greatly to improving the reliability of the product in terms of preventing cracks. The slit portion 8 may be formed parallel to the ridge line LY closer to the element body 2, or may be formed at an angle. 6A , when the line on the ridge side of the slit portion 8 is formed so as to move away from the ridge line LY of the adjacent element body 2 as it moves from the opening to the end face, the solder 13A, 13B tends to wet upward near the end face of the side surface, and is less likely to stagnate. Also, when the line on the ridge side of the slit portion 8 is formed so as to move closer to the ridge line LY of the adjacent element body 2 as it moves from the opening to the end face, the solder 13A, 13B can be more effectively prevented from wetting upward at the slit portion 8.

The side of each of the external electrodes 6A and 6B has a height dimension T and a length dimension L. The width of the slit portion 8 is preferably (T/30) μm or more and (T/10) μm or less. The width of the slit portion 8 can be determined by measuring the exposed dimension of the element body 2 at the center position of the slit portion in the length direction. The length of the slit portion 8 is preferably (L/5) μm or more and (L/1.5) μm or less. The length of the slit portion 8 can be determined by measuring the length of the element body 2 in the length direction from the opening of the slit portion 8 to the end of the opposite side of the slit portion 8. The slit portion 8 is preferably (T/30) μm or more and (T/3) μm or less away from the ridge line LY of the element body 2 closest to the slit portion 8 in the height direction. The height position of the slit portion 8 can be determined by the center position of the width of the slit portion 8 at the center position of the slit portion 8 in the length direction.

For example, the height T of each of the external electrodes 6A, 6B is 300 μm and the length L is 150 μm. In this case, the width of the slit portion 8 is preferably 10 μm or more and 30 μm or less. The length of the slit portion 8 is preferably 30 μm or more and 100 μm or less. The slit portion 8 is preferably spaced from the edge line LY of the element body 2 by 10 μm or more and 100 μm or less.

Here, by making the width of the slit portion 8 at least (W/30) μm and the length of the slit portion 8 at least (L/5) μm, it is possible to reduce the amount of solder that wets upward in the slit portion 8 and reduce the stress concentrated at the position S where the ridge line LY of the element body 2 contacts the external electrodes 6A, 6B. By making the width of the slit portion 8 no more than (W/10) μm and the length of the slit portion 8 no more than (L/1.5) μm, it is possible to suppress a decrease in the strength of each of the external electrodes 6A, 6B.

By separating the slit portion 8 by (T/30) μm or more from the edge line LY of the element body 2 that is closest to the slit portion 8 , even if stress is applied to the multilayer ceramic capacitor 1A during mounting or transportation, it is possible to prevent an impact from being applied directly to the corners of the element body 2 and suppress damage to the element body 2. By setting the distance between the slit portion 8 and the edge line LY of the element body 2 that is closest to the slit portion 8 to be (T/3) μm or less, it is possible to reduce the amount of solder that wets upward at the slit portion 8 and reduce stress concentration at the position S where the edge line LY of the element body 2 and the external electrodes 6A, 6B contact each other.

At least one slit 8 is effective in the side surface of the external electrodes 6A, 6B, but if a pair of slits are formed at positions spaced apart in the height direction, the mounting surfaces can be both the top and bottom of the element body . Two slits 8 may be formed on each side surface of the external electrodes 6A, 6B of the product.

In the length direction DL, the internal electrode layers 3A, 3B are alternately arranged at different positions in the laminate 2A. The internal electrode layer 3A can be arranged on one end face side of the element body 2 with respect to the internal electrode layer 3B, and the internal electrode layer 3B can be arranged on the other end face side of the element body 2 with respect to the internal electrode layer 3A. The end of the internal electrode layer 3A is drawn to the end of the dielectric layer 4 at one end face side in the length direction DL of the element body 2 and connected to the external electrode 6A. The end of the internal electrode layer 3B is drawn to the end of the dielectric layer 4 at the other end face side in the length direction DL of the element body 2 and connected to the external electrode 6B.
On the other hand, in the width direction DW of the element body 2, the ends of the internal electrode layers 3A, 3B are covered with the dielectric layer 4. In the width direction DW, the positions of the ends of the internal electrode layers 3A, 3B may be aligned. The element body 2 may include a side margin portion 10 that covers the internal electrode layers 3A, 3B in the width direction DW. In the examples of Figures 1 and 2B, the slit portion 8 is located on the surface of the element body 2 in the side margin portion 10.
Furthermore, when the component is viewed from the end face side as in Figure 2B, the uppermost slit portion 8 formed in the portion covering each side surface overlaps in the height direction with the uppermost internal electrode 3A or 3B, and the lowermost slit portion 8 formed in the portion covering each side surface overlaps in the height direction with the lowermost internal electrode 3A or 3B , the stress applied from the external electrodes 6A, 6B to the internal electrodes 3A, 3B is reduced, and cracks are less likely to occur along the outermost internal electrodes 3A, 3B.

The thickness of the internal electrode layers 3A, 3B and the dielectric layer 4 in the stacking direction DS can be within a range of 0.2 μm to 20 μm, for example, 0.3 μm. The material of the internal electrode layers 3A, 3B can be selected from metals such as Cu (copper), Fe (iron), Zn (zinc), Al (aluminum), Sn (tin), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), or may be an alloy containing these metals.

The material of the dielectric layer 4 can be, for example, mainly composed of a ceramic material having a perovskite structure. The main component may be contained at a ratio of 50 at% or more. The ceramic material of the dielectric layer 4 can be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanate zirconate, and titanium oxide.

The material of the lower cover layer 5A and the upper cover layer 5B may be mainly composed of a ceramic material, for example. The main component of the ceramic material of the lower cover layer 5A and the upper cover layer 5B may be the same as the main component of the ceramic material of the dielectric layer 4. The thickness of each of the lower cover layer 5A and the upper cover layer 5B is preferably 5 μm or more and 100 μm or less.

Each of the external electrodes 6A, 6B comprises, as a conductive layer, an underlayer 7 formed on the element body 2 and a plating layer 9 laminated on the underlayer 7. The underlayers 7 are formed on the element body 2 while being separated from each other in the longitudinal direction DL. Each underlayer 7 is formed continuously from the underside of the element body 2 to the upper side of the element body 2 via an end face with which the underlayer is in contact , and is also formed continuously from the underside of the element body 2 to a pair of side faces that are opposite to each other . In this manner, each of the underlayers 7 is formed continuously from one end face of the element body 2 over the four adjacent peripheral faces.

The metal used as the conductive material of the underlayer 7 may be, for example, a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn as the main component. The underlayer 7 may also contain a common material in which a metal is mixed. The common material is mixed in the underlayer 7 in an island shape to reduce the difference in thermal expansion coefficient between the element body 2 and the underlayer 7, and to relieve the stress applied to the underlayer 7. The common material is, for example, a ceramic component that is the main component of the dielectric layer 4. The underlayer 7 may also contain a glass component. The glass component is mixed into the underlayer 7 to densify the underlayer 7. The glass component is, for example, an oxide of Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), or B (boron).

Here, the underlayer 7 is preferably made of a sintered body of conductive metal paste. This makes it possible to thicken the underlayer 7 while ensuring adhesion between the element body 2 and the underlayer 7, and ensures the strength of each of the external electrodes 6A, 6B while ensuring conductivity with the internal electrode layers 3A, 3B.

The plating layer 9 is continuously formed for each of the external electrodes 6A, 6B so as to cover the underlayer 7. The plating layer 9 can cover the underlayer 7 around the slit portion 8. The plating layer 9 is electrically connected to the internal electrode layers 3A, 3B via the underlayer 7. The plating layer 9 is also electrically connected to a terminal of the mounting board via solder.

The material of the plating layer 9 is, for example, a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The plating layer 9 may be a plating layer of a single metal component, or may be a plating layer of multiple metal components different from each other. The plating layer 9 may have a three-layer structure of, for example, a Cu plating layer 9A formed on the underlayer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B. The Cu plating layer 9A can improve the adhesion of the plating layer 9 to the underlayer 7. The Ni plating layer 9B can improve the heat resistance of each of the external electrodes 6A and 6B during soldering. The Sn plating layer 9C can improve the wettability of the solder to the plating layer 9.

Figure 3A is a cross-sectional view showing an example of stress acting on the element body when the external electrode in Figure 2A has a slit portion, and Figure 3B is a cross-sectional view showing an example of stress acting on the element body when the external electrode in Figure 2A does not have a slit portion.

3A , a compressive stress of vectors indicated by arrows acts on the element body 2 from the external electrode 6A. The edge line LY of the element body 2 receives the stress of the external electrode 6A from two faces, so the stress is concentrated thereon. At the position of the slit portion 8, the stress K2 transmitted from the external electrode 6A in the surface direction of the element body 2 is divided, and the concentration of stress on the edge line LY of the element body 2 is alleviated. As a result, the stress K1 acting on the edge line LY of the element body 2 can be reduced, and the occurrence of cracks in the element body 2 starting from the edge line LY of the element body 2 can be suppressed.

On the other hand, in FIG. 3B, the multilayer ceramic capacitor 1A' is provided with an external electrode 6A' that does not have a slit portion 8. The external electrode 6A' includes a base layer 7' formed on the element body 2 and a plating layer 9' laminated on the base layer 7'. The plating layer 9' can have a three-layer structure of a Cu plating layer 9A' formed on the base layer 7', a Ni plating layer 9B' formed on the Cu plating layer 9A', and a Sn plating layer 9C' formed on the Ni plating layer 9B'.

In FIG. 3B, in an external electrode 6A' without a slit portion 8, stress K2' is transmitted in the surface direction of the element body 2, and stress is concentrated in the direction of the edge line LY of the element body 2. As a result, stress K1' acting on the edge line LY of the element body 2 increases, making it easier for cracks to occur in the element body 2 starting from the edge line LY of the element body 2. In this way, the presence of the slit portion 8 can reduce the stress from the external electrodes 6A, 6B on the edge line LY of the adjacent element body 2, and can suppress the occurrence of cracks in the element body 2.

Figure 4 is a flow chart showing an example of a method for manufacturing a multilayer ceramic capacitor according to the first embodiment, and Figures 5A to 5I are cross-sectional views showing an example of a method for manufacturing a multilayer ceramic capacitor according to the first embodiment. Note that Figures 5C to 5I show an example in which three layers of internal electrode layers 3A and 3B are alternately stacked with dielectric layers 4 interposed therebetween.

In S1 of FIG. 4, an organic binder and an organic solvent as a dispersant and a molding aid are added to the dielectric material powder, and the powder is pulverized and mixed to generate a slurry. The dielectric material powder includes, for example, ceramic powder. The dielectric material powder may include an additive. The additive is, for example, an oxide or glass of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), Y (yttrium), Sm (samarium), Eu (europium), Gd (cadmium), Tb (teubium), Dy (dysprosium, Ho (holmium), Er (erbium), Tm (thulium), Yb (ytterbium), Co (cobalt), Ni, Li (lithium), B, Na (sodium), K (potassium), or Si. The organic binder is, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

Next, as shown in S2 of FIG. 4 and FIG. 5A, the slurry containing ceramic powder is applied in sheet form onto a carrier film and dried to produce a green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. The slurry can be applied using a doctor blade method, a die coater method, a gravure coater method, or the like.

Next, as shown in S3 of FIG. 4 and FIG. 5B, the conductive paste for the internal electrodes is applied to the green sheets 24 of the layers forming the internal electrode layers 3A and 3B among the multiple green sheets in a predetermined pattern to form the internal electrode patterns 23. At this time, multiple internal electrode patterns 23 separated in the longitudinal direction of the green sheets 24 can be formed on one green sheet 24. The conductive paste for the internal electrodes contains powder of the metal used as the material for the internal electrode layers 3A and 3B. For example, when the metal used as the material for the internal electrode layers 3A and 3B is Ni, the conductive paste for the internal electrodes contains Ni powder. The conductive paste for the internal electrodes also contains a binder, a solvent, and, if necessary, an auxiliary. The conductive paste for the internal electrodes may contain a ceramic material, which is the main component of the dielectric layer 4, as a common material. The conductive paste for the internal electrodes can be applied by screen printing, inkjet printing, gravure printing, or the like.

Next, as shown in S4 of FIG. 4 and FIG. 5C, a laminated block is produced by stacking a plurality of green sheets 24 on which the internal electrode pattern 23 is formed and green sheets 25A, 25B for outer layers on which the internal electrode pattern 23 is not formed, in a predetermined order. The thickness of the green sheets 25A, 25B for outer layers is greater than the thickness of the green sheet 24 on which the internal electrode pattern 23 is formed. At this time, the green sheets 24 adjacent in the stacking direction are stacked so that the internal electrode patterns 23A, 23B are alternately shifted in the longitudinal direction of the green sheets 24. Also, there are parts where only the internal electrode pattern 23A is stacked in the stacking direction, parts where the internal electrode patterns 23A, 23B are alternately stacked in the stacking direction, and parts where only the internal electrode pattern 23B is stacked in the stacking direction.

Next, as shown in S5 and 5D of FIG. 4, the laminated block obtained in the molding step S4 of FIG. 4 is pressed to pressure-bond the green sheets 24, 25A, and 25B. As a method for pressing the laminated block, for example, a method of isostatically pressing the laminated block can be used.

Next, as shown in S6 of FIG. 4 and FIG. 5E, the pressed laminated block is cut and separated into individual rectangular parallelepiped elements. The laminated block is cut at a portion where only the internal electrode patterns 23A are stacked in the stacking direction and at a portion where only the internal electrode patterns 23B are stacked in the stacking direction. For example, a method such as blade dicing can be used to cut the laminated block.

As shown in Fig. 5F , the singulated element body 2' has internal electrode layers 3A and 3B alternately stacked with dielectric layers 4 interposed therebetween, and cover layers 5A and 5B are formed on the bottom and top layers. The internal electrode layer 3A is drawn out from the surface of the dielectric layer 4 at one end face of the element body 2', and the internal electrode layer 3B is drawn out from the surface of the dielectric layer 4 at the other end face of the element body 2'. Note that Fig. 5F shows one singulated element body of Fig. 5E enlarged in the length direction.

Next, as shown in S7 of FIG. 4 and FIG. 5G, the element body 2' is chamfered to form an element body 2 having curved surfaces R at the corners of the element body 2'. The element body 2' can be chamfered by barrel polishing, for example.

Next, as shown in S8 of Fig. 4, the binder contained in the element body 2 chamfered in S7 of Fig. 4 is removed. In order to remove the binder, the element body 2 is heated in a _N2 atmosphere at about 350°C, for example.

Next, as shown in S9 of FIG. 4, an inhibitor that inhibits the adhesion of the conductive paste for the base layer is selectively applied to the element body 2. At this time, the inhibitor is selectively applied to the formation position of the slit portion 8 in FIG. 1. The inhibitor is, for example, silicone that is not wetted by the conductive paste for the base layer. Methods that can be used to selectively apply the inhibitor to the element body 2 include screen printing, inkjet printing, and gravure printing.

Next, as shown in S10 of FIG. 4, the conductive paste for the base layer is applied to both end faces of the element body 2 to which the inhibitor was applied in S9 of FIG. 4 and the four surfaces (upper surface, lower surface, and a pair of side surfaces) of the peripheral surface of each end face, and then dried. For example, a dipping method can be used to apply the conductive paste for the base layer. At this time, since the inhibitor is applied to the formation position of the slit portion 8 in FIG. 1, the conductive paste for the base layer does not adhere to the formation position of the slit portion 8. The conductive paste for the base layer contains a powder or filler of a metal used as a conductive material for the base layer 7. For example, when the metal used as the conductive material for the base layer 7 is Ni, the conductive paste for the base layer contains a powder or filler of Ni. In addition, the conductive paste for the base layer contains, for example, a ceramic component that is the main component of the dielectric layer 4 as a common material. For example, the conductive paste for the underlayer contains oxide ceramic particles (e.g., D50 particle size 0.1 μm to 4 μm) whose main component is barium titanate as a co-material. The conductive paste for the underlayer also contains a binder and a solvent.

Next, as shown in S11 of FIG. 4 and FIG. 5H, the element body 2 coated with the conductive paste for the underlayer in S10 of FIG. 5 is fired to integrate the internal electrode layers 3A, 3B and the dielectric layer 4, and to form the underlayer 7 integrated with the element body 2. Since the conductive paste for the underlayer is not applied to the position where the slit portion 8 is to be formed, the underlayer 7 is not formed at the position where the slit portion 8 is to be formed. The element body 2 and the conductive paste for the underlayer are fired, for example, in a firing furnace at 1000 to 1400° C. for 10 minutes to 2 hours. When a base metal such as Ni or Cu is used for the internal electrode layers 3A, 3B, firing can be performed in a reducing atmosphere in the firing furnace to prevent oxidation of the internal electrode layers 3A, 3B. In addition, in forming the underlayer 7, a reoxidation treatment may be performed in an N2 gas atmosphere at a temperature of 600° C. to 1000° C.

Next, as shown in S12 of Fig. 4 and Fig. 5I, a Cu plating layer 9A, a Ni plating layer 9B and a Sn plating layer 9C are successively formed on the underlayer 7. Here, the element body 2 on which the underlayer 7 has been formed is placed in a barrel together with a plating solution, and an electric current is applied while the barrel is rotated, thereby forming the plating layer 9. At this time, the plating layer 9 is formed in a slit shape around the position where the slit portion 8 is formed so as to cover the underlayer 7.

(Second embodiment)

Figure 6A is a cross-sectional view showing the configuration of a circuit board on which a multilayer ceramic capacitor according to the second embodiment is mounted, and Figure 6B is a cross-sectional view showing the configuration of a circuit board on which a multilayer ceramic capacitor is mounted when the external electrode of Figure 6A does not have a slit portion. Note that Figure 6A shows a schematic diagram of the multilayer ceramic capacitor 1A of Figure 1.

In FIG. 6A, land electrodes 12A and 12B are formed on a circuit board 11. The circuit board 11 may be a printed circuit board or a semiconductor substrate such as Si. The multilayer ceramic capacitor 1A is connected to the land electrodes 12A and 12B via the solder layers 13A and 13B attached to the external electrodes 6A and 6B.

Here, the amount of solder 13A, 13B that wets upward at the slit portion 8 is suppressed, so that the amount of solder on the side surface is reduced. This makes it possible to reduce stress concentrated at the position S where the ridge line LY of the element body 2 and the external electrodes 6A, 6B contact each other, and to suppress the occurrence of cracks. If the ridge line side line of the slit portion 8 is formed so as to move away from the ridge line LY of the adjacent element body 2 as it moves from the opening to the end surface of the element body 2, the solder 13A, 13B is likely to wet upward near the end surface of the side surface, and the solder 13A, 13B is unlikely to stagnate. Furthermore, if the ridge line side line of the slit portion 8 is formed so as to move closer to the ridge line LY of the adjacent element body 2 as it moves from the opening to the end surface of the element body 2, the solder 13A, 13B can be more effectively suppressed from wetting upward at the slit portion 8.

On the other hand, in FIG. 6B, the multilayer ceramic capacitor 1A' has external electrodes 6A', 6B' that do not have slit portions 8. The multilayer ceramic capacitor 1A' is connected to the land electrodes 12A, 12B via the solder layers 13A', 13B' attached to the external electrodes 6A', 6B'.

Here, the solder 13A', 13B' wets and rises onto the side surfaces of the external electrodes 6A', 6B', but the stress from the upper solder 13A', 13B' is concentrated at position S' where the ridge line LY of the element body 2 formed by the underside and side surfaces meets the external electrodes 6A, 6B, making it easy for cracks to occur.

Third Embodiment
FIG. 7 is a flowchart showing another example of the method for manufacturing the multilayer ceramic capacitor in accordance with the third embodiment.
In steps S21 to S28 in FIG. 7, the same steps as steps S1 to S8 in FIG. 4 are carried out to produce an element body 2 from which the binder has been removed.

Next, as shown in S29 of FIG. 7, the element body 2 from which the binder has been removed in S28 of FIG. 7 is fired to integrate the internal electrode layers 3A, 3B and the dielectric layer 4. The element body 2 is fired, for example, in a firing furnace at 1000 to 1350°C for 10 minutes to 2 hours. If base metals such as Ni or Cu are used for the internal electrode layers 3A, 3B, firing can be performed in a reducing atmosphere in the firing furnace to prevent oxidation of the internal electrode layers 3A, 3B.

Next, as shown in S30 of FIG. 7, an inhibitor that inhibits the adhesion of the conductive paste for the base layer is selectively applied to the element body 2. At this time, the inhibitor is selectively applied to the formation position of the slit portion 8 in FIG. 1. The inhibitor is, for example, silicone that is not wetted by the conductive paste for the base layer. The inhibitor can be selectively applied to the element body 2 by screen printing, inkjet printing, gravure printing, or the like.

Next, as shown in S31 of Fig. 7, a conductive paste for the underlayer is applied to both end faces of the element body 2 to which the inhibitor has been applied in S30 of Fig. 7 and the four peripheral faces of each end face, and then dried. The conductive paste for the underlayer contains a powder or filler of a metal used as a conductive material for the underlayer 7. For example, when the metal used as the conductive material for the underlayer 7 is Cu, the conductive paste for the underlayer contains a powder or filler of Cu. The conductive paste for the underlayer also contains a glass sintering aid (e.g., _SiO2 , etc.).

Next, the conductive paste for the base layer that has been applied to the element body 2 is fired so as to avoid the positions where the slits 8 will be formed, forming the base layer 7 that is integrated with the element body 2. The conductive paste for the base layer is fired, for example, in a firing furnace at a temperature of 600 to 900°C for 10 minutes to 2 hours.

Next, as shown in S32 of FIG. 7, plating is performed in a process similar to S12 of FIG. 4.

(Fourth embodiment)
FIG. 8A is a perspective view showing the configuration of the multilayer ceramic capacitor in accordance with the fourth embodiment.
8A, a multilayer ceramic capacitor 1B includes external electrodes 36A and 36B instead of the external electrodes 6A and 6B of the multilayer ceramic capacitor 1A in FIG.

The external electrodes 36A and 36B have slits 38 instead of the slits 8 in FIG. 1. The slits 38 open toward the opposite external electrode at the edge of the external electrode 36A or 36B. The slits 38 can reduce stress applied to the ridge line LY of the element body 2 through the external electrodes 36A and 36B. Except for the slits 38 instead of the slits 8 in FIG. 1, the external electrodes 36A and 36B can be configured in the same manner as the external electrodes 6A and 6B in FIG. 1. The external electrodes 36A and 36B have a base layer 37 formed on the element body 2 and a plating layer 39 laminated on the base layer 37. The plating layer 39 can have a three-layer structure, for example, a Cu plating layer 39A formed on the base layer 37, a Ni plating layer 39B formed on the Cu plating layer 39A, and a Sn plating layer 39C formed on the Ni plating layer 39B.

The slits 38 extend from the ends of the external electrodes 36A and 36B along the ridge line LY of the element body 2. The slits 38 are provided at positions away from the ridge line LY of the element body 2. The slits 38 can be configured in the same manner as the slits 8 of FIG. 1, except that the slits 38 are arranged at different positions and have different numbers from the slits 8 of FIG. 1. For example, the slits 38 can be provided in parallel at equal intervals on one surface of the element body 2. Note that FIG. 8A shows an example in which the slits 38 are provided on each of the external electrodes 36A and 36B on a surface (a pair of side surfaces of the element body 2) having the width direction DW as a normal line. The slits 38 may have a side far from the ridge line that is an oblique arc shape with respect to the ridge line LY of the element body 2 that is closest to the slits 38 , or may be wedge-shaped. The slits 38 may be formed in a straight line parallel to the ridge line LY, and the tip of the slits 38 may be acute-angled. The width, length and distance from the ridge line LY of the slit portions 38 of the external electrodes 36A, 36B can be set similarly to the width, length and distance from the ridge line LY of the slit portions 8 of the external electrodes 6A, 6B in FIG.

Here, by increasing the number of slit portions 38 provided in each external electrode 36A, 36B, the stress applied to the ridge line LY of the element body 2 via the external electrodes 36A, 36B can be more effectively reduced, and the occurrence of cracks in the element body 2 can be suppressed.
Furthermore, since the effect of reducing stress due to the behavior of the solder during mounting, as described in the first and second embodiments, can be obtained in the same way, the occurrence of cracks in the element body 2 can be suppressed.

Fifth Embodiment
FIG. 8B is a perspective view showing the configuration of the multilayer ceramic capacitor in accordance with the fifth embodiment.
8B, a multilayer ceramic capacitor 1C includes external electrodes 46A and 46B instead of the external electrodes 6A and 6B of the multilayer ceramic capacitor 1A in FIG.

The external electrodes 46A and 46B have slits 48 instead of the slits 8 in FIG. 1. The slits 48 open toward the opposite external electrode at the edge of the external electrode 46A or 46B. The slits 48 can divide the stress directed toward the ridge line LY of the element body 2 through the external electrodes 46A and 46B. Each external electrode 46A and 46B can be configured similarly to the external electrodes 6A and 6B in FIG. 1, except that the slits 48 are provided instead of the slits 8 in FIG. 1. Each external electrode 46A and 46B has a base layer 47 formed on the element body 2 and a plating layer 49 laminated on the base layer 47. The plating layer 49 can have a three-layer structure, for example, a Cu plating layer 49A formed on the base layer 47, a Ni plating layer 49B formed on the Cu plating layer 49A, and a Sn plating layer 49C formed on the Ni plating layer 49B.

The slits 48 extend from the ends of the external electrodes 46A and 46B along the ridge line LY of the element body 2. The slits 48 are provided at positions away from the ridge line LY of the element body 2. The slits 48 can be configured in the same manner as the slits 8 of FIG. 1, except that the positions and number of the slits 48 are different from those of the slits 8 of FIG. 1. For example, the slits 48 can be provided not only on the surface (a pair of side surfaces of the element body 2) having the width direction DW as a normal line, but also on the surface (lower and upper surfaces of the element body 2) having the stacking direction DS as a normal line. The slits 48 may have a side far from the ridge line that is an oblique arc shape with respect to the ridge line LY of the element body 2 that is closest to the slits 48 , or may be wedge-shaped. The slits 48 may be formed in a straight line parallel to the ridge line LY, and the tip of the slits 48 may be acute-angled. The width, length and distance from the ridge line LY of the slit portions 48 of the external electrodes 46A, 46B can be set similarly to the width, length and distance from the ridge line LY of the slit portions 8 of the external electrodes 6A, 6B in FIG.

Here, by providing slit portions 48 on a pair of opposite side surfaces, bottom surface and top surface of the element body 2, not only the stress transmitted from each external electrode 46A, 46B to the ridge line LY in the stacking direction DS, but also the stress transmitted from each external electrode 46A, 46B to the ridge line LY in the width direction DW can be reduced, thereby suppressing the occurrence of cracks in the element body 2.

Sixth Embodiment
Fig. 9 is a perspective view showing an example of the configuration of a ceramic electronic component according to a sixth embodiment. In Fig. 9, a chip inductor is taken as an example of the ceramic electronic component.
8, the chip inductor 21 includes an element body 22 and external electrodes 26A, 26B. The element body 22 includes a coil pattern 23, internal electrode layers 23A, 23B, and a magnetic material 24. The magnetic material 24 is also used as a dielectric that insulates the internal electrode layers 23A, 23B. The shape of the element body 22 may be a substantially rectangular parallelepiped shape.

The coil pattern 23 and the internal electrode layers 23A and 23B are covered with a magnetic material 24. However, an end of the internal electrode layer 23A is exposed from the magnetic material 24 at one end surface of the element body 22 and is connected to an external electrode 26A. An end of the internal electrode layer 23B is exposed from the magnetic material 24 at the other end surface of the element body 22 and is connected to an external electrode 26B.

The material of the coil pattern 23 and the internal electrode layers 23A, 23B can be selected from metals such as Cu, Fe, Zn, Al, Sn, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or may be an alloy containing these metals. The magnetic material 24 is, for example, ferrite.

The external electrodes 26A, 26B are located on opposite end faces of the element body 22 and are separated from each other. Each external electrode 26A, 26B is continuous from each end face to the side and top and bottom faces of the element body 22. The external electrodes 26A, 26B have slits 28. The slits 28 open at the edge of the external electrode 26A or 26B toward the opposite external electrode . The slits 28 can divide stress directed toward the ridge line of the element body 22 via the external electrodes 26A, 26B.

The slits 28 extend from the ends of the external electrodes 26A and 26B along the ridge of the element body 2. The slits 28 are provided at positions away from the ridge of the element body 22. In the example of FIG. 9, the slits 28 are provided on the surfaces (pair of side surfaces of the element body 22) normal to the width direction DW, but the slits 28 may also be provided on the surfaces (lower and upper surfaces of the element body 22) normal to the stacking direction DS. The slits 28 may have a side far from the ridge that is an oblique arc with respect to the ridge of the element body 22 closest to the slits 28 , or may be wedge-shaped. The slits 28 may be formed in a straight line parallel to the ridge, or the tip of the slits 28 may be acute-angled. The width, length , and distance from the ridge LY of the slits 28 of the external electrodes 26A and 26B can be set in the same manner as the width, length, and distance from the ridge LY of the slits 8 of the external electrodes 6A and 6B in FIG. 1.

In the above-described embodiment, a multilayer ceramic capacitor and a chip inductor are used as examples of ceramic electronic components, but chip resistors or sensor chips may also be used. In addition, in the above-described embodiment, a ceramic electronic component having two external electrodes is used as an example, but a ceramic electronic component having three or more external electrodes may also be used.

1A Multilayer ceramic capacitor 2 Element body 2A Multilayer body 3A, 3B Internal electrode layer 4 Dielectric layer 5A, 5B Cover layer 6A, 6B External electrode 7 Base layer 8 Slit portion 9, 9A to 9C Plating layer

Claims (18)

An element body having a dielectric and an internal electrode;
a pair of external electrodes connected to the internal electrodes at end surfaces opposite to each other in the length direction of the element body, and formed continuously on the end surfaces of the element body, side surfaces opposite to each other in the width direction, and top and bottom surfaces opposite to each other in the height direction,
a slit portion is formed in a portion of each external electrode covering at least one side surface of the element body, the slit portion opens toward the external electrode on the opposite side and extends from the opening toward an end portion of the external electrode but does not reach the end portion;
A ceramic electronic component characterized in that no slits are formed along the ridge line at the boundary between the upper surface and side surface of the element body, along the ridge line at the boundary between the lower surface and side surface of the element body, and along the portion covering the end surface of the element body in each external electrode. 2. The ceramic electronic component according to claim 1, wherein no slits are formed on the upper surface and the lower surface of the element body in each of the external electrodes . A plurality of the slits are formed in a portion of each external electrode that covers both side surfaces of the element body,
the element body has a plurality of layers of the internal electrodes arranged at intervals within the dielectric,
The uppermost slit portion formed in the portion covering each side surface overlaps with the uppermost internal electrode in the height direction,
3. The ceramic electronic component according to claim 2, wherein the lowermost slit portion formed in the portion covering each side surface overlaps with the lowermost internal electrode in the height direction. 4. The ceramic electronic component according to claim 1, wherein the element body is exposed from the external electrodes at the positions of the slits. 5. The ceramic electronic component according to claim 1, wherein the width of the slit portion is equal to or greater than (T/30) μm and equal to or less than (T/10) μm, where T is a height dimension of the side surface of the external electrode. 6. The ceramic electronic component according to claim 1, wherein, when the length of the external electrode is L, the length of the slit portion is not less than (L/ 5 ) μm and not more than (L/1.5) μm. 7. The ceramic electronic component according to claim 1, wherein the slit portion is spaced apart from the edge line of the element body closest to the slit portion by at least (T/30) μm and not more than (T/ 3 ) μm, where T is a height dimension of the side surface of the external electrode. 8. The ceramic electronic component according to claim 1, wherein the slit portion has a side farther from the ridge line of the element body that is closest to the slit portion and is formed in an oblique arc shape with respect to the ridge line. 9. The ceramic electronic component according to claim 1, wherein the slits are provided in parallel at equal intervals on each side surface of the element body. Each of the external electrodes is
A base layer including a metal;
10. The ceramic electronic component according to claim 1, further comprising a plating layer formed on the underlayer. The ceramic electronic component according to claim 10 , wherein the underlayer comprises a common material mixed with the metal. The ceramic electronic component according to claim 11 , wherein the common material contains the dielectric material contained in the element body as a main component. 13. The ceramic electronic component according to claim 10 , wherein the underlayer contains Ni as a main component. 13. The ceramic electronic component according to claim 10 , wherein the underlayer is mainly composed of Cu. 15. The ceramic electronic component according to claim 10 , wherein the plating layer covers the base layer around the slit portion. The internal electrodes are
A first internal electrode layer;
a second internal electrode layer laminated on the first internal electrode layer via a dielectric layer including the dielectric,
The external electrode is
a first external electrode connected to the first internal electrode layer;
16. The ceramic electronic component according to claim 1, further comprising a second external electrode provided separately from the first external electrode and connected to the second internal electrode layer. A circuit board on which the ceramic electronic component according to any one of claims 1 to 16 is mounted,
The ceramic electronic components are connected to the external electrodes via solder layers attached to the external electrodes . A method for producing a ceramic electronic component according to any one of claims 1 to 16, comprising the steps of:
forming an element body having the dielectric and the internal electrodes, the element body having two end faces, two side faces, a top face, and a bottom face, the internal electrodes being extended to the end faces;
applying an inhibitor that inhibits adhesion of a base material of a base layer of an external electrode to a portion where the slit portion is to be formed so as to extend in a slit shape;
applying the base material to the two end faces , the two side faces, the top face, and a portion of the bottom face of the element ;
Firing the base material to form a base layer having the slit portion;
forming a plating layer on the underlayer.

Images