JP7654419B2 - Polishing Pads - Google Patents

Description

The present invention relates to a polishing pad and a method for manufacturing a conductive semiconductor substrate.

Various methods have been disclosed for polishing the surfaces of conductive semiconductor substrates such as gallium nitride (GaN) substrates and silicon carbide (SiC) substrates. For example, Patent Document 1 discloses a catalyst-referred etching (CARE) method that uses a catalyst such as platinum to promote an etching reaction. Patent Document 2 discloses a chemical mechanical polishing (CMP) method that uses an oxidizing polishing liquid.

JP 2006-114632 A International Publication No. 2015/152021

The object of the present invention is to provide a technology that can perform polishing while minimizing damage to the surface of a conductive semiconductor substrate.

According to one aspect of the present invention,
A polishing pad used for polishing a surface of a conductive semiconductor substrate, comprising:
There is provided a polishing pad, the polishing surface which comes into contact with the surface to be polished being impregnated with at least a solid polymer electrolyte.

According to another aspect of the present invention,
A step of preparing a polishing pad, the polishing surface of which contacts the surface to be polished of the conductive semiconductor substrate being impregnated with at least a solid polymer electrolyte;
a step of bringing the polishing surface of the polishing pad into contact with the surface to be polished of the conductive semiconductor substrate under pressure while water molecules are in contact with the solid polymer electrolyte, and polishing the surface to be polished by moving the polishing pad and the conductive semiconductor substrate relative to each other while applying a voltage between the polishing pad and the conductive semiconductor substrate;
A method for manufacturing a conductive semiconductor substrate is provided, comprising:

According to the present invention, polishing can be performed while suppressing damage to the surface of a conductive semiconductor substrate.

FIG. 1 is a plan view showing a schematic example of a polishing surface 13 of a polishing pad 10 according to a first embodiment of the present invention. Fig. 2(a) is an enlarged schematic view of the polishing surface 13 when a nonwoven fabric is used as the substrate of the polishing pad 10 of the first embodiment of the present invention. Fig. 2(b) is an enlarged schematic view of the polishing surface 13 when a substrate having an open cell structure is used for the polishing pad 10 of the first embodiment of the present invention. FIG. 3 is a plan view showing a schematic diagram of another example of the polishing surface 13 of the polishing pad 10 according to the first embodiment of the present invention. FIG. 4 is an enlarged schematic view of the polishing surface 13 of the polishing pad 10 according to the first embodiment of the present invention, in which abrasive grains 32 are dispersed on the polishing surface 13. As shown in FIG. FIG. 5 is a schematic diagram of a polishing apparatus used in the first embodiment of the present invention. FIG. 6 is a flow chart showing an example of a method for manufacturing the conductive semiconductor substrate according to the first embodiment of the present invention. Fig. 7(a) is a cross-sectional view showing the polished surface 14 of the GaN substrate 20 in the preparation step S100 of the first embodiment of the present invention. Fig. 7(b) is a cross-sectional view showing the polished surface 14 of the GaN substrate 20 and the polishing surface 13 of the polishing pad 10 in the oxidation step S111 of the first embodiment of the present invention. Fig. 7(c) is a cross-sectional view showing the polished surface 14 of the GaN substrate 20 and the polishing surface 13 of the polishing pad 10 in the removal step S112 of the first embodiment of the present invention. FIG. 8 is a graph showing a schematic diagram of the current flowing through the polishing pad 10 in the polishing step S110 according to the first embodiment of the present invention. FIG. 9 is a cross-sectional photograph of the vicinity of the polished surface 14 of the GaN substrate 20 in the polishing step S110 of the first embodiment of the present invention. 10A and 10B are plan views each showing a schematic diagram of a polishing surface 13 of a polishing pad 40 according to a second embodiment of the present invention. FIG. 11 is a graph showing a schematic diagram of a current flowing through the polishing pad 40 in the polishing step S110 of the second embodiment of the present invention. FIG. 12 is a graph showing the amount of polishing according to the first embodiment of the present invention. FIG. 13 is a diagram showing the arithmetic mean roughness Ra before and after polishing according to the first embodiment of the present invention.

<Insights gained by the inventors>
First, the findings of the inventors will be described.

Various methods have been disclosed for polishing the surfaces of conductive semiconductor substrates such as GaN substrates and SiC substrates. However, because Group III nitrides such as GaN are chemically and mechanically more stable than silicon (Si), which is widely used in semiconductor devices, it is very difficult to polish the surface of a GaN substrate at a practical polishing rate (e.g., 100 nm/h or more).

The modified Mohs hardness of GaN is 13, making it the second hardest after diamond. This means that when mechanically polishing the surface of a GaN substrate, it is necessary to use hard abrasives such as diamond abrasives, which may cause damage to the substrate surface. In addition, the use of diamond abrasives also poses the problem of high polishing costs.

In addition, the surface of a GaN substrate, especially the +c plane, is chemically very stable, so to chemically modify it using a chemical solution, it is necessary to use a strong oxidizing agent such as potassium permanganate. Therefore, when polishing the surface of a GaN substrate using CMP, there are problems such as the components that make up the polishing device being corroded by the oxidizing agent and the high polishing costs.

The inventors of the present application have conducted extensive research into the above-mentioned phenomenon. As a result, they have discovered that by using a polishing pad whose polishing surface is impregnated with at least a solid polymer electrolyte, it is possible to perform polishing while suppressing damage to the surface of a conductive semiconductor substrate. In the embodiment of the present invention shown below, there is also the advantage that polishing can be performed in a neutral region, since there is no need to use a special oxidizing agent or the like.

[Details of the embodiment of the present invention]
Next, an embodiment of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

First Embodiment of the Present Invention
(1) Configuration of the Polishing Pad 10 First, the configuration of the polishing pad 10 of this embodiment will be described. In this embodiment, the case where the polishing pad 10 is used to polish the surface (hereinafter, also referred to as the polished surface 14) of a GaN substrate 20 serving as a conductive semiconductor substrate will be described.

The polishing pad 10 is, for example, disk-shaped and is used to polish the polished surface 14 of the GaN substrate 20 as a conductive semiconductor substrate. The base material of the polishing pad 10 may be nonwoven fabric, urethane resin, epoxy resin, suede, or the like. From the viewpoint of ensuring the sliding property with respect to the polished surface 14, it is preferable to use nonwoven fabric as the base material of the polishing pad 10. From the viewpoint of ensuring the conductivity in the thickness direction of the polishing pad 10, it is preferable to use nonwoven fabric or a base material having an open cell structure as the base material of the polishing pad 10. In this specification, the surface of the main surface of the polishing pad 10 that contacts the polished surface 14 of the GaN substrate 20 is referred to as the "polishing surface 13", and the surface opposite to the polishing surface 13 is referred to as the "rear surface".

The diameter of the polishing pad 10 is preferably, for example, 200 mm or more and 2000 mm or less. This allows the polishing surface 14 of a GaN substrate 20 with a large diameter (for example, 4 inches or more) to be polished. The thickness of the polishing pad 10 is preferably, for example, 0.5 mm or more and 10 mm or less. If the thickness of the polishing pad 10 is less than 0.5 mm, the durability of the polishing pad 10 may decrease. In contrast, by making the thickness of the polishing pad 10 0.5 mm or more, the durability of the polishing pad 10 can be improved. On the other hand, if the thickness of the polishing pad 10 exceeds 10 mm, the conductivity of the polishing pad 10 in the thickness direction may decrease. In contrast, by making the thickness of the polishing pad 10 10 mm or less, the conductivity of the polishing pad 10 in the thickness direction can be improved.

FIG. 1 is a plan view showing an example of the polishing surface 13 of the polishing pad 10 of this embodiment. The polishing pad 10 of this embodiment has at least a solid polymer electrolyte (Solid Polymer Electrolyte, SPE) impregnated on the polishing surface 13. In this embodiment, the solid polymer electrolyte is attached to the substrate surface of the polishing pad 10 (or at least a part of the substrate surface is coated) by impregnation (i.e., by impregnating the substrate of the polishing pad 10 with a liquid material containing the solid polymer electrolyte, evaporating the liquid, and leaving the solid polymer electrolyte in the polishing pad 10). In this specification, the solid polymer electrolyte being attached to the substrate surface of the polishing pad 10 (or at least a part of the substrate surface is coated) is referred to as the polishing pad 10 being impregnated with the solid polymer electrolyte.

As the solid polymer electrolyte, for example, Nafion (registered trademark, chemical formula: C ₇ HF ₁₃ O ₅ S.C ₂ F ₄ ), which is a polymer having a fluorocarbon skeleton and a side chain of a fluorocarbon ether having a sulfonic acid group at the end, can be used. That is, the polishing surface 13 is impregnated with Nafion 15 as a solid polymer electrolyte. Note that Nafion 15 is omitted in FIG. 1. Nafion 15 can generate OH radicals from water by applying a voltage, for example. By generating OH radicals, the polished surface 14 of the GaN substrate 20 can be oxidized. Gallium oxide (Ga ₂ O ₃ ) generated by oxidizing the GaN 30 constituting the polished surface 14 is softer than GaN 30. Therefore, gallium oxide generated by oxidizing the polished surface 14 of the GaN substrate 20 can be removed more easily than GaN 30. In this specification, to avoid complexity, oxidizing the GaN 30 constituting the polished surface 14 of the GaN substrate 20 is also referred to as oxidizing the polished surface 14 of the GaN substrate 20 .

It is preferable that Nafion 15 is also impregnated in the thickness direction of the polishing pad 10. Since Nafion 15 has ionic conductivity, this can ensure ionic conductivity in the thickness direction of the polishing pad 10. In addition, since Nafion 15 exhibits electrical conductivity in the presence of water, it is preferable that electrical conduction is established between the polishing surface 13 and the back surface at least when water molecules are in contact with Nafion 15.

In the polishing pad 10, Nafion 15 is preferably impregnated with a density of, for example, 3 mg/cm ³ or more and 20 mg/cm ³ or less. If the density of Nafion 15 is less than 3 mg/cm ³ , it is difficult to obtain the effect of oxidizing the polished surface 14. On the other hand, by making the density of Nafion 15 3 mg/cm ³ or more, it becomes easier to oxidize the polished surface 14. On the other hand, if the density of Nafion 15 exceeds 20 mg/cm ³ , the flexibility of the polishing pad 10 decreases, so that the polished surface 14 may be scratched during polishing. On the other hand, by making the density of Nafion 15 20 mg/cm ³ or less, the flexibility of the polishing pad 10 is maintained, so that the possibility of scratching the polished surface 14 during polishing can be reduced. In this specification, the density of Nafion 15 is the value obtained by dividing the mass of Nafion 15 contained in the polishing pad 10 by the apparent volume of the polishing pad 10 (volume including internal voids).

2(a) is an enlarged schematic diagram of the polishing surface 13 when nonwoven fabric is used as the base material of the polishing pad 10. As shown in FIG. 2(a), Nafion 15 is preferably attached to the surface of the fibers 16 of the nonwoven fabric (or at least a part of the surface is coated). In general, a Nafion film is not suitable as a base material of the polishing pad 10 because it has poor sliding properties against the GaN substrate 20. In contrast, in this embodiment, Nafion 15 is attached to the surface of the fibers 16 of the nonwoven fabric, so that the sliding properties against the polished surface 14 can be improved compared to the case where a Nafion film is used for the polishing pad 10. In addition, in order to confirm that Nafion 15 is attached to the surface of the fibers 16, for example, the fibers 16 are cut and the vicinity of the cross section of the fibers 16 is measured using energy dispersive X-ray analysis (EDX) to check whether fluorine (F) is detected.

It is preferable that Nafion 15 exists so as to connect multiple fibers 16. This allows the Nafion 15 to be connected in the polishing pad 10, thereby improving the conductivity of the polishing pad 10. Also, FIG. 2(b) is an enlarged schematic diagram of the polishing surface 13 when a substrate having an open-cell structure is used for the polishing pad 10. In this case, too, as shown in FIG. 2(b), the Nafion 15 covering the inside of the bubbles 17 is connected, thereby improving the conductivity of the polishing pad 10.

Figure 3 is a plan view showing a schematic diagram of another example of the polishing surface 13 of the polishing pad 10 of this embodiment. As shown in Figure 3, abrasive grains 32 may be dispersed on the polishing surface 13. This makes it possible to remove oxides 31 (e.g., gallium oxide) that are generated when GaN 30 constituting the polished surface 14 of the GaN substrate 20 is oxidized by OH radicals. In this case, it is also preferable that the abrasive grains 32 are impregnated in the thickness direction of the polishing pad 10. This makes it possible to maintain the polishing rate even if the polishing surface 13 is worn during polishing.

The abrasive grains 32 are preferably lower in hardness than the GaN 30 constituting the polished surface 14 of the GaN substrate 20. Examples of such abrasive grains 32 include cerium oxide (CeO ₂ ), silicon oxide (SiO ₂ ), zirconium oxide (ZrO ₂ ), and the like. Normally, in mechanical polishing, abrasive grains harder than the object to be polished are used, but in this embodiment, since only the oxide 31 is removed, the polished surface 14 of the GaN substrate 20 can be polished even if abrasive grains 32 softer than the GaN 30 are used. As a result, it is possible to perform polishing while suppressing damage to the polished surface 14 of the GaN substrate 20. Note that, although there are Vickers hardness, Knoop hardness, and the like as a scale for expressing hardness, it is important that the scale for hardness can simply express the resistance to scratches. Therefore, it is preferable to use Mohs hardness or modified Mohs hardness as a scale for hardness.

When cerium oxide having an average particle size (D50) of about 1 μm (for example, 0.5 μm to 2 μm) as measured by a laser diffraction/scattering method is used as the abrasive grains 32, the abrasive grains 32 are preferably dispersed in the polishing pad 10 at a density of, for example, 0.1 g/cm ³ to 0.5 g/cm ^3. If the density of the abrasive grains 32 is less than 0.1 g/cm ³ , it is difficult to obtain the effect of removing the oxides 31. In contrast, by setting the density of the abrasive grains 32 to 0.1 mg/cm ³ or more, it becomes easier to remove the oxides 31. On the other hand, when an attempt is made to manufacture a polishing pad 10 having a density of the abrasive grains 32 exceeding 0.5 g/cm ³ , when the polishing pad 10 is impregnated with a dispersion of the abrasive grains 32, the viscosity of the dispersion becomes too large, so that the polishing pad 10 may not be impregnated with the dispersion. In contrast, by setting the density of the abrasive grains 32 to 0.5 g/ ^cm3 or less, it becomes easier to impregnate the polishing pad 10 with a dispersion of the abrasive grains 32. In this specification, the density of the abrasive grains 32 is a value obtained by dividing the mass of the abrasive grains 32 contained in the polishing pad 10 by the apparent volume of the polishing pad 10 (volume including internal voids).

Figure 4 is an enlarged schematic diagram of the polishing surface 13 when abrasive grains 32 are dispersed on the polishing surface 13. As shown in Figure 4, it is preferable that Nafion 15 is also attached to the surface of the abrasive grains 32. This can improve the electrical conductivity of the polishing pad 10.

If the abrasive grains 32 are not dispersed on the polishing surface 13, for example, in the polishing step S110 described below, polishing can be performed while supplying a slurry containing the abrasive grains 32 to the polishing surface 13. In this case, the risk of a decrease in the polishing rate due to the abrasive grains 32 falling off the polishing pad 10 can be reduced. From the viewpoint of reducing the consumption of the abrasive grains 32, it is preferable that the abrasive grains 32 are dispersed on the polishing surface 13 in advance.

It is preferable that the polishing pad 10 has water retention properties. This allows OH radicals to be efficiently generated from water. In addition, since Nafion 15 exhibits electrical conductivity in the presence of water, the electrical conductivity of the polishing pad 10 can be improved. Specifically, for example, the water retention properties of the polishing pad 10 can be improved by dispersing a small amount of water-absorbent polymer in the polishing pad 10.

The polishing surface 13 of the polishing pad 10 preferably has sliding properties with respect to the polished surface 14 of the GaN substrate 20, for example. This makes it easier to move the polishing pad 10 and the GaN substrate 20 relative to each other while keeping them in contact.

The back surface of the polishing pad 10 preferably has a conductive adhesive. Alternatively, a conductive aluminum tape or the like may be used instead of the conductive adhesive. This ensures conductivity between the platen 21 and the polishing pad 10, for example, when the polishing pad 10 is attached to the platen 21 described below.

(2) Manufacturing Method of Polishing Pad 10 Next, a manufacturing method of the polishing pad 10 of this embodiment will be described. In this embodiment, a case will be described in which a nonwoven fabric is used as the base material of the polishing pad 10, Nafion 15 as a solid polymer electrolyte is impregnated into the polishing surface 13, and cerium oxide is dispersed as the abrasive grains 32. Note that, since a nonwoven fabric is used as the base material of the polishing pad 10 in this embodiment, Nafion 15 can be easily impregnated in the thickness direction of the polishing pad 10, and the abrasive grains 32 can be easily dispersed.

First, the nonwoven fabric is impregnated with a cerium oxide dispersion (e.g., 60% by weight, average particle size (D50) 1 μm). It is preferable to add a small amount of sodium alginate (e.g., 0.25% by weight) to the cerium oxide dispersion. This increases the viscosity of the cerium oxide dispersion, making it easier to disperse cerium oxide in the polishing pad 10 (on the polishing surface 13 and in the thickness direction of the polishing pad 10).

After the nonwoven fabric is impregnated with the cerium oxide dispersion, it is preferable to place the nonwoven fabric in an aqueous calcium chloride solution (e.g., 20% by weight). This causes the sodium alginate and calcium chloride to react and gel, making it easier to disperse the cerium oxide in the polishing pad 10.

Rare earth oxides such as praseodymium oxide, neodymium oxide, and lanthanum oxide may also be added to the cerium oxide dispersion. This makes it easier to remove the oxides 31 with the abrasive grains 32.

After the nonwoven fabric is impregnated with the cerium oxide dispersion, excess cerium oxide dispersion is removed, for example, using a squeezer, and then the fabric is dried for 30 minutes at 70°C using a constant temperature dryer. This allows cerium oxide to be dispersed on the polishing surface 13 as abrasive grains 32.

Next, the nonwoven fabric is impregnated with a Nafion dispersion (5 to 20% by weight, for example, it is preferable to use any of the following products manufactured by Sigma-Aldrich: product numbers 274704, 527084, 510211, 527106, 663492, and 527122).

After the nonwoven fabric is impregnated with the Nafion dispersion liquid, excess Nafion dispersion liquid is removed, for example, using a squeezer or the like, and then the nonwoven fabric impregnated with the Nafion dispersion liquid is dried for 30 minutes at 70°C using a constant temperature dryer or the like. In this way, the polishing surface 13 can be impregnated with Nafion 15. Note that the impregnation with the Nafion dispersion liquid and drying may be repeated multiple times.

By using a Nafion dispersion liquid when impregnating the nonwoven fabric with Nafion 15, the sliding properties of the polishing pad 10 can be improved compared to when a Nafion film is used. As a result, it becomes easier to move the polishing pad 10 and the GaN substrate 20 relative to each other while in contact with each other, and it becomes possible to efficiently polish the polished surface 14 of the GaN substrate 20.

By the above steps, a polishing pad 10 can be obtained in which the polishing surface 13 is impregnated with Nafion 15 and has abrasive grains 32 dispersed therein. It is preferable to first disperse the abrasive grains 32 in the nonwoven fabric and then impregnate the fabric with Nafion 15. In this case, Nafion 15 can easily adhere to the surface of the abrasive grains 32, improving the electrical conductivity of the polishing pad 10.

(3) Configuration of the Polishing Apparatus Next, the configuration of the polishing apparatus used in this embodiment will be described. Fig. 5 is a schematic diagram of the polishing apparatus used in this embodiment. As shown in Fig. 5, the polishing apparatus of this embodiment has, for example, a surface plate 21, a substrate holder 22, a power source 23, and a pure water supply unit 24. Note that in Fig. 5, Nafion 15 impregnated in the polishing surface 13 and abrasive grains 32 dispersed on the polishing surface 13 are omitted.

The surface plate 21 is, for example, a stainless steel disk, and is configured so that the polishing pad 10 is attached to the upper surface. The surface plate 21 is configured to rotate at a predetermined rotation speed in the horizontal direction with the polishing pad 10 attached to the upper surface. Note that the surface plate 21 is not limited to being made of stainless steel, and may be any material that is conductive and rigid.

The substrate holder 22 is made of, for example, stainless steel, and is configured to attach the GaN substrate 20 to its bottom surface. The GaN substrate 20 is preferably attached to the substrate holder 22 using, for example, a conductive adhesive, with the polished surface 14 exposed. In other words, it is preferable to electrically connect the back surface of the GaN substrate 20 (the surface opposite the polished surface 14) to the substrate holder 22. This allows the polished surface 14 of the GaN substrate 20 to be exposed in its entirety, and the entire polished surface 14 can be polished.

The substrate holder 22 is configured to rotate at a predetermined rotation speed in the horizontal direction with the GaN substrate 20 attached to its bottom surface. The substrate holder 22 is also configured to press the polished surface 14 of the GaN substrate 20 against the polishing surface 13 of the polishing pad 10 with a predetermined pressure. The substrate holder 22 is not limited to being made of stainless steel, and may be made of any material that is conductive and rigid.

The power supply 23 is, for example, electrically connected to the platen 21 and the substrate holder 22, and is configured to apply a predetermined voltage to the polishing pad 10. The power supply 23 is configured so that the substrate holder 22 side (GaN substrate 20 side) serves as the anode. When the power supply 23 applies a voltage to the polishing pad 10, OH radicals can be generated from water on the surface of the Nafion 15 impregnated in the polishing surface 13. The power supply 23 can be, for example, a combination of a commercially available potentiostat and a function generator.

The pure water supply unit 24 is configured to supply pure water to the polishing surface 13 of the polishing pad 10, for example, in the form of a spray. By supplying pure water to the polishing surface 13 by the pure water supply unit 24, the electrical conductivity of the polishing pad 10 can be improved. In addition, OH radicals can be generated from water on the surface of the Nafion 15. Furthermore, the oxide 31 removed from the polished surface 14 of the GaN substrate 20 can be discharged from the polishing surface 13. In this specification, pure water means, for example, water having a resistivity of 0.1 MΩ·cm or more and 18 MΩ·cm or less.

(4) Manufacturing method of conductive semiconductor substrate Next, a manufacturing method of a conductive semiconductor substrate using the polishing pad 10 of this embodiment will be described. FIG. 6 is a flow chart showing an example of a manufacturing method of a conductive semiconductor substrate of this embodiment. As shown in FIG. 6, the manufacturing method of a conductive semiconductor substrate of this embodiment has, for example, a preparation step S100, an oxidation step S111, and a removal step S112. The oxidation step S111 and the removal step S112 are also referred to as a polishing step S110. In this embodiment, a case will be described in which the polished surface 14 of a GaN substrate 20 is polished using a polishing pad 10 to manufacture a GaN substrate 20 having a polished surface.

(Preparation step S100)
In the preparation step S100, a polishing pad 10 and a GaN substrate 20 as a conductive semiconductor substrate are prepared. The GaN substrate 20 is, for example, a disk-shaped free-standing substrate made of a single crystal of GaN. The diameter of the GaN substrate 20 is, for example, 2 inches to 6 inches. The thickness of the GaN substrate 20 is, for example, 0.25 mm or more. Such a GaN substrate 20 is obtained by slicing a GaN crystal epitaxially grown by, for example, HVPE (hydride vapor phase epitaxy). The polished surface 14 of the GaN substrate 20 is, for example, a +c plane and is an as-sliced surface, so that the polished surface 14 needs to be polished in order to use the GaN substrate 20 in the manufacture of semiconductor devices, etc. In this specification, the "+c plane" includes a plane that is slightly inclined (for example, at an off angle of 5° or less) from the (0001) plane of the GaN crystal.

Figure 7(a) is a cross-sectional view showing the polished surface 14 of the GaN substrate 20 in the preparation step S100 of this embodiment. Figure 7(b) is a cross-sectional view showing the polished surface 14 of the GaN substrate 20 and the polishing surface 13 of the polishing pad 10 in the oxidation step S111 of this embodiment. Figure 7(c) is a cross-sectional view showing the polished surface 14 of the GaN substrate 20 and the polishing surface 13 of the polishing pad 10 in the removal step S112 of this embodiment. As shown in Figure 7(a), the polished surface 14 of the GaN substrate 20 in the preparation step S100 is made of GaN 30, and has many irregularities because it is an as-sliced surface.

The carrier concentration of the polished surface 14 of the GaN substrate 20 is preferably, for example, 1.0×10 ¹⁶ cm ⁻³ or more, which ensures electrical conductivity in the thickness direction of the GaN substrate 20. There is no particular upper limit to the carrier concentration of the polished surface 14 of the GaN substrate 20, but an example of this is 1.0×10 ²⁰ cm ⁻³ or less.

(Polishing step S110)
In the polishing step S110, for example, the polishing pad 10 and the above-mentioned polishing apparatus are used to polish the polished surface 14 of the GaN substrate 20. First, the polishing pad 10 is attached to a platen 21 so that the polishing surface 13 is exposed, and the GaN substrate 20 is attached to a substrate holder 22 so that the polished surface 14 is exposed.

In the polishing step S110, with water molecules in contact with the Nafion 15, the polishing surface 13 of the polishing pad 10 is brought into contact with the polished surface 14 of the GaN substrate 20 under pressure, and the polishing pad 10 and the GaN substrate 20 are moved relative to each other while a voltage is applied between them, thereby polishing the polished surface 14.

In the polishing step S110, the polished surface 14 of the GaN substrate 20 is pressed against the polishing surface 13 of the polishing pad 10 with a predetermined pressure. The pressure (polishing pressure) at which the polished surface 14 of the GaN substrate 20 is pressed against the polishing surface 13 is preferably, for example, 10 kPa or more and 100 kPa or less. It is also preferable to press the polished surface 14 of the GaN substrate 20 so that pressure is applied uniformly to the polished surface 14 of the GaN substrate 20. This makes it possible to polish the polished surface 14 of the GaN substrate 20 uniformly across its surface.

In the polishing step S110, the polished surface 14 of the GaN substrate 20 is pressed against the polishing surface 13 of the polishing pad 10 with a predetermined pressure, and a predetermined voltage is applied to the polishing pad 10 using the power source 23 to oxidize the polished surface 14. The power source 23 is electrically connected to the substrate holder 22, the GaN substrate 20, the polishing pad 10, and the platen 21, for example, in that order from the anode side.

The voltage applied by the power supply 23 is preferably 20V or more and 300V or less. If the voltage applied by the power supply 23 is less than 20V, it is difficult to generate OH radicals from water on the surface of the Nafion 15 impregnated in the polishing surface 13. In contrast, by setting the voltage applied by the power supply 23 to 20V or more, it becomes easier to generate OH radicals. On the other hand, if the voltage applied by the power supply 23 exceeds 300V, the polishing surface 14 of the GaN substrate 20 may become rough. In contrast, by setting the voltage applied by the power supply 23 to 300V or less, the polishing surface 14 of the GaN substrate 20 can be polished smoothly and at an appropriate polishing rate.

The polishing rate varies depending on the voltage V applied by the power source 23, and the polishing rate may be maximum (local maximum) at a certain voltage Vm (for example, when polishing a SiC substrate as a conductive semiconductor substrate). In this case, it is preferable to control the voltage V applied by the power source 23 so that it does not exceed the voltage Vm at which the polishing rate is maximum (local maximum). If the voltage V exceeds the voltage Vm, the removal of the oxide 31 becomes rate-limiting, and the polished surface 14 may become rough. In contrast, by controlling the voltage V so that it does not exceed the voltage Vm, the polished surface 14 can be polished smoothly and at an appropriate polishing rate.

In the polishing step S110, the surface plate 21 and the substrate holder 22 are rotated at a predetermined rotation speed in the horizontal direction while a predetermined voltage is applied to the polishing pad 10. The rotation speed of the surface plate 21 is preferably, for example, 10 rpm or more and 300 rpm or less. The rotation speed of the substrate holder 22 is preferably, for example, 10 rpm or more and 300 rpm or less. The rotation speeds of the surface plate 21 and the substrate holder 22 may be the same or different. The rotation directions of the surface plate 21 and the substrate holder 22 may be the same or different.

In the polishing step S110, for example, it is preferable to supply pure water to the polishing surface 13 using the pure water supply unit 24. This can improve the conductivity of the polishing pad 10. In addition, it is preferable that the amount of water supplied by the pure water supply unit 24 is, for example, 0.1 mL/min or more and 5 mL/min or less. If the amount of water supplied is less than 0.1 mL/min, the conductivity of the polishing pad 10 may be insufficient. In contrast, by setting the amount of water supplied to 0.1 mL/min or more, the conductivity of the polishing pad 10 can be sufficiently improved. On the other hand, if the amount of water supplied exceeds 5 mL/min or less, the Nafion 15 or abrasive grains 32 may be washed away by the pure water. In contrast, by setting the amount of water supplied to 5 mL/min or less, the risk of the Nafion 15 or abrasive grains 32 being washed away by the pure water can be reduced.

In this embodiment, since only pure water is supplied without using an oxidizing agent such as potassium permanganate, polishing can be performed in a neutral region. In this specification, "polishing in a neutral region" means, for example, performing the polishing step S110 while maintaining the pH of the polishing surface 13 of the polishing pad 10 in a state of 6.0 to 8.0. The pH of the polishing surface 13 can be measured, for example, using a pH meter. If necessary, the pH of the polishing surface 13 may be adjusted to be outside the above range.

In the polishing step S110, it is preferable to supply pure water to the polishing surface 13 so as to maintain the humidity of the polishing surface 13 within a certain range (e.g., 60% or more and 100% or less). That is, since the value of the current flowing through the polishing pad 10 differs depending on the humidity of the polishing surface 13, it is preferable to monitor the value of the current flowing through the polishing pad 10 using, for example, a digital multimeter, and control the humidity of the polishing surface 13 so that the current value is constant. This makes it possible to stabilize the polishing rate.

When using a polishing pad 10 on which abrasive grains 32 are not dispersed, it is preferable to supply a slurry containing abrasive grains 32 to the polishing surface 13 in the polishing step S110. This makes it possible to polish the surface 14 to be polished in the same way as when using a polishing pad 10 on which abrasive grains 32 are dispersed in advance. In addition, the risk of a decrease in the polishing rate due to the abrasive grains 32 falling off the polishing pad 10 can be reduced.

Figure 8 is a graph showing a schematic diagram of the current flowing through the polishing pad 10 in the polishing step S110 of this embodiment. In this embodiment, it is preferable to apply a pulse voltage to the polishing pad 10 using the power source 23, for example, to cause a current to flow intermittently through the polishing pad 10. As shown in Figure 8, the oxidation step S111 is performed while a current is flowing through the polishing pad 10. On the other hand, the removal step S112 is performed continuously regardless of whether a current is flowing through the polishing pad 10. That is, in this embodiment, the oxidation step S111 and the removal step S112 are performed simultaneously while a current is flowing through the polishing pad 10.

In this embodiment, the oxidation step S111 and the removal step S112 are performed simultaneously while a current is flowing through the polishing pad 10. This allows the oxides 31 generated on the polished surface 14 of the GaN substrate 20 to be quickly removed by the abrasive grains 32, thereby improving the polishing rate. In addition, the removal step S112 is performed while no current is flowing through the polishing pad 10. At that time, the removed oxides 31 can be discharged from the polishing surface 13 by, for example, the pure water supplied to the polishing surface 13 by the pure water supply unit 24.

In this embodiment, while the polishing pad 10 and the GaN substrate 20 are in contact and moved relative to each other, the entire surface of the polished surface 14 of the GaN substrate 20 is always in contact with the polishing surface 13 impregnated with Nafion 15. This allows the polished surface 14 of the GaN substrate 20 to be oxidized uniformly within the surface. As a result, it becomes possible to polish the polished surface 14 of the GaN substrate 20 uniformly within the surface.

As shown in FIG. 8, if the pulse period is T and the time during which the current flows in one period is t, the duty ratio D is defined as D=t/T. It is preferable that the duty ratio D is, for example, 1% or more and 100% or less. In this embodiment, by controlling the duty ratio D, the rate at which the polished surface 14 is oxidized can be adjusted, and therefore the polishing rate can be controlled.

In the polishing step S110, it is preferable that all of the oxide 31 generated during one cycle of the oxidation step S111 is removed before the next oxidation step S111 is performed. In other words, it is preferable to control the current flowing through the polishing pad 10 so that the amount of oxide 31 generated during one cycle of the oxidation step S111 does not exceed the amount of oxide 31 that can be removed during the period T. This allows the polished surface 14 to be polished smoothly and at an appropriate polishing rate.

(Oxidation step S111)
In the oxidation step S111, OH radicals are generated from water on the surface of Nafion 15, and the OH radicals oxidize GaN 30 constituting polished surface 14 of GaN substrate 20. When a current flows through polishing pad 10, OH radicals are generated from water on the surface of Nafion 15 by a reaction as shown in the following reaction formula (1).

H ₂ O → OH・+H ⁺ +e ^−・・・(1)

When OH radicals are generated, GaN 30 is oxidized on the polished surface 14 of the GaN substrate 20 by the reaction shown in the following reaction formula (2), and an oxide 31 (here, gallium oxide) is generated.

2GaN+6OH・→Ga ₂ O ₃ +N ₂ +3H ₂ O...(2)

As shown in FIG. 7(b), in the oxidation step S111, the convex portions of the GaN 30 are preferentially oxidized to generate oxides 31. In other words, the portions of the polished surface 14 of the GaN substrate 20 that are in contact with (or close to) the polished surface 13 are preferentially oxidized. This makes it possible to efficiently planarize the polished surface 14 of the GaN substrate 20 by removing the oxides 31 generated on the convex portions in the removal step S112 described below.

OH radicals usually have a short life span and cannot exist for a long time. However, in the polishing pad 10 of this embodiment, OH radicals are generated on the polishing surface 13 that is in contact with the polished surface 14 of the GaN substrate 20, so that the generation of OH radicals and the oxidation of the polished surface 14 of the GaN substrate 20 can be performed simultaneously. Therefore, the polished surface 14 of the GaN substrate 20 can be oxidized before the OH radicals disappear.

In addition, OH radicals may decompose the side chains of Nafion 15, degrading Nafion 15. However, in the polishing pad 10 of this embodiment, the generated OH radicals are used to oxidize the polished surface 14 of the GaN substrate 20, so degradation of Nafion 15 due to OH radicals can be suppressed.

(Removal step S112)
In the removal step S112, the oxide 31 generated by the oxidation of the GaN 30 by the OH radicals is removed. Specifically, for example, as shown in FIG. 7(c), the oxide 31 is mechanically removed by the abrasive grains 32 dispersed on the polishing surface 13. Since the abrasive grains 32 have a lower hardness than the GaN 30, only the oxide 31 can be removed without scratching the GaN 30. As a result, it is possible to polish the polishing surface 14 of the GaN substrate 20 while suppressing damage to the polishing surface 14 of the GaN substrate 20. In this specification, polishing the polishing surface 14 of the GaN substrate 20 means, for example, as shown in FIG. 7(c), scraping off a part of the GaN 30 constituting the polishing surface 14 of the GaN substrate 20 to flatten the surface.

The time for performing the polishing process S110 can be set arbitrarily depending on the application of the GaN substrate 20, etc.

In the polishing step S110, the surface of the GaN substrate 20 can be planarized by repeatedly performing the above-mentioned oxidation step S111 and removal step S112. The arithmetic mean roughness Ra (see JIS B 0601-2001) of the surface (polished surface) of the GaN substrate 20 after the polishing step S110 is preferably, for example, 0.7 nm or less. This makes the GaN substrate 20 after the polishing step S110 suitable for use in the manufacture of semiconductor devices, etc. The lower limit of the arithmetic mean roughness Ra of the surface of the GaN substrate 20 after the polishing step S110 is not particularly limited, but is exemplified as 0.1 nm or more.

In the polishing step S110, the polished surface 14 of the GaN substrate 20 is efficiently oxidized by highly reactive OH radicals, and the oxides 31 are removed to polish the polished surface 14 of the GaN substrate 20, thereby improving the polishing rate compared to the conventional method. Specifically, the polishing rate in the polishing step S110 can be, for example, 100 nm/h or more and 10,000 nm/h or less. In this specification, the polishing rate means the thickness removed per unit time of polishing.

Figure 9 is a cross-sectional photograph of the vicinity of the polished surface 14 of the GaN substrate 20 in the polishing step S110. In the polishing step S110, it is preferable to form a porous structure on the polished surface 14 of the GaN substrate 20 and then remove the porous structure. In this specification, a porous structure means a structure in which multiple voids are formed in a crystal. In Figure 9, multiple void layers (porous layers 18) are formed parallel to the polished surface 14. By forming a porous structure, the crystal above it is easier to remove, so the polishing rate can be improved. In addition, the above-mentioned porous structure is easily formed when polishing a conductive semiconductor substrate, particularly a GaN substrate 20.

When polishing step S110 is to be completed, it is preferable to stop the power supply 23 for a predetermined time, and move the polishing pad 10 and the GaN substrate 20 relative to each other while in contact with each other, without applying a voltage to the polishing pad 10. This allows the polishing step S110 to be completed with no oxide 31 remaining on the polished surface 14 of the GaN substrate 20. It also reduces uneven polishing caused by the distribution of the in-plane electrical properties of the polished surface 14.

By carrying out the above steps, a GaN substrate 20 having a polished surface can be manufactured.

(5) Effects of the Present Embodiment According to the present embodiment, one or more of the following effects can be obtained.

(a) The polishing pad 10 of this embodiment is impregnated with a solid polymer electrolyte that generates OH radicals on the polishing surface 13 and oxidizes the polished surface 14 of the GaN substrate 20 with the OH radicals. Therefore, the polished surface 14 of the GaN substrate 20 can be oxidized. As a result, it is possible to perform polishing while suppressing damage to the polished surface 14 of the GaN substrate 20. In addition, in this embodiment, the polished surface 14 of the GaN substrate 20 is efficiently oxidized by highly reactive OH radicals, so the polishing rate can be improved compared to conventional methods. Furthermore, in this embodiment, no oxidizing agent such as potassium permanganate is used, and only pure water is supplied, so polishing can be performed in a neutral region.

(b) In the polishing pad 10 of this embodiment, the polishing surface 13 is impregnated with Nafion 15, a solid polymer electrolyte that generates OH radicals from water when a voltage is applied. Therefore, the generation of OH radicals and the oxidation of the polished surface 14 of the GaN substrate 20 can be performed simultaneously. Therefore, the polished surface 14 of the GaN substrate 20 can be oxidized before the OH radicals disappear. Furthermore, in the polishing pad 10 of this embodiment, the generated OH radicals are used to oxidize the polished surface 14 of the GaN substrate 20, so the deterioration of Nafion 15 due to OH radicals can be suppressed.

(c) In the polishing pad 10 of this embodiment, it is preferable that abrasive grains 32 that remove oxides 31 are dispersed on the polishing surface 13. In this embodiment, since only oxides 31 are removed, the polished surface 14 of the GaN substrate 20 can be polished even using abrasive grains 32 that are softer than GaN 30. As a result, it is possible to perform polishing while suppressing damage to the polished surface 14 of the GaN substrate 20.

Second Embodiment of the Present Invention
Next, a second embodiment of the present invention will be described, focusing on the differences from the first embodiment. Elements that are substantially the same as those described in the first embodiment will be denoted by the same reference numerals, and the description thereof will be omitted.

(1) Configuration of the polishing pad 40 FIGS. 10(a) and 10(b) are plan views that show the polishing surface 13 of the polishing pad 40 of this embodiment. As shown in FIGS. 10(a) and 10(b), the polishing pad 40 of this embodiment has a first region 11 and a second region 12 on the polishing surface 13. The first region 11 and the second region 12 are, for example, fan-shaped and arranged adjacent to each other. FIG. 10(a) shows an example in which the first region 11 is fan-shaped with a central angle of 90 degrees and the second region 12 is fan-shaped with a central angle of 270 degrees. The arrangement of the first region 11 and the second region 12 is not limited to the above-mentioned embodiment and can be changed in various ways. For example, as shown in FIG. 10(b), the fan-shaped first region 11 and the second region 12 may be arranged so that a plurality of them are alternately adjacent to each other.

In the polishing pad 40 of this embodiment, the first region 11 and the second region 12 are arranged so as to alternately come into contact with the polished surface 14 of the GaN substrate 20 due to the relative movement between the polishing pad 40 and the GaN substrate 20. The effect of this will be described later.

The first region 11 is a region for generating OH radicals and oxidizing the GaN 30 as a semiconductor crystal constituting the polished surface 14 of the GaN substrate 20 with the OH radicals.

The first region 11 is impregnated with, for example, Nafion 15 as a solid polymer electrolyte. It is preferable that the Nafion 15 is impregnated throughout the entire thickness of the polishing pad 40. Since Nafion 15 has ionic conductivity, this ensures ionic conductivity in the thickness of the polishing pad 40. Note that Nafion 15 is omitted in Figures 10(a) and 10(b).

The second region 12 is a region for removing oxides 31 (e.g., gallium oxide) that are generated when GaN 30 constituting the polished surface 14 of the GaN substrate 20 is oxidized by OH radicals. The polishing pad 40 of this embodiment has the first region 11 and the second region 12 on the polishing surface 13, so that a single polishing pad 40 can be used to oxidize and remove oxides 31 from the polished surface 14 of the GaN substrate 20.

In the second region 12, for example, abrasive grains 32 for removing the oxide 31 are dispersed. The abrasive grains 32 preferably have a hardness lower than that of the GaN 30 constituting the polished surface 14 of the GaN substrate 20. Examples of such abrasive grains 32 include cerium oxide (CeO ₂ ), silicon oxide (SiO ₂ ), and zirconium oxide (ZrO ₂ ).

(2) Manufacturing method of the polishing pad 40 First, the nonwoven fabric is impregnated with the Nafion dispersion. At this time, for example, only the first region 11 may be immersed in the Nafion dispersion so that only the first region 11 is impregnated with the Nafion dispersion, or wax or the like may be applied to the portion other than the first region 11. By applying wax or the like to the portion other than the first region 11, only the first region 11 can be impregnated with the Nafion dispersion. The Nafion dispersion may be the same as that used in the first embodiment.

After the first region 11 is impregnated with the Nafion dispersion liquid, excess Nafion dispersion liquid is removed, for example, using a squeezer or the like, and then the nonwoven fabric impregnated with the Nafion dispersion liquid is dried for 30 minutes at 70°C using a constant temperature dryer or the like. In this way, the first region 11 can be impregnated with Nafion 15. Note that the impregnation with the Nafion dispersion liquid and drying may be repeated multiple times.

After the first region 11 is impregnated with Nafion 15, the nonwoven fabric is impregnated with a cerium oxide dispersion. In this case, for example, only the second region 12 may be immersed in the cerium oxide dispersion, or wax or the like may be applied to the portion other than the second region 12 so that only the second region 12 is impregnated with the cerium oxide dispersion. By applying wax or the like to the portion other than the second region 12, only the second region 12 can be impregnated with the cerium oxide dispersion. In addition, it is preferable to add a small amount of sodium alginate (for example, 0.25 wt%) to the cerium oxide dispersion. This increases the viscosity of the cerium oxide dispersion, making it easier to disperse cerium oxide in the second region 12. The cerium oxide dispersion may be the same as that used in the first embodiment.

After the second region 12 is impregnated with the cerium oxide dispersion, it is preferable to place the nonwoven fabric in an aqueous calcium chloride solution (e.g., 20% by weight). This causes the sodium alginate and calcium chloride to react and gel, making it easier to disperse the cerium oxide in the second region 12.

Rare earth oxides such as praseodymium oxide, neodymium oxide, and lanthanum oxide may also be added to the cerium oxide dispersion. This makes it easier to remove the oxides 31 with the abrasive grains 32.

After the second region 12 is impregnated with the cerium oxide dispersion, excess cerium oxide dispersion is removed, for example, using a squeezer or the like, and then the pad is dried at 70°C for 30 minutes using a constant temperature dryer or the like. This results in a polishing pad 40 having a first region 11 and a second region 12 on the polishing surface 13.

(3) Manufacturing method of conductive semiconductor substrate In the polishing step S110 of this embodiment, the polishing pad 40 and the GaN substrate 20 are moved relative to each other to alternately bring the first region 11 and the second region 12 into contact with the polished surface 14 of the GaN substrate 20. Specifically, for example, the GaN substrate 20 is arranged so that the center of the polished surface 14 is located at a position radially away from the center of the polishing surface 13 at a predetermined distance, and the platen 21 is rotated horizontally at a predetermined rotation speed to alternately bring the first region 11 and the second region 12 into contact with the polished surface 14 of the GaN substrate 20. As a result, in the polishing step S110, the oxidation step S111 and the removal step S112 can be performed continuously and alternately. That is, the oxidation step S111 can be performed when the first region 11 is in contact with the polished surface 14 of the GaN substrate 20, and the removal step S112 can be performed when the second region 12 is in contact with the polished surface 14 of the GaN substrate 20. In this specification, when a portion of the polished surface 14 is in contact with the first region 11 (for example, when the polished surface 14 is in contact with both the first region 11 and the second region 12), it is determined that the first region 11 is in contact with the polished surface 14 of the GaN substrate 20.

Figure 11 is a graph showing a schematic of the current flowing through the polishing pad 40 in the polishing step S110 of this embodiment. As shown in Figure 11, in the polishing step S110 of this embodiment, even if a voltage is applied continuously, a current flows intermittently through the polishing pad 40, as in the first embodiment. Since the first region 11 is impregnated with Nafion 15 exhibiting electrical conductivity, when the first region 11 is in contact with the polished surface 14 of the GaN substrate 20 (oxidation step S111), a predetermined current flows through the polishing pad 40. On the other hand, since the second region 12 is not impregnated with a material exhibiting electrical conductivity such as Nafion 15, when the second region 12 is in contact with the polished surface 14 of the GaN substrate 20 (removal step S112), no current flows through the polishing pad 40.

As shown in FIG. 11, in the oxidation step S111 of this embodiment, the value of the current flowing through the polishing pad 40 changes depending on the area of contact between the polished surface 14 and the first region 11. From the viewpoint of controlling the current value to a constant value and uniformly oxidizing the polished surface 14, it is preferable that the entire surface of the polishing surface 13 is impregnated with Nafion 15, as in the first embodiment described above.

(4) Effects of the Present Embodiment According to the present embodiment, one or more of the following effects can be obtained.

(a) The polishing pad 40 of this embodiment has a first region 11 on the polishing surface 13 that generates OH radicals and oxidizes the polished surface 14 of the GaN substrate 20 with the OH radicals, and a second region 12 that removes the oxides 31. Therefore, as in the first embodiment, a single polishing pad 40 can be used to oxidize and remove the oxides 31 from the polished surface 14 of the GaN substrate 20. As a result, it is possible to perform polishing while suppressing damage to the polished surface 14 of the GaN substrate 20.

(b) In the polishing pad 40 of this embodiment, the first region 11 and the second region 12 are arranged so as to alternately come into contact with the polished surface 14 of the GaN substrate 20 due to the relative movement between the polishing pad 40 and the GaN substrate 20. This allows the oxidation step S111 and the removal step S112 to be performed alternately in succession.

(c) In the polishing step S110 of this embodiment, the area (first area 11) where the oxidation step S111 is performed and the area (second area 12) where the removal step S112 is performed are separated within the polishing surface 13 of the polishing pad 40. Therefore, for example, in the oxidation step S111, the abrasive grains 32 do not come into contact with the polished surface 14 of the GaN substrate 20. This makes it possible to prevent the abrasive grains 32 from interfering with the oxidation of the polished surface 14 of the GaN substrate 20 in the oxidation step S111.

<Other embodiments of the present invention>
Although the embodiment of the present invention has been specifically described above, the present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the gist of the present invention.

For example, in the above-mentioned second embodiment, a case where one sheet of nonwoven fabric is used to manufacture the polishing pad 40 has been described, but two or more sheets of nonwoven fabric may be used to manufacture the polishing pad 40. For example, Nafion 15 may be fixed to one nonwoven fabric and cerium oxide may be fixed to the other nonwoven fabric, and the respective nonwoven fabrics may be bonded together to manufacture a polishing pad 40 having a first region 11 and a second region 12 on the polishing surface 13.

In the above embodiment, for example, the case of polishing a GaN substrate 20 made of a single crystal of GaN has been described as a conductive semiconductor substrate. However, the conductive semiconductor substrate may be a III-nitride substrate made of a III-nitride other than GaN, such as InAlGaN, a silicon substrate made of a single crystal of silicon, or a SiC substrate made of a single crystal of silicon carbide (SiC). In addition, the conductive semiconductor substrate may be a template substrate in which a III-nitride is heteroepitaxially grown on an insulating substrate, such as a sapphire substrate. In this case, for example, the entire surface of the substrate can be polished by making contact from the side of the template substrate and applying a voltage. Among various conductive semiconductor substrates, it is very difficult to polish a GaN substrate at a practical polishing rate (for example, 100 nm/h or more), so the present invention is particularly effective when polishing a GaN substrate.

In addition, for example, in the above embodiment, the case of polishing the +c plane of the GaN substrate 20 has been described, but the present invention can also be applied, for example, when polishing the -c plane, a plane, m plane, etc. of the GaN substrate 20.

In addition, for example, in the above-mentioned first embodiment, a pulse voltage is applied to the polishing pad 10, but a voltage may be applied to the polishing pad 10 continuously.

Also, for example, in the above embodiment, the case where OH radicals are generated and the polished surface 14 is oxidized has been described, but radicals other than OH radicals, atomic oxygen, etc. may be generated to oxidize the polished surface 14. For example, an aqueous solution (e.g., an aqueous solution of potassium peroxodisulfate) containing peroxodisulfate ions (S ₂ O ₈ ²⁻ ) is supplied to the first region 11, and sulfate ion radicals (SO ₄ ⁻ .) can be generated by at least one of heating the peroxodisulfate ions and irradiating the peroxodisulfate ions with light. By generating sulfate ion radicals, it becomes possible to oxidize the polished surface 14 in the same manner as in the above embodiment.

In addition, for example, in the above embodiment, the pure water is supplied in a spray form using the pure water supply unit 24, but the manner in which the pure water is supplied to the polishing surface 13 is not limited to the above embodiment. For example, gauze soaked in pure water may be brought into contact with the polishing surface 13, and the pure water may be supplied to the polishing surface 13 by capillary action. In this case, it is easy to keep the humidity of the polishing surface 13 constant.

Next, examples of the present invention will be described. These examples are merely examples of the present invention, and the present invention is not limited to these examples.

Example 1
(1) Preparation of GaN Substrate 20 First, a plurality of GaN substrates 20 (diameter 2 inches) before polishing the polished surface 14 (+c-plane) were prepared as conductive semiconductor substrates, and these were designated as Samples 1 to 3. The carrier concentration of Sample 1 was 1.6×10 ¹⁷ cm ^-3 . The carrier concentrations of Samples 2 and 3 were 2.56×10 ¹⁸ cm ^-3 .

(2) Polishing of GaN Substrate 20 Using the polishing pad 40 described in the second embodiment of the present invention, the surface 14 to be polished of the sample 1 was polished while a voltage was continuously applied. The polishing conditions were as follows.
Voltage (voltage applied by power supply 23): 100 V
Polishing pressure (pressure for pressing the polished surface 14 against the polishing surface 13): 18.3 kPa
Rotation speed of the platen (rotation speed of the platen 21): 60 rpm
Substrate rotation speed (rotation speed of the substrate holder 22): 60 rpm
Polishing time (time to perform polishing step S110): 30 minutes (10 minutes x 3 times)

Moreover, the polishing surface 14 of the sample 2 was polished using the polishing pad 10 described in the first embodiment of the present invention while applying a pulse voltage. The polishing conditions were as follows.
Voltage (voltage applied by power supply 23): 100 V
Duty ratio D: 5%
Pulse period T: 40 seconds Polishing pressure (pressure for pressing the polished surface 14 against the polishing surface 13): 18.3 kPa
Rotation speed of the platen (rotation speed of the platen 21): 120 rpm
Substrate rotation speed (rotation speed of the substrate holder 22): 120 rpm
Polishing time (time to perform polishing step S110): 30 minutes (10 minutes x 3 times)

For comparison, the polished surface 14 of the sample 3 was polished using a polishing pad in which only cerium oxide was dispersed in a nonwoven fabric without applying a voltage. The polishing conditions were as follows:
Polishing pressure (pressure for pressing the polished surface 14 against the polishing surface 13): 18.3 kPa
Rotation speed of the platen (rotation speed of the platen 21): 120 rpm
Substrate rotation speed (rotation speed of the substrate holder 22): 120 rpm
Polishing time (time to perform polishing step S110): 30 minutes (10 minutes x 3 times)

(3) Evaluation of Polishing Rate The polishing rate was calculated by measuring the weight and thickness of the GaN substrate 20 before and after polishing. The polishing rate of the sample 1 polished using the polishing pad 40 was 132 nm/h. From the above, it was confirmed that the polishing rate can be increased to 100 nm/h or more by polishing the polished surface 14 of the GaN substrate 20 using the polishing pad 40.

Figure 12 shows the amount of polishing (thickness removed by polishing) of Sample 2 and Sample 3. Sample 2, which was polished using polishing pad 10, had a larger amount of polishing than Sample 3, which was polished using a polishing pad with only cerium oxide fixed thereto. From the above, it was confirmed that the polishing rate can be improved by using polishing pad 10 to polish surface 14 (+c surface) of GaN substrate 20.

(4) Evaluation of surface roughness FIG. 13 shows the results of measuring the arithmetic mean roughness Ra of sample 1 before and after polishing using an optical surface texture measuring instrument (Zygo NewView 7300). The arithmetic mean roughness Ra before polishing was 1.39 nm. The arithmetic mean roughness Ra after 10 minutes of polishing was 1.06 nm. The arithmetic mean roughness Ra after 20 minutes of polishing was 0.840 nm. The arithmetic mean roughness Ra after 30 minutes of polishing was 0.687 nm. From the above, it was confirmed that a GaN substrate 20 having a surface arithmetic mean roughness Ra of 0.7 nm or less can be manufactured by polishing the polished surface 14 of the GaN substrate 20 using the polishing pad 40.

Example 2
(1) Preparation of Polishing Pad 10 First, the polishing pad 10 was prepared by the following procedure.

A nonwoven fabric (apparent volume: 31.4 cm ³ ) having a diameter of 200 mm and an (apparent) thickness of 1 mm was prepared. The mass of the nonwoven fabric was 2.80 g.

The nonwoven fabric was impregnated with a cerium oxide dispersion liquid to which a small amount of sodium alginate was added. The nonwoven fabric was then placed in an aqueous calcium chloride solution, and excess liquid was removed from the nonwoven fabric using a squeezer. The nonwoven fabric was then dried at 70°C for 30 minutes using a constant temperature dryer. The mass of the nonwoven fabric after drying was 23.88g. The increase in mass was 20.58g, and since 40% by mass of the increase was cerium oxide (the remaining 60% by mass was sodium alginate), the density of the abrasive grains 32 was 0.26g/ ^cm3 .

Next, the nonwoven fabric was impregnated with the Nafion dispersion, and excess liquid was removed from the nonwoven fabric using a squeezer, and then the nonwoven fabric was dried at 70° C. for 30 minutes using a constant temperature dryer. The mass of the nonwoven fabric after drying was 23.53 g. The increase in mass was 0.15 g, and the density of Nafion 15 was 4.8 mg/cm ³ .

(2) Polishing of GaN Substrate 20 and SiC Substrate Polishing of a GaN substrate 20 and a SiC substrate was performed using the polishing pad 10 produced in (1). The GaN substrate 20 was prepared to be 2 inches in diameter, n-type, with the polished surface 14 being a +c-plane. The SiC substrate was prepared to be 4H—SiC, 2 inches in diameter, n-type, with the polished surface 14 being a Si-plane.

The polishing conditions were as follows:
Voltage (voltage applied by power supply 23): 40 V
Current value: 100-150mA
Duty ratio D: 90%
Pulse period T: 120 seconds Polishing pressure (pressure for pressing the polished surface 14 against the polishing surface 13): 12 kPa
Rotation speed of the platen (rotation speed of the platen 21): 60 rpm
Substrate rotation speed (rotation speed of the substrate holder 22): 60 rpm
Water supply amount: 0.4mL/min
Temperature: RT
Polishing time (time to perform polishing step S110): 10 minutes

(3) Evaluation of polishing rate The polishing rate was calculated by measuring the weight and thickness of the GaN substrate 20 and the SiC substrate before and after polishing. The polishing rate of the GaN substrate 20 was 1 μm/h. In other words, it was confirmed that the polishing rate when the GaN substrate 20 was polished using the polishing pad 10 under the above polishing conditions was 1 μm/h or more.

The polishing rate of the SiC substrate was 4.5 μm/h. In other words, it was confirmed that the polishing rate when polishing a SiC substrate using the polishing pad 10 under the above polishing conditions was 4.5 μm/h or more.

<Preferred embodiment of the present invention>
Preferred embodiments of the present invention will be described below.

(Appendix 1)
According to one aspect of the present invention,
A polishing pad used for polishing a surface of a conductive semiconductor substrate, comprising:
There is provided a polishing pad, the polishing surface which comes into contact with the surface to be polished being impregnated with at least a solid polymer electrolyte.

(Appendix 2)
2. The polishing pad according to claim 1,
The solid polymer electrolyte is also impregnated in the polishing pad in the thickness direction.

(Appendix 3)
10. The polishing pad according to claim 1 or 2,
The solid polymer electrolyte is impregnated at a density of 3 mg/cm ³ or more and 20 mg/cm ³ or less.

(Appendix 4)
A polishing pad according to any one of claims 1 to 3,
With water molecules in contact with the solid polymer electrolyte, electrical continuity is established between the polished surface and the back surface opposite to the polished surface.

(Appendix 5)
5. The polishing pad according to claim 1,
The polishing pad comprises a nonwoven fabric,
The solid polymer electrolyte is attached to the surface of the fibers of the nonwoven fabric.

(Appendix 6)
6. The polishing pad according to claim 1,
The solid polymer electrolyte is a polymer (Nafion) having a fluorocarbon skeleton and fluorocarbon ether side chains having sulfonic acid groups at their ends.

(Appendix 7)
7. The polishing pad according to claim 1,
A conductive adhesive is applied to the back surface opposite the polished surface.

(Appendix 8)
8. The polishing pad according to claim 1,
Abrasive grains are dispersed on the polishing surface.
Preferably, the abrasive grains have a hardness lower than that of the semiconductor crystals that constitute the surface to be polished.

(Appendix 9)
9. The polishing pad according to claim 8,
The abrasive grains include cerium oxide,
The abrasive grains are dispersed at a density of 0.1 g/cm ³ or more and 0.5 g/cm ³ or less.

(Appendix 10)
10. The polishing pad according to claim 8 or 9,
The solid polymer electrolyte is attached to the surface of the abrasive grain.

(Appendix 11)
11. The polishing pad according to claim 8,
A gallium nitride substrate made of a single crystal of gallium nitride is polished at a polishing rate of 1 μm/h or more while a voltage of 40 V is intermittently applied between the polishing pad and the gallium nitride substrate.
Preferably, the value of the current flowing through the gallium nitride substrate is not less than 100 mA and not more than 150 mA.
Preferably, the duty ratio D is 90%.
Preferably, the period T of the pulses is 120 seconds.
Preferably, the pressure with which the polished surface is pressed against the polishing surface is 12 kPa.
Preferably, the rotation speed of the polishing pad and the gallium nitride substrate is 60 rpm.
Preferably, the amount of water supplied to the polishing surface is 0.4 mL/min.

(Appendix 12)
12. The polishing pad according to any one of claims 8 to 11,
When a silicon carbide substrate made of a single crystal of silicon carbide is polished while a voltage of 40 V is intermittently applied between the polishing pad and the silicon carbide, the polishing rate is 4.5 μm/h or more.
Preferably, a value of a current flowing through the silicon carbide substrate is equal to or greater than 100 mA and equal to or less than 150 mA.
Preferably, the duty ratio D is 90%.
Preferably, the period T of the pulses is 120 seconds.
Preferably, the pressure with which the polished surface is pressed against the polishing surface is 12 kPa.
Preferably, the rotation speed of the polishing pad and the silicon carbide substrate is 60 rpm.
Preferably, the amount of water supplied to the polishing surface is 0.4 mL/min.

(Appendix 13)
According to another aspect of the present invention,
A step of preparing a polishing pad, the polishing surface of which contacts the surface to be polished of the conductive semiconductor substrate being impregnated with at least a solid polymer electrolyte;
a step of bringing the polishing surface of the polishing pad into contact with the surface to be polished of the conductive semiconductor substrate under pressure while water molecules are in contact with the solid polymer electrolyte, and polishing the surface to be polished by moving the polishing pad and the conductive semiconductor substrate relative to each other while applying a voltage between the polishing pad and the conductive semiconductor substrate;
A method for manufacturing a conductive semiconductor substrate is provided, comprising:

(Appendix 14)
A method for producing a conductive semiconductor substrate according to claim 13, comprising the steps of:
In the polishing step, the surface to be polished is oxidized while the voltage is being applied.

(Appendix 15)
A method for producing a conductive semiconductor substrate according to claim 13 or 14, comprising the steps of:
In the polishing step, the voltage is applied intermittently.

(Appendix 16)
A method for producing a conductive semiconductor substrate according to any one of claims 13 to 15, comprising:
In the polishing step, a slurry containing abrasive grains is supplied to the polishing surface.

(Appendix 17)
A method for producing a conductive semiconductor substrate according to any one of claims 13 to 16, comprising the steps of:
In the polishing step, a porous structure is formed on the surface to be polished of the conductive semiconductor substrate, and then the porous structure is removed.
Preferably, the conductive semiconductor substrate is a gallium nitride substrate made of a single crystal of gallium nitride.

(Appendix 18)
A method for producing a conductive semiconductor substrate according to any one of claims 13 to 17, comprising:
In the polishing step, a voltage V applied between the polishing pad and the conductive semiconductor substrate is controlled so as not to exceed a voltage Vm at which the polishing rate of the conductive semiconductor substrate is maximized.
Preferably, the conductive semiconductor substrate is a silicon carbide substrate made of a single crystal of silicon carbide.

(Appendix 19)
A method for producing a conductive semiconductor substrate according to any one of claims 13 to 18, comprising the steps of:
In the polishing step, the polishing pad and the conductive semiconductor substrate are moved relative to each other for a predetermined time without applying a voltage between the polishing pad and the conductive semiconductor substrate, and then the polishing step is terminated.

(Appendix 20)
According to another aspect of the present invention,
A polishing pad for use in polishing a surface of a conductive semiconductor substrate, comprising:
On a surface in contact with the surface of the conductive semiconductor substrate,
a first region for generating radicals and oxidizing a semiconductor crystal constituting the surface of the conductive semiconductor substrate by the radicals;
and a second region that removes oxides produced by the oxidation of the semiconductor crystal by the radicals.
Preferably, the polishing pad has water retention properties.
Preferably, the surface of the polishing pad which comes into contact with the surface of the conductive semiconductor substrate has slidability relative to the surface of the conductive semiconductor substrate.
Preferably, the polishing pad has a conductive adhesive on the back surface.

(Appendix 21)
21. The polishing pad according to claim 20,
The radical is an OH radical.

(Appendix 22)
22. The polishing pad according to claim 20 or 21,
The first region is impregnated with a solid polymer electrolyte that generates the radicals (from water upon application of a voltage).
Preferably, the solid polymer electrolyte is impregnated throughout the entire polishing pad in the thickness direction.
Preferably, the voltage is greater than or equal to 20V and less than or equal to 300V.

(Appendix 23)
23. The polishing pad according to any one of claims 20 to 22,
Abrasive grains for removing the oxides are dispersed in the second region.
Preferably, the abrasive grains have a hardness lower than that of the semiconductor crystals.

(Appendix 24)
24. The polishing pad according to any one of claims 20 to 23,
The first region and the second region are arranged so as to alternately come into contact with the conductive semiconductor substrate by relative movement between the polishing pad and the conductive semiconductor substrate.

(Appendix 25)
According to another aspect of the present invention,
A polishing pad for use in polishing a surface of a conductive semiconductor substrate, comprising:
Abrasive grains with a lower hardness than gallium nitride are dispersed in the material.
There is provided a polishing pad having a polishing rate of 100 nm/h to 10,000 nm/h when polishing (the +c plane of) a gallium nitride substrate made of a single crystal of gallium nitride in a neutral region.
Preferably, OH radicals are generated from water by applying a voltage, and the gallium nitride is oxidized by the OH radicals.
Preferably, gallium oxide produced by oxidizing the gallium nitride is removed.
Preferably, the voltage is greater than or equal to 20V and less than or equal to 300V.
Preferably, the carrier concentration in the surface of the gallium nitride substrate is not less than 1.0×10 ¹⁶ cm ⁻³ and not more than 1.0×10 ²⁰ cm ⁻³ .

(Appendix 26)
According to another aspect of the present invention,
A method for manufacturing a conductive semiconductor substrate, comprising the steps of:
generating radicals and oxidizing semiconductor crystals constituting the surface of the conductive semiconductor substrate by the radicals;
and removing an oxide produced by oxidizing the semiconductor crystal with the radicals,
There is provided a method for manufacturing a conductive semiconductor substrate, in which the oxidizing step and the removing step are carried out by relatively moving a polishing pad that polishes the surface of the conductive semiconductor substrate and the conductive semiconductor substrate.
Preferably, the oxidizing step and the removing step are carried out simultaneously or alternately.

REFERENCE SIGNS LIST 10 Polishing pad 11 First region 12 Second region 13 Polishing surface 14 Polished surface 15 Nafion 16 Fiber 17 Bubbles 18 Porous layer 20 GaN substrate 21 Plate 22 Substrate holder 23 Power source 24 Pure water supply unit 30 GaN
31 oxide 32 abrasive grain 40 polishing pad S100 preparation step S110 polishing step S111 oxidation step S112 removal step

Claims (9)

A polishing pad used for polishing a surface of a conductive semiconductor substrate, comprising:
the polishing surface in contact with the polished surface is impregnated with at least a solid polymer electrolyte at a density of 3 mg/cm3 or ^more and 20 mg/cm3 or ^less ;
the substrate having the polishing surface has an open-cell structure,
The solid polymer electrolyte covers at least a portion of the surface of the substrate . The polishing pad according to claim 1, wherein the solid polymer electrolyte is also impregnated in the thickness direction of the polishing pad. 3. The polishing pad according to claim 1, wherein the solid polymer electrolyte covers and connects the inside of the cells of the substrate. The polishing pad according to any one of claims 1 to 3, wherein electrical conduction is established between the polishing surface and the back surface opposite the polishing surface when water molecules are in contact with the solid polymer electrolyte. 5. The polishing pad according to claim 1 , wherein the solid polymer electrolyte is a polymer having a fluorocarbon skeleton and a fluorocarbon ether side chain having a sulfonic acid group at its terminal. 6. The polishing pad according to claim 1, further comprising a conductive adhesive on a back surface opposite to the polishing surface. 7. The polishing pad according to claim 1, wherein abrasive grains are dispersed on the polishing surface. 8. The polishing pad according to claim 7 , wherein the solid polymer electrolyte is attached to the surfaces of the abrasive grains. The polished surface has a solid polymer electrolyte concentration of at least 3 mg/cm ³ More than 20 mg/cm ³ and a second region in which abrasive grains are dispersed,
9. The polishing pad according to claim 1, wherein the first region and the second region are arranged to alternately contact the polished surface due to relative movement between the polishing pad and the conductive semiconductor substrate.

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