JP7655066B2 - COMMUNICATION DEVICE, SOFTWARE UPDATE METHOD, AND COMPUTER PROGRAM - Google Patents

Description

The present disclosure relates to a communication device, a program update method, and a computer program.

For communication devices used in backbone networks, there is a demand for an In Service Software Upgrade (ISSU) that performs software updates while maintaining the communication functions of the main signal so as not to halt the provision of services. Patent Document 1 discloses a method for updating the firmware of an optical line terminal (OLT) in a passive optical network (PON) without stopping the OLT.

JP 2014-78784 A

However, the method disclosed in Patent Document 1 does not take into consideration updates to the operating system (hereinafter also referred to as "OS"). Therefore, when updating the OS, the device is restarted and the device is stopped for a certain period of time.

A communication device according to one aspect of the present disclosure includes a memory for storing data, a processor capable of reading data stored in the memory, a first hardware function unit providing a function related to communication of a main signal, a second hardware function unit providing a function linked to the processor, a storage processing unit that stores handover data including a start-up code for starting a second operating system, which is an operating system after an update, a second code, which is an executable code of the second operating system, and first control information used for controlling the second hardware function unit by a first operating system, which is an operating system before an update, in an area different from the storage area in the memory for the first code, which is the executable code of the first operating system, without initializing the processor and the first hardware function unit, a switching processing unit that causes the processor to stop the first operating system and start the second operating system by executing the start-up code and the second code, and a control information acquisition processing unit that causes the processor to acquire the first control information from the handover data when the second operating system is started.

A communication device according to another aspect of the present disclosure includes a processor capable of executing software, a first hardware function unit providing a function related to communication of a main signal, a third hardware function unit providing a function different from the function related to communication of the main signal, a control circuit capable of outputting a restart command signal to the processor, the first hardware function unit, and the third hardware function unit, and a restart target setting unit that sets a target for restart when software executed by the processor is updated, and when the processor and the third hardware function unit are set as targets for restart by the restart target setting unit and the first hardware function unit is not set as a target for restart, the control circuit outputs a restart command signal to the processor and the third hardware function unit and does not output a restart command signal to the first hardware function unit.

A software update method according to one aspect of the present disclosure is a software update method for updating software in a communication device, and includes the steps of: storing handover data including a start-up code for starting a second operating system, which is an operating system after the update, a second code, which is an executable code of the second operating system, and first control information used for controlling the second hardware function unit by the first operating system, which is an operating system before the update, in an area different from the storage area in memory of the first code, which is the executable code of the first operating system, without initializing the processor and each of the first hardware function unit providing a function related to communication of a main signal; causing the processor to stop the first operating system and execute the start-up code and the second code to start the second operating system; and causing the processor to obtain the first control information from the handover data when the second operating system is started.

A software update method according to another aspect of the present disclosure is a software update method for updating software in a communication device, and includes the steps of: when software executed by a processor is updated, setting a restart target from among the processor, a first hardware function unit that provides a function related to communication of a main signal, and a third hardware function unit that provides a function different from the function related to communication of the main signal; and when the processor and the third hardware function unit are set as the restart targets and the first hardware function unit is not set as the restart target, not outputting a restart command signal to the first hardware function unit, and outputting a restart command signal to the processor and the third hardware function unit.

A computer program according to one aspect of the present disclosure is a computer program for updating software in a communication device, and causes the communication device to execute the steps of: storing, in an area in memory different from the storage area of the first code, which is the executable code of the first operating system, handover data including a start-up code for starting a second operating system, which is an operating system after the update, a second code, which is executable code of the second operating system, and first control information used for controlling the second hardware function unit by the first operating system, which is an operating system before the update, without initializing the processor and each of the first hardware function unit that provides functions related to communication of main signals; causing the processor to stop the first operating system and start the second operating system by executing the start-up code and the second code; and causing the processor to obtain the first control information from the handover data when the second operating system is started.

A computer program according to another aspect of the present disclosure is a computer program for updating software in a communication device, and causes the communication device to execute the steps of: when software executed by a processor is updated, setting a restart target from among the processor, a first hardware function unit that provides a function related to communication of a main signal, and a third hardware function unit that provides a function different from the function related to communication of the main signal; and, when the processor and the third hardware function unit are set as the restart targets and the first hardware function unit is not set as the restart target, not outputting a restart command signal to the first hardware function unit and outputting a restart command signal to the processor and the third hardware function unit.

The present disclosure can be realized not only as a communication device having the above-mentioned characteristic configuration, but also as a software update method having steps corresponding to characteristic processes in the communication device, or as a computer program for causing a computer to execute such steps. Furthermore, part or all of the communication device can be realized as a semiconductor integrated circuit, or as a relay system including the communication device.

According to the present disclosure, it is possible to update the operating system while maintaining the communication function of the main signal.

FIG. 1 is a schematic diagram illustrating an example of a configuration of a communication system according to an embodiment. 1 is a block diagram showing an example of a configuration of a communication device according to an embodiment. FIG. 2 is a block diagram showing an example of functions of a communication device according to an embodiment. 1 is a diagram for explaining combinations of software to be updated in each of a conventional method, a live boot method, and a reboot target selection method. FIG. FIG. 13 is a diagram illustrating data loaded into a volatile memory during a normal boot. FIG. 2 is a diagram illustrating data loaded into a volatile memory during a live boot. FIG. 11 is a diagram illustrating an example of handover data. 11 is a diagram for explaining an example of adding second control information to handover data. FIG. FIG. 13 is a diagram illustrating an example of a restart target in a normal boot. FIG. 13 is a diagram illustrating an example of a restart target in the restart target selection method. FIG. 13 is a diagram illustrating the saving of setting information and state information. FIG. 13 is a diagram illustrating the recovery of an internal table. 10 is a flowchart illustrating an example of a software update operation of the communication device according to the embodiment. 13 is a flowchart illustrating an example of a restart target selection update process. 13 is a flowchart illustrating an example of a live boot update process.

Overview of the embodiments of the present disclosure
Below, an overview of the embodiments of the present disclosure will be listed and described.

(1) The communication device according to the present embodiment includes a memory for storing data, a processor capable of reading data stored in the memory, a first hardware function unit providing a function related to communication of a main signal, a second hardware function unit providing a function linked to the processor, a storage processing unit for storing a start code for starting a second operating system, which is an operating system after an update, a second code, which is an executable code of the second operating system, and handover data including first control information used for controlling the second hardware function unit by the first operating system, which is an operating system before an update, in an area different from the storage area in the memory for the first code, which is the executable code of the first operating system, without initializing each of the processor and the first hardware function unit, a switching processing unit for causing the processor to stop the first operating system and execute the start code and the second code to start the second operating system, and a control information acquisition processing unit for causing the processor to acquire the first control information from the handover data when the second operating system is started. This allows the second operating system to be live-booted on the running first operating system. In the live boot of the second operating system, the first hardware function unit is not initialized, so that the operating system can be updated while maintaining the communication function of the main signal. In the case of a SoC (System on a Chip) in which a processor and hardware functional units are implemented on a single integrated circuit, in a live boot in which an operating system is started without going through bootstrap, the control information of the hardware functional units that is acquired by the processor in bootstrap is not acquired. The above disclosure allows the processor to acquire the first control information when the second operating system is started, so that a live boot is also possible in an SoC. Note that "live boot" refers to loading executable code of a new operating system into memory on a running operating system.

(2) The switching processing unit may provide notification information to the processor indicating that the second operating system will be started without initializing the processor when the second operating system is started, and the control information acquisition processing unit may cause the processor to acquire the first control information from the handover data when the notification information is provided to the processor. This allows the control information acquisition processing unit to determine whether the operating system is started as a normal start via bootstrap or a live boot, depending on whether notification information is provided to the processor. In the case of a live boot, the processor can acquire the first control information when the second operating system is started.

(3) The memory, the processor, and the second hardware function unit may be included in a single integrated circuit. This allows a communication device to be configured using a SoC.

(4) The communication device may further include a handover data generation unit that generates the handover data based on the first control information acquired by the processor when the first operating system is started and stores the generated handover data in a storage device, and the storage processing unit may store the handover data stored in the storage device in the memory. This allows the handover data to be loaded into the memory when the second operating system is started.

(5) When second control information used for controlling the second hardware function unit by the second operating system is acquired by the processor at the time of booting the second operating system, the control information acquisition processing unit may add the second control information to the handover data. This makes it possible to add second control information that was not required by the first operating system but is required by the second operating system to the handover data for the next live boot.

(6) The communication device according to this embodiment includes a processor capable of executing software, a first hardware function unit providing a function related to communication of a main signal, a third hardware function unit providing a function different from the function related to communication of the main signal, a control circuit capable of outputting a restart command signal to the processor, the first hardware function unit, and the third hardware function unit, and a restart target setting unit that sets a target for restart when software executed by the processor is updated. When the processor and the third hardware function unit are set as targets for restart by the restart target setting unit and the first hardware function unit is not set as a target for restart, the control circuit outputs a restart command signal to the processor and the third hardware function unit and does not output a restart command signal to the first hardware function unit. As a result, the first hardware function unit is excluded from targets for restart and the processor is included as a target for restart, so that software including the operating system can be updated while maintaining the communication function of the main signal.

(7) When the control circuit outputs the restart command signal, the control circuit may restart the control circuit. This allows the control circuit to be included in the target of restart.

(8) The software to be updated may include an operating system. This allows the operating system to be updated while maintaining the communication function of the main signal.

(9) The software to be updated may include a boot loader. This makes it possible to update the boot loader, which requires a processor restart, while maintaining the communication function of the main signal.

(10) The first hardware function unit may include a transceiver that transmits and receives the main signal, a signal processing circuit that processes the main signal, and a clock generator that supplies a clock signal to the transceiver and the signal processing circuit. This makes it possible to update software, including an operating system, without initializing the transceiver, the signal processing circuit, and the clock generator.

(11) The communication device may further include an information evacuation unit that stores, in a storage device, setting information of the first hardware function unit included in internal information of the software before updating the software for controlling the first hardware function unit executed by the processor, and a recovery unit that recovers, after updating the software, the setting information stored in the storage device as internal information of the updated software. This makes it possible to recover, after updating the software, the setting information of the first hardware function unit that is lost from the internal information when updating the software.

(12) The information saving unit may store the state information of the first hardware function unit included in the internal information in the storage device, and the communication device may further include a notification unit that notifies a user when there is a difference between the state information indicating the current state of the first hardware function unit and the state information stored in the storage device. In this way, when the state of the first hardware function unit changes during a software update, the user can be notified of the change after the software update.

(13) The software update method according to the present embodiment is a software update method for updating software in a communication device, and includes the steps of: storing a startup code for starting a second operating system, which is an operating system after the update, a second code, which is an executable code of the second operating system, and handover data, which includes first control information used for controlling the second hardware function unit by the first operating system, which is an operating system before the update, in an area different from the storage area in the memory of the first code, which is the executable code of the first operating system, without initializing each of the processor and the first hardware function unit that provides a function related to communication of a main signal; causing the processor to stop the first operating system and execute the startup code and the second code to start the second operating system; and causing the processor to obtain the first control information from the handover data when the second operating system is started. As a result, the first hardware function unit is not initialized in a live boot of the second operating system, so that the operating system can be updated while maintaining the communication function of the main signal. Furthermore, since the first control information can be obtained when the second operating system is started, a live boot is also possible in a SoC.

(14) The software update method according to this embodiment is a software update method for updating software in a communication device, and includes the steps of: when software executed by a processor is updated, setting a restart target from among the processor, a first hardware function unit providing a function related to communication of a main signal, and a third hardware function unit providing a function different from the function related to communication of the main signal; and when the processor and the third hardware function unit are set as the restart targets and the first hardware function unit is not set as the restart target, not outputting a restart command signal to the first hardware function unit and outputting a restart command signal to the processor and the third hardware function unit. As a result, the first hardware function unit is excluded from the restart targets and the processor is included as the restart target, so that software including the operating system can be updated while maintaining the communication function of the main signal.

(15) A computer program according to this embodiment is a computer program for updating software in a communication device, and causes the communication device to execute the steps of: storing, in an area in a memory different from the storage area of the first code, which is the executable code of the first operating system, a start code for starting a second operating system, which is an operating system after the update, a second code, which is an executable code of the second operating system, and handover data, which includes first control information used for controlling the second hardware function unit by the first operating system, which is an operating system before the update, without initializing each of the processor and the first hardware function unit that provides a function related to communication of a main signal; causing the processor to stop the first operating system and start the second operating system by executing the start code and the second code; and causing the processor to obtain the first control information from the handover data when the second operating system is started. As a result, in a live boot of the second operating system, the first hardware function unit is not initialized, so that the operating system can be updated while maintaining the communication function of a main signal. Furthermore, since the first control information can be obtained when the second operating system is started, a live boot is also possible in a SoC.

(16) A computer program according to this embodiment is a computer program for updating software in a communication device, and causes the communication device to execute the steps of: when software executed by a processor is updated, setting a restart target from among the processor, a first hardware function unit providing a function related to communication of a main signal, and a third hardware function unit providing a function different from the function related to communication of the main signal; and, when the processor and the third hardware function unit are set as the restart targets and the first hardware function unit is not set as the restart target, not outputting a restart command signal to the first hardware function unit and outputting a restart command signal to the processor and the third hardware function unit. As a result, the first hardware function unit is excluded from the restart targets and the processor is included as the restart target, so that software including the operating system can be updated while maintaining the communication function of the main signal.

<Details of the embodiment of the present disclosure>
Hereinafter, the details of the embodiments of the present disclosure will be described with reference to the drawings. Note that at least some of the embodiments described below may be combined in any combination.

[1. Relay system configuration]
FIG. 1 is a schematic diagram showing an example of a configuration of a communication system 10 according to an embodiment. The communication system 10 shown in FIG. 1 is a mobile fronthaul (MFH) included in a mobile communication network. The communication system 10 includes a master station 20 and a slave station 30. The master station 20 is a baseband unit (BBU) in the case of 4G (fourth generation mobile communication system), and is a device having the functions of a centralized unit (CU) and a distributed unit (DU) in the case of 5G (fifth generation mobile communication system). The slave station 30 is a remote radio head (RRH) in the case of 4G, and is a radio unit (RU) in the case of 5G (fifth generation mobile communication system).

The communication system 10 includes a relay system 100 between the master station 20 and the slave station 30. The relay system 100 relays communication between the master station 20 and the slave station 30. Note that in this embodiment, the relay system 100 applied to the MFH is described, but is not limited thereto. The relay system 100 may also be applied to a mobile midhaul (MMH) or a mobile backhaul (MBH).

The relay system 100 includes two opposing communication devices 200. The communication devices 200 are optical transmission devices that comply with OTN (Optical Transport Network), a communication standard defined by the International Telecommunication Union Telecommunication Standardization Sector (ITU-T). One of the communication devices 200 is connected to a master station 20 via an optical fiber cable. The other communication device 200 is connected to a slave station 30 via an optical fiber cable. The two communication devices 200 are connected to each other via a single optical fiber cable 25.

The two communication devices 200 are located at remote locations. The optical fiber cable 25 has a length of, for example, 20 km or more. The optical fiber cable 25 is, for example, a dark fiber.

2. Hardware configuration of communication device
FIG. 2 is a block diagram illustrating an example of a configuration of a communication device according to the embodiment.

The communication device 200 includes a processing circuit 210, a control circuit 220, optical transceivers 231 and 233, a signal processing circuit 232, a PLL (Phase Locked Loop) 234, a second control circuit 241, an L2 switch (Layer 2 switch, also written as "L2SW") 242, a PHY 243, and a transceiver 244.

The processing circuit 210 controls the entire communication device 200. The processing circuit 210 includes a processor 211, a non-volatile memory 212, a volatile memory 213, a communication interface (I/F) 214, an internal communication management unit 215A, a queue management unit 215B, a buffer management unit 215C, and a frame management unit 215D. The processing circuit 210 is an SoC, and the processor 211, the non-volatile memory 212, the volatile memory 213, the communication I/F 214, the internal communication management unit 215A, the queue management unit 215B, the buffer management unit 215C, and the frame management unit 215D are implemented in a single integrated circuit.

The volatile memory 213 is a dynamic random access memory (DRAM). The volatile memory 213 may be a static random access memory (SRAM). The non-volatile memory 212 is writable and may be, for example, a flash memory. The non-volatile memory 212 may be a hard disk. The non-volatile memory 212 stores an operating system (OS) 250, a boot loader 251, a device file 252, a startup program 253, and application software (APP) 254. The operating system 250, the boot loader 251, the startup program 253, and the application software 254 stored in the non-volatile memory 212 are executable program codes. The communication device 200 is configured with a computer, and each function of the communication device 200 is realized by the processor 211 executing the operating system 250 and the application software 254, which are computer programs stored in the storage device of the computer.

The processor 211 is, for example, a CPU (Central Processing Unit). However, the processor 211 is not limited to a CPU. The processor 211 may be a GPU (Graphics Processing Unit). In a specific example, the processor 211 is a multi-core CPU. The processor 211 is configured to be able to execute computer programs.

The operating system 250 manages the entire system of the communication device 200 and provides a common usage environment for the application software 254. The operating system 250 includes a kernel. The boot loader 251 starts after the processor 211 is reset and loads the operating system 250 (its executable program code) into the volatile memory 213. The device file 252 is a driver for controlling each device implemented in the communication device 200. The startup program 253 is a program for live booting the operating system. In other words, the startup program 253 is a program for starting a new operating system (kernel) instead of the boot loader 251 while the operating system 250 is running. The application software 254 is a program for implementing various functions of the communication device 200.

The communication I/F 214 is an Ethernet interface ("Ethernet" is a registered trademark). The communication I/F 214 is used for communication with a terminal device for maintenance management.

The internal communication management unit 215A, queue management unit 215B, buffer management unit 215C, and frame management unit 215D are each hardware circuits. The internal communication management unit 215A manages communications within the SoC. The queue management unit 215B manages queues used for sending and receiving packets between the CPU core and the accelerator (functional unit within the SoC). The buffer management unit 215C manages buffers in the memory area, and acquires and releases buffers upon request. The frame management unit 215D is an Ethernet controller, and performs various offloading operations, and determines and sorts packet types based on protocol or address.

The queue management unit 215B, the buffer management unit 215C, and the frame management unit 215D are examples of a second hardware function unit that provides functions in cooperation with the processor 211.

The control circuit 220 is, for example, a hardware circuit for controlling communication with a terminal device for maintenance management. The control circuit 220 is configured, for example, by an FPGA (Field Programmable Gate Array). However, the configuration of the control circuit 220 is not limited to this. The control circuit 220 may be configured, for example, by a gate array or an ASIC (Application Specific Integrated Circuit).

The control circuit 220 is connected to the processor 211, the optical transceivers 231 and 233, the signal processing circuit 232, the PLL 234, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244 by signal lines. The control circuit 220 includes a restart control unit 221. The control circuit 220 can transmit a reset signal to command a restart to each of the processor 211, the optical transceivers 231 and 233, the signal processing circuit 232, the PLL 234, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244.

The optical transceiver 231 is a client port connected to the parent station 20 or the child station 30 via an optical fiber cable. The optical transceiver 231 is compatible with, for example, 25G Ethernet. The optical transceiver 233 is a communication port connected to the communication device 200, which is the opposing device, via an optical fiber cable 25. The optical transceiver 233 is capable of transmitting and receiving optical signals of, for example, 100 Gbps. The optical transceivers 231 and 233 convert between optical signals and electrical signals.

The signal processing circuit 232 is a hardware circuit for performing a predetermined process on multiple client signals (main signals) received from the parent station 20 or the child station 30. Specifically, the signal processing circuit 232 multiplexes the client signals to generate one multiplexed signal. For example, the signal processing circuit 232 includes a transmission circuit, a reception circuit, and a frame processing circuit (not shown). The reception circuit performs a predetermined signal processing on the electrical signal output from the optical transceiver 231. The communication device 200 is a muxponder. The frame processing circuit has a function of a framer that converts multiple client signals into an OTN frame. The signal processing circuit 232 outputs the generated electrical signal of the OTN frame to the optical transceiver 233. Furthermore, the frame processing circuit has a function of a deframer that converts the OTN frame into multiple client signals. The electrical signal of the OTN frame output from the optical transceiver 233 is given to the frame processing circuit, and multiple client signals are restored from the OTN frame. The transmission circuit performs a predetermined signal processing on the electrical signal, which is the client signal, output from the frame processing circuit, and outputs it to the optical transceiver 231.

The PLL 234 generates a clock signal and supplies the generated clock signal to the optical transceivers 231 and 233 and the signal processing circuit 232.

The optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234 are examples of a first hardware function unit that provides functions related to the communication of the main signal.

The second control circuit 241 is, for example, a hardware circuit for supporting the control circuit 220, and controls communication with a terminal device for maintenance management. The second control circuit 241 is, for example, configured by a programmable logic device such as an FPGA or a gate array, or an ASIC.

The L2 switch 242, PHY 243, and transceiver 244 are used for communication with a terminal device for maintenance management. The communication I/F 214 is connected to a port of the L2 switch 242. Another port of the L2 switch 242 is connected to the transceiver 244 via the PHY 243. The transceiver 244 includes an RJ45 connector, and an Ethernet cable connector is connected to the transceiver 244. The PHY 243 is an Ethernet physical transceiver.

The second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244 are examples of a third hardware function unit that provides functions different from the functions related to the communication of main signals.

3. Functions of communication devices
3 is a block diagram showing an example of the functions of the communication device according to the embodiment. The communication device 200 has the functions of a first storage processing unit 211A, a handover data generating unit 211B, a second storage processing unit 211C, a switching processing unit 211D, a control information acquisition processing unit 211E, a restart target setting unit 211F, an information saving unit 211G, a recovery unit 211H, and a notification unit 211I.

The communication device 200 according to this embodiment can select and execute a process of updating the firmware of an application or the control circuit 220 while the operating system is running (hereinafter also referred to as the "conventional method"), a process of updating software by live boot (hereinafter also referred to as the "live boot method"), and a process of updating software by selecting a reboot target (hereinafter also referred to as the "reboot target selection method"). The conventional method is, for example, a software update method disclosed in Japanese Patent Application Laid-Open No. 2014-78784. The conventional method, the live boot method, and the reboot target selection method all allow software updates to be performed while maintaining main signal communication.

Figure 4 is a diagram for explaining the combination of software to be updated in each of the conventional method, the live boot method, and the restart target selection method. In the conventional method, the boot loader and the operating system cannot be updated. Therefore, if either or both of the boot loader and the operating system are included in the update target, the conventional method is not selected. If either or both of the application software (written as "application" in Figure 4) and the firmware of the control circuit 220 (hereinafter also simply referred to as "firmware") are the update target, the conventional method is selected. In the live boot method, the operating system can be updated, but the boot loader cannot be updated. Therefore, if the update target includes the operating system and not the boot loader, the live boot method is selected. In the restart target selection method, the boot loader can be updated. Therefore, if the update target includes the boot loader, the restart target selection method is selected. In the restart target selection method, if the update target includes the boot loader, the update target may also include the operating system.

Refer to FIG. 3 again. The first storage processing unit 211A restarts the processor 211 and starts the operating system 250 by bootstrap (hereinafter referred to as "normal boot"). FIG. 5A is a diagram explaining the data loaded into the volatile memory in a normal boot. The first storage processing unit 211A executes the boot loader 251 and loads (stores) the first operating system 250A and the first device file 252A into the volatile memory 213. The first operating system 250A is the operating system before the update. The first device file 252A is a device file used by the first operating system 250A. The first device file 252A is used by the first operating system 250A to control the communication I/F 214, the internal communication management unit 215A, the queue management unit 215B, the buffer management unit 215C, the frame management unit 215D, the control circuit 220, the optical transceivers 231 and 233, the signal processing circuit 232, the PLL 234, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244.

In a normal boot, when the processing circuit 210, which is an SoC, restarts, the processor 211 executes initialization processing such as loading microcode before starting the boot loader. When the initialization is complete, bootstrap is executed and the operating system starts up. Furthermore, the processor 211 acquires first control information, which is control information for the queue management unit 215B, the buffer management unit 215C, and the frame management unit 215D. The first control information is information, such as a memory address, used to control each of the queue management unit 215B, the buffer management unit 215C, and the frame management unit 215D. The first control information is used by the operating system 250 and the application software 254.

Refer to FIG. 3 again. The handover data generating unit 211B generates handover data from the acquired first control information. The handover data is data for providing the first control information to the live-booted operating system. FIG. 6A is a diagram showing an example of handover data. The first control information stored in the non-volatile memory 212 includes queue control information used to control the queue management unit 215B, buffer control information used to control the buffer management unit 215C, and frame control information used to control the frame management unit 215D. The handover data generating unit 211B extracts each of the queue control information, buffer control information, and frame control information from the first control information to generate handover data 300. For example, the handover data 300 is data in a TLV (type-length-value) format. In the handover data 300, the queue control information is associated with the type "1" assigned to the queue control information and the length "X" of the queue control information. The buffer control information is associated with a type "2" assigned to the buffer control information and a length "Y" of the buffer control information. The frame control information is associated with a type "3" assigned to the frame control information and a length "Z" of the frame control information.

[3.1. Live Boot Method]
Referring again to FIG. 3, the second storage processing unit 211C is an example of a storage processing unit. The second storage processing unit 211C performs live boot of the updated operating system. FIG. 5B is a diagram for explaining data loaded into the volatile memory in the live boot. The second storage processing unit 211C loads (stores) the boot program 253, the second operating system 250B, and the second device file 252B into the volatile memory 213 without initializing the processor 211, the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234 (i.e., the first hardware function unit). The storage areas in the volatile memory 213 for the boot program 253, the second operating system 250B, and the second device file 252B are different areas from the storage areas for the first operating system and the first device file 252A. The second operating system 250B is the operating system after the update. The second device file 252B is a device file used by the second operating system 250B. The second device file 252B is used for control by the second operating system 250B of the communication I/F 214, the internal communication management unit 215A, the queue management unit 215B, the buffer management unit 215C, the frame management unit 215D, the high-speed I/O management unit 215E, the control circuit 220, the optical transceivers 231, 233, the signal processing circuit 232, the PLL 234, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244.

The second storage processing unit 211C further loads the handover data 300 generated by the handover data generation unit 211B into the volatile memory 213.

Referring again to FIG. 3, the switching processing unit 211D causes the processor 211 to stop the first operating system 250A and execute the startup program 253 and the second operating system 250B. In other words, the switching processing unit 211D switches the execution target from the first operating system 250A to the second operating system 250B. This starts up the second operating system 250B.

When the second operating system 250B is started, the switching processing unit 211D provides the processor 211 with notification information indicating that it is a live boot. One example of the notification information is a flag indicating that it is a live boot, and another example is a command line indicating that it is a live boot. For example, the switching processing unit 211D saves the notification information before the first operating system 250A is stopped. When the second operating system 250B is started, the switching processing unit 211D provides the saved notification information to the processor 211. This allows the processor 211 to determine whether the current startup of the operating system is a live boot or not.

When the second operating system 250B is started, the control information acquisition processing unit 211E causes the processor 211 to acquire the first control information from the handover data 300 loaded into the volatile memory 213. In a live boot, the processing circuit 210, which is a SoC, is not restarted. In a normal boot, the control information (first control information) of the queue management unit 215B, the buffer management unit 215C, and the frame management unit 215D is acquired, but in a live boot that does not involve restarting the SoC, the first control information already acquired in the normal boot is not acquired. For this reason, when notification information is provided to the processor 211, the control information acquisition processing unit 211E can cause the processor 211 to acquire the first control information from the handover data 300. If the notification information is a flag, the processor 211 refers to the flag and determines whether the current startup of the operating system is a live boot. If the flag is set, the processor 211 acquires the first control information from the handover data 300. If the notification information is a command line, the command line is provided to the processor 211 in the bootstrap. The processor 211 determines whether the current boot of the operating system is a live boot based on the command line. If a command line indicating a live boot is given, the processor 211 obtains the first control information from the handover data 300.

Updating the operating system may add a function that uses new hardware functions of the processing circuit 210. For example, assume that a function that uses the high-speed I/O management unit 215E (see FIG. 2) that was not used in the first operating system 250A is added to the second operating system 250B. When the second operating system 250B is started by live boot, the first control information does not include control information for the high-speed I/O management unit 215E, so the processor 211 cannot obtain the control information for the high-speed I/O management unit 215E from the handover data 300. The control information for the high-speed I/O management unit 215E is obtained by the processor 211 from the processing circuit 210 when the second operating system 250B is started.

The control information acquisition processing unit 211E adds the second control information acquired at the time of booting the second operating system 250B to the handover data 300. The second control information is control information used to control the second hardware function unit that was not used in the first operating system 250A, and is control information acquired by the processor 211 at the time of booting the second operating system 250B. The control information of the high-speed I/O management unit 215E described above is an example of the second control information. FIG. 6B is a diagram for explaining an example of adding the second control information to the handover data. The control information acquisition processing unit 211E assigns type "4" to the high-speed I/O control information, which is the control information of the high-speed I/O management unit 215E, and generates a data string 300A in which the type "4" and the length "N" of the high-speed I/O control information correspond to the high-speed I/O control information. The control information acquisition processing unit 211E adds the generated data string 300A to the handover data 300. The handover data 300 with the second control information added is stored in the non-volatile memory 212 for the next live boot.

[3.2. Restart target selection method]
7A is a diagram showing an example of a restart target in a normal boot, and FIG. 7B is a diagram showing an example of a restart target in a restart target selection method. In a normal boot, when the updated software is stored in the non-volatile memory 212, the processor 211 transmits a reset request to the control circuit 220. When the control circuit 220 receives the reset request, it transmits a reset signal to each part of the communication device 200, that is, the processor 211, the optical transceivers 231 and 233, the signal processing circuit 232, the PLL 234, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244. The reset signal is a restart instruction signal. When the processor 211, the optical transceivers 231 and 233, the signal processing circuit 232, the PLL 234, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244 receive the reset signal, they are restarted. Furthermore, the control circuit 220 that transmitted the reset signal is also restarted. In such a normal boot, the first hardware functional unit, that is, the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234 are restarted, and therefore main signal communication is interrupted during the software update.

Refer back to FIG. 3. In the restart target selection method, the first hardware function unit, i.e., the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234, are not restarted during a software update. Therefore, main signal communication is maintained during the software update. The restart target setting unit 211F sets the restart target when the software executed by the processor 211 is updated. Specifically, the restart target setting unit 211F sets the processor 211, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244 as the restart targets.

Refer to FIG. 7B. The restart target setting unit 211F notifies the control circuit 220 of the restart target that has been set. The control circuit 220 transmits a reset signal to the restart target. That is, a reset signal is transmitted to the processor 211, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244, but a reset signal is not transmitted to the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234. The processor 211, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244 are restarted, and the software is updated.

Referring again to FIG. 3, when the processor 211 restarts, the first storage processing unit 211A executes a normal boot.

[3.3. Common Processing]
Next, a common process between the live boot method and the restart target selection method will be described. When the application software 254 executed by the processor 211 controls the signal processing circuit 232 or the optical transceivers 231 and 233, the setting information and status information of the signal processing circuit 232 or the optical transceivers 231 and 233 are stored in an internal table of the application software 254. The setting information of the signal processing circuit 232 is, for example, information on a communication path. The setting information of the optical transceivers 231 and 233 is, for example, information indicating a setting value for enabling/disabling transmission and a setting value for an operation mode. The status information of the signal processing circuit 232 is, for example, information indicating an abnormality such as an alarm or warning, a value of a transmission/reception counter, etc. The status information of the optical transceivers 231 and 233 is, for example, information indicating a cable insertion/removal state, information indicating an abnormality such as an alarm or warning, a value of a transmission/reception power, etc.

The application software 254 uses the setting information and state information in the internal table to control the signal processing circuit 232 or the optical transceivers 231 and 233. When such application software 254 is updated, the internal table is initialized. In the live boot method or the restart target selection method, the signal processing circuit 232 and the optical transceivers 231 and 233 are not restarted, so the application software 254 after restart may not be able to obtain the setting information. During the software update, the state of the signal processing circuit 232 and the optical transceivers 231 and 233 may change. For this reason, before the software update using the live boot method or the restart target selection method, the information saving unit 211G saves the setting information and state information stored in the internal table of the application software 254 to the non-volatile memory 212, and the recovery unit 211H restores the internal table of the application software 254 using the setting information saved after the software update. Furthermore, if the saved status information differs from the status of the signal processing circuit 232 or the optical transceivers 231 and 233 after the software update, the notification unit 211I notifies the user.

FIG. 8A is a diagram for explaining the saving of setting information and state information. Before updating the application software 254 for controlling the signal processing circuit 232 and/or the optical transceivers 231 and 233 using the live boot method or the restart target selection method, the information saving unit 211G generates saved data 500 including the setting information 412A, 413A and state information 412B, 413B included in the internal table 411 of the application software 254A before the update. The information saving unit 211G stores the generated saved data 500 in the non-volatile memory 212. Note that if it is known in advance that the software update will be performed using the live boot method that does not involve restarting the processor 211, the saved data 500 may be stored in the volatile memory 213.

Figure 8B is a diagram explaining the recovery of the internal table. After the application software 254 is updated, the recovery unit 211H writes the setting information 412A, 413A contained in the saved data 500 to the internal table 421 of the updated application software 254B. This causes the internal table 421 to be recovered.

Refer to FIG. 3 again. The processor 211 can obtain the status information from the signal processing circuit 232 and the optical transceivers 231 and 233 even after the application software 254 is updated. The notification unit 211I compares the current status information of the signal processing circuit 232 and the optical transceivers 231 and 233 with the status information 412B and 413B included in the saved data 500. If there is a difference between the current status information of the signal processing circuit 232 and the optical transceivers 231 and 233 and the status information 412B and 413B included in the saved data 500, the notification unit 211I determines that the status of the signal processing circuit 232 or the optical transceivers 231 and 233 has changed during the software update, and notifies the user that the status of the signal processing circuit 232 or the optical transceivers 231 and 233 has changed. The notification can be made, for example, by sending a packet containing information indicating that the state of the signal processing circuit 232 or the optical transceivers 231 and 233 has changed to a maintenance and management terminal device.

4. Software update operation of communication device
FIG. 9 is a flowchart illustrating an example of a software update operation of the communication device according to the embodiment.

The new software is provided to the user by storing it in a non-volatile memory such as a flash memory, or is downloaded to the communication device 200 from a server (not shown). The software update file contains image data of the updated software. The processor 211 checks the versions of the current software (operating system 250, boot loader 251, application software 254, and firmware of the control circuit 220) (step S1). The processor 211 checks the image data contained in the update file (step S2), and checks the software to be updated, for example, by referring to the version of the updated software contained in the header of the update file (step S3).

The processor 211 determines whether the update target includes an operating system or a boot loader (step S4). If the update target does not include an operating system or a boot loader (NO in step S4), the processor 211 executes an uninterrupted software update using the conventional method (step S5).

If the update target includes the operating system or the boot loader (YES in step S4), the processor 211 executes an information evacuation process (step S6). In the information evacuation process, evacuation data 500 including the setting information 412A, 413A and the state information 412B, 413B included in the internal table 421 of the application software 254 is generated, and the evacuation data 500 is saved in the non-volatile memory 212.

The processor 211 determines whether the update target includes a boot loader (step S7). If the update target includes a boot loader (YES in step S7), the processor 211 executes a reboot target selection update process (step S8). If the update target does not include a boot loader (NO in step S7), the processor 211 executes a live boot update process (step S9).

The restart target selection update process is an uninterrupted software update using the restart target selection method. Figure 10 is a flowchart showing an example of the restart target selection update process.

The processor 211 installs the new version of the software into the non-volatile memory 212 (step S101).

The processor 211 sets the processor 211, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244 as targets for restart (step S102). The first hardware function unit, i.e., the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234, are excluded from the targets for restart.

The processor 211 notifies the control circuit 220 of the restart target that has been set (step S103). The control circuit 220 transmits a reset signal to the restart target, and also resets the control circuit 220 itself. The processor 211 receives the reset signal and resets (restarts) the processor 211 (step S104).

The processor 211 loads the boot loader 251, the operating system 250, and the device file 252 into the volatile memory 213 (step S105). In the reboot target selection method, the boot loader 251 is included in the update targets. Therefore, the updated boot loader is loaded. If the update targets include the operating system, the updated operating system is loaded. If the update targets do not include the operating system, the same operating system as before the reboot is loaded.

The processor 211 executes the boot loader 251 loaded in the volatile memory 213 and starts the bootstrap (step S106). The processor 211 then starts the operating system 250 loaded in the volatile memory 213 (step S107). That is, in this case, the operating system is started by normal boot.

In normal boot, the processor 211 acquires first control information of the queue management unit 215B, the buffer management unit 215C, and the frame management unit 215D included in the SoC during the boot sequence (step S108). After starting the operating system, the processor 211 generates handover data 300 from the acquired first control information (step S109). The processor 211 saves the generated handover data 300 in the non-volatile memory 212 (step S110). This completes the restart target selection update process.

The live boot update process is an uninterrupted software update using the live boot method. Figure 11 is a flowchart showing an example of the live boot update process.

The processor 211 installs the new version of the software into the non-volatile memory 212 (step S201).

The processor 211 loads the startup program 253, the operating system 250, and the device file 252 into the volatile memory 213 without resetting the processor 211, i.e., while the operating system is running (step S202). In the live boot method, the boot loader 251 is not loaded into the volatile memory 213. Instead, the startup program 253 is loaded. In the live boot method, the operating system 250 is included in the update target. Therefore, the updated second operating system 250B and the second device file 252B used by the second operating system 250B are loaded into the volatile memory 213.

The processor 211 further loads the handover data stored in the non-volatile memory 212 into the volatile memory 213 (step S203).

Next, the processor 211 stores the live boot notification information in the non-volatile memory 212 (step S204).

The processor 211 stops the running operating system, i.e., the first operating system 250A (step S205).

The processor 211 executes the startup program 253 loaded into the volatile memory 213 (step S206). Furthermore, the processor 211 starts the updated operating system, i.e., the second operating system 250B, in accordance with the startup program 253 (step S207).

The processor 211 checks the notification information and determines whether the operating system is being started by live boot (step S208). If it is determined that the operating system is being started by live boot, the processor 211 obtains the first control information from the handover data loaded into the volatile memory 213 (step S209).

When a hardware function unit of the processing circuit 210 that was not used in the first operating system 250A is to be newly used in the second operating system 250B, the processor 211 acquires second control information, which is control information for the hardware function unit, when the second operating system is started (step S210). The processor 211 adds the acquired second control information to the handover data 300 (step S211). This makes it possible to provide the control information to the processor 211 when the operating system is started up by the next live boot. Note that if there is no hardware function unit to be newly used in the second operating system 250B, steps S210 and S211 are skipped. This completes the live boot update process.

Refer to FIG. 9 again. When the restart target selection update process or the live boot update process is completed, the processor 211 executes a recovery process (step S10). In the recovery process, the setting information 412A, 413A included in the saved data 500 is written to the internal table 421 of the application software 254. Furthermore, the processor 211 executes a notification process (step S11). In the notification process, if there is a difference between the current state information of the signal processing circuit 232 and the optical transceivers 231, 233 and the state information 412B, 413B included in the saved data 500, the user is notified that the state of the signal processing circuit 232 or the optical transceivers 231, 233 has changed during the software update. Note that if there is no difference between the current state information of the signal processing circuit 232 and the optical transceivers 231, 233 and the state information 412B, 413B included in the saved data 500, step S11 is skipped. With this, the software update operation of the communication device 200 is completed.

5. Modifications
In the above embodiment, the configuration is described in which the reboot target selection update process and the live boot update process are selected according to the software to be updated, but the present invention is not limited to this. When the boot loader is not included in the update target and the operating system is included in the update target, the configuration may be such that only the reboot target selection update process is executed, or the configuration may be such that only the live boot update process is executed.

In the above-described embodiment, the relay system 100 applied to a mobile communication system has been described, but is not limited to this. The relay system 100 may be applied to a communication system other than a mobile communication system. Furthermore, the communication device 200 included in the relay system 100 is an optical transmission device that complies with OTN, but is not limited to this. The communication device 200 may be an optical transmission device that does not comply with OTN, or may be a transmission device that transmits an electrical signal instead of an optical signal.

[6. Effects]
The communication device 200 includes a volatile memory 213 for storing data, a processor 211 capable of reading data stored in the volatile memory 213, optical transceivers 231 and 233, a signal processing circuit 232, and a PLL 234 (first hardware function unit), a queue management unit 215B, a buffer management unit 215C, and a frame management unit 215D (second hardware function unit), a second storage processing unit 211C (storage processing unit), a switching processing unit 211D, and a control information acquisition processing unit 211E. The optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234 provide functions related to communication of main signals. The queue management unit 215B, the buffer management unit 215C, and the frame management unit 215D provide functions in cooperation with the processor 211. The second storage processing unit 211C loads (stores) the boot program 253, the second operating system 250B, and the handover data 300 in an area in the volatile memory 213 different from the storage area of the first operating system 250A, which is the operating system before the update, without initializing the processor 211, the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234. The boot program 253 is a boot code for booting the second operating system 250B, which is the operating system after the update. The handover data 300 includes first control information used for the control of the queue management unit 215B, the buffer management unit 215C, and the frame management unit 215D by the first operating system 250A. The switching processing unit 211D causes the processor 211 to stop the first operating system 250A and execute the boot program 253 and the second operating system 250B, thereby booting the second operating system 250B. When the second operating system 250B is started, the control information acquisition processing unit 211E causes the processor 211 to acquire the first control information from the handover data 300. This allows the second operating system 250B to be live booted on the running first operating system 250A. In the live boot of the second operating system 250B, the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234 are not initialized, so that the operating system can be updated while maintaining the communication function of the main signal. Since the processor 211 can acquire the first control information when the second operating system 250B is started, live boot is also possible in the SoC.

The switching processing unit 211D may provide the processor 211 with notification information indicating that the second operating system 250B will be started by a live boot when the second operating system 250B is started. When the notification information is provided to the processor 211, the control information acquisition processing unit 211E may cause the processor 211 to acquire the first control information from the handover data 300. This allows the control information acquisition processing unit 211E to determine whether the startup of the operating system 250 is a normal startup via bootstrap or a live boot, depending on whether the notification information is provided to the processor 211. In the case of a live boot, the processor 211 can acquire the first control information when the second operating system 250B is started.

The volatile memory 213, the processor 211, the queue management unit 215B, the buffer management unit 215C, and the frame management unit 215D may be included in a single integrated circuit. This allows the communication device 200 to be configured using a SoC.

The communication device 200 may further include a handover data generation unit 211B. The handover data generation unit 211B generates handover data 300 based on the first control information acquired by the processor 211 when the first operating system 250A is started, and stores the generated handover data 300 in the non-volatile memory 212. The second storage processing unit 211C may store the handover data 300 stored in the non-volatile memory 212 in the volatile memory 213. This allows the handover data 300 to be loaded into the volatile memory 213 when the second operating system 250B is started.

The control information acquisition processing unit 211E may add the second control information to the handover data 300 if the second control information is acquired by the processor 211 when the second operating system 250B is started. The second control information is information used for control of the second hardware function unit by the second operating system 250B. This makes it possible to add the second control information that was not required by the first operating system 250A but is required by the second operating system 250B to the handover data 300 for the next live boot.

The communication device 200 includes a processor 211 capable of executing software, optical transceivers 231 and 233, a signal processing circuit 232, and a PLL 234 (first hardware function unit), a second control circuit 241, an L2 switch 242, a PHY 243, and a transceiver 244 (third hardware function unit), a control circuit 220, and a restart target setting unit 211F. The optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234 provide functions related to communication of main signals. The second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244 provide functions different from the functions related to communication of main signals. The control circuit 220 is capable of outputting a reset signal, which is a restart command signal, to the processor 211, the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234, as well as the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244. The restart target setting unit 211F sets a target for restart when software executed by the processor 211 is updated. When the processor 211, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244 are set as targets for restart by the restart target setting unit 211F, and the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234 are not set as targets for restart, the control circuit 220 outputs a reset signal to the processor 211, the second control circuit 241, the L2 switch 242, the PHY 243, and the transceiver 244, and does not output a reset signal to the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234. As a result, the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234 are excluded from targets for restart, and the processor 211 is included as a target for restart, so that software including the operating system 250 can be updated while maintaining the communication function of the main signal.

When the control circuit 220 outputs a reset signal, the control circuit 220 may be restarted. This allows the control circuit 220 to be included as a target for restart.

The software to be updated may include the operating system 250. This allows the operating system 250 to be updated while maintaining the communication function of the main signal.

The software to be updated may include the boot loader 251. This allows the boot loader 251, which requires the processor 211 to be restarted, to be updated while maintaining the communication function of the main signal.

The first hardware function unit may include optical transceivers 231, 233 that transmit and receive a main signal, a signal processing circuit 232 for processing the main signal, and a PLL 234 that supplies a clock signal to the optical transceivers 231, 233 and the signal processing circuit 232. This makes it possible to update software including the operating system 250 without initializing the optical transceivers 231, 233, the signal processing circuit 232, and the PLL 234.

The communication device 200 may include an information saving unit 211G and a restoration unit 211H. Before updating the application software 254 for controlling the optical transceivers 231 and 233, the signal processing circuit 232, and the PLL 234, the information saving unit 211G stores the setting information 412A, 413A of the optical transceivers 231 and 233 and the signal processing circuit 232 contained in the internal table 411 of the application software 254 in the non-volatile memory 212. After updating the application software 254, the restoration unit 211H restores the setting information 412A, 413A stored in the non-volatile memory 212 as the internal table 421 of the updated application software 254. This allows the setting information 412A, 413A of the optical transceivers 231 and 233 and the signal processing circuit 232, which is lost from the internal table 421 when the application software 254 is updated, to be restored after the application software 254 is updated.

The information saving unit 211G may store the status information 412B, 413B of the optical transceivers 231, 233 and the signal processing circuit 232 contained in the internal table 411 in the non-volatile memory 212. The communication device 200 may further include a notification unit 211I. The notification unit 211I notifies the user when there is a difference between the status information indicating the current status of the optical transceivers 231, 233 and the signal processing circuit 232 and the status information stored in the non-volatile memory 212. In this way, if the status of the optical transceivers 231, 233 and the signal processing circuit 232 changes during a software update, the user can be notified of the change after the software update.

[7. Supplementary Notes]
The embodiments disclosed herein are illustrative in all respects and are not restrictive. The scope of the present invention is defined by the claims rather than the above-described embodiments, and includes the meaning equivalent to the claims and all modifications within the scope thereof.

REFERENCE SIGNS LIST 10 Communication system 20 Parent station 25 Optical fiber cable 30 Child station 100 Relay system 200 Communication device 210 Processing circuit 211 Processor 211A First storage processing unit 211B Handover data generation unit 211C Second storage processing unit 211D Switching processing unit 211E Control information acquisition processing unit 211F Restart target setting unit 211G Information evacuation unit 211H Recovery unit 211I Notification unit 212 Non-volatile memory 213 Volatile memory 214 Communication interface (communication I/F)
215A Internal communication management unit 215B Queue management unit (second hardware function unit)
215C Buffer Management Unit (Second Hardware Function Unit)
215D Frame Management Unit (Second Hardware Function Unit)
215E High-speed I/O management unit 220 Control circuit 221 Restart control unit 231, 233 Optical transceiver (first hardware function unit)
232 signal processing circuit (first hardware function unit)
234 PLL (first hardware function unit)
241 Second control circuit (third hardware function unit)
242 L2 switch (third hardware function unit)
243 PHY (third hardware function unit)
H.244 Transceiver (TRx) (third hardware function unit)
250 Operating system 250A First operating system 250B Second operating system 251 Boot loader 252 Device file 252A First device file 252B Second device file 253 Startup program 254, 254A, 254B Application software 300 Inheritance data 300A Data string 411, 421 Internal table 412A, 413A Setting information 412B, 413B Status information 500 Saved data

Claims (10)

A memory for storing data;
A processor capable of reading data stored in the memory;
A first hardware function unit that provides a function related to communication of a main signal;
A second hardware function unit that provides a function in cooperation with the processor;
a storage processing unit that stores handover data including a startup code for starting a second operating system, which is an operating system after the update, without initializing the processor, without initializing the processor and the first hardware function unit, a second code that is an executable code of the second operating system, and first control information used for controlling the second hardware function unit by a first operating system, which is an operating system before the update, in an area different from a storage area in the memory for a first code that is the executable code of the first operating system;
a switching processing unit that causes the processor to stop the first operating system and execute the startup code and the second code to start up the second operating system;
a control information acquisition processing unit that causes the processor to acquire the first control information from the handover data when the second operating system is started;
Equipped with
Communications equipment. the switching processing unit, when starting up the second operating system, provides notification information to the processor indicating that the second operating system will be started up without initializing the processor;
the control information acquisition processing unit, when the notification information is provided to the processor, causes the processor to acquire the first control information from the handover data;
The communication device according to claim 1 . the memory, the processor, and the second hardware function are included in a single integrated circuit;
The communication device according to claim 1 or 2. a takeover data generating unit that generates the takeover data based on the first control information acquired by the processor when the first operating system is started, and stores the generated takeover data in a storage device;
The storage processing unit stores the takeover data stored in the storage device in the memory.
The communication device according to any one of claims 1 to 3. the control information acquisition processing unit adds second control information to the handover data when second control information used for control of the second hardware function unit by the second operating system is acquired by the processor at the time of booting of the second operating system.
The communication device according to any one of claims 1 to 4. the first hardware functional unit includes a transceiver for transmitting and receiving the main signal, a signal processing circuit for processing the main signal, and a clock generator for supplying a clock signal to the transceiver and the signal processing circuit;
The communication device according to any one of claims 1 to 5 . an information saving unit configured to store, in a storage device, setting information of the first hardware function unit, which is included in internal information of the software, before updating the software for controlling the first hardware function unit, which is executed by the processor;
a recovery unit that recovers the setting information stored in the storage device after updating the software as internal information of the updated software;
Further comprising:
The communication device according to any one of claims 1 to 6 . the information saving unit stores state information of the first hardware function unit included in the internal information in the storage device;
the communication device further includes a notification unit that notifies a user when there is a difference between state information indicating a current state of the first hardware function unit and the state information stored in the storage device;
The communication device according to claim 7 . A software updating method for updating software in a communication device, comprising:
storing handover data including a start-up code for starting a second operating system, which is an operating system after the update, without initializing the processor and a first hardware function unit providing a function related to communication of a main signal, without initializing the processor , a second code which is an executable code of the second operating system, and first control information used for controlling the second hardware function unit providing a function linked to the processor by the first operating system, which is an operating system before the update, in an area different from the storage area in a memory of the first code which is the executable code of the first operating system;
causing the processor to stop the first operating system and to start the second operating system by executing the start-up code and the second code;
when the second operating system is started, causing the processor to obtain the first control information from the handover data;
Including,
How to update software. 1. A computer program product for updating software in a communication device, comprising:
The communication device includes:
storing handover data including a start-up code for starting a second operating system, which is an operating system after the update, without initializing the processor and a first hardware function unit providing a function related to communication of a main signal, without initializing the processor , a second code which is an executable code of the second operating system, and first control information used for controlling the second hardware function unit providing a function linked to the processor by the first operating system, which is an operating system before the update, in an area different from the storage area in a memory of the first code which is the executable code of the first operating system;
causing the processor to stop the first operating system and to start the second operating system by executing the start-up code and the second code;
when the second operating system is started, causing the processor to obtain the first control information from the handover data;
Execute the
Computer program.

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