JP7655201B2 - Semiconductor Device - Google Patents

Description

This disclosure relates to a semiconductor device.

A silicon carbide semiconductor device with a built-in Miller clamp circuit to suppress false ignition in an inverter circuit has been proposed (Patent Document 1).

JP 2016-174033 A

The structure of a silicon carbide semiconductor device that incorporates a Miller clamp circuit is more complex than that of a silicon carbide semiconductor device that does not incorporate a Miller clamp circuit. This makes it easier for the yield to decrease. Furthermore, to manufacture a silicon carbide semiconductor device that incorporates a Miller clamp circuit, a process is required just for forming the Miller clamp circuit. For these reasons, the manufacturing cost of a silicon carbide semiconductor device that incorporates a Miller clamp circuit is significantly higher than the manufacturing cost of a silicon carbide semiconductor device that does not incorporate a Miller clamp circuit.

The present disclosure aims to provide a semiconductor device that can suppress false firing while suppressing increases in cost.

The semiconductor device disclosed herein includes a first semiconductor chip having a first semiconductor substrate, a first control electrode, a first main electrode, and a second main electrode, and a second semiconductor chip having a second semiconductor substrate, a second control electrode, a third main electrode, and a fourth main electrode and mounted on the first semiconductor chip, the first semiconductor substrate having a first main surface and a second main surface opposite the first main surface, the second semiconductor substrate having a third main surface facing the first main surface and a fourth main surface opposite the third main surface, the first control electrode and the first main electrode are provided on the first main surface, the second control electrode and the third main electrode are provided on the fourth main surface, the fourth main electrode is provided on the third main surface, a first connection member electrically connecting the first main electrode and the fourth main electrode, and a second connection member electrically connecting the first control electrode and the third main electrode.

This disclosure makes it possible to prevent false firing while minimizing increases in costs.

FIG. 1 is a top view showing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 3 is a circuit diagram showing the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing a semiconductor device according to the second embodiment. FIG. 5 is a top view showing a wiring board included in the second embodiment. FIG. 6 is a cross-sectional view showing a wiring board included in the second embodiment.

The form for implementing this is explained below.

[Description of the embodiments of the present disclosure]
First, the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[1] A semiconductor device according to one aspect of the present disclosure includes a first semiconductor chip having a first semiconductor substrate, a first control electrode, a first main electrode, and a second main electrode, and a second semiconductor chip having a second semiconductor substrate, a second control electrode, a third main electrode, and a fourth main electrode and mounted on the first semiconductor chip, the first semiconductor substrate having a first main surface and a second main surface opposite the first main surface, the second semiconductor substrate having a third main surface facing the first main surface and a fourth main surface opposite the third main surface, the first control electrode and the first main electrode are provided on the first main surface, the second control electrode and the third main electrode are provided on the fourth main surface, the fourth main electrode is provided on the third main surface, a first connection member electrically connecting the first main electrode and the fourth main electrode, and a second connection member electrically connecting the first control electrode and the third main electrode.

When the first semiconductor chip is turned off, the second semiconductor chip is turned on to short-circuit the first control electrode and the first main electrode of the first semiconductor chip, thereby suppressing false firing. Since there is no need to incorporate a Miller clamp circuit in the first semiconductor chip, the increase in costs associated with the creation of a Miller clamp circuit can be suppressed.

[2] In [1], the first connection member may have a first solder layer provided between the first main electrode and the fourth main electrode. In this case, it is easy to connect the first main electrode and the fourth main electrode.

[3] In [1], the first connection member may have a second solder layer provided on the first main electrode, a wiring board provided on the second solder layer, and a third solder layer provided on the wiring board, and the wiring board may have an insulating substrate having a fifth main surface facing the first main surface and a sixth main surface opposite the fifth main surface and facing the third main surface, a first conductive layer provided on the fifth main surface and connected to the first main electrode by the second solder layer, a second conductive layer provided on the sixth main surface and connected to the fourth main electrode by the third solder layer, and a conductive via that electrically connects the first conductive layer and the second conductive layer. In this case, since the thermal conductivity of the insulating substrate is relatively low, the transfer of heat generated in the first semiconductor chip to the second semiconductor chip can be suppressed.

[4] In [1] to [3], the first semiconductor chip may be a field effect transistor chip of a first conductivity type, and the second semiconductor chip may be a field effect transistor chip of a second conductivity type. In this case, the second semiconductor chip can be easily used as a Miller clamp circuit for the first semiconductor chip.

[5] In [1] to [4], the second connection member may have a bonding wire that connects the first control electrode and the third main electrode. In this case, it is easy to connect the first control electrode and the third main electrode.

[6] In [1] to [5], the first semiconductor chip may be a silicon carbide semiconductor chip, and the second semiconductor chip may be a silicon semiconductor chip. In this case, the first semiconductor chip can achieve high-speed operation, while the second semiconductor chip can be easily used as a Miller clamp circuit for the first semiconductor chip.

[7] In [1] to [6], the second main electrode may be provided on the second main surface. In this case, the first semiconductor chip can have a vertical structure, making it easier to obtain good breakdown voltage.

[8] In [1] to [7], the semiconductor device may further include a first external terminal electrically connected to the first control electrode, a second external terminal electrically connected to the first main electrode, a third external terminal electrically connected to the second main electrode, a fourth external terminal electrically connected to the second control electrode, and a sealing resin that seals the first semiconductor chip and the second semiconductor chip, and each of the first external terminal, the second external terminal, the third external terminal, and the fourth external terminal may be partially covered with the sealing resin. In this case, it is easy to realize a discrete package.

[9] In [1] to [8], the first control electrode may be a gate electrode, the first main electrode may be a source electrode, the second main electrode may be a drain electrode, the second control electrode may be a gate electrode, the third main electrode may be a source electrode, and the fourth main electrode may be a drain electrode. In this case, field effect transistors can be used as the first semiconductor chip and the second semiconductor chip.

[Details of the embodiment of the present disclosure]
Hereinafter, the embodiments of the present disclosure will be described in detail, but the present embodiment is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to omit redundant description. In this specification and drawings, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is defined as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is defined as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is defined as the ZX plane. For convenience, the Z1 direction is defined as the upward direction, and the Z2 direction is defined as the downward direction. In addition, in this disclosure, planar view refers to viewing an object from the Z1 side.

First Embodiment
First, a first embodiment will be described. Fig. 1 is a top view showing a semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. Fig. 2 shows a cross section taken along line II-II in Fig. 1.

As shown in Figures 1 and 2, the semiconductor device 1 according to the first embodiment mainly includes a first semiconductor chip 100, a second semiconductor chip 200, a lead frame 300, and a sealing resin 400.

The first semiconductor chip 100 is, for example, a MOS field effect transistor (FET) chip. The first semiconductor chip 100 has a silicon carbide substrate 110, a gate electrode 121, a source electrode 122, and a drain electrode 123. The first semiconductor chip 100 is an N-channel FET, and the silicon carbide substrate 110 includes two N-type regions and one P-type region that constitute the FET. The source electrode 122 is electrically connected to one N-type region, and the drain electrode 123 is electrically connected to the other N-type region. The gate electrode 121 controls the potential of the P-type region through a gate insulating film. The silicon carbide substrate 110 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101. The gate electrode 121 and the source electrode 122 are provided on the first main surface 101, and the drain electrode 123 is provided on the second main surface 102. The silicon carbide substrate 110 is an example of a first semiconductor substrate. The silicon carbide substrate 110 may include a silicon carbide single crystal substrate and a silicon carbide epitaxial layer formed on the silicon carbide single crystal substrate. The gate electrode 121 is an example of a first control electrode, the source electrode 122 is an example of a first main electrode, and the drain electrode 123 is an example of a second main electrode. The first semiconductor chip 100 is also a silicon carbide semiconductor chip. The N-type, which is the conductivity type of the channel of the first semiconductor chip 100, is an example of a first conductivity type.

The second semiconductor chip 200 is, for example, a MOS type FET chip. The second semiconductor chip 200 has a silicon substrate 210, a gate electrode 221, a source electrode 222, and a drain electrode 223. The second semiconductor chip 200 is a P-channel type FET, and the silicon substrate 210 includes two P-type regions and one N-type region that constitute the FET. The source electrode 222 is electrically connected to one P-type region, and the drain electrode 223 is electrically connected to the other P-type region. The gate electrode 221 controls the potential of the N-type region through a gate insulating film. The silicon substrate 210 has a third main surface 203 and a fourth main surface 204 opposite to the third main surface 203. The gate electrode 221 and the source electrode 222 are provided on the fourth main surface 204, and the drain electrode 223 is provided on the third main surface 203. The silicon substrate 210 is an example of a second semiconductor substrate. The gate electrode 221 is an example of a second control electrode, the source electrode 222 is an example of a third main electrode, and the drain electrode 223 is an example of a fourth main electrode. The second semiconductor chip 200 is also a silicon semiconductor chip. The P type, which is the conductivity type of the channel of the second semiconductor chip 200, is an example of the second conductivity type.

The lead frame 300 has a die pad 310, a first lead 321, a second lead 322, a third lead 323, and a fourth lead 324. The die pad 310 has a rectangular planar shape with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction. The first lead 321, the second lead 322, the third lead 323, and the fourth lead 324 are provided on the Y2 side of the die pad 310 and extend in the Y1-Y2 direction. The first lead 321, the second lead 322, the third lead 323, and the fourth lead 324 are electrically insulated from each other. The second lead 322 is provided on the X1 side of the third lead 323, the first lead 321 is provided on the X1 side of the second lead 322, and the fourth lead 324 is provided on the X1 side of the first lead 321. The third lead 323 is integrated with the die pad 310 and is electrically connected to the die pad 310. The first lead 321 is an example of a first external terminal, the second lead 322 is an example of a second external terminal, the third lead 323 is an example of a third external terminal, and the fourth lead 324 is an example of a fourth external terminal.

The first semiconductor chip 100 is mounted on the die pad 310. A solder layer 511 is provided between the die pad 310 and the drain electrode 123, and the die pad 310 and the drain electrode 123 are joined to each other by the solder layer 511. The drain electrode 123 is electrically connected to the die pad 310 via the solder layer 511.

The drain electrode 123 is formed over almost the entire second major surface 102. The gate electrode 121 is provided near the edge of the first major surface 101 on the X1 side and near the center in the Y1-Y2 direction. The source electrode 122 is formed over almost the entire remaining portion of the first major surface 101.

In a plan view, the dimensions of the second semiconductor chip 200 are such that it fits within a portion of the source electrode 122 of the first semiconductor chip 100. The second semiconductor chip 200 is mounted on the first semiconductor chip 100. The third main surface 203 faces the first main surface 101. A solder layer 512 is provided between the source electrode 122 and the drain electrode 223, and the source electrode 122 and the drain electrode 223 are joined to each other by the solder layer 512. The drain electrode 223 is electrically connected to the source electrode 122 via the solder layer 512. The solder layer 512 is an example of a first connection member and a first solder layer.

The drain electrode 223 is formed over almost the entire third major surface 203. The gate electrode 221 is provided near the edge of the fourth major surface 204 on the X1 side and near the center in the Y1-Y2 direction. The source electrode 222 is formed over almost the entire remaining portion of the fourth major surface 204.

The semiconductor device 1 has a bonding wire 521, a bonding wire 522, a bonding wire 523, and a bonding wire 524. The bonding wire 521 connects the source electrode 222 of the second semiconductor chip 200 to the first lead 321. The bonding wire 522 connects the source electrode 122 of the first semiconductor chip 100 to the second lead 322. The bonding wire 523 connects the gate electrode 121 of the first semiconductor chip 100 to the source electrode 222 of the second semiconductor chip 200. The bonding wire 524 connects the gate electrode 121 of the second semiconductor chip 200 to the fourth lead 324. The bonding wires 521, 522, 523, and 524 are, for example, aluminum (Al) wires. The bonding wire 523 is an example of a second connection member.

The first lead 321 is electrically connected to the source electrode 222 via a bonding wire 521, and is electrically connected to the gate electrode 121 via bonding wires 521 and 523. The bonding wire 521 and the bonding wire 523 may be composed of a single bonding wire. The second lead 322 is electrically connected to the source electrode 122 via a bonding wire 522. The third lead 323 is electrically connected to the drain electrode 123 via the die pad 310 and the solder layer 511. The fourth lead 324 is electrically connected to the gate electrode 221 via a bonding wire 524.

The number of each of the bonding wires 521, 522, 523, and 524 is not limited and can be selected, for example, taking into consideration the magnitude of the current flowing. For example, the number of the bonding wires 521, 523, and 524 may be 1, and the number of the bonding wires 522 may be 2.

The sealing resin 400 seals the die pad 310, the first semiconductor chip 100, and the second semiconductor chip 200. A portion of each of the first lead 321, the second lead 322, the third lead 323, and the fourth lead 324 is covered with the sealing resin 400, and the remaining portion of each extends outside the sealing resin 400.

Here, the circuit configuration of the semiconductor device 1 according to the first embodiment will be described. FIG. 3 is a circuit diagram showing the semiconductor device according to the first embodiment.

As shown in FIG. 3, the gate electrode 121 of the first semiconductor chip 100 and the source electrode 222 of the second semiconductor chip 200 are commonly connected to a first lead 321. The source electrode 122 of the first semiconductor chip 100 and the drain electrode 223 of the second semiconductor chip 200 are commonly connected to a second lead 322. The drain electrode 123 of the first semiconductor chip 100 is connected to a third lead 323. The gate electrode 221 of the second semiconductor chip 200 is connected to a fourth lead 324.

The first semiconductor chip 100 and the second semiconductor chip 200 may each include a free wheel diode.

In the semiconductor device 1, the second semiconductor chip 200 functions as a Miller clamp circuit for the first semiconductor chip 100. That is, when the first semiconductor chip 100 is turned off, the second semiconductor chip 200 is turned on, thereby shorting the gate electrode 121 and source electrode 122 of the first semiconductor chip 100 and suppressing false firing.

According to this embodiment, since the second semiconductor chip 200 is appropriately connected to the first semiconductor chip 100, false firing in the first semiconductor chip 100 can be suppressed. Therefore, since there is no need to incorporate a Miller clamp circuit in the first semiconductor chip 100, the increase in cost associated with the creation of a Miller clamp circuit can be suppressed. Although the semiconductor device 1 includes the second semiconductor chip 200, a silicon semiconductor chip having a simple structure can be used as the second semiconductor chip 200. Therefore, the increase in cost associated with the use of the second semiconductor chip 200 is extremely small compared to the increase in cost associated with the incorporation of a Miller clamp circuit.

The gate electrode 121 of the first semiconductor chip 100 and the source electrode 222 of the second semiconductor chip 200 can be connected using a bonding wire 523, and the source electrode 122 of the first semiconductor chip 100 and the drain electrode 223 of the second semiconductor chip 200 can be connected using a solder layer 512. Therefore, by arranging the gate electrode 121 and the source electrode 222 so that they are close to each other, the bonding wire 523 can be shortened, and the path of the gate loop of the first semiconductor chip 100 can be shortened, making it easier to suppress false firing. In addition, since the bonding wire 523 is short and the inductance is reduced accordingly, it is also advantageous for high-speed switching operations.

By providing a solder layer 512 between the source electrode 122 of the first semiconductor chip 100 and the drain electrode 223 of the second semiconductor chip, it is easy to connect the source electrode 122 and the drain electrode 223.

Because the first semiconductor chip 100 and the second semiconductor chip 200 are FET chips, the second semiconductor chip 200 can be easily used as a Miller clamp circuit for the first semiconductor chip 100.

The gate electrode 121 of the first semiconductor chip 100 and the source electrode 222 of the second semiconductor chip 200 are connected by a bonding wire 523, making it easy to connect the gate electrode 121 and the source electrode 222.

The first semiconductor chip 100 is a silicon carbide semiconductor chip and the second semiconductor chip 200 is a silicon semiconductor chip, so that the first semiconductor chip 100 can achieve high-speed operation while the second semiconductor chip 200 can be easily used as a Miller clamp circuit for the first semiconductor chip 100.

By providing the drain electrode 123 of the first semiconductor chip 100 on the second main surface 102, the structure of the first semiconductor chip 100 is made vertical, making it easier to obtain good voltage resistance.

By covering a portion of each of the first lead 321, the second lead 322, the third lead 323, and the fourth lead 324 with the sealing resin 400, it becomes easier to realize a discrete package.

Second Embodiment
Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the first connection member. Fig. 4 is a cross-sectional view showing a semiconductor device according to the second embodiment. Fig. 5 is a top view showing a wiring board included in the second embodiment. Fig. 6 is a cross-sectional view showing a wiring board included in the second embodiment.

The semiconductor device 2 according to the second embodiment has a solder layer 711, a wiring board 710, and a solder layer 712 instead of the solder layer 512 in the first embodiment. In the second embodiment, the first connection member has the solder layer 711, the wiring board 710, and the solder layer 712.

For example, the wiring board 710 is a printed wiring board. The wiring board 710 has an insulating substrate 720, a first conductive layer 731, and a second conductive layer 732. The insulating substrate 720 has a fifth main surface 721 and a sixth main surface 722 opposite to the fifth main surface 721. The insulating substrate 720 has a rectangular planar shape with dimensions similar to those of the second semiconductor chip 200. The first conductive layer 731 is provided on the fifth main surface 721, and the second conductive layer 732 is provided on the sixth main surface 722. The first conductive layer 731 and the second conductive layer 732 are, for example, copper (Cu) foil. The material of the insulating substrate 720 is, for example, an epoxy resin containing glass fiber. The thermal conductivity of the insulating substrate 720 is lower than that of solder.

A plurality of through holes 723 are formed in the insulating substrate 720, and conductive vias 724 are provided in the through holes 723. The conductive vias 724 are in contact with the first conductive layer 731 and the second conductive layer 732, and the first conductive layer 731 and the second conductive layer 732 are electrically connected via the conductive vias 724. The material of the conductive vias 724 is, for example, copper. Note that the electrical connection between the first conductive layer 731 and the second conductive layer 732 is not limited to the connection via the through holes 723. For example, the electrical connection between the first conductive layer 731 and the second conductive layer 732 may be a connection by a conductive via such as a blind via.

The wiring substrate 710 is provided on the first semiconductor chip 100. The fifth main surface 721 faces the first main surface 101. A solder layer 711 is provided between the source electrode 122 and the first conductive layer 731, and the source electrode 122 and the first conductive layer 731 are joined to each other by the solder layer 711. The solder layer 711 is an example of a second solder layer.

The second semiconductor chip 200 is provided on the wiring substrate 710. The third main surface 203 faces the sixth main surface 722. A solder layer 712 is provided between the second conductive layer 732 and the drain electrode 223, and the second conductive layer 732 and the drain electrode 223 are joined to each other by the solder layer 712. The solder layer 712 is an example of a third solder layer.

As described above, the first conductive layer 731 and the second conductive layer 732 are electrically connected through the conductive via 724. Therefore, the drain electrode 223 of the second semiconductor chip 200 is electrically connected to the source electrode 122 through the solder layer 712, the wiring board 710, and the solder layer 711.

The other configurations are the same as in the first embodiment.

The second embodiment also provides the same effect as the first embodiment. In addition, since the thermal conductivity of the insulating substrate 720 included in the wiring substrate 710 is lower than that of the solder, the second embodiment can suppress the transfer of heat generated in the first semiconductor chip 100 to the second semiconductor chip 200. In general, the heat resistance of silicon is lower than that of silicon carbide. Therefore, according to the second embodiment, the fluctuation in the characteristics of the second semiconductor chip 200 due to heat can be suppressed, improving reliability.

In the present disclosure, an insulated gate bipolar transistor (IGBT) chip may be used as the first semiconductor chip 100. When an IGBT is used, the emitter electrode is an example of a first main electrode, and the collector electrode is an example of a second main electrode.

The semiconductor device according to the present disclosure may be used as a discrete device or as a module.

Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and variations are possible within the scope of the claims.

1, 2: Semiconductor device 100: First semiconductor chip 101: First main surface 102: Second main surface 110: Silicon carbide substrate (first semiconductor substrate)
121: Gate electrode (first control electrode)
122: Source electrode (first main electrode)
123: Drain electrode (second main electrode)
200: second semiconductor chip 203: third main surface 204: fourth main surface 210: silicon substrate (second semiconductor substrate)
221: Gate electrode (second control electrode)
222: Source electrode (third main electrode)
223: Drain electrode (fourth main electrode)
300: lead frame 310: die pad 321: first lead (first external terminal)
322: Second lead (second external terminal)
323: Third lead (third external terminal)
324: Fourth lead (fourth external terminal)
400: sealing resin 511: solder layer 512: solder layer (first connection member)
521: bonding wire 522: bonding wire 523: bonding wire (second connection member)
524: bonding wire 710: wiring board 711: solder layer 712: solder layer 720: insulating board 721: fifth main surface 722: sixth main surface 723: through hole 724: conductive via 731: first conductive layer 732: second conductive layer

Claims (9)

a first semiconductor chip having a first semiconductor substrate, a first control electrode, a first main electrode, and a second main electrode;
a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip having a second semiconductor substrate, a second control electrode, a third main electrode, and a fourth main electrode;
having
The first semiconductor substrate is
A first major surface;
A second major surface opposite the first major surface;
having
The second semiconductor substrate is
a third main surface opposite to the first main surface;
a fourth main surface opposite the third main surface; and
having
the first control electrode and the first main electrode are provided on the first main surface,
the second control electrode and the third main electrode are provided on the fourth main surface,
the fourth main electrode is provided on the third main surface,
a first connection member that electrically connects the first main electrode and the fourth main electrode;
a second connection member electrically connecting the first control electrode and the third main electrode;
A semiconductor device having the above structure. The semiconductor device according to claim 1, wherein the first connection member has a first solder layer provided between the first main electrode and the fourth main electrode. The first connection member is
a second solder layer provided on the first main electrode;
a wiring substrate provided on the second solder layer;
A third solder layer provided on the wiring board;
having
The wiring board includes:
an insulating substrate including a fifth main surface facing the first main surface and a sixth main surface facing the third main surface on the opposite side to the fifth main surface;
a first conductive layer provided on the fifth main surface and connected to the first main electrode by the second solder layer;
a second conductive layer provided on the sixth main surface and connected to the fourth main electrode by the third solder layer;
a conductive via that electrically connects the first conductive layer and the second conductive layer;
The semiconductor device according to claim 1 , the first semiconductor chip is a field effect transistor chip of a first conductivity type;
4. The semiconductor device according to claim 1, wherein the second semiconductor chip is a field effect transistor chip of a second conductivity type. The semiconductor device according to any one of claims 1 to 4, wherein the second connection member has a bonding wire connecting the first control electrode and the third main electrode. the first semiconductor chip is a silicon carbide semiconductor chip;
The semiconductor device according to claim 1 , wherein the second semiconductor chip is a silicon semiconductor chip. The semiconductor device according to any one of claims 1 to 6, wherein the second main electrode is provided on the second main surface. a first external terminal electrically connected to the first control electrode;
a second external terminal electrically connected to the first main electrode;
a third external terminal electrically connected to the second main electrode;
a fourth external terminal electrically connected to the second control electrode;
a sealing resin that seals the first semiconductor chip and the second semiconductor chip;
having
8 . The semiconductor device according to claim 1 , wherein each of the first external terminal, the second external terminal, the third external terminal, and the fourth external terminal is partially covered with the sealing resin. The first control electrode is a gate electrode,
The first main electrode is a source electrode,
The second main electrode is a drain electrode,
The second control electrode is a gate electrode,
The third main electrode is a source electrode,
9. The semiconductor device according to claim 1, wherein the fourth main electrode is a drain electrode.

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