JP7656216B2 - Wiring design device for semiconductor integrated circuits and wiring design program for semiconductor integrated circuits - Google Patents

Description

This invention relates to a wiring design device for semiconductor integrated circuits and a wiring design program for semiconductor integrated circuits.

Patent Document 1 discloses a wiring board suitable for narrowing the pitch between lead wiring layers in a connector section where migration prevention is required, and a method for manufacturing the same. For this purpose, the wiring board includes a flexible insulating substrate constituting a connector terminal section having an insertion edge in a direction intersecting with the connector insertion direction into an external connector, and first and second lead wiring layers of thin strips having a silver component formed on the insulating substrate surface of the connector terminal section in an arrangement pattern parallel to the insertion direction. The wiring board also includes first and second electrode terminal layers respectively coated over the upper surface and side edge of each tip on the insertion edge side, and an insulating protective layer for migration prevention coated over the upper surface and side edge of each lead wiring layer other than each tip. Here, the first and second electrode terminal layers are arranged in a distant relationship with each other with respect to the insertion edge.

In addition, the presence of an insulating protective layer sufficiently prevents electrical shorts between the lead wiring layers and ensures insulation, and the spacing can be designed with a large degree of freedom, and the wiring layer width is not subject to significant dimensional constraints, allowing a larger width to be secured for the same pitch compared to conventional techniques. As a result, the internal resistance of the lead wiring layer can be reduced and the current capacity increased, while also making it easy to accommodate narrower wiring pitches P.

Patent Document 2 discloses a wiring board for flip-chip connecting a semiconductor integrated circuit, which can maintain a gap between the flip-chip connected semiconductor integrated circuit and the board, and can effectively avoid short circuits on the side walls. In this wiring board, the flip-chip connection part is formed of a convex part formed of a conductor on the insulating resin layer surface and an electrode pattern formed on the convex part, and the entire side surface of the convex part is covered with an insulating material, and an insulating material is formed on the insulating resin layer surface that is thinner than the convex part.

Patent Document 3 discloses an automatic wiring method for semiconductor integrated circuits that has a function to estimate the signal wiring delay of the signal to be wired, and in particular a function to predict the wiring length of each signal based on the placement results because actual wiring has not been performed at this stage. This method also has a function to calculate the delay due to wiring based on the wiring length, and in particular a function to calculate the delay assuming the worst case, although various methods are possible for these predictions and calculation methods.

The method of Patent Document 3 also has a function for extracting target wiring in descending order of delay in order to process wiring with the greatest difficulty from the viewpoint of reducing delay, and a function for switching between wiring methods to select the automatic wiring method to be used in order to prevent unnecessary execution, since automatic wiring that takes wiring delay into account requires a much longer calculation time than wiring that does not.

When performing multi-layer wiring, in order to avoid a situation where the same layer is assigned to wiring that intersects at the same point, a function is provided to move one of the shorted wiring layers to another wiring layer. This wiring layer change function evaluates the effect of the wiring layer change on signal delays and switches the signal wiring that will have the least effect to another layer.

The invention of Patent Document 3 uses a method of completing the wiring by appropriately repeating the steps of first determining a path that connects two appropriate terminal pairs, and second determining a path that connects a point on a path already determined in a previous step to another terminal or a point on another path already determined.

In particular, in the second stage, when selecting a point on an already determined route as a branch point, a configuration is adopted in which the center point of the route is calculated, and a branch point is selected within a certain distance from the center point. Alternatively, in the second stage, a cost is set for the branch point that increases with distance from the center point on the already determined route, and a branch point is selected so that the sum of the length of a newly generated wiring route between the branch points with a set cost and the cost is minimized.

The above means allows the delay estimation function for each signal and the function of extracting the nets to be routed in order of the largest delay to route nets that are difficult to comply with constraints on signal delays at an early stage with a high degree of freedom. On the other hand, the function of predicting and estimating the delay and the function of switching the wiring method depending on the estimated wiring delay distinguish between signals that require special handling of signal delays and those that do not, reducing the number of times that wiring that takes into account signal delays, which takes a lot of processing time, is performed, thereby saving processing time.

When performing multi-layer wiring using an automatic wiring program, the wiring direction assigned to each wiring layer is generally fixed. When three or more wiring layers are available, it becomes possible to assign multiple wiring layers to the same direction. However, each wiring layer has its own electrical characteristics such as electrical resistance and capacitance, and the signal propagation delay is different. Therefore, by assigning wiring layers with small propagation delay first, the propagation delay of the wiring can be reduced.

In a method of wiring according to the priority allocation direction of wiring layers, which determines the direction in which wiring layers are preferentially used, the function of preferentially allocating wiring layers with small signal delays when there are multiple wiring layers that can be allocated has the effect of keeping delays in wiring as small as possible. Furthermore, this can increase the probability that the resulting wiring satisfies delay constraints.

In addition, when converting the wiring layers to resolve a short circuit in a temporary wiring, the function calculates the effect on signal delay of the change in electrical parameters corresponding to the wiring layer change of both wirings, and changes the wiring layer that constitutes the wiring of the signal that is least affected to avoid a short circuit, making it possible to minimize the wiring delay that increases due to the work of avoiding a short circuit.

JP 2009-147130 A JP 2015-018945 A Japanese Patent Application Publication No. 6-283602

As mentioned above, various methods have been developed to prevent short circuits in wiring of semiconductor integrated circuits, etc., but they do not cover the design of preventing short circuits in the power rails.

In semiconductor integrated circuits, in order to reduce the resistance of the power supply wiring, a wiring layer and via holes are stacked on the power supply rail laid in each block cell to form a backing wiring. In this case, if there is a signal line that intersects perpendicularly with the backing wiring, it is necessary to separate the backing wiring side to avoid wiring shorts. However, this work is done manually, and there is an issue that it takes a lot of time and effort to divide the via cells.

The present invention has been made in consideration of the problems in the conventional wiring design of semiconductor integrated circuits as described above, and its purpose is to provide a wiring design device for semiconductor integrated circuits and a wiring design program for semiconductor integrated circuits that can reduce the number of steps in the wiring process.

The wiring design device for a semiconductor integrated circuit according to this embodiment is characterized by comprising: a primary parameter setting means for back-wiring a via parametric cell to the power rail of an instance cell generated based on design information for the semiconductor integrated circuit, and setting parameters for the wired via parametric cell; a short circuit detection means for detecting short circuits where the via parametric cell crosses the wiring in a layer above the layer of the instance cell; and a shape modification means for updating the setting value of the via parametric cell and modifying it to a new shape by cutting the back-wiring in order to remove the short circuit detected by the short circuit detection means.

The wiring design device for a semiconductor integrated circuit according to this embodiment includes a short circuit part coordinate detection means for detecting the coordinate values of the short circuit part detected by the short circuit part detection means, and a second parameter setting means for setting parameters of a new via parametric cell based on the coordinate values of the short circuit part detected by the short circuit part coordinate detection means, and the shape change means changes the backing wiring to a new shape by cutting the backing wiring based on the parameters set by the second parameter setting means.

In the wiring design device for a semiconductor integrated circuit according to this embodiment, the power rails are composed of a first power rail that provides a voltage to the circuit and a second power rail that provides a ground potential, and the wiring in the upper layer of the layer of the instance cell is characterized in that it crosses the first power rail and the second power rail.

In the wiring design device for semiconductor integrated circuits according to this embodiment, the layer above the layer of the instance cell has multiple layers, and the short circuit part detection means, the shape modification means, the short circuit part coordinate detection means, and the secondary parameter setting means perform processing on the wiring of each layer.

In the wiring design device for semiconductor integrated circuits according to this embodiment, the vias of the via parametric cell are formed in multiple rows and multiple columns.

The wiring design device for semiconductor integrated circuits according to this embodiment is characterized in that one or more upper layer wirings that cross the via parametric cell can be placed on each layer.

The wiring design program for semiconductor integrated circuits according to this embodiment is characterized in that it causes a computer to function as a primary parameter setting means for back-wiring a via parametric cell to the power rail of an instance cell generated based on design information for the semiconductor integrated circuit and setting parameters for the wired via parametric cell, a short-circuit part detection means for detecting a short-circuit part where the via parametric cell crosses with wiring in a layer above the layer of the instance cell, and a shape modification means for updating the setting value of the via parametric cell and modifying it to a new shape by cutting the back-wiring in order to remove the short-circuit part detected by the short-circuit part detection means.

The wiring design program for semiconductor integrated circuits according to this embodiment is characterized in that the computer is further made to function as a short circuit part coordinate detection means for detecting the coordinate values of the short circuit part detected by the short circuit part detection means, and a second parameter setting means for setting parameters of a new via parametric cell based on the coordinate values of the short circuit part detected by the short circuit part coordinate detection means, and is made to function as the shape change means for changing the backing wiring to a new shape by cutting the backing wiring based on the parameters set by the second parameter setting means.

In the wiring design program for semiconductor integrated circuits according to this embodiment, the power rails are composed of a first power rail that provides a voltage to the circuit and a second power rail that provides a ground potential, and the wiring in the upper layer of the layer of the instance cell is characterized by being a wiring that crosses the first power rail and the second power rail.

The semiconductor integrated circuit wiring design program according to this embodiment is characterized in that the layer above the instance cell has multiple layers, and the short circuit part detection means, shape modification means, short circuit part coordinate detection means, and secondary parameter setting means perform processing on the wiring of each layer.

The wiring design program for semiconductor integrated circuits according to this embodiment is characterized in that the vias of the via parametric cell are formed in multiple rows and multiple columns.

The wiring design program for semiconductor integrated circuits according to this embodiment is characterized in that one or more upper layer wirings that cross the via parametric cell can be placed on each layer.

FIG. 1 is a block diagram of a computer constituting an apparatus for designing wiring for a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing each unit for realizing a wiring design program for a semiconductor integrated circuit according to an embodiment of the present invention. 4 is a flowchart showing an operation of the wiring design apparatus for a semiconductor integrated circuit according to the embodiment of the present invention. 2 is a diagram showing an example of an instance cell generated based on design information of a semiconductor integrated circuit according to the embodiment of the present invention; FIG. 1 is a schematic diagram showing a state where via parametric cells are back-wired to the power rails of instance cells generated based on design information of a semiconductor integrated circuit according to this embodiment of the present invention. FIG. 13 is an enlarged view of a main portion when a via parametric cell is backed with wiring for a power rail of an instance cell generated based on design information of a semiconductor integrated circuit according to this embodiment of the present invention. FIG. 6 is a schematic diagram showing a state in which upper layer wiring has been performed from the state shown in FIG. 5 . FIG. 8 is a schematic diagram showing a state in which the setting values of the via parametric cell are updated and the backing wiring is cut to change the shape from the state shown in FIG. 7 to a new shape in order to remove the short circuit portion detected by the short circuit portion detection means. FIG. 9 is an enlarged view of a main part of FIG. 8 .

The wiring design device for a semiconductor integrated circuit and the wiring design program for a semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to the attached drawings. In each drawing, the same components are given the same reference numerals and duplicated descriptions will be omitted.

The wiring design device for a semiconductor integrated circuit according to the embodiment of the present invention having the above configuration can be configured using a computer, as shown in FIG. 1. That is, the CPU 10 configures the wiring design device for a semiconductor integrated circuit using programs and data in the main memory 11. The CPU 10 is connected to an external memory interface 13, an input interface 14, a display interface 15, and a network interface 16 via a bus 12.

The external storage interface 13 is connected to an external storage device 23. The external storage device 23 stores programs and data for the operation of the wiring design device for semiconductor integrated circuits, which can be read by the CPU 10 into the main memory 11 as appropriate for use. For this reason, the external storage device 23 stores programs for implementing each means of the wiring design device for semiconductor integrated circuits, which will be described later. The input interface 14 is connected to an input device 24 such as a keyboard or touch panel, and a pointing device 22 such as a mouse. The display interface 15 is connected to a display device 25 having a screen such as an LCD, which realizes the display of images and the like required for the wiring design device for semiconductor integrated circuits. The network interface 16 is connected to a network, and the wiring design device for semiconductor integrated circuits can import data and the like to be used for wiring design. As described above, the input interface 14 is connected to an input device 24 such as a keyboard for inputting data and commands, and a pointing device 22 such as a mouse, so that the wiring design device for semiconductor integrated circuits can perform the necessary operations and processes by operating the input device 24 and the mouse 22.

The external storage device 23 stores the various means for implementing a program for designing wiring for semiconductor integrated circuits, as shown in FIG. 2. These means are composed of a primary parameter setting means 31, a short circuit part detection means 32, a shape modification means 33, a short circuit part coordinate detection means 34, and a secondary parameter setting means 35.

The wiring design device for a semiconductor integrated circuit according to this embodiment operates according to a program corresponding to the flowchart shown in FIG. 3. Therefore, the operation will be explained below based on this flowchart. First, information on the placement and wiring of elements and layout generated based on design information for the semiconductor integrated circuit to be designed is retrieved, for example, from the external storage device 23, and verification is started (S11).

Next, via parametric cells are back-wired to the power rails of the instance cells generated based on the design information of the semiconductor integrated circuit, and the parameters of the wired via parametric cells are set (S12). This step S12 can be executed by the primary parameter setting means 31. The design information of the semiconductor integrated circuit of this embodiment can be stored in advance in the external storage device 23 as described above, or can be obtained from a specified device or the like via the network interface 16 and stored in the external storage device 23.

The instance cell generated based on the design information of the semiconductor integrated circuit of this embodiment is, for example, as shown in FIG. 4. That is, FIG. 4 shows a circuit in which two pairs of inverters are arranged, each of which has the drain 42 of a PMOS transistor 41 and the source 44 of an NMOS transistor 43 connected to each other. The line connected to the source of the PMOS transistor 41 is connected to a power supply rail 51 with potential (VDD), and the line connected to the drain of the NMOS transistor 43 is connected to a power supply rail 52 with earth potential (VSS).

Figure 5 shows a schematic diagram of the via parametric cell 61 (62) backing wiring for the power rail 51 (52), and Figure 6 shows an enlarged view of the main part. The parameters <1> to <8> set at this time are shown in the upper part of Figure 6, and their contents are shown in the right frame of Figure 6. Parameter <1> indicates row (Row), and parameter <2> indicates column (Column). In the example of Figure 6, the via 63 indicates 2 rows (Row) x 4 columns (Column), but in reality the number of columns reaches about 1000. Therefore, it is understood that it is extremely inefficient to manually avoid short circuits for each via 63. Also, in Figure 5, only one row (Row) of the via parametric cell 61 (62) is shown for the power rail 51 (52).

Parameter <3> is the hole width, parameter <4> is the hole spacing, parameter <5> is the X-direction perimeter width of Layer 1 (Layer1 Enclosure X), parameter <6> is the Y-direction perimeter width of Layer 1 (Layer1 Enclosure Y), parameter <7> is the X-direction perimeter width of Layer 2 (Layer2 Enclosure X), and parameter <8> is the Y-direction perimeter width of Layer 2 (Layer2 Enclosure Y).

In the next process of the device according to this embodiment, the process proceeds to step S13 in FIG. 3, where wiring 47 is performed on the upper layer of the layer of the above-mentioned instance cell, and short sites SR1 and SR2 of the above-mentioned via parametric cells 61 and 62 are detected (S13). This step S13 is performed by the short site detection means 32. FIG. 7 shows the state in which wiring 47 on the upper layer has been performed from the state in FIG. 5. The short sites SR1 and SR2 are generated on the power rails 51 and 52. At this time, the short site coordinate detection means 34 detects the coordinate values of the short sites SR1 and SR2 detected by the above-mentioned short site detection means 32.

In step S14 following step S13, the parameters of the via parametric cells 61A, 61B, 62A, and 62B are set as shown in FIG. 8 based on the coordinate values of the short sites SR1 and SR2 detected above (S14). That is, the secondary parameter setting means 35 updates the setting values of the via parametric cells to remove the short sites based on the coordinate values of the short sites SR1 and SR2 detected by the short site coordinate detection means 34, and sets parameters so that the backing wiring is cut into a new shape (61A (62A), 61B (62B)). This process is performed by the secondary parameter setting means 35. In this embodiment, as shown in FIG. 9, the parameters <9> of the coordinates (Layer1 Cut Coords) of the cut positions of the via parametric cell 61A (62A) and the via parametric cell 61B (62B) are set (FIG. 9).

Specifically, the semiconductor integrated circuit to be designed is represented by the XY coordinates in FIG. 7, and the coordinate values of the short sites SR1 and SR2 are based on these XY coordinates. In contrast, the positions within the via parametric cell are represented by the XY coordinates shown in FIG. 6 and FIG. 9. For this reason, in step S14, the coordinate values of the short sites SR1 and SR2 in the XY coordinates are converted to coordinate values in the XY coordinates. In this example, the coordinate values of the via parametric cells backed by wiring to the two power rails 51 and 52 are expressed by different coordinate values, so conversion to coordinate values based on the respective coordinates is performed. Note that the conversion formulas are created for each system and are publicly known, so they will not be described in detail here.

Next, in step S15, in order to remove the short sites SR1 and SR2 detected by the short site detection means 32, the setting value of the via parametric cell is updated to change to a new shape 61A (62A), 61B (62B) in which the backing wiring is cut (S15). This process is performed by the shape modification means 33. In practice, the shape modification means 33 updates the setting value of the via parametric cell to change to a new shape 61A (62A), 61B (62B) in which the backing wiring is cut based on the parameters set by the secondary parameter setting means 35 in order to remove the short site. As a result, the via parametric cell is changed from the state shown in FIG. 7 or FIG. 6 to the state shown in FIG. 8 or FIG. 9. That is, as shown in FIG. 8 or FIG. 9, the backing wiring is cut and divided into via parametric cells 61A (62A), 61B (62B) according to the position of the coordinates (Layer1 Cut Coords) indicated by the parameter <9>. Thus, by changing the via parametric cell to a new shape, wiring shorts are avoided.

After the above process is completed, it is checked whether any changes have been made to the wiring route in the design (S16), and if the answer is YES, the process returns to step S13 and continues. If the process branches to NO in step S16, the process ends.

10 CPU
REFERENCE SIGNS LIST 11 Main memory 12 Bus 13 External storage interface 14 Input interface 15 Display interface 16 Network interface 22 Pointing device 23 External storage device 24 Input device 25 Display device 31 Primary parameter setting means 32 Shorted portion detection means 33 Shape modification means 34 Shorted portion coordinate detection means 35 Secondary parameter setting means 41 PMOS transistor 42 Drain 43 NMOS transistor 44 Source 47 Wiring 51 Power supply rail 52 Power supply rail 61 Via parametric cell 61A Via parametric cell 61B Via parametric cell 62 Via parametric cell 62A Via parametric cell 62B Via parametric cell 63 Via SR1, SR2 Shorted portion

Claims (12)

a first parameter setting means for backwiring a via parametric cell to a power rail of an instance cell generated based on design information of a semiconductor integrated circuit, and setting parameters of the wired via parametric cell;
a short circuit portion detection means for detecting a short circuit portion where a wiring in a layer above the layer of the instance cell and the via parametric cell cross each other;
a shape changing means for changing a setting value of a via parametric cell to a new shape by cutting a backing wiring in order to remove the short-circuit portion detected by the short-circuit portion detecting means;
1. A wiring design device for a semiconductor integrated circuit comprising: a short circuit part coordinate detection means for detecting a coordinate value of the short circuit part detected by the short circuit part detection means;
a second parameter setting means for setting parameters of a new via parametric cell based on the coordinate values of the short circuit portion detected by the short circuit portion coordinate detection means;
Equipped with
2. The wiring design device for a semiconductor integrated circuit according to claim 1, wherein said shape changing means changes said backing wiring to a new shape by cutting said backing wiring based on the parameters set by said secondary parameter setting means. The wiring design device for a semiconductor integrated circuit according to claim 1 or 2, characterized in that the power rails are composed of a first power rail that provides a voltage to the circuit and a second power rail that provides a ground potential, and the wiring in the upper layer of the layer of the instance cell is wiring that crosses the first power rail and the second power rail. The wiring design device for a semiconductor integrated circuit according to claim 2, characterized in that the layer above the instance cell has multiple layers, and the short circuit detection means, the shape modification means, the short circuit coordinate detection means, and the secondary parameter setting means perform processing for the wiring of each layer. The wiring design device for a semiconductor integrated circuit according to claim 1, characterized in that the vias of the via parametric cell are formed in multiple rows and multiple columns. The wiring design device for a semiconductor integrated circuit according to claim 1, characterized in that one or more upper layer wirings that cross the via parametric cell can be placed on each layer. Computer,
a first parameter setting means for back-wiring a via parametric cell to a power rail of an instance cell generated based on design information of the semiconductor integrated circuit, and setting parameters of the wired via parametric cell;
a short circuit portion detection means for detecting a short circuit portion where a wiring in a layer above the layer of the instance cell crosses the via parametric cell;
a shape changing means for changing a setting value of a via parametric cell to a new shape by cutting a backing wiring in order to remove the short-circuit portion detected by the short-circuit portion detecting means;
4. A wiring design program for a semiconductor integrated circuit, comprising: The computer further comprises:
a short circuit part coordinate detection means for detecting a coordinate value of the short circuit part detected by the short circuit part detection means;
a second parameter setting means for setting parameters of a new via parametric cell based on the coordinate values of the short circuit portion detected by the short circuit portion coordinate detection means;
Function as a
8. The wiring design program for a semiconductor integrated circuit according to claim 7, wherein the computer is caused to function as the shape changing means so as to change the backing wiring to a new shape by cutting the backing wiring based on the parameters set by the second parameter setting means. The wiring design program for semiconductor integrated circuits according to claim 7 or 8, characterized in that the power rails are composed of a first power rail that provides a voltage to the circuit and a second power rail that provides a ground potential, and the wiring in the upper layer of the layer of the instance cell is wiring that crosses the first power rail and the second power rail. The wiring design program for semiconductor integrated circuits described in claim 8, characterized in that the layer above the instance cell has multiple layers, and the short circuit detection means, the shape modification means, the short circuit coordinate detection means, and the secondary parameter setting means perform processing for the wiring of each layer. The wiring design program for semiconductor integrated circuits according to claim 7, characterized in that the vias of the via parametric cell are formed in multiple rows and multiple columns. The wiring design program for semiconductor integrated circuits described in claim 7, characterized in that one or more upper layer wirings that cross the via parametric cell can be placed on each layer.

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