JP7660636B2 - Display device - Google Patents

Description

This specification relates to a display device that can prevent the penetration of external moisture.

Recently, display devices that can display a variety of information and interact with users who view that information are being required to have a variety of sizes, shapes, and functions.

Such display devices include liquid crystal display devices (LCDs), electrophoretic display devices (FPDs), and organic light emitting diode display devices (OLEDs).

Organic light-emitting display devices are self-emitting displays that, unlike liquid crystal displays (LCDs), do not require a separate light source, making them lightweight and thin. In addition, organic light-emitting diode display devices are advantageous in terms of power consumption due to their low voltage operation, and are also excellent in color realization, response speed, viewing angle, and contrast ratio (CR), making them the subject of research as the next generation of displays.

Organic light-emitting diode display devices use a number of thin film transistors (or "TFTs") to control the current flowing through organic light-emitting diodes to display images.

The display device is being developed with the addition of cameras, speakers, sensors, etc.

In particular, a hole-in-display structure is used in which a hole is formed in the device to place a sensor such as a camera on the display device.

By forming holes in the display device, there is a problem that external moisture can penetrate into the display area inside the display panel.

This specification allows for the creation of a through hole in an area for placing a camera within the display area of the display device.

The through holes can be formed by removing the substrate and layers on the substrate.

To form a through hole within the display area, a first area including a hole area, a first pattern portion, a first dam portion, and a second pattern portion can be arranged.

The first pattern portion adjacent to the hole region of the first region may have a plurality of first patterns including a columnar lower pattern and a trapezoidal upper pattern on the lower pattern to disconnect the light emitting layer.

The insulating layer disposed on the first patterns may not fill the taper regions formed between the first patterns, forming empty spaces (ES).

A seam may be formed due to the empty space (ES) and the end of the trapezoidal upper pattern.

The hole area formed by removing the substrate and the layer on the substrate may expose the side of the layer on the substrate to the outside.

External moisture that seeps into the organic insulating layer, which is made of organic material and is one of the layers on the substrate exposed to the outside, can seep into the panel display area through the seam formed in the first pattern part adjacent to the hole area, resulting in a deterioration in the quality of the display device.

Therefore, this specification invents a display device that can prevent the penetration of external moisture by improving the laminated structure of the insulating layer and protective layer on the first pattern part of the first region formed to place the camera of the Hole In Display.

The problem to be solved by the embodiments of this specification is to provide a display device and a manufacturing method thereof that can prevent the penetration of external moisture by disposing a protective layer between insulating layers on a first pattern portion of a first region formed for arranging a camera.

The problems to be solved by the embodiments of this specification are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment of the present specification includes a substrate including a display region and a non-display region, and a first region disposed in the display region, and includes a hole region, a first pattern portion, a first dam portion, and a second pattern portion in the first region, a sealing layer on at least a portion of the first region, a first insulating layer, a second insulating layer, and a plurality of first patterns disposed in the first pattern portion, the first insulating layer and the second insulating layer being spaced apart from each other between the plurality of first patterns, and the first insulating layer and the second insulating layer being in contact with each other on at least a portion of the upper surface of the plurality of first patterns.

Specific details of other embodiments are included in the detailed description and drawings.

The display device according to the embodiment of this specification is provided with an insulating layer and a protective layer structure on the first pattern portion of the first region formed for arranging a camera within the display region, thereby effectively preventing external moisture from penetrating the panel, and providing a display device and a manufacturing method thereof that can improve degradation of panel quality due to moisture permeation.

The effects of this specification are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

In the above, the contents of the invention described in the problem to be solved, the means for solving the problem, and the effects do not specify the essential features of the claims, so the scope of the claims is not limited by the matters described in the contents of the invention.

1 is a plan view illustrating a display device according to an embodiment of the present specification; 1 is a three-dimensional view illustrating a display device according to an embodiment of the present specification; 1 is a three-dimensional view illustrating a display device according to an embodiment of the present specification; FIG. 2 is an enlarged view illustrating a first region PH portion of FIG. 1 . 2 is a cross-sectional view illustrating an example of a cross section taken along line A-A' in FIG. 1. 2 is a cross-sectional view illustrating an example of a cross section taken along line B-B' in FIG. 1. FIG. 7 is an enlarged view illustrating a PT1 portion of FIG. 6.

The advantages and features of the present specification, and the methods for achieving them, will become apparent from the detailed description of the embodiments described below in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be embodied in various different forms, and the embodiments are provided to complete the disclosure of the present specification and to fully inform those skilled in the art of the invention to which the present specification pertains, and the present specification is defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative only, and this specification is not limited to the matters shown in the drawings. The same reference symbols indicate the same components throughout the specification. Furthermore, in the description of this specification, if it is determined that a specific description of related publicly known technology may unnecessarily obscure the gist of this specification, the detailed description will be omitted. When the terms "include," "have," "consist of," etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

When interpreting elements, error ranges are interpreted as being included even if there is no separate explicit mention of the error range.

When describing the positional relationship between two parts, for example, when the positional relationship between the two parts is described using "above," "on top," "below," "beside," etc., one or more other parts may be located between the two parts, as long as words such as "immediately" or "directly" are not used.

When describing a temporal relationship, if the temporal sequence is explained using "after," "following," "next," "before," etc., it can also include cases where the events are not consecutive, as long as "immediately" or "directly" are not used.

Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Thus, a first component referred to below may be a second component within the technical concept of this specification.

In describing components in this specification, terms such as first, second, A, B, (a), (b), etc. may be used. Such terms are merely intended to distinguish the component from other components, and do not limit the nature, order, sequence, or number of the components. When a component is described as being "coupled," "connected," or "connected" to another component, it should be understood that the component may be directly coupled or connected to the other component, but that other components may be "intervening" between each component that may be indirectly coupled or connected, unless otherwise expressly specified.

"At least one" should be understood to include all combinations of one or more of the associated components. For example, "at least one of the first, second, and third components" means not only the first, second, or third components, but also all combinations of two or more of the first, second, and third components.

In this specification, the term "apparatus" may include display devices such as a liquid crystal module (LCM) or an organic light emitting display module (OLED module) that includes a display panel and a driver for driving the display panel. It may also include set electronic apparatuses or set devices such as notebook computers, televisions, computer monitors, automotive apparatuses, and mobile electronic apparatuses such as smartphones or electronic pads that are complete or final products that include an LCM or an OLED module.

Therefore, the device in this specification can include the display device itself, such as an LCM, an OLED module, etc., as well as a set device that is an application product or end consumer device that includes an LCM, an OLED module, etc.

In some embodiments, an LCM/OLED module composed of a display panel and a driver may be referred to as a "display device," and a completed electronic device including the LCM/OLED module may be referred to as a "set device." For example, the display device may include a liquid crystal display (LCD) or organic light emitting diode (OLED) display panel and a source PCB, which is a controller for driving the display panel. The set device may further include a set PCB, which is a set controller electrically connected to the source PCB and drives the entire set device.

The display panel used in the embodiments of the present specification may be any type of display panel, such as a liquid crystal display panel, an organic light emitting diode (OLED) display panel, and an electroluminescent display panel, and the embodiments are not limited thereto. For example, the display panel may be a display panel that can generate sound by vibrating with a vibration device according to the embodiments of the present specification. The display panel applied to the display device according to the embodiments of the present specification is not limited to the shape or size of the display panel.

The features of the various embodiments of this specification may be combined or combined with each other in part or in whole, and various technical interlocking and driving mechanisms may be possible, and each embodiment may be implemented independently of the others or may be implemented together in a related relationship.

The following detailed description of the embodiments of the present specification will be given with reference to the accompanying drawings and examples. The scales of the components shown in the drawings are different from the actual scales for the convenience of explanation, and are not limited to the scales shown in the drawings.

Various embodiments of the present specification will be described in detail below with reference to the drawings.

Figure 1 is a plan view that shows a schematic diagram of an example of a display device according to one embodiment of the present specification.

The display device 10 may include a plurality of regions. For example, the display device 10 may include one or more display areas AA in which an image is displayed, and a pixel PXL array is formed inside the display area AA. One or more non-display areas NA in which no image is displayed may include a driving circuit section and a dam section, and may be provided on one side of the display area AA. For example, the non-display area NA may be adjacent to one or more sides of the display area AA.

Referring to FIG. 1, the non-display area NA may be located outside and surround the substantially rectangular display area AA. However, it should be understood that the shape of the display area AA and the arrangement of the non-display area NA adjacent to the display area AA are not specifically limited to the exemplary display device 10 illustrated in FIG. 1. The display area AA and the non-display area NA may be any shape of the display device 10. Examples of such shapes may include pentagons, hexagons, circles, ellipses, etc., and examples herein are not limited thereto.

Each pixel PXL in the display area AA includes a subpixel, which can display colors such as red (R), green (G), blue (B), and white (W). Each pixel PXL and subpixel may also be associated with a pixel circuit including one or more transistors (TFTs: Thin Film Transistors) fabricated on a substrate of the display device 10. Each pixel circuit may be electrically coupled to gate lines and data lines for communication with one or more driving circuits, e.g., a gate driver GIP and a data driver D-IC located in the non-display area NA of the display device 10.

One or more driving circuits may be implemented with TFTs arranged in the non-display area NA as shown in FIG. 1. For example, the gate driver GIP may be implemented using a plurality of TFTs on the substrate of the display device 10. Non-limiting examples of circuits that may be implemented with TFTs on the substrate may include inverter circuits, multiplexers, and ESD (electro static discharge) circuits, and the embodiments herein are not limited thereto.

Some of the driving circuits may be provided as integrated circuit (IC) chips and mounted in the non-display area NA of the display device 10 using chip-on-glass (COG) or other similar methods. Some of the driving circuits may also be mounted on another substrate and coupled to connection interfaces (pads/bumps, pins) located in the non-display area NA using a printed circuit such as a flexible printed circuit board (PCB), chip-on-film (COF), tape-carrier-package (TCP) or other suitable technology.

In embodiments herein, at least two different types of TFTs are used in a TFT substrate for a display. The types of TFTs employed as part of the pixel circuitry and as part of the driving circuitry may vary depending on the requirements of the display.

For example, the pixel circuits may be implemented with TFTs having an oxide active layer (oxide TFTs) and the drive circuits may be implemented with TFTs having a low temperature polysilicon active layer (LTPS TFTs) and TFTs having an oxide active layer. Unlike LTPS TFTs, oxide TFTs do not have issues with threshold voltage Vth variation from the pixel-to-pixel. A uniform threshold voltage Vth may also be obtained in an array of pixel circuits for a display. Issues with threshold voltage Vth uniformity among TFTs implementing the drive circuits will have less direct impact on pixel brightness uniformity.

The drive circuit (e.g., GIP) incorporates gate drive ICs inside the display panel, reducing the number of drive ICs and thereby reducing costs, and can provide high-speed scan signals to the display area of the display panel.

By using on-substrate driving circuits implemented with LTPS TFTs, signals and data can be provided to pixels at a higher clock than if all TFTs in a TFT panel were formed with oxide TFTs. Thus, a display capable of high speed operation can be provided without unevenness. For example, the advantages of oxide TFTs and LTPS TFTs can be combined with the design of a TFT panel, and oxide TFTs and LTPS TFTs can be selected and used according to their respective advantages.

The display area AA can include a first area PH. The first area PH includes a hole area H and a first pattern portion PT1, a first dam portion DM, a second pattern portion PT2, and a routing wiring area RK surrounding the hole area H in order to position a camera within the display area AA, and the configurations of these will be described in detail below.

Figures 2 and 3 are three-dimensional diagrams that diagrammatically illustrate an example of a display device according to one embodiment of the present specification.

A display device according to one embodiment of this specification may be applied to a foldable display device.

A foldable display device can include at least one display area AA.

A foldable display device may be arranged such that one display area of the display device is folded along a folding line to be divided into a first display area AA1 and a second display area AA2, or may have multiple display areas inside and outside the display device. Pixels PXL are formed in the display areas.

Referring to FIG. 3, the foldable display device may further include a first display area AA1 and a second display area AA2 arranged inside the display device, and a third display area AA3 arranged outside the display device.

Referring to Figures 2 and 3, the first area PH for arranging a camera within the display area AA may be arranged in one or more of the first display area AA1 arranged inside the display device, the second display area AA2, or the third display area AA3 arranged outside the display device.

Figure 4 is an enlarged view that shows a schematic diagram of the first region PH of the display device 10 of this specification.

The first area PH includes a hole area H and a first pattern portion PT1, a first dam portion DM, a second pattern portion PT2, and a routing wiring area RK surrounding the hole area H in order to position a camera within the display area AA.

Figure 5 is a cross-sectional view that shows a schematic example of a cross section taken along line A-A' in Figure 1.

Referring to FIG. 5, the substrate 100 of the display device according to the embodiment of the present specification may consist of a first substrate, a second substrate, and an intermediate layer between the first substrate and the second substrate.

The first and second substrates may be formed of at least one of polyimide, polyethersulfone, polyethylene terephthalate, and polycarbonate, and the embodiments of the present specification are not limited thereto. When the substrate is made of a plastic material, the display device may be manufactured with a support substrate made of glass disposed under the substrate, and the support substrate may be released after the display device manufacturing process is completed. In addition, after the support substrate is released, a back plate (or plate) for supporting the substrate may be disposed under the substrate. When the substrate is made of a plastic material, moisture may penetrate the substrate and reach the thin film transistor or light emitting element layer, thereby degrading the performance of the display device. The display device according to the embodiment of the present specification may be composed of two substrates, a first substrate and a second substrate, each of which is made of a plastic material, in order to prevent the performance of the display device from deteriorating due to moisture permeation. In addition, by forming an intermediate layer, which is an inorganic film, between the first substrate and the second substrate, it is possible to block moisture from penetrating the substrates and improve the performance reliability of the product. The intermediate layer may be composed of an inorganic film. For example, the intermediate layer may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, but is not limited thereto.

The display device formed on the substrate 100 may include multiple regions. In this specification, it is configured with a display region AA and a non-display region NA, but is not limited to this.

A buffer layer consisting of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of these may be disposed on one side of the display area AA and the non-display area NA on the substrate 100. The buffer layer may improve the adhesion between the layers formed on the buffer layer and the substrate 100, and may serve to block various types of defect factors such as alkaline components that flow out from the substrate 10. The buffer layer may also delay the diffusion of moisture or oxygen that has penetrated into the substrate 100.

The buffer layer may be omitted depending on the type and material of the substrate, the structure and type of thin film transistor, etc.

Transistors of the display area AA and the non-display area NA may be formed on the substrate 100 and the buffer layer. The transistors of the display area AA may include a switching transistor SW Tr and a driving transistor DR Tr for driving the subpixel, and the transistors of the non-display area NA may include a first gate driving transistor GT1 and a second gate driving transistor GT2 for driving the gate driver GIP.

The drive transistor DR Tr may have a light-shielding layer 200 disposed on the substrate 100 or buffer layer.

The light-shielding layer 200 blocks light directed toward the first semiconductor layer 210 of the driving transistor DR Tr, and is connected to the first drain electrode 230D to prevent a phenomenon in which parasitic carriers accumulate in the first semiconductor layer 210, causing a sudden increase in drain current, and a change in threshold voltage due to this phenomenon.

The light-shielding layer 200 may be formed of a single layer or multiple layers having at least one of titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), gold (Au), neodymium (Nd) and nickel (Ni), and the embodiments herein are not limited thereto.

A first insulating layer 110 may be disposed on top of the light-shielding layer 200.

The first insulating layer 110 may be formed of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be formed of other insulating inorganic or organic materials, but the embodiments of this specification are not limited thereto.

The first semiconductor layer 210 of the driving transistor DR Tr in the display area AA and the second semiconductor layer 400 of the first gate driving transistor GT1 in the non-display area NA may be arranged on the first insulating layer 110, and the first semiconductor layer 210 may overlap the light-shielding layer 200.

The first semiconductor layer 210 and the second semiconductor layer 400 may be made of a metal oxide semiconductor, for example, any one of IGZO (indium-gallium-zinc-oxide), IZO (indium-zinc-oxide), IGTO (indium-gallium-tin-oxide), and IGO (indium-gallium-oxide), but are not limited thereto.

The conductive properties of the metal oxide semiconductor can be improved by a doping process in which impurities are injected, and the metal oxide semiconductor can include a channel region in which a channel through which electrons and holes move is formed, and a source region and a drain region, which are conductive regions on both sides of the channel region. A source electrode and a drain electrode can be connected to the source region and the drain region.

A first gate insulating layer 120 may be disposed on the first semiconductor layer 210 and the second semiconductor layer 400. The first gate insulating layer 120 may be formed of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be formed of an insulating inorganic or organic material, and the embodiments of the present specification are not limited thereto.

The first gate electrode 220 and the second gate electrode 410 may be disposed on the first gate insulating layer 120, overlapping the first semiconductor layer 210 and the second semiconductor layer 400, and the first gate electrode 220 and the second gate electrode 410 may be formed of one or more materials selected from the group consisting of silver (Ag), molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and gold (Au), but the embodiments of the present specification are not limited thereto.

The first capacitor electrode Cst1 of the capacitance PXL Cst included in the subpixel, the first metal layer 300 overlapping the switching transistor SW Tr of the subpixel, and the second metal layer 500 overlapping the second gate driving transistor GT2 can be formed and arranged in the same process as the first gate electrode 220 and the second gate electrode 410.

The first metal layer 300 and the second metal layer 500 may be driven by the lower gate electrodes of the switching transistor SW Tr and the second gate drive transistor GT2, respectively, or may be used as a light blocking layer that blocks light reflected by the third semiconductor layer 310 and the fourth semiconductor layer 510 of the switching transistor SW Tr and the second gate drive transistor GT2, but the embodiments of this specification are not limited thereto.

A second insulating layer 130 may be disposed on the first gate electrode 220, the second gate electrode 410, the first metal layer 300, the second metal layer 500 and the first capacitor electrode Cst1.

The second insulating layer 130 may be formed of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be formed of other insulating inorganic or organic materials, but the embodiments of this specification are not limited thereto.

A second capacitor electrode Cst2 of the subpixel capacitance PXL Cst may be disposed on the second insulating layer 130. The second capacitor electrode Cst2 may be disposed to overlap the first capacitor electrode Cst1 and may be formed of the same material as the first capacitor electrode Cst1.

A third insulating layer 140 may be disposed on the second capacitor electrode Cst2.

The third insulating layer 140 may be formed of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be formed of an insulating organic material, but the embodiments of this specification are not limited thereto.

The third insulating layer 140 may have the third semiconductor layer 310 of the switching transistor SWTr in the display area AA and the fourth semiconductor layer 510 of the second gate driving transistor GT2 in the non-display area NA disposed on it.

The third semiconductor layer 310 and the fourth semiconductor layer 510 may be formed of low temperature polycrystalline silicon (LTPS).

A second gate insulating layer 150 may be disposed on the third semiconductor layer 310 and the fourth semiconductor layer 510. The second gate insulating layer 150 may be disposed between the third semiconductor layer 310 and the fourth semiconductor layer 510 and the third gate electrode 320 and the fourth gate electrode 520 to insulate the third semiconductor layer 310 and the fourth semiconductor layer 510 from the third gate electrode 320 and the fourth gate electrode 520.

The LPTS semiconductor layer may be doped to form a channel region and source/drain regions connected to the source/drain electrodes.

The second gate insulating layer 150 may be formed of an insulating inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may be formed of an insulating organic material, but is not limited thereto.

The third gate electrode 320 and the fourth gate electrode 520 can be arranged to overlap the third semiconductor layer 310 and the fourth semiconductor layer 510.

The third gate electrode 320 and the fourth gate electrode 520 may be formed of a single layer or multiple layers of any one of silver (Ag), molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and gold (Au), or an alloy thereof, but are not limited thereto.

A fourth insulating layer 160 may be disposed on the third gate electrode 320 and the fourth gate electrode 520.

The fourth insulating layer 160 may be formed of an insulating inorganic material such as silicon nitride (SiNx) and silicon oxide (SiOx), or may be formed of one or more organic insulating materials such as BCB (BenzoCycloButene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but the embodiments of the present specification are not limited thereto.

On the fourth insulating layer 160, a first source electrode 230S and a first drain electrode 230D connected to the first semiconductor layer 210, a second source electrode 420S and a second drain electrode 420D connected to the second semiconductor layer 400, a third source electrode 330S and a third drain electrode 330D connected to the third semiconductor layer 310, and a fourth source electrode 530S and a fourth drain electrode 530D connected to the fourth semiconductor layer 510 may be arranged.

The first source electrode 230S, the first drain electrode 230D, the second source electrode 420S and the second drain electrode 420D are connected to the first semiconductor layer 210 and the second semiconductor layer 400 through contact holes formed in the first gate insulating layer 120, the second insulating layer 130, the third insulating layer 140, the second gate insulating layer 150 and the fourth insulating layer 160.

The third source electrode 330S, the third drain electrode 330D, the fourth source electrode 530S and the fourth drain electrode 530D are connected to the third semiconductor layer 310 and the fourth semiconductor layer 510 through contact holes formed in the second gate insulating layer 150 and the fourth insulating layer 160.

The first source electrode 230S, the first drain electrode 230D, the second source electrode 420S, the second drain electrode 420D, the third source electrode 330S, the third drain electrode 330D, the fourth source electrode 530S and the fourth drain electrode 530D may be formed through the same process and may be made of one or more of silver (Ag), molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W) and gold (Au).

The first wiring 630 can be formed and arranged in the non-display area NA in the same process as the first source electrode 230S, the first drain electrode 230D, the second source electrode 420S, the second drain electrode 420D, the third source electrode 330S, the third drain electrode 330D, the fourth source electrode 530S and the fourth drain electrode 530D.

The first wiring 630 may be a wiring for transmitting a voltage applied to the cathode electrode 620.

A first planarization layer 170 may be disposed on the first source electrode 230S, the first drain electrode 230D, the second source electrode 420S, the second drain electrode 420D, the third source electrode 330S, the third drain electrode 330D, the fourth source electrode 530S and the fourth drain electrode 530D.

The first planarization layer 170 is formed of an organic insulating layer such as polyacrylate and polyimide, and can reduce steps caused by wiring and contact holes formed below.

A connecting electrode 240 for connecting the first drain electrode 230D and the anode electrode 600 may be disposed on the first planarization layer 170.

The connecting electrode 240 can be electrically connected to the first drain electrode 230D through a hole formed in the first planarization layer 170.

The connecting electrode 240 may be made of at least one of titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), gold (Au), neodymium (Nd), and nickel (Ni), or an alloy thereof, but the embodiments of this specification are not limited thereto.

A second planarization layer 180 may be disposed on the connecting electrode 240. The second planarization layer 180 may be formed of an organic insulating layer such as polyacrylate and polyimide, but the embodiments of the present specification are not limited thereto.

An anode electrode 600 may be disposed on the second planarization layer 180. The anode electrode 600 may be electrically connected to the connecting electrode 240 through a hole formed in the second planarization layer 180.

The second wiring 640 can be formed in the non-display area NA in the same process as forming the anode electrode 600. The second wiring 640 can be arranged to overlap a portion of the first gate driving transistor GT1 and the second gate driving transistor GT2, and can be connected to the first wiring 630 arranged in the non-display area NA to apply a voltage to the cathode electrode 620.

The anode electrode 600 and the second wiring 640 may be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), lead (Pd), indium tin oxide (ITO), indium zinc oxide (IZO), or an alloy thereof, but the embodiments of this specification are not limited thereto.

A bank 190 may be disposed on the anode electrode 600, the second wiring 640, and the second planarization layer 180.

The bank 190 can separate multiple sub-pixels SP, minimizing the light bleeding phenomenon and preventing color mixing that occurs at various viewing angles.

The bank 190 exposes the anode electrode 600 corresponding to the light-emitting area and may overlap the end of the anode electrode 600.

The bank 190 may be made of at least one of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiOx) or organic insulating materials such as BCB (BenzoCycloButene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

A spacer 191 may be further disposed on the bank 190. The spacer 191 supports the gap between the substrate 100 on which the light emitting element layer 610 is formed and the upper substrate, thereby minimizing damage to the elements inside the display panel when a physical impact occurs from the outside. The spacer 191 may be formed of the same material as the bank 190 and may be formed at the same time as the bank 190, but is not limited thereto.

The light emitting element layer 610 may be disposed on the opening of the bank 190 exposing the anode electrode 600. The light emitting element layer 610 may include one or more organic light emitting layers selected from a red light emitting layer, a green light emitting layer, a blue light emitting layer, and a white light emitting layer to emit light of a specific color. In addition to the organic light emitting layer, the light emitting element layer 610 may further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like, but is not limited thereto.

The hole injection layer, hole transport layer, electron transport layer, and electron injection layer may be arranged in each subpixel with different thicknesses and materials, or may be commonly arranged on the front surface.

When the light-emitting element layer 610 includes a white organic light-emitting layer, the light-emitting element layer 610 can be disposed over the opening of the bank 190 and the entire substrate.

A color filter may be disposed on top of the light emitting element layer 610 to convert the light emitted from the white organic light emitting layer into light of a different color.

A cathode electrode 620 may be disposed on the light emitting element layer 610. The cathode electrode 620 supplies electrons to the light emitting element layer 610 and may be made of a conductive material with a low work function.

When the display device 10 is a top emission type, the cathode electrode 620 may be disposed using a transparent conductive material through which light can pass. For example, the cathode electrode 620 may be formed of at least one of indium tin oxide (ITO) and indium zinc oxide (IZO), but is not limited thereto.

It may also be arranged using a semi-transparent conductive material that transmits light. For example, it may be formed of at least one of alloys such as LiF/Al, CsF/Al, Mg:Ag, Ca/Ag, Ca:Ag, LiF/Mg:Ag, LiF/Ca/Ag, and LiF/Ca:Ag, but is not limited thereto.

When the display device 10 is a bottom emission type, the cathode electrode 620 may be a reflective electrode that reflects light and may be disposed using an opaque conductive material. For example, the cathode electrode 620 may be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

The non-display area NA of the display device 10 is provided with a drive circuit section and a terminal section including a second dam section in which multiple dams are arranged.

The end of the non-display area NA may be a connection part electrically connected to the cathode electrode 620 and wiring that applies a voltage to the cathode electrode 620, and may be an area where the display device 10 is sealed using a number of dams.

The first insulating layer 110, the first gate insulating layer 120, the second insulating layer 130 and the third insulating layer 140 arranged on the substrate 100 may be extended to the termination portion.

Wiring may be arranged at the end so that the power supply voltage and touch signals applied to the FPCB of the display device 10 are connected to the display panel through the wiring.

The first wiring 630 may be disposed on the top of the fourth insulating layer 160 and in contact with the sides of the fourth insulating layer 160 and the second gate insulating layer 150, and may extend between the first dam DM1 and the third insulating layer 140 in the non-display area NA.

The first dam DM1 can be formed and stacked using the same material and process as the first planarization layer 170 and the bank 190.

The second dam DM2 can be formed and stacked using the same material and process as the first planarization layer 170, the second planarization layer 180, the bank 190 and the spacer 191.

The first dam DAM1 and the second dam DAM2 can have a first height and a second height, respectively, and can surround the display area AA.

The second height may be greater than the first height. Even if the second sealing layer 720 exceeds the first dam DM1 of the second dam portion, it may not be formed on the outer periphery of the second dam portion due to the second dam DM2.

The first sealing layer 710 and the third sealing layer 730 may be arranged to extend beyond the second dam DM2 to the outer shell.

The second wiring 640 may be arranged to extend between the first planarization layer 170 and the bank 190 of the first dam DM1 and between the second planarization layer 180 and the bank 190 of the second dam DM2.

The cathode electrode 620 may extend to the region between the first dam DM1 and the second dam DM2 and be electrically connected to the first wiring 630 and the second wiring 640.

A sealing layer 700 may be disposed on the cathode electrode 620 in the display area AA, the cathode electrode 620 in the non-display area NA, and the second dam DM2.

The encapsulation layer 700 can protect the display device 10 from external moisture, oxygen, or foreign matter. For example, the encapsulation layer 700 can prevent the penetration of oxygen and moisture from the outside to prevent oxidation of the luminescent material and electrode material.

The encapsulation layer 700 may be made of a transparent material so that the light emitted from the light emitting element layer 610 can pass through.

The sealing layer 700 may include a first sealing layer 710, a second sealing layer 720, and a third sealing layer 730 that block the penetration of moisture and oxygen, but the examples of this specification are not limited thereto. The first sealing layer 710, the second sealing layer 720, and the third sealing layer 730 may have a structure in which they are stacked in sequence, but the examples of this specification are not limited thereto.

The first sealing layer 710 and the third sealing layer 730 may be made of at least one inorganic material selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx) and aluminum oxide (AlyOz), but are not limited thereto.

The second sealing layer 720 can cover foreign matter or particles that may occur during the manufacturing process. In addition, the second sealing layer 720 can flatten the surface of the first sealing layer 710.

The second sealing layer 720 may be an organic material, such as, but not limited to, silicon oxycarbon (SiOCz), epoxy, polyimide, polyethylene, acrylate, and other polymers.

A touch buffer layer 800 may be disposed on the third sealing layer 730. The touch buffer layer 800 may be disposed on the front surface of the display area AA and the non-display area NA, and may be disposed extending to the pad portion. The touch buffer layer 800 may be a first insulating layer, and is not limited to the term.

The touch buffer layer 800 may be made of at least one inorganic material selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx) and aluminum oxide (AlyOz), but is not limited thereto.

A first touch electrode 810 may be disposed on the touch buffer layer 800.

Touch drive can be performed using a plurality of sensing electrodes and a plurality of driving electrodes arranged in the display area AA. The sensing electrodes extend along a first direction and include a plurality of sub-sensing electrodes Rx arranged at regular intervals from each other along a second direction. The plurality of sensing electrodes can be formed continuously without interruption in the first direction.

The plurality of driving electrodes extend along the second direction and include a plurality of sub-driving electrodes Tx arranged at regular intervals from each other along the first direction. The plurality of sub-driving electrodes Tx may be electrically connected to each other in the second direction.

When multiple sub-sensing electrodes Rx and multiple sub-driving electrodes Tx are formed in the same layer, the multiple sub-driving electrodes Tx can be electrically connected by a bridge pattern.

The multiple sub-sensing electrodes Rx and the multiple sub-driving electrodes Tx may have a metal mesh structure.

In addition, a plurality of sub-sensing electrodes Rx can be electrically connected by a bridge pattern, and a plurality of sub-driving electrodes Tx can be formed continuously without interruption and electrically connected.

The first touch electrode 810 may electrically connect a plurality of sub-sensing electrodes Rx or a plurality of sub-driving electrodes Tx to each other.

The first touch electrode 810 may have a single layer or multi-layer structure made of a metal material such as molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Ti), titanium/aluminum/titanium (Ti/Al/Ti), molybdenum/aluminum/molybdenum (Mo/Al/Mo), etc., but is not limited thereto.

A touch insulating layer 820 may be disposed on the first touch electrode 810. The touch insulating layer 820 may be disposed on the front surface of the display area AA and the non-display area NA, and may be disposed extending to the pad portion. The touch insulating layer 820 may be a second insulating layer, and is not limited to the term.

The touch insulating layer 820 may be made of at least one inorganic material selected from the group consisting of silicon nitride (SiNx), silicon oxide (SiOx) and aluminum oxide (AlyOz), but is not limited thereto.

A second touch electrode 830 may be disposed on the touch insulation layer 820. The second touch electrode 830 may be a plurality of sub-sensing electrodes Rx or a plurality of sub-driving electrodes Tx for touch driving.

A touch line 840 for transmitting a touch driving signal to the non-display area NA can be arranged in the same process in which the second touch electrode 830 is formed.

The touch line 840 may overlap the first gate driving transistor GT1 or the second gate driving transistor GT2 and may be arranged to extend to the pad portion.

The second touch electrode 830 and the touch line 840 may have a single-layer or multi-layer structure made of a metal material such as molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Ti), titanium/aluminum/titanium (Ti/Al/Ti), molybdenum/aluminum/molybdenum (Mo/Al/Mo), etc., but are not limited thereto.

A third planarization layer 850 may be disposed on the second touch electrode 830 and the touch line 840.

The third planarization layer 850 may cover and planarize the second touch electrode 830, the touch line 840, and the touch insulating layer 820. In addition, the third planarization layer 850 may be made of one or more organic insulating materials such as BCB (BenzoCycloButene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

An adhesive layer 900 and a cover window 910 may be disposed on the third planarization layer 850.

The first region PH shown in FIG. 4 will be described in detail with reference to FIG. 6 and FIG. 7.

The first region PH includes a hole region H, a first pattern portion PT1 surrounding the hole region H, a first dam portion DM, and a second pattern portion PT2 and a routing wiring region RK in order to position a camera within the display region AA.

The hole region H may be located in the center of the first region PH and may be formed to physically penetrate from the substrate 100 to the third planarization layer 850. The hole region H may include a camera, a sensor, and a light source, and the hole region H may allow light to easily pass through above the camera or sensor.

The routing wiring region RK has routing wiring arranged to electrically connect the sub-pixels of the display area AA to each other between the first region PH.

The first routing wiring 20 may be formed on the first gate insulating layer 120 extending into the first region PH in the same process as the process of forming the first gate electrode 220, the second gate electrode 410, the first metal layer 300, the second metal layer 500 and the first capacitor electrode Cst1, but the embodiments of this specification are not limited thereto.

The second routing wiring 30 may be formed in the same process as the process of forming the second capacitor electrode Cst2 on the second insulating layer 130 extending in the first region PH, but the embodiments of this specification are not limited thereto.

The third routing wiring 40 may be formed on the fourth insulating layer 160 extending into the first region PH in the same process as the first source electrode 230S, the first drain electrode 230D, the second source electrode 420S, the second drain electrode 420D, the third source electrode 330S, the third drain electrode 330D, the fourth source electrode 530S and the fourth drain electrode 530D, but the embodiments of this specification are not limited thereto.

The fourth routing wiring 50 may be formed in the same process as the connecting electrode 240 on the first planarization layer 170 that is arranged to extend into the first region PH, but the embodiments of this specification are not limited thereto.

In the routing wiring area RK, the first touch electrode 810 and the second touch electrode 830 are formed with wiring for routing wiring, and can electrically connect the touch driving signal of the display area AA.

The gate lines of the subpixels in the display area AA can be electrically connected to the first routing wiring 20 and the second routing wiring 30, and the data lines of the subpixels can be electrically connected to the third routing wiring 40 and the fourth routing wiring 50, and the data lines of the subpixels can be electrically connected to the first area PH.

The first pattern portion PT1 and the second pattern portion PT2 are arranged to surround the hole region H. The first pattern portion PT1 and the second pattern portion PT2 include a plurality of patterns PT, and each of the plurality of patterns PT may include a lower pattern PTa and an upper pattern PTb. The lower pattern PTa may be formed of the same material as the fourth insulating layer 160 at the same time. The upper pattern PTb may be formed of the same material as the second planarization layer 180 at the same time. However, the material and number of layers of the insulating layers of the plurality of patterns PT are not limited thereto.

In addition, multiple patterns PT can be arranged at a fixed distance from each other.

The multiple patterns PT can prevent moisture from penetrating into the display area AA through the light emitting element layer 610, which is vulnerable to moisture penetration.

The width of the bottom surface of the upper pattern PTb, which is placed on the lower pattern PTa, is wider than the top surface of the lower pattern PTa.

The light emitting element layer 610 arranged on the upper and side surfaces of the upper pattern PTb may be disconnected by multiple patterns PT because the light emitting element layer 610 is not formed on the side surface of the lower pattern PTa due to the separation space between the lower surface of the upper pattern PTb and the side surface of the lower pattern PTa.

The first sealing layer 710 arranged in the routing wiring region RK, the first pattern portion PT1, the first dam portion DM, and the second pattern portion PT2 of the first region PH may be formed on the upper surface and side surfaces of the upper pattern PTb and part of the lower surface of the upper pattern PTb, and may not be formed on part of the side surfaces of the lower pattern PTb, so that an empty space (ES) may be formed.

A hold dam HDM may be disposed in the first dam portion DM between the first pattern portion PT1 and the second pattern portion PT2.

The hole dam HDM can prevent the second sealing layer 720 from overflowing into the hole region H. One or more of the hole dam HDM can be arranged in succession and can be arranged within the first pattern portion PT1 and the second pattern portion PT2.

The hole dam HDM may be formed by stacking patterns formed of the same material and in the same process when forming the fourth insulating layer 160, the second planarization layer 180, and the bank 190, but the embodiments of this specification are not limited thereto.

The second sealing layer 720 may be disposed only on the second pattern portion PT2 and a portion of the hold dam HDM due to the hold dam HDM.

The third sealing layer 730 may be disposed in the routing wiring region RK, the first pattern portion PT1, the dam portion DM, and the second pattern portion PT2 of the first region PH, and may be in contact with or in contact with the first sealing layer 710 on the top and side surfaces of the multiple patterns PT of the first pattern portion PT1.

The touch buffer layer 800 may be disposed extending on the third sealing layer 730 in the routing wiring region RK, the first pattern portion PT1, the dam portion DM and the second pattern portion PT2 of the first region PH.

The touch insulation layer 820 is arranged to extend over the routing wiring region RK, the first pattern portion PT1, the dam portion DM and the second pattern portion PT2 of the first region PH, and may be arranged on the touch buffer layer 800 in contact with the upper surface of the touch buffer layer 800 on the second pattern portion PT2 and the hole dam HDM.

In the area between the patterns PT of the first pattern unit PT1, a protective layer 60 may be disposed between the touch buffer layer 800 and the touch insulation layer 820 to separate the touch buffer layer 800 and the touch insulation layer 820.

The protective layer 60 may have an end that partially overlaps with the multiple patterns PT between the multiple patterns PT of the first pattern portion PT1.

The protective layer 60 may be made of at least one organic insulating material such as, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

Moisture introduced through the hole region H may permeate the voids (ES) formed in the pattern PT of the first pattern unit PT1 through the third planarization layer 850 made of an organic material and move to the display area AA, thereby degrading the quality of the display panel.

The protective layer 60 may be disposed between the multiple patterns PT, and the touch buffer layer 800 on the upper surface of the multiple patterns PT may be in contact with the touch insulating film 820.

Even though the protective layer 60 is made of an organic material, it is not connected by the touch buffer layer 800 and the touch insulating film 820 on the upper surfaces of the multiple patterns PT, so the protective layer 60 can prevent moisture from moving.

In addition, the formation of the protective layer 60 increases the distance between the void (ES) and the seam and the third planarization layer 850, so that moisture in the third planarization layer 850 is not transferred.

The first height H1 from the lower surface of the lower pattern PTa to the upper surface of the upper pattern PTb of the multiple patterns PT of the first pattern portion PT1 and the second height H2 from the lower surface of the lower pattern PTa to the upper surface of the protective layer 60 may be different from each other, and the second height H2 may be higher than the first height H1.

The first pattern part PT1 is adjacent to the hole region H, and the sides of insulating layers such as the pattern PT, the first sealing layer 710, the third sealing layer 730, the touch buffer layer 800 and the touch insulating layer 820 arranged at the end Ed of the first pattern part PT1 may be exposed to the hole region H.

The support plate 70 of the display device 10 may be disposed on the lower part of the substrate 100, and a hole may be formed in the hole region H so that the support plate 70 corresponds to the hole region H, and an optical unit 101 including a camera, a sensor, a light source, etc. may be disposed in the hole.

The display device according to the embodiment of this specification can be described as follows.

A display device according to an embodiment of the present specification includes a substrate including a display region and a non-display region, a first region disposed in the display region and a hole region in the first region, a first pattern portion, a first dam portion, and a second pattern portion, and includes a sealing layer on at least a portion of the first region, a first insulating layer and a second insulating layer, and a plurality of first patterns disposed in the first pattern portion, the first insulating layer and the second insulating layer being spaced apart from each other between the plurality of first patterns, and the first insulating layer and the second insulating layer being in contact with each other on at least a portion of the upper surface of the plurality of first patterns.

According to some embodiments of the present specification, the second pattern portion may include a plurality of second patterns disposed therein, the sealing layer being on the plurality of second patterns, and the first insulating layer and the second insulating layer may be in contact with each other in the second pattern portion.

According to some embodiments herein, a protective layer may be disposed between the first insulating layer and the second insulating layer between the plurality of first patterns.

According to some embodiments of the present specification, a first height from the lower surface to the upper surface of the plurality of first patterns and a second height from the lower surface of the first patterns to the upper surface of the protective layer may be different from each other.

According to some embodiments herein, the second height may be greater than the first height.

According to some embodiments herein, the end of the protective layer may overlap the first patterns.

According to some embodiments of the present disclosure, the display may include a plurality of pixels disposed in a display area and a plurality of transistors disposed in the plurality of pixels.

According to some embodiments of the present disclosure, the device may include an anode electrode, a light-emitting layer, and a cathode electrode electrically connected to the plurality of transistors.

According to some embodiments herein, the sealing layer may be disposed on the cathode electrode.

According to some embodiments herein, the touch panel may include a first touch electrode disposed on a first insulating layer, a second insulating layer, and a second touch electrode.

According to some embodiments herein, the sealing layer can include a first sealing layer, a second sealing layer, and a third sealing layer.

According to some embodiments herein, the sides of the first sealing layer, the third sealing layer, the first insulating layer, and the second insulating layer may be exposed in the first region.

According to some embodiments herein, the device may further include a camera, a sensor, and a light source disposed in the first region.

According to some embodiments of the present specification, the display device may further include a driving circuit section and a second dam section arranged in the non-display area.

The display device according to the embodiment of the present specification includes a substrate including a display region and a non-display region, a first region and a plurality of pixels arranged in the display region, and a plurality of transistors arranged in the plurality of pixels, a planarization layer arranged on the plurality of transistors, an anode electrode, a light-emitting layer, and a cathode electrode arranged on the planarization layer, a sealing layer arranged on the cathode electrode, and a first insulating layer arranged on the sealing layer. The display device includes a first touch electrode, a second insulating layer, and a second touch electrode, and a first pattern portion, a first dam portion, and a second pattern portion in the first region, and the first insulating layer and the second insulating layer are arranged to extend to the first pattern portion, the first dam portion, and the second pattern portion.

According to some embodiments herein, the first pattern portion may include a plurality of first patterns disposed thereon.

According to some embodiments of the present specification, the first insulating layer and the second insulating layer may contact each other on a portion of the upper surface of the first patterns.

According to some embodiments herein, the first insulating layer and the second insulating layer may be spaced apart between the first patterns.

According to some embodiments herein, a protective layer may be disposed between the first insulating layer and the second insulating layer between the plurality of first patterns.

According to some embodiments of the present specification, a first height from the lower surface to the upper surface of the plurality of first patterns and a second height from the lower surface of the first patterns to the upper surface of the protective layer may be different from each other.

According to some embodiments herein, the second height may be greater than the first height.

According to some embodiments herein, the end of the protective layer may overlap the first patterns.

According to some embodiments herein, the second pattern portion may include a plurality of second patterns disposed thereon.

According to some embodiments of the present specification, a sealing layer, a first insulating layer and a second insulating layer may be disposed extending over the plurality of second patterns.

According to some embodiments herein, the first insulating layer and the second insulating layer may be in contact on the second pattern portion.

According to some embodiments herein, the sealing layer can include a first sealing layer, a second sealing layer, and a third sealing layer.

According to some embodiments herein, the sides of the first sealing layer, the third sealing layer, the first insulating layer, and the second insulating layer may be exposed in the first region.

According to some embodiments herein, the hall region disposed in the first region may further include a camera, a sensor, and a light source.

According to some embodiments of the present specification, the display device may further include a driving circuit section and a second dam section arranged in the non-display area.

Although the embodiments of the present specification have been described in more detail above with reference to the attached drawings, the present specification is not necessarily limited to such embodiments, and various modifications may be made without departing from the technical ideas of the present specification. Therefore, the embodiments disclosed in the present specification are intended to illustrate, not limit, the technical ideas of the present specification, and such embodiments do not limit the scope of the technical ideas of the present specification. Therefore, the embodiments described above should be understood to be illustrative in all respects and not limiting. The scope of protection of the present specification should be interpreted according to the scope of the claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of rights of the present specification.

PH: First region RK: Routing wiring region PT1: First pattern portion PT2: Second pattern portion H: Hole region 101: Optical portion 70: Support plate HDM: Hole dam 60: Protective layer 710: First sealing layer 720: Second sealing layer 730: Third sealing layer 800: Touch buffer layer 820: Touch insulation layer

Claims (29)

Display area;
a first region disposed in the display region , the first region having a hole region and a first pattern portion adjacent to the hole region ;
A plurality of first patterns disposed in the first pattern portion; and
a first insulating layer and a second insulating layer disposed on the plurality of first patterns ;
A display device comprising:
the first insulating layer and the second insulating layer are spaced apart from each other between the first patterns ;
the first insulating layer and the second insulating layer are in contact with each other on an upper surface of each of the first patterns;
A display device , wherein a height of the first insulating layer above each of the plurality of first patterns is greater than a height of the first insulating layer between the plurality of first patterns . the first region further includes a second pattern portion adjacent to the first pattern portion and a plurality of second patterns disposed in the second pattern portion,
A sealing layer is disposed on the plurality of second patterns without extending to the first pattern portion;
The display device according to claim 1 , wherein the first insulating layer and the second insulating layer are disposed on the sealing layer in the second pattern portion . The display device of claim 1 , wherein the first insulating layer and the second insulating layer are separated from each other by a protective layer between the plurality of first patterns. The display device of claim 3 , wherein an upper surface of each of the plurality of first patterns is lower than an upper surface of the protective layer . The display device according to claim 3 , wherein the protective layer partially overlaps the first patterns . The display device of claim 2 , wherein the first region further includes a first dam portion between the first pattern portion and the second pattern portion, and a hole dam disposed in the first dam portion . The display device of claim 6 , wherein an upper surface of the hole dam is higher than an upper surface of each of the second patterns . each of the plurality of first patterns includes a lower pattern and an upper pattern disposed on the lower pattern;
The display device of claim 1 , wherein a lower surface of the upper pattern is wider than an upper surface of the lower pattern . The display device of claim 8 , wherein an empty space is formed between a side surface of the lower pattern and a lower surface of the upper pattern . The display device according to claim 2 , further comprising an anode electrode, a light-emitting layer, and a cathode electrode, which are disposed in the display region . The display device of claim 10 , wherein the sealing layer is disposed on the cathode electrode . The display device of claim 1 , further comprising: a first touch electrode disposed on the first insulating layer; and a second touch electrode disposed on the second insulating layer . The display device of claim 1 , wherein a side surface of the first insulating layer and a side surface of the second insulating layer are exposed to a hole region . The display device according to claim 1 , further comprising a camera, a sensor or a light source disposed in the hole region . The display device according to claim 6 , further comprising: a non-display area; and a second dam portion disposed in the non-display area. The display device according to claim 1 , wherein a height of the first insulating layer between the plurality of first patterns is lower than a height of each of the plurality of first patterns . Display area;
a first region and a plurality of pixels disposed in the display area ;
an anode electrode , a light-emitting layer, and a cathode electrode disposed in each of the plurality of pixels;
a sealing layer disposed on the cathode electrode;
a first insulating layer disposed on the encapsulation layer ;
a first touch electrode disposed on the first insulating layer ;
a second insulating layer disposed on the first touch electrode; and
a second touch electrode disposed on the second insulating layer ;
A display device comprising:
the first region includes a first pattern portion, a second pattern portion, and a first dam portion between the first pattern portion and the second pattern portion,
the first insulating layer and the second insulating layer extend to the first pattern portion, the second pattern portion, and the first dam portion;
the first pattern portion includes a plurality of first patterns,
A display device , wherein a height of the first insulating layer above each of the plurality of first patterns is greater than a height of the first insulating layer between the plurality of first patterns . The display device of claim 17 , wherein the first insulating layer and the second insulating layer are in contact with each other on an upper surface of each of the first patterns. The display device of claim 17 , wherein the first insulating layer and the second insulating layer are spaced apart from each other between the first patterns. The display device of claim 19 , wherein the first insulating layer and the second insulating layer are separated from each other by a protective layer between the first patterns . The display device of claim 20 , wherein a top surface of each of the plurality of first patterns is lower than a top surface of the protective layer . The display device of claim 20 , wherein the protective layer partially overlaps the first patterns . The display device according to claim 17 , wherein the second pattern portion includes a plurality of second patterns. The display device according to claim 23 , wherein the sealing layer is disposed on the second patterns without extending to the first pattern portion . The display device of claim 24 , wherein the first insulating layer and the second insulating layer are in contact with each other in the second pattern portion . The display device of claim 17 , wherein the first region further includes a hole region adjacent to the first pattern portion, and a camera, a sensor, or a light source is disposed in the hole region . The display device of claim 26 , wherein a side surface of the first insulating layer and a side surface of the second insulating layer are exposed in the hole region. The display device according to claim 17 , further comprising : a non-display area; and a second dam portion disposed in the non-display area . The display device according to claim 17 , wherein a height of the first insulating layer between the plurality of first patterns is lower than a height of each of the plurality of first patterns .

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