JP7662124B2 - SENSING CIRCUIT, SENSING METHOD, AND RESISTANCE CHANGE MEMORY - Google Patents

Description

The present invention relates to a sensing circuit, a sensing method, and a resistance change memory.

Known examples of resistance change memory include ReRAM (Resistive Random Access Memory), MRAM (Magnetic Random Access Memory), and PCRAM (Phase-Change Random Access Memory) (see, for example, Patent Documents 1 and 2).

A memory cell of a resistance change memory changes to a high resistance state or a low resistance state in response to an applied voltage, and holds each resistance state in association with binary data.
When reading, a sense circuit (also called a sense amplifier) is connected to the memory cell to be read. Then, for example, depending on the magnitude relationship between the cell potential, which is the product of the current value of a constant reference current and the resistance value of the memory cell, and a predetermined reference potential, data (0 or 1) corresponding to the resistance value of the memory cell is output. In such a sense circuit, the closer the resistance value of the memory cell is to the value obtained by dividing the reference potential by the current value of the reference current, the smaller the potential difference between the cell potential and the reference potential. Then, when this potential difference falls below the limit of the read sensitivity (read margin) of the sense circuit, normal reading is not possible, the memory cell is deemed "defective," and the yield decreases.

Conventionally, there has been a sense circuit that uses a current mirror circuit to copy the current flowing through a memory cell (hereinafter referred to as the cell current) and a reference current, and outputs the complementary potential difference resulting from the difference between the two currents as read data using a differential amplifier (see, for example, Patent Document 3). With this sense circuit, a fixed bias voltage is applied to the memory cell, so there is no drop in the cell current, and a relatively large current difference is input to the differential amplifier, achieving a relatively high read sensitivity.

JP 2007-172703 A JP 2011-134383 A JP 2004-164766 A

A sense circuit that uses a current mirror circuit to increase the current difference between the cell current and the reference current has many current paths and consumes a large current during reading.
In one aspect, the present invention has an object to provide a sense circuit, a sense method, and a resistance change memory that can suppress current consumption during reading.

In one embodiment, a sense circuit is provided that includes a current source that generates a first current having a second current value that is n times (n is a real number equal to or greater than 3) the first current value of a reference current, a first current path through which a cell current having a third current value corresponding to the resistance value of a memory cell of a resistance change type memory flows from the first current, a second current path through which a second current having a fourth current value obtained by subtracting n-1 times the third current value from the second current value flows from the first current, a first current mirror circuit that copies the cell current flowing in the first current path to generate a third current having the third current value, a second current mirror circuit that copies the second current flowing in the second current path to generate a fourth current having the fourth current value, and an output circuit that outputs a result of reading data from the memory cell based on a current difference that is n times the difference between the third current value and the first current value, which is obtained from the third current value of the third current and the fourth current value of the fourth current.

Also provided in one embodiment is a method of sensing.
Also, in one embodiment, a resistive change memory is provided.

In one aspect, the present invention can reduce current consumption during readout.

FIG. 2 illustrates an example of a sense circuit according to the first embodiment; FIG. 13 is a diagram illustrating a sense circuit of a comparative example. FIG. 1 is a diagram showing an example of a resistance change memory. FIG. 2 is a diagram showing an example of a circuit of one input/output portion of a column control circuit; FIG. 1 is a diagram showing an example of a memory in a resistance change memory. FIG. 2 is a diagram illustrating an example of a voltage control circuit. FIG. 2 is a diagram illustrating an example of a current source. FIG. 13 illustrates an example of a sense circuit according to a second embodiment; FIG. 13 illustrates an example of a sense circuit according to a third embodiment; FIG. 13 illustrates an example of a sense circuit according to a fourth embodiment;

Hereinafter, an embodiment of the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 illustrates an example of a sense circuit according to a first embodiment.

The sense circuit 10 of the first embodiment is used to read data stored in a memory cell 20 (including a memory element 20a) of a resistance change memory. Other configurations of the resistance change memory will be described later (see Figures 3 and 4, etc.).

The sense circuit 10 has a current source 11 that generates a current having a current value (3Iref) three times the current value (Iref) of the reference current. This current source 11 limits the maximum value of the current flowing through the sense circuit 10 to 3Iref.

The sense circuit 10 also has a current path 12a through which a cell current of 3Iref flows, the current value (Icell) corresponding to the resistance value of the memory cell 20. The sense circuit 10 also has a current path 12b through which a current of 3Iref minus twice the value of Icell flows, the current value (Idif) generated by the current source 11.

Furthermore, the sense circuit 10 includes current mirror circuits 13 and 14 , an output circuit 15 , and a current adjustment circuit 16 .
The current mirror circuit 13 copies the cell current flowing through the current path 12a and generates a current of the same current value (Icell) as the cell current in the output circuit 15. In the example of FIG. 1, the current mirror circuit 13 has p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) (hereinafter referred to as pMOS) 13a and 13b and n-channel MOSFETs (hereinafter referred to as nMOS) 13c and 13d. In the sense circuit 10 of the first embodiment, the transistor sizes of the pMOSs 13a and 13b are the same (their channel lengths and channel widths are equal), and the transistor sizes of the nMOSs 13c and 13d are the same. Note that the transistor sizes being the same also include cases where there are some manufacturing errors (the same applies below).

pMOS13a is provided on current path 12a, its source is connected to current source 11, and its drain is connected to memory cell 20. The gate of pMOS13a is connected to its own drain, and is also connected to the gate of pMOS13b and current adjustment circuit 16.

pMOS13b is provided on current path 12c through which a current that is a copy of the cell current flows, its source is connected to current source 11, and its drain is connected to the drain of nMOS13c.

nMOS13c is provided on current path 12c through which a current that is a copy of the cell current flows, and its source is at ground potential (VSS (e.g., 0 V)). The gate of nMOS13c is connected to its own drain and is also connected to the gate of nMOS13d, which also functions as an input transistor of output circuit 15.

The current mirror circuit 13 in FIG. 1 includes a current mirror circuit formed by pMOSs 13a and 13b, and a current mirror circuit formed by nMOSs 13c and 13d.
The current mirror circuit 14 copies the current flowing through the current path 12b and generates a current having the same current value (Idif) as that current in the output circuit 15. In the example of Fig. 1, the current mirror circuit 14 has nMOSs 14a and 14b. The transistor sizes of the nMOSs 14a and 14b are the same.

nMOS14a is provided on current path 12b, and its drain is connected to current source 11 via pMOS16b (described later) of current adjustment circuit 16. Furthermore, the drain of nMOS14a is connected to its own gate as well as to the gate of nMOS14b, which also functions as another input transistor of output circuit 15. The source of nMOS14a is VSS.

The output circuit 15 in FIG. 1 outputs the result of reading data from the memory cell 20 based on the current difference obtained from Icell and Idif, which is three times the difference between Icell and Iref. In the example in FIG. 1, the output circuit 15 is an amplifier circuit that amplifies the difference in the differentially input signals, and has pMOSs 15a and 15b, nMOS 15c, and nMOSs 13d and 14b that are part of the current mirror circuits 13 and 14.

The power supply voltage (VDD) is applied to the sources of pMOS15a and 15b, and the gates of pMOS15a and 15b are connected to each other and to the drain of pMOS15b. The drain of pMOS15a is connected to the output terminal OUT and the drain of nMOS13d. The drain of pMOS15b is connected to the drain of nMOS14b. The sources of nMOS13d and 14b are connected to the drain of nMOS15c. The source of nMOS15c is VSS. An enable signal SAen is input to the gate of nMOS15c to enable the sense circuit 10 during a read operation.

The current adjustment circuit 16 detects the voltage (bias voltage) applied to the memory cell 20 and adjusts the value of the current (Idif) flowing through the current path 12b so that the bias voltage value (VBIAS) is equal to the reference voltage value (Vref). The current adjustment circuit 16 has a voltage control circuit 16a and a pMOS 16b.

The voltage control circuit 16a detects the gate voltages of the pMOSs 13a and 13b of the current mirror circuit 13, which are the bias voltages applied to the memory cells 20, and controls the gate voltage value (VGP) of the pMOS 16b so that VBIAS = Vref. This keeps the source voltage value (VC) of the pMOSs 13a and 13b constant. An example of the voltage control circuit 16a will be described later (see FIG. 6).

pMOS16b is provided on current path 12b, its source is connected to current source 11, and its drain is connected to the drain of nMOS14a of current mirror circuit 14. pMOS16b adjusts Idif according to VGP. Note that Icell is also adjusted by adjusting Idif.

By providing such a current adjustment circuit 16, it is possible to limit the voltage applied to the memory element 20a, and to prevent an overvoltage from being applied to the memory element 20a.
The operation of the sense circuit 10 will now be described.

When data is read from the memory cell 20, the logical level of the enable signal SAen becomes H (High) level, and nMOS 15c turns on. In addition, the voltage control circuit 16a adjusts VBIAS to Vref, and the absolute value of the gate-source voltage of pMOS 13a, 13b of the current mirror circuit 13 becomes greater than the absolute value of the threshold voltage of pMOS 13a, 13b, and pMOS 13a, 13b turns on. In addition, the current source 11 generates a current of 3Iref.

The current 3Iref is branched into current paths 12a, 12b, and 12c. A cell current having a current value (Icell) corresponding to the resistance value of the memory cell 20 flows through the current path 12a, which is part of the current 3Iref. The current mirror circuit 13 also causes the current Icell to flow through the current path 12c. In addition, the nMOSs 13c and 13d of the current mirror circuit 13 are turned on, so that the current Icell is supplied to the output circuit 15.

On the other hand, a current of Icell flows through current paths 12a and 12c, causing a current of Idif = 3Iref - 2Icell to flow through current path 12b. Then, nMOSs 14a and 14b of current mirror circuit 14 are turned on, supplying a current of Idif to output circuit 15.

The pMOSs 15a and 15b of the output circuit 15 are turned on when VDD is applied to their sources. In addition, because the pMOSs 15a and 15b are connected as a current mirror, the current Idif that flows between the source and drain of pMOS 15b also flows between the source and drain of pMOS 15a.

As a result, the output circuit 15 outputs the result of reading data from the memory cell 20 (voltage ΔV) from the output terminal OUT based on the current difference of three times Icell and Iref obtained from Idif and Icell. The reason that the current difference of three times Icell and Iref is obtained is because Idif-Icell=(Iref-Icell)×3. When Icell>Iref, "1" data (H level voltage ΔV) is output from the output terminal OUT, and when Icell<Iref, "0" data (Low (Low) level voltage ΔV) is output from the output terminal OUT.

In the sense circuit 10 described above, the output circuit 15 does not output the data read result based on the difference between the current value of the reference current (Iref) and the current value of the cell current (Icell), but rather outputs the read result based on (Iref-Icell) x 3. In other words, since the signal difference (Idif-Icell) differentially input to the output circuit 15, which is an amplifier circuit, is an enlarged version of Iref-Icell, data can be read with high read sensitivity even if Iref-Icell is a small value.

In addition, the sense circuit 10 described above can reduce current consumption more than a sense circuit that uses a current mirror circuit to copy the cell current and the reference current, and outputs the complementary potential difference resulting from the difference between the two currents as read data using a differential amplifier.

For comparison, an example of the above sense circuit is given below.
FIG. 2 is a diagram showing a sense circuit of a comparative example.
The sense circuit 30 of the comparative example has pMOSs 31 to 37 and nMOSs 38 to 42. During readout, pMOS 31 and nMOS 42 turn on when the logical level of enable signal SAen is H level and the logical level of signal /SAen, which has the opposite logic to enable signal SAen, is L level. VDD is applied to the source of pMOS 31, and the sources of pMOSs 32 and 35 are connected to the drain of pMOS 31. The drain of nMOS 42 is connected to the sources of nMOSs 38 to 41, and the source of nMOS 42 is VSS.

pMOS32, 33, and 34 are connected in a current mirror configuration, and a current of the same value (Icell) as the cell current flowing between the source and drain of pMOS32 also flows between the source and drain of pMOS33 and 34.

In addition, pMOSs 35, 36, and 37 are also connected as a current mirror, and a current of the same value (Iref) as the reference current flowing between the source and drain of pMOS 35 also flows between the source and drain of pMOSs 36 and 37.

The current Icell also flows between the drain and source of nMOS38, whose drain is connected to the drain of pMOS33, and between the drain and source of nMOS39, which is current-mirror connected to nMOS38.

In addition, a current of Iref also flows between the drain and source of nMOS 40, whose drain is connected to the drain of pMOS 36, and a current of Iref also flows between the drain and source of nMOS 41, which is current-mirror connected to nMOS 40.

Here, because the drains of pMOS34 and nMOS41 are connected to each other, a potential difference +ΔV corresponding to the current difference Icell-Iref is output from the node between the drains of pMOS34 and nMOS41 as one of the complementary outputs of the sense circuit 30.

In addition, since the drains of pMOS37 and nMOS39 are connected to each other, a potential difference -ΔV corresponding to the current difference Iref-Icell is output from the node between the drains of pMOS37 and nMOS39 as the other complementary output of the sense circuit 30.

To obtain a current difference of (Icell - Iref) x 2 = ΔI x 2, which produces the complementary output difference ΔV x 2 as described above, a current of Icell x 3 + Iref x 3 is consumed. When Icell ≈ Iref, a current of Iref x 6 is consumed. This is because there are six current paths through which current is consumed.

In contrast, in the sense circuit 10 of the first embodiment, the current consumption required to obtain the current difference Icell-Idif = (Icell-Iref) x 3 = ΔI x 3 that generates the above voltage ΔV is Iref x 3 + Idiff x 2 = Iref x 9 - Icell x 4. Even when Icell ≈ Iref, the current consumption is Iref x 5, and although the current difference is larger (read sensitivity is higher) than the sense circuit 30 of the comparative example, there are only five current paths through which current is consumed, and the current consumption is low.

In addition, by changing the mirror ratio of the mirror circuit in the sense circuit 30, a current difference (ΔI×3) similar to that of the sense circuit 10 can be obtained. That is, the channel width of pMOS 34 is set to 1.5 times the channel width of pMOS 32, 33, and the channel width of pMOS 37 is set to 1.5 times the channel width of pMOS 35, 36. Also, the channel width of nMOS 39 is set to 1.5 times the channel width of nMOS 38, and the channel width of nMOS 41 is set to 1.5 times the channel width of nMOS 40. As a result, a current difference of ΔI×3 can be obtained in the sense circuit 30, but in this case, the current consumption is Icell×3.5+Iref×3.5. When Icell≒Iref, the current consumption is Iref×7. The current consumption of the sense circuit 10 in the first embodiment is suppressed to 5/7 times this.

(Resistance change memory)
A resistance change memory including the sense circuit 10 as described above will be described below.
FIG. 3 is a diagram showing an example of a resistance change memory.

The resistance change memory 50 has an I/F (interface) circuit 51, an address decoder 52, a command decoder 53, a data input/output buffer 54, a row control circuit 55, a column control circuit 56, a memory cell array 57, and a power supply circuit 58.

The I/F circuit 51 receives inputs of addresses, commands, and write data from outside the resistance change memory 50, and outputs read data.
The address decoder 52 generates a row selection address and a column selection address from the address supplied from the I/F circuit 51 , supplies the row selection address to a row control circuit 55 , and supplies the column selection address to a column control circuit 56 .

The command decoder 53 decodes the command supplied from the I/F circuit 51 and outputs various control signals.
The data input/output buffer 54 holds write data supplied from the I/F circuit 51 and read data read from the memory cell array 57 .

The row control circuit 55 selects and drives one of a number of word lines (not shown) in the memory cell array 57 based on the row selection address supplied from the address decoder 52 and the control signal output from the command decoder 53.

The column control circuit 56 selects one of a plurality of bit lines and a plurality of source lines (not shown) of the memory cell array 57 based on a column selection address supplied from the address decoder 52. The column control circuit 56 then applies a voltage for reading or writing to the selected bit line or source line based on a control signal output from the command decoder 53. The column control circuit 56 also has a sense circuit 10 as shown in FIG. 1. An example of the circuit of the column control circuit 56 will be described later.

The memory cell array 57 has a plurality of memory cells arranged in an array, each of which is connected to a word line, a bit line, and a source line.
The power supply circuit 58 supplies a predetermined voltage to the row control circuit 55 and the column control circuit 56 .

(Column control circuit)
FIG. 4 is a diagram showing an example of a circuit of one input/output portion of a column control circuit.
For example, if the resistance change memory 50 has 32 input/output terminals, the column control circuit 56 includes 32 circuit units as shown in FIG.

The circuit section of the column control circuit 56 shown in FIG. 4 includes column switches 61 and 62, a BL driver 63, an SL driver 64, a write control circuit 65, a read switch 66, a read control circuit 67, a data output circuit 68, a data input circuit 69, and the sense circuit 10 shown in FIG. 1.

The column switch 61 connects one of multiple bit lines (32 bit lines (BL<0> to BL<31>) in the example of FIG. 4) to the BL driver 63 and the lead switch 66 based on the column selection address supplied from the address decoder 52.

The column switch 62 connects one of a number of source lines (32 source lines (SL<0> to SL<31>) in the example of FIG. 4) to the SL driver 64 based on the column selection address supplied from the address decoder 52.

The BL driver 63 applies a voltage corresponding to the write data to the bit line connected to the BL driver 63 by the column switch 61 in response to a control signal output by the write control circuit 65.

The SL driver 64 applies a voltage corresponding to the write data to the source line connected to the SL driver 63 by the column switch 62 in response to a control signal output by the write control circuit 65.

The write control circuit 65 receives a write signal "Write", which is one of the control signals output by the command decoder 53. When the write control circuit 65 is instructed to write data by "Write", it outputs a control signal to the BL driver 63 and the SL driver 64 to generate a voltage corresponding to the write data ("0" or "1") supplied from the data input circuit 69.

The reed switch 66 receives a read signal "Read", which is one of the control signals output by the command decoder 53. When "Read" instructs the reed switch 66 to read data, the reed switch 66 connects the bit line connected to the reed switch 66 by the column switch 61 to the sense circuit 10.

When "Read" is instructed to read data, the read control circuit 67 sets the logic level of the enable signal SAen shown in FIG. 1 to H level in order to enable the sense circuit 10.

When the data output circuit 68 is instructed to output data by the control signal "Read-Out" output by the command decoder 53, it outputs the read result of the data output by the sense circuit 10 as data "DQ<#>" of input/output number "#".

When data input is instructed by the control signal "Write-In" output by the command decoder 53, the data input circuit 69 supplies the write data input as data "DQ<#>" of input/output number "#" to the write control circuit 65.

(Memory cell)
Next, an example of a memory cell in the resistance change memory 50 will be described.
FIG. 5 is a diagram showing an example of a memory in a resistance change memory.

The memory cell 20 includes a memory element 20a and an nMOS 20b, which is an example of a cell transistor.
The memory element 20a is an element whose resistance value changes according to the applied voltage. For example, the memory element 20a changes to a low resistance state or a high resistance state, and holds each resistance state in correspondence with binary data ("0" or "1"). The memory element 20a has a structure in which a metal oxide is sandwiched between electrodes. A source line (SL) is connected to one end of the memory element 20a, and one of the drain or source of the nMOS 20b is connected to the other end.

The other of the drain or source of the nMOS 20b is connected to a bit line (BL), and the gate of the nMOS 20b is connected to a word line (WL).
When "0" is written to such a memory element 20a (when writing "0"), a high voltage (+HV) is applied to SL and BL is set to VSS (for example, 0V). This causes the memory element 20a to have a high resistance. When "1" is written to the memory element 20a (when writing "1"), SL is set to VSS and a high voltage (+HV) is applied to BL. This causes the memory element 20a to have a low resistance.

On the other hand, when data is read from the memory element 20a, a voltage (+LV) lower than +HV is applied to SL, and BL is set to VSS.
(Voltage control circuit)
Next, a circuit example of the voltage control circuit 16a included in the sense circuit 10 shown in FIG. 1 will be described.

FIG. 6 is a diagram illustrating an example of a voltage control circuit.
The voltage control circuit 16a has pMOSs 16a1 and 16a2 and nMOSs 16a3, 16a4, and 16a5.

VDD is applied to the sources of pMOS16a1 and 16a2, and the gates of pMOS16a1 and 16a2 are connected to each other and to the drain of pMOS16a2. The drain of pMOS16a1 is connected to the drain of nMOS16a3, and the drain of pMOS16a2 is connected to the drain of nMOS16a4.

The bias voltage VBIAS shown in FIG. 1 is applied to the gate of nMOS 16a3, and the reference voltage Vref shown in FIG. 1 is applied to the gate of nMOS 16a4. The sources of nMOS 16a3 and 16a4 are connected to the drain of nMOS 16a5.

The enable signal SAen is input to the gate of the nMOS 16a5, and the source of the nMOS 16a5 becomes VSS.
The potential of the node between the drain of pMOS 16a1 and the drain of nMOS 16a3 is output as the voltage value (VGP) of the gate of pMOS 16b.

In such a voltage control circuit 16a, when Vref>VBIAS, VGP rises, and as a result, the voltage value (VC) of the sources of pMOS 13a and 13b shown in FIG. 1 rises, and VBIAS also rises. When Vref<VBIAS, VGP falls, and as a result, VC falls, and VBIAS also falls.

In this way, the voltage control circuit 16a can perform control such that VBIAS≈Vref.
The value of the current consumed by the voltage control circuit 16a as described above is sufficiently smaller than Iref, which is the current value of the reference current (for example, 1/10 or less of Iref).

(Current Source)
Next, a circuit example of the current source 11 included in the sense circuit 10 shown in FIG. 1 will be described.
FIG. 7 is a diagram illustrating an example of a current source.

Although not shown in FIG. 1, the current source 11 is connected to a power supply circuit 58 shown in FIG.
The power supply circuit 58 includes resistors 58a and 58b, a pMOS 58c, and a differential amplifier 58d.

One end of resistor 58a is connected to VSS, and the other end is connected to one end of resistor 58b and the inverting input terminal ("-") of differential amplifier 58d. The other end of resistor 58b is connected to the drain of pMOS 58c and the output terminal of differential amplifier 58d.

The gate of the pMOS 58c is connected to its own drain and is also connected to the current source 11. VDD is applied to the source of the pMOS 58c.
A signal of a constant potential (VREFC) is input to the non-inverting input terminal ("+") of the differential amplifier 58d which operates on VDD.

Current source 11 has pMOS11a, 11b, and 11c. VDD is applied to the sources of pMOS11a to 11c, and the gates of pMOS11a to 11c are connected to the gate and drain of pMOS58c of power supply circuit 58. In other words, pMOS11a to 11c and pMOS58c are current mirror connected. The drains of pMOS11a to 11c are connected to each other. The transistor size of each of pMOS11a to 11c is the same as that of pMOS58c. This realizes a current mirror circuit with a mirror ratio of 1:3, and a current three times the reference current Iref (3Iref) flowing between the source and drain of pMOS58c is generated and output by current source 11.

The output potential of the differential amplifier 58d is Vo, the potential of the inverting input terminal is Vfb, the resistance value of resistor 58a is R0, and the resistance value of resistor 58b is R1. In this case, resistors 58a and 58b are used that have R0 and R1 such that Iref = Vo/(R0 + R1) and Vfb = R0/Vo(R0 + R1) = VREFC for the desired Iref.

It should be noted that constant potentials such as Vref and VREFC can be generated by, for example, a bandgap reference circuit.
Second Embodiment
Fig. 8 is a diagram showing an example of a sense circuit according to the second embodiment, in which the same elements as those shown in Fig. 1 are denoted by the same reference numerals.

The sense circuit 70 of the second embodiment performs complementary output, similar to the sense circuit 30 of the comparative example shown in FIG. 2. In order to generate the current Icell and the current Idif in the output circuit 73 that performs complementary output, the configuration of the current mirror circuits 71 and 72 is also different from the configuration of the current mirror circuits 13 and 14 of the sense circuit 10 shown in FIG. 1.

Current mirror circuit 71 has nMOSs 71a, 71b, pMOSs 71c, and 71d in addition to pMOSs 13a, 13b, and nMOS 13c included in current mirror circuit 13.

nMOS71a and 71b are connected to nMOS13c as a current mirror. In addition, nMOS13c, 71a, and 71b have the same transistor size. Therefore, the current Icell that flows between the drain and source of nMOS13c also flows between the drain and source of nMOS71a and 71b. nMOS71b also functions as one of the input transistors of the output circuit 73.

The drain of pMOS71c is connected to the drain of nMOS71a. pMOS71d is current-mirror connected to pMOS71c. VDD is applied to the sources of pMOS71c and 71d. Furthermore, pMOS71c and 71d have the same transistor size. Therefore, the current Icell that flows between the source and drain of pMOS71c also flows between the source and drain of pMOS71d. pMOS71d also functions as one of the input transistors of output circuit 73.

The current mirror circuit 72 includes nMOSs 72a and 72b, and pMOSs 72c and 72d, in addition to the nMOS 14a included in the current mirror circuit 14.
The nMOSs 72a and 72b are connected to the nMOS 14a as a current mirror. The transistor sizes of the nMOSs 14a, 72a, and 72b are the same. Therefore, a current Idif=3Iref-2Icell that flows between the drain and source of the nMOS 14a also flows between the drain and source of the nMOSs 72a and 72b. The nMOS 72b also functions as one of the input transistors of the output circuit 73.

The drain of pMOS72c is connected to the drain of nMOS72a. pMOS72d is current-mirror connected to pMOS72c. VDD is applied to the sources of pMOS72c and 72d. Furthermore, pMOS72c and 72d have the same transistor size. Therefore, the current Idif that flows between the source and drain of pMOS72c also flows between the source and drain of pMOS72d. pMOS72d also functions as one of the input transistors of output circuit 73.

In the output circuit 73, the drain of the pMOS 71d is connected to the drain of the nMOS 72b, and the drain of the pMOS 72d is connected to the drain of the nMOS 71b.
As a result, a potential difference -ΔV corresponding to the current difference Idif-Icell is output from the output terminal OUT connected to the node between the drain of nMOS 71b and the drain of pMOS 72d. Also, a potential difference +ΔV corresponding to the current difference Icell-Idif is output from the output terminal /OUT connected to the node between the drain of nMOS 72b and the drain of pMOS 71d. In this way, complementary outputs are obtained from the output circuit 73.

The current consumed to obtain a current difference of (Icell-Idif)x2=((Icell-Iref)x3)x2=ΔIx6, which produces a complementary output difference (ΔVx2), is Irefx3+Icellx2+Idifx2=Irefx9-Icellx2. When Icell≈Iref, a current of Irefx7 is consumed.

According to the sense circuit 70 of the second embodiment, the current difference obtained in the output circuit 73 is ΔI×6, so that the read sensitivity can be improved compared to the sense circuit 10 of the first embodiment (the current difference obtained is ΔI×3). The current consumption of the sense circuit 70 is larger than the current consumption of the sense circuit 10, but the current consumption can be suppressed more than when the same read sensitivity is realized by the sense circuit 30 of the comparative example shown in FIG. 2.

In the sense circuit 30 shown in FIG. 2, to obtain the same current difference (ΔI×6) as the sense circuit 70, the channel width of pMOS 34 is tripled relative to the channel width of pMOS 32, 33, and the channel width of pMOS 37 is tripled relative to the channel width of pMOS 35, 36. The channel width of nMOS 39 is tripled relative to the channel width of nMOS 38, and the channel width of nMOS 41 is tripled relative to the channel width of nMOS 40. This allows a current difference of ΔI×6 to be obtained in the sense circuit 30 as well, but in this case, the current consumption is Icell×5+Iref×5. When Icell≈Iref, the current consumption is Iref×10. The current consumption of the sense circuit 70 in the second embodiment is suppressed to 7/10 times this.

Third Embodiment
Fig. 9 is a diagram showing an example of a sense circuit according to the third embodiment, in which the same elements as those shown in Fig. 1 are denoted by the same reference numerals.

In the sense circuit 80 of the third embodiment, the current source 81 generates a current having a current value four times Iref (4Iref), unlike the current source 11 of the sense circuit 10 of FIG. 1. Such a current source 81 can be realized by adding one pMOS (having the same transistor size as pMOS 58c) that is current-mirror connected to pMOS 58c of the power supply circuit 58 in the current source 11 shown in FIG. 7.

Current mirror circuit 82 also has pMOSs 82a, 82b, nMOSs 82c, and 82d that have the same connection relationship as pMOSs 13a, 13b, and nMOSs 13c, 13d of current mirror circuit 13 in FIG. 1.

However, in the current mirror connection of pMOS 82a and 82b, the channel width of pMOS 82b is twice that of pMOS 82a. Therefore, the mirror ratio is 1:2, and a current of 2Icell flows between the source and drain of pMOS 82b and in current path 12c. As a result, a current of Idif = 4ref - 3Icell flows in current path 12b.

In addition, in the nMOS 82c and 82d that are connected as a current mirror, the channel width of nMOS 82c is twice the channel width of nMOS 82d. Therefore, the mirror ratio is 2:1, and the current Icell flows between the drain and source of nMOS 82d.

The current difference obtained in the output circuit 15 of the sense circuit 80 of the third embodiment is Icell-Idif = (Icell-Iref) x 4 = ΔI x 4. The current consumed to obtain this current difference is Iref x 4 + Idif x 2 = Iref x 12 - Icell x 6. When Icell ≈ Iref, a current of Iref x 6 is consumed.

According to the sense circuit 80 of the third embodiment, the current difference obtained in the output circuit 15 is ΔI×4, so that the read sensitivity can be improved compared to the sense circuit 10 of the first embodiment (the current difference obtained is ΔI×3). The current consumption of the sense circuit 80 is larger than the current consumption of the sense circuit 10, but the current consumption can be suppressed more than when the same read sensitivity is realized by the sense circuit 30 of the comparative example shown in FIG. 2.

In the sense circuit 30 shown in FIG. 2, to obtain the same current difference (ΔI×4) as the sense circuit 80, the channel width of pMOS 34 is doubled relative to the channel width of pMOS 32, 33, and the channel width of pMOS 37 is doubled relative to the channel width of pMOS 35, 36. The channel width of nMOS 39 is doubled relative to the channel width of nMOS 38, and the channel width of nMOS 41 is doubled relative to the channel width of nMOS 40. This allows a current difference of ΔI×4 to be obtained in the sense circuit 30 as well, but in this case, the current consumption is Icell×4+Iref×4. When Icell≈Iref, the current consumption is Iref×8. The current consumption of the sense circuit 80 in the third embodiment is suppressed to 6/8 times this.

In the sense circuit 70 of the second embodiment shown in FIG. 8, the magnitude of the current generated by the current source 11 may be set to 4Iref, as in the sense circuit 80 described above. The channel width of pMOS 13b may be set to twice the channel width of pMOS 13a, and the channel width of nMOS 13c may be set to twice the channel width of nMOS 71c and 71b.

In this case, the resulting current difference is (Icell-Idf)×2=((Icell-Iref)×4)×2=ΔI×8, making it possible to further increase the read sensitivity.
(Fourth embodiment)
Fig. 10 is a diagram showing an example of a sense circuit according to the fourth embodiment, in which the same elements as those shown in Figs. 1 and 9 are denoted by the same reference numerals.

The sense circuit 90 of the fourth embodiment has a current source 81 that generates a current of 4Iref, similar to the sense circuit 80 shown in FIG.
A sense circuit 90 of the fourth embodiment differs from the sense circuits 10 and 80 in that the current path 12c is divided into two current paths 12c1 and 12c2, and a current of 4Iref branches into four current paths to flow.

Therefore, the circuit configuration of the current mirror circuit 91 is different from the circuit configurations of the current mirror circuits 13 and 82 of the sense circuits 10 and 80 .
The current mirror circuit 91 includes a pMOS 91a and an nMOS 91 in order to form the above-mentioned current path 12c2, in addition to the respective elements of the current mirror circuit 13 in FIG.

pMOS91a is connected to pMOS13a in a current mirror configuration, and a current of Icell flows between the source and drain. The source of pMOS91a is connected to current source 81, and the drain is connected to the drain of nMOS91b. The gate of nMOS91b is connected to its own drain, and the source is VSS.

In this sense circuit 90, Idif = 4Iref - 3Icell is obtained, and a current difference of ΔI x 4 is obtained in the output circuit 15, similar to the sense circuit 80. The amount of current consumption is also similar to that of the sense circuit 80. Therefore, the sense circuit 90 of the fourth embodiment can achieve the same effect as the sense circuit 80 of the third embodiment.

The above describes one aspect of the sense circuit, sense method, and resistance change memory of the present invention based on the embodiment, but these are merely examples and are not limited to the above description.

For example, in the above example, the value of the current generated by the current sources 11 and 81 is three or four times Iref, but this is not limited to this and may be n times (n is a real number equal to or greater than 3). The value of the current flowing through the current path 12b may be anything between Iref×n and Icell×(n-1). The circuit configuration and mirror ratio of the current mirror circuits 13, 71, and 82 may be appropriately changed so that a current of such value flows through the current path 12b.

In addition, modifications can be made as appropriate, such as swapping pMOS and nMOS.

10 Sense circuit 11 Current source 12a, 12b, 12c Current path 13, 14 Current mirror circuit 13a, 13b, 15a, 15b, 16b pMOS
13c, 13d, 14a, 14b, 15c nMOS
15 Output circuit 16 Current adjustment circuit 16a Voltage control circuit 20 Memory cell 20a Memory element

Claims (5)

a current source that generates a first current having a second current value that is n times (n is a real number equal to or greater than 3) a first current value of a reference current;
a first current path through which a cell current having a third current value corresponding to a resistance value of a memory cell of a resistance change type memory flows, the cell current being included in the first current;
a second current path through which a second current of a fourth current value, which is obtained by subtracting a value that is n-1 times the third current value from the second current value, flows, out of the first current;
a first current mirror circuit that copies the cell current flowing through the first current path to generate a third current having the third current value;
a second current mirror circuit that copies the second current flowing through the second current path to generate a fourth current having the fourth current value;
an output circuit that outputs a result of reading data from the memory cell based on a current difference that is n times a difference between the third current value and the first current value, the current difference being obtained from the third current value of the third current and the fourth current value of the fourth current;
A sense circuit having The sense circuit according to claim 1, further comprising a current adjustment circuit that detects a voltage applied to the memory cell and adjusts the fourth current value of the second current flowing through the second current path so that the voltage value of the voltage is equal to a reference voltage value. The sense circuit according to claim 1 or 2, wherein the output circuit outputs the complementary read result based on the current difference obtained from the third current value and the fourth current value, which is n×2 times the difference between the third current value and the first current value. a current source generating a first current having a second current value that is n times (n is a real number equal to or greater than 3) a first current value of a reference current;
a first current path passes a cell current of a third current value corresponding to a resistance value of a memory cell of a resistance change type memory, among the first currents;
a second current path flows a second current of the first current, the second current having a fourth current value obtained by subtracting a value that is n-1 times the third current value from the second current value;
a first current mirror circuit that copies the cell current flowing through the first current path to generate a third current having the third current value;
a second current mirror circuit copies the second current flowing through the second current path to generate a fourth current having the fourth current value;
an output circuit outputs a result of reading data from the memory cell based on a current difference that is n times a difference between the third current value and the first current value, the current difference being obtained from the third current value of the third current and the fourth current value of the fourth current;
Sense method. A memory cell whose resistance value changes depending on an applied voltage;
a first current path through which a cell current of a third current value corresponding to a resistance value of the memory cell flows from the first current; a second current path through which a second current of a fourth current value obtained by subtracting n-1 times the third current value from the second current value flows from the first current; a first current mirror circuit that copies the cell current flowing through the first current path to generate a third current of the third current value; a second current mirror circuit that copies the second current flowing through the second current path to generate a fourth current of the fourth current value; and an output circuit that outputs a result of reading data from the memory cell based on a current difference of n times a difference between the third current value and the first current value, the current difference being obtained from the third current value of the third current and the fourth current value of the fourth current;
A resistive change memory having the above structure.

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