JP7662409B2 - Power Supplies - Google Patents

Description

The present invention relates to a power supply device.

There is a known power supply device in which an inverter circuit converts a DC voltage input from a DC power supply into a high-frequency voltage, a transformer transforms the high-frequency voltage, and a rectifier circuit rectifies and outputs the voltage. Phase shift control is also known as a control method for a single-phase full-bridge inverter circuit. Patent Document 1 discloses a power supply device for arc processing that performs phase shift control. In general phase shift control, the output current is controlled by adjusting the start timing of the on-period of the switching elements of one arm while keeping the length of the on-period of each switching element of the inverter circuit fixed.

Figure 5 is a diagram for explaining general phase shift control. Figure 5(a) is a diagram showing the overall configuration of the power supply device A10. Figure 5(b) is a waveform diagram showing an example of a drive signal input to each switching element. As shown in Figure 5(a), the inverter circuit 20 has a first arm consisting of switching elements TR1 and TR3, and a second arm consisting of switching elements TR2 and TR4. Drive signals P1 to P4 generated by the control circuit 50 are amplified by the drive circuit 60 and input to the switching elements TR1 to TR4, respectively.

As shown in FIG. 4B, each of the drive signals P1 to P4 is a pulse signal with a period T and a pulse width Ton. The rising timing of the pulse of the drive signal P3 is delayed by half a period (T/2) from the drive signal P1. The drive signals P1 and P3 have fixed waveforms. On the other hand, the drive signals P2 and P4 do not have fixed waveforms, and the rising timing of the pulse is adjusted according to the deviation between the output current and the target current value. In FIG. 4B, the rising timing of the pulse is advanced by an adjustment value t _adj according to the deviation between the output current and the target current value compared to the case where no adjustment is made (shown by a dashed line in FIG. 4B). The overlapping time of the pulses of the drive signals P1 and P4 (drive signals P2 and P3) is adjusted according to the adjustment value t _adj , and the output current of the power supply device A10 is controlled.

JP 2004-074258 A

Since the output current changes, the adjustment value t _adj takes a different value depending on the calculation timing. As shown in FIG. 4B, after the adjustment value t _adj (t1) for the drive signal P4 is calculated, the adjustment value t _adj (t2) for the drive signal P2 is calculated. If the adjustment value t _adj (t2) is too large compared to the adjustment value t _adj (t1), the pulse of the drive signal P2 rises before the pulse of the drive signal P4 falls. In this case, the pulse of the drive signal P4 and the pulse of the drive signal P2 overlap, so that the switching element TR4 and the switching element TR2 are turned on at the same time, and the DC power supply 10 is short-circuited. To prevent this, the following is set for t _adj (t2):
t _adj (t2)<T/2-Ton+t _adj (t1)
For this reason, there are cases where the output current control cannot keep up with a sudden change in the load.

The same applies to the case where the rising timings of the pulses of the drive signals P4 and P2 are delayed by the adjustment value t _adj . In order to prevent the switching elements TR4 and TR2 from being turned on at the same time,
t _adj (t2)>-T/2+Ton+t _adj (t1)
Therefore, in this case too, the output current control may not be able to keep up with a sudden change in the load.

The present invention was conceived in light of the above circumstances, and its purpose is to provide a power supply device that prevents short circuits and can respond to sudden changes in the load.

To solve the above problems, the present invention provides the following technical solutions:

The power supply device provided by the first aspect of the present invention includes an inverter circuit having a first arm and a second arm, each of which has two switching elements connected in series; and a control circuit that generates a first drive signal input to the first switching element of the first arm, a second drive signal input to the second switching element connected to the same polarity side as the first switching element in the second arm, a third drive signal input to the third switching element of the first arm, and a fourth drive signal input to the fourth switching element connected to the same polarity side as the third switching element in the second arm. The control circuit generates a pulse signal having a predetermined first pulse width at a predetermined period as the first drive signal, generates a pulse signal shifted by half a period from the first drive signal as the third drive signal, generates a pulse signal having a changing second pulse width and whose pulse rises after a predetermined dead time has elapsed from the falling edge of the pulse of the second drive signal as the fourth drive signal, and generates a pulse signal having the first pulse width and whose pulse rises after the dead time has elapsed from the falling edge of the pulse of the fourth drive signal as the second drive signal.

In a preferred embodiment of the present invention, the control circuit includes an adjustment value calculation unit that calculates an adjustment value based on the deviation between the output current of the power supply device and a target current value, a period setting unit that sets the predetermined period, a pulse width setting unit that sets the first pulse width, a dead time setting unit that sets the dead time based on the predetermined period and the first pulse width, an addition unit that adds the adjustment value input from the adjustment value calculation unit to the first pulse width input from the pulse width setting unit to calculate the second pulse width, a first drive signal generation unit that generates the first drive signal by raising a pulse at each of the predetermined periods and lowering the pulse after the first pulse width has elapsed from the rising edge of the pulse, and The third drive signal generating unit generates the third drive signal by raising a pulse after the dead time has elapsed from the falling edge of the signal and lowering the pulse after the first pulse width has elapsed from the rising edge of the pulse, a fourth drive signal generating unit generates the fourth drive signal by raising a pulse after the half cycle and the dead time have elapsed from the falling edge of the pulse of the fourth drive signal and lowering the pulse after the second pulse width has elapsed from the rising edge of the pulse, and a second drive signal generating unit generates the second drive signal by raising a pulse after the dead time has elapsed from the falling edge of the pulse of the fourth drive signal and lowering the pulse after the first pulse width has elapsed from the rising edge of the pulse.

In a preferred embodiment of the present invention, the power supply device further includes a DC power supply that supplies a DC voltage to the inverter circuit, a transformer that transforms the high-frequency voltage output by the inverter circuit, and a rectifier circuit that rectifies the high-frequency voltage transformed by the transformer, and outputs a DC current controlled by the inverter circuit to a welding torch.

According to the present invention, the control circuit changes the pulse width of the fourth drive signal. The fourth drive signal has a pulse that rises after the dead time has elapsed from the falling edge of the pulse of the second drive signal. Also, the second drive signal has a pulse that rises after the dead time has elapsed from the falling edge of the pulse of the fourth drive signal. Therefore, the control circuit can prevent the pulse of the fourth drive signal from overlapping with the pulse of the second drive signal. Thus, the control circuit can prevent a short circuit in which the fourth switching element and the second switching element are simultaneously turned on without limiting the adjustment value. As a result, the power supply device according to the present invention can prevent a short circuit and follow the control even if the load changes suddenly.

Other features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

1 is a diagram showing an overall configuration of a welding power supply according to a first embodiment; 5 is a waveform diagram showing an example of each drive signal input to each switching element. FIG. 4 is a functional block diagram showing an example of an internal configuration of a drive signal generating unit. FIG. FIG. 13 is a diagram showing a modification of the welding power supply according to the first embodiment. FIG. 1A is a diagram showing the overall configuration of a conventional welding power supply, and FIG. 1B is a waveform diagram showing an example of a drive signal input to each switching element.

The following describes in detail an embodiment of the present invention with reference to the drawings, taking as an example a case in which the power supply device according to the present invention is used as a welding power supply device.

First Embodiment
FIG. 1 is a diagram for explaining a welding power supply A1 according to a first embodiment, and shows the overall configuration of the welding power supply A1.

The welding power supply A1 generates an arc between the tip of the electrode of the welding torch B and the workpiece W, and supplies power to the arc. As shown in FIG. 1, the welding power supply A1 includes a DC power supply 1, an inverter circuit 2, a transformer 3, a rectifier circuit 4, a control circuit 5, a drive circuit 6, and a current sensor 7.

The DC power supply 1 outputs a DC voltage, and includes, for example, a rectifier circuit that rectifies the AC voltage input from the power grid, and a smoothing capacitor that smoothes the AC voltage. The configuration of the DC power supply 1 is not limited, and it may be any configuration that outputs a DC voltage to the inverter circuit 2.

The inverter circuit 2 converts the DC voltage input from the DC power supply 1 into a high-frequency voltage and outputs it to the transformer 3. The inverter circuit 2 is a single-phase full-bridge inverter, and includes four switching elements TR1 to TR4. In this embodiment, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as the switching elements TR1 to TR4. Note that the switching elements TR1 to TR4 are not limited to MOSFETs, and may be bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), etc.

The switching element TR1 and the switching element TR3 are connected in series with the source terminal of the switching element TR1 and the drain terminal of the switching element TR3 connected. The drain terminal of the switching element TR1 is connected to the positive side of the DC power supply 1, and the source terminal of the switching element TR3 is connected to the negative side of the DC power supply 1 to form a bridge structure. The switching element TR2 and the switching element TR4 are connected in series with the source terminal of the switching element TR2 and the drain terminal of the switching element TR4 connected. The drain terminal of the switching element TR2 is connected to the positive side of the DC power supply 1, and the source terminal of the switching element TR4 is connected to the negative side of the DC power supply 1 to form a bridge structure. The bridge structure formed by the switching element TR1 and the switching element TR3 is the first arm 21, and the bridge structure formed by the switching element TR2 and the switching element TR4 is the second arm 22. An output line C1 is connected to the connection point between switching element TR1 and switching element TR3 of the first arm 21, and an output line C2 is connected to the connection point between switching element TR2 and switching element TR4 of the second arm 22.

A free wheel diode is connected in anti-parallel to each of the switching elements TR1 to TR4. A snubber capacitor is connected between the drain terminal and the source terminal of each of the switching elements TR1 to TR4. Drive signals P1 to P4 (described later) output from the drive circuit 6 are input to the gate terminal of each of the switching elements TR1 to TR4. Each of the switching elements TR1 to TR4 is switched on and off based on the drive signals P1 to P4, respectively. This converts the DC voltage into a high-frequency voltage. The configuration of the inverter circuit 2 is not limited.

The transformer 3 transforms the high-frequency voltage output by the inverter circuit 2 and outputs it to the rectifier circuit 4. The transformer 3 has a primary winding 31 and a secondary winding 32. One input terminal of the primary winding 31 is connected to the output line C1, and the other input terminal is connected to the output line C2. One output terminal of the secondary winding 32 is connected to one input terminal of the rectifier circuit 4, and the other output terminal is connected to the other input terminal of the rectifier circuit 4. The secondary winding 32 is provided with a center tap in addition to the two output terminals. The primary winding 31 and the secondary winding 32 are each wound around a core (not shown), and can be magnetically coupled to each other.

The rectifier circuit 4 is a full-wave rectifier circuit using the center tap of the transformer 3, and rectifies the high-frequency current output by the transformer 3 and outputs it as a direct current. The rectifier circuit 4 includes two rectifier diodes 41 and 42 and a direct current reactor 43. The rectifier diodes 41 and 42 have their anode terminals connected to the output terminals of the secondary winding 32 of the transformer 3, respectively, and their cathode terminals connected to each other. The direct current reactor 43 is connected in series between the connection point on the cathode terminal side of the rectifier diodes 41 and 42 and the output terminal a of the welding power supply A1, and stabilizes the output current. The center tap of the transformer 3 is connected to the output terminal b of the welding power supply A1. The direct current output by the rectifier circuit 4 flows to the welding torch B as a welding current. The configuration of the rectifier circuit 4 is not limited.

The current sensor 7 is disposed on the connection line between the center tap of the transformer 3 and the output terminal b, and detects the output current of the welding power supply A1 and outputs it to the control circuit 5 as a current signal I. The location of the current sensor 7 is not limited, and it is sufficient if it can detect the output current of the rectifier circuit 4.

The control circuit 5 is configured to control the inverter circuit 2, and is realized by, for example, a microcomputer. The control circuit 5 generates drive signals P1 to P4 for controlling the inverter circuit 2, and outputs them to the drive circuit 6. The control circuit 5 performs output current control, and feedback controls the output current of the welding power supply A1 based on the current signal I input from the current sensor 7. The control circuit 5 also performs control similar to phase shift control. The control circuit 5 has, as its functional configuration, a target setting unit 51, a subtraction unit 52, an adjustment value calculation unit 53, and a drive signal generation unit 54.

The target setting unit 51 sets a target current value I ^* , which is a target value of the output current of the welding power supply A1. The target setting unit 51 outputs the set target current value I ^* to the subtraction unit 52. The target setting unit 51 sets the target current value I ^* based on welding conditions input by an operator or preprogrammed. The subtraction unit 52 calculates a deviation ΔI (=I ^* -I) between the current signal I input from the current sensor 7 and the target current value I ^* input from the target setting unit 51, and outputs the deviation ΔI to the adjustment value calculation unit 53. The adjustment value calculation unit 53 calculates an adjustment value t adj for making the deviation ΔI "0" based on the input deviation ΔI, and outputs the adjustment value t _adj to the drive signal generation unit 54. Note that the calculation method of the adjustment value t _adj is not limited. When the deviation ΔI is a positive value, the adjustment value t _adj is a positive value, and when the deviation ΔI is a negative value, the adjustment value t _adj is a negative value.

The drive signal generation unit 54 generates drive signals P1 to P4 based on the adjustment value t _adj input from the adjustment value calculation unit 53, and outputs them to the drive circuit 6. The drive signals P1 to P4 are amplified by the drive circuit 6 and input to the switching elements TR1 to TR4, respectively.

FIG. 2 is a waveform diagram showing an example of each of the drive signals P1 to P4. The drive signals P1 and P3 are pulse signals having a predetermined period T and a predetermined pulse width Ton. The drive signals P1 and P3 are out of phase with each other by a half period (T/2). The period T and the pulse width Ton are set to fixed values in advance. Therefore, the waveforms of the drive signals P1 and P3 are fixed and do not change. The period obtained by subtracting the pulse width Ton from the half period (T/2) is the dead time _td , which is provided to prevent the pulse of the drive signal P1 from overlapping with the pulse of the drive signal P3.

On the other hand, the waveforms of the drive signals P2 and P4 are not fixed, but change according to the adjustment value t _adj . The drive signal P2 is a pulse signal with a fixed pulse width Ton, but the rising timing of the pulse changes according to the drive signal P4. The drive signal P4 is a pulse signal with a variable pulse width. The pulse width of the drive signal P4 changes according to the adjustment value t _adj , and is the sum of the pulse width Ton and the adjustment value t _adj . When the adjustment value t _adj is a positive value, the pulse width of the drive signal P4 is larger than the pulse width Ton. On the other hand, when the adjustment value t _adj is a negative value, the pulse width of the drive signal P4 is smaller than the pulse width Ton. Since the pulse width of the drive signal P4 is not fixed, the control performed by the control circuit 5 is different from normal phase shift control. Furthermore, the pulse width of the drive signal P4 changes according to the adjustment value t _adj , but the pulse widths of the drive signals P1, P2, and P3 are fixed, so the control performed by the control circuit 5 is also different from normal PWM control. The pulse of the drive signal P2 rises when the dead time _td has elapsed from the falling edge of the pulse of the drive signal P4. The pulse of the drive signal P4 rises when the dead time _td has elapsed from the falling edge of the pulse of the drive signal P2.

In FIG. 2, the pulse width of the leftmost pulse of the drive signal P4 is t _adj (t0)=0, which is a pulse width Ton. The pulse width of the next pulse of the drive signal P4 is Ton+t _adj (t1). The pulse width of the next pulse of the drive signal P4 is Ton+t _adj (t2). By changing the pulse width, the overlap period (hatched in FIG. 2) between the pulse of the drive signal P4 and the pulse of the drive signal P1 changes. Each pulse of the drive signal P2 is arranged between each pulse of the drive signal P4. As a result, the overlap period (hatched in FIG. 2) between the pulse of the drive signal P2 and the pulse of the drive signal P3 changes in the same manner. In FIG. 2, the waveform when the adjustment value t _adj is "0" is shown by a dashed line. In this way, the control circuit 5 controls the output current of the power supply device A10 by _adjusting the length of the overlap period between the pulse of drive signal P4 and the pulse of drive signal P1, and the length of the overlap period between the pulse of drive signal P2 and the pulse of drive signal P3, in accordance with the adjustment value t adj.

Figure 3 is a functional block diagram showing an example of the internal configuration of the drive signal generation unit 54. As shown in Figure 3, the drive signal generation unit 54 has, as its functional configuration, a P1 generation unit 541, a P2 generation unit 542, a P3 generation unit 543, a P4 generation unit 544, a period setting unit 545, a pulse width setting unit 546, a dead time setting unit 547, and an addition unit 548.

The cycle setting unit 545 sets a predetermined cycle T. The cycle setting unit 545 outputs the set cycle T to the P1 generating unit 541. The cycle setting unit 545 also outputs a half cycle (T/2) of the cycle T to the P3 generating unit 543, the P4 generating unit 544, and the dead time setting unit 547. The pulse width setting unit 546 sets a predetermined pulse width Ton. The pulse width setting unit 546 outputs the set pulse width Ton to the P1 generating unit 541, the P2 generating unit 542, the P3 generating unit 543, the adding unit 548, and the dead time setting unit 547. The dead time setting unit 547 sets a dead time t _d (=T/2-Ton) based on the half cycle (T/2) input from the cycle setting unit 545 and the pulse width Ton input from the pulse width setting unit 546. The dead time setting unit 547 outputs the set dead time _td to the P2 generating unit 542, the P3 generating unit 543, and the P4 generating unit 544. The adding unit 548 adds the adjustment value _tadj input from the adjustment value calculating unit 53 to the pulse width Ton input from the pulse width setting unit 546, and outputs the result to the P4 generating unit 544 as the pulse width (Ton+ _tadj ) of the drive signal P4.

The P1 generating unit 541 generates the drive signal P1 based on the period T input from the period setting unit 545 and the pulse width Ton input from the pulse width setting unit 546. The P1 generating unit 541 generates the drive signal P1 by raising a pulse for each period T and lowering the pulse after the pulse width Ton has elapsed since the rising edge of the pulse.

The P3 generating unit 543 generates the driving signal P3 based on the half cycle (T/2) input from the cycle setting unit 545, the pulse width Ton input from the pulse width setting unit 546, the dead time _td input from the dead time setting unit 547, and the driving signal P1 input from the P1 generating unit 541. The P3 generating unit 543 generates the driving signal P3 by raising the pulse after the dead time _td has elapsed from the falling edge of the driving signal P1, and lowering the pulse after the pulse width Ton has elapsed from the rising edge of the pulse. The P3 generating unit 543 may raise the pulse after the half cycle (T/2) has elapsed from the rising edge of the driving signal P1. The P3 generating unit 543 may raise the pulse after the half cycle (T/2) and the dead time _td have elapsed from the falling edge of the pulse of the driving signal P3.

The P4 generating unit 544 generates the driving signal P4 based on the half period (T/2) input from the period setting unit 545, the pulse width (Ton+t _adj ) input from the adding unit 548, the dead time t _d input from the dead time setting unit 547, and the driving signal P4 input from the P4 generating unit 544. The P4 generating unit 544 generates the driving signal P4 by raising the pulse after the half period (T/2) and the dead time t _d have elapsed from the falling edge of the pulse of the driving signal P4, and lowering the pulse after the pulse width (Ton+t _adj ) has elapsed from the rising edge of the pulse. Note that the P4 generating unit 544 may raise the pulse after the dead time t _d has elapsed from the falling edge of the pulse of the driving signal P2.

The P2 generating unit 542 generates the driving signal P2 based on the pulse width Ton input from the pulse width setting unit 546, the dead time _td input from the dead time setting unit 547, and the driving signal P4 input from the P4 generating unit 544. The P2 generating unit 542 generates the driving signal P2 by causing a pulse to rise after the dead time _td has elapsed from the falling edge of the pulse of the driving signal P4, and causing the pulse to fall after the pulse width Ton has elapsed from the rising edge of the pulse.

The drive signal P1 generated by the P1 generating unit 541, the drive signal P2 generated by the P2 generating unit 542, the drive signal P3 generated by the P3 generating unit 543, and the drive signal P4 generated by the P4 generating unit 544 are amplified by the drive circuit 6 and input to the switching elements TR1 to TR4 of the inverter circuit 2, respectively. Note that the internal configuration of the drive signal generating unit 54 is not limited to the above. It is sufficient for the drive signal generating unit 54 to be able to generate the drive signals P1 to P4 shown in FIG. 2.

Each part of the control circuit 5 may be implemented as a digital circuit or an analog circuit.

Next, we will explain the effects of the welding power supply A1.

According to this embodiment, the control circuit 5 generates the drive signals P1 to P4 and inputs them to the switching elements TR1 to TR4 of the inverter circuit 2, thereby controlling the inverter circuit 2. The control circuit 5 also controls the output current by changing the pulse width of the drive signal P4 according to the adjustment value t _adj . The pulse of the drive signal P2 rises when the dead time t _d has elapsed since the falling edge of the pulse of the drive signal P4. The pulse of the drive signal P4 rises when the dead time t _d has elapsed since the falling edge of the pulse of the drive signal P2. Therefore, the control circuit 5 can prevent the pulse of the drive signal P4 from overlapping with the pulse of the drive signal P2. Therefore, the control circuit 5 can prevent a short circuit in which the switching elements TR4 and TR2 are turned on at the same time, without limiting the adjustment value t _adj . As a result, the welding power supply A1 can prevent a short circuit and follow the control even if the load changes suddenly.

Furthermore, in this embodiment, when the pulse width of drive signal P4 changes in response to adjustment value t _adj , the overlap period between the pulse of drive signal P4 and the pulse of drive signal P1 changes. The overlap period between the pulse of drive signal P2 and the pulse of drive signal P3 also changes. Therefore, the current flow time on the positive electrode side and the current flow time on the negative electrode side become equal, so that welding power supply A1 can suppress bias magnetism of transformer 3.

In addition, according to this embodiment, there is a period during which switching element TR1 and switching element TR2 are simultaneously on, and a period during which switching element TR3 and switching element TR4 are simultaneously on. The energy stored in the leakage inductance causes current to circulate during these periods, allowing the inverter circuit 2 to achieve zero-volt switching of switching elements TR1 to TR4.

In the present embodiment, the case where the drive signal P1 is input to the switching element TR1, the drive signal P2 is input to the switching element TR2, the drive signal P3 is input to the switching element TR3, and the drive signal P4 is input to the switching element TR4 has been described, but the present invention is not limited to this. For example, as shown in FIG. 4(a), the drive signal P1 may be input to the switching element TR2, the drive signal P2 may be input to the switching element TR1, the drive signal P3 may be input to the switching element TR4, and the drive signal P4 may be input to the switching element TR3. That is, the first arm 21 may be a reference arm or an arm to be controlled. Also, as shown in FIG. 4(b), the drive signal P1 may be input to the switching element TR3, the drive signal P2 may be input to the switching element TR4, the drive signal P3 may be input to the switching element TR1, and the drive signal P4 may be input to the switching element TR2. In other words, the switching element that adjusts the on-period in accordance with the adjustment value t _adj may be a positive switching element or a negative switching element.

In addition, in this embodiment, the control circuit 5 outputs each of the drive signals P1 to P4 fixedly to one of the switching elements TR1 to TR4, but this is not limited to the above. The control circuit 5 may periodically switch the output destination of each of the drive signals P1 to P4 between the switching elements TR1 to TR4. In this case, the switching element to which the drive signal P4 is input and whose on-period varies is not fixed, so it is possible to prevent a burden from being placed on only the same switching element.

In addition, in this embodiment, the present invention has been described as being applied to a welding power supply, but this is not limited to this. The present invention is applicable to all power supplies that convert DC voltage to high-frequency voltage using an inverter circuit.

The power supply device according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the power supply device according to the present invention can be freely designed in various ways.

A1: Welding power supply, 1: DC power supply, 2: Inverter circuit, TR1 to TR4: Switching elements, 3: Transformer, 4: Rectifier circuit, 5: Control circuit, 53: Adjustment value calculation unit, 541: P1 generation unit, 542: P2 generation unit, 543: P3 generation unit, 544: P4 generation unit, 545: Period setting unit, 546: Pulse width setting unit, 547: Dead time setting unit, 548: Addition unit, B: Welding torch

Claims (3)

an inverter circuit having a first arm and a second arm, each of which has two switching elements connected in series;
a control circuit that generates a first drive signal to be input to a first switching element of the first arm, a second drive signal to be input to a second switching element connected in the second arm to the same polarity side as the first switching element, a third drive signal to be input to a third switching element of the first arm, and a fourth drive signal to be input to a fourth switching element connected in the second arm to the same polarity side as the third switching element;
Equipped with
The control circuit always
generating a pulse signal having a predetermined first pulse width at a predetermined period as the first drive signal;
generating a pulse signal obtained by shifting the first drive signal by half a period as the third drive signal;
generating, as the fourth drive signal, a pulse signal having a second pulse width that varies and in which the pulse rises after a predetermined dead time has elapsed since the falling edge of the pulse of the second drive signal;
generating, as the second drive signal, a pulse signal having the first pulse width and a pulse rising after the dead time has elapsed from the falling edge of the pulse of the fourth drive signal;
Power supply. The control circuit includes:
an adjustment value calculation unit that calculates an adjustment value based on a deviation between an output current of the power supply device and a target current value;
A period setting unit that sets the predetermined period;
A pulse width setting unit that sets the first pulse width;
a dead time setting unit that sets the dead time based on the predetermined period and the first pulse width;
an adder that calculates the second pulse width by adding the adjustment value input from the adjustment value calculation unit to the first pulse width input from the pulse width setting unit;
a first drive signal generating unit that generates the first drive signal by causing a pulse to rise at each of the predetermined cycles and causing the pulse to fall after the first pulse width has elapsed from the rising edge of the pulse;
a third drive signal generating unit that generates the third drive signal by causing a pulse to rise after the dead time has elapsed since the falling edge of the first drive signal and causing a pulse to fall after the first pulse width has elapsed since the rising edge of the pulse;
a fourth drive signal generating unit that generates the fourth drive signal by causing a pulse to rise after the half cycle and the dead time have elapsed from the falling edge of a pulse of the fourth drive signal, and causing a pulse to fall after the second pulse width has elapsed from the rising edge of the pulse;
a second drive signal generating unit that generates the second drive signal by causing a pulse to rise after the dead time has elapsed from the falling edge of a pulse of the fourth drive signal and causing a pulse to fall after the first pulse width has elapsed from the rising edge of the pulse;
Equipped with
2. The power supply device of claim 1. A DC power supply that supplies a DC voltage to the inverter circuit;
a transformer that transforms a high-frequency voltage output by the inverter circuit;
a rectifier circuit that rectifies the high-frequency voltage transformed by the transformer;
Further equipped with
The power supply device according to claim 1 or 2, wherein the power supply device outputs a direct current controlled by the inverter circuit to a welding torch.

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