JP7664683B2 - Logic state determination method and logic state determination circuit - Google Patents

Description

This disclosure relates to a logic state determination method and a logic state determination circuit.

As an example of a conventional technique for distinguishing between high, low, and Hi-Z states in a logic input/output circuit, there is a logic state determination circuit described in Patent Document 1. This circuit uses a measurement current limiting circuit made up of an RC circuit to distinguish the logic state in the logic input/output circuit. The Hi-Z state is an electrically isolated state, and is treated as an open state that is neither a high state nor a low state.

Japanese Unexamined Patent Publication No. 63-316516

A measurement current limiting circuit cannot be configured in logic input/output circuits such as a microcomputer, a complex programmable logic device (CPLD), or a field programmable gate array (FPGA). For this reason, the logic state determination circuit described in Patent Document 1 requires the addition of a new measurement current limiting circuit for determining the logic state, which poses the problem of increasing the number of parts.

The present disclosure aims to solve the above problem and provide a logic state determination method and logic state determination circuit that can determine the logic state without increasing the number of measurement current limiting circuits.

A logic state determination method according to the present disclosure includes the steps of: applying a signal to a bus line; releasing application of the signal to the bus line; and, when it is determined that the signal level of the bus line is a high level and is held in a bus hold section and is the same as the signal level applied in the step of applying a signal to the bus line, determining that the state of the bus line is an open state or a pull-up state; subsequently, applying to the bus line a signal of a level different from the signal level applied in the step of applying a signal to the bus line, thereby setting the signal level of the bus line to an opposite level to that immediately before; releasing application of the signal to the bus line; and, when the signal level in the step of setting the signal level of the bus line to an opposite level to that immediately before is different from the current signal level of the bus line, determining that the state of the bus line is a pull-down state or a pull-up state according to the signal level applied to the bus line; and, when the signal level in the step of setting the signal level of the bus line to an opposite level to that immediately before is the same as the current signal level of the bus line, determining that the bus line is in an open state.

According to the present disclosure, a signal is applied to a bus line, the application of the signal to the bus line is released, and the logic state of the signal level of the bus line held in the bus hold section is determined. In this way, the logic state determination method according to the present disclosure can determine the logic state without adding a measurement current limiting circuit.

1 is a block diagram showing a configuration of a logic state determination circuit according to a first embodiment; 1 is a circuit diagram showing a circuit (example 1) whose logic state is to be determined by a logic state determination circuit according to a first embodiment; 1 is a circuit diagram showing a circuit (example 2) whose logic state is to be determined by the logic state determination circuit according to the first embodiment; 1 is a circuit diagram showing a circuit (example 3) whose logic state is to be determined by the logic state determination circuit according to the first embodiment; 4 is a flowchart showing a logic state determination method according to the first embodiment; 11 is a timing diagram showing a logic state determination (example 1) according to the first embodiment. FIG. FIG. 11 is a timing diagram showing a logic state determination (example 2) according to the first embodiment. FIG. 11 is a timing diagram showing a logic state determination (example 3) according to the first embodiment. 1 is a circuit diagram showing a circuit (example 4) whose logic state is to be determined by the logic state determination circuit according to the first embodiment; 11 is a circuit diagram showing a circuit (example 5) whose logic state is to be determined by the logic state determination circuit according to the first embodiment; FIG.

Embodiment 1.
1 is a block diagram showing the configuration of a logic state judgment circuit 1 according to embodiment 1. The logic state judgment circuit 1 is a circuit that judges the logic state of a signal at a measurement point M, and includes a timing control unit 2, a judgment level supply unit 3, a three-state buffer 4, a bus hold unit 5, a bus line 6, a comparison unit 7, and a judgment unit 8.

The timing control unit 2 controls the supply of the judgment level to the three-state buffer 4 by the judgment level supply unit 3 and the timing of judgment by the judgment unit 8. The judgment level supply unit 3 outputs an output signal (OUT) to the three-state buffer 4 and sets an output enable signal (OE). The output signal is a first signal of a high level (hereinafter referred to as H level) or a low level (hereinafter referred to as L level). Similarly, the output enable signal is a second signal of an H level or L level.

The three-state buffer 4 inputs the output signal output from the evaluation level supply unit 3, and when an output enable signal is set by the evaluation level supply unit 3, it applies a signal of a level corresponding to the levels of both signals to the bus line 6. The bus hold unit 5 holds the signal level applied to the bus line 6. The bus line 6 is connected to the measurement point M, and is in the same signal level state as the measurement point M.

The comparator 7 determines whether the signal level of the bus line 6 is H level or L level.

The determination unit 8 determines whether the state of the bus line 6 is a pull-down state, a pull-up state, or an open state based on the determination result by the comparison unit 7. The determination unit 8 also outputs a signal indicating the determination result of the logical state of the bus line 6.

The measurement point M, whose logic state is judged by the logic state judgment circuit 1, includes the following circuits.
Fig. 2 is a circuit diagram showing a circuit (example 1) whose logic state is to be judged by the logic state judgment circuit 1. In Fig. 2, measurement point M in Fig. 1 is a circuit that pulls down the bus line 6 to ground 10 via a pull-down resistor R _pd . A buffer 9 holds an input signal (IN) used to check the state of the bus line 6. The input signal (IN) is a signal that indicates the signal level of the bus line 6.

Fig. 3 is a circuit diagram showing a circuit (example 2) to be judged by the logic state judgment circuit 1. In Fig. 3, the measurement point M in Fig. 1 is a circuit that pulls up the bus line 6 to the potential of the power supply 11 via a pull-up resistor _Rpa .

Figure 4 is a circuit diagram showing a circuit (example 3) to be judged by the logic state judgment circuit 1. In Figure 4, the measurement point M in Figure 1 is the open end 12 that puts the bus line 6 in an open state.

2, 3 and 4, the three-state buffer 4 has a resistor _Rb connected to its output, and can set the bus line 6 to one of three states: L level, H level, or open state. For example, the three-state buffer 4 enables the output when an H level output enable signal (OE) is set. That is, when an H level output signal (OUT) is input, the three-state buffer 4 applies an H level signal to the bus line 6, and when an L level output signal (OUT) is input, the three-state buffer 4 applies an L level signal to the bus line 6. When an L level output enable signal is set, the three-state buffer 4 sets the output to an open state. Note that the current _Ib flowing through the three-state buffer 4 when the output is enabled is the drive current.

The bus hold unit 5 operates to output an H level signal when the state of the bus line 6 is H level, and to output an L level signal when the state of the bus line 6 is L level. The bus hold unit 5 is composed of two inverters whose input terminals and output terminals are connected to each other, and a resistor _Rh is connected to one of the connection points.

The influence of the bus hold unit 5 on the state of the bus line 6 is reduced by minimizing the current _Ih (holding current) flowing through the resistor _Rh with high resistance. As a result, even if the element (measurement point M) that drives the bus line 6 is opened, the bus hold unit 5 holds the level of the bus line 6 immediately before it was opened.

Current _Ipd is a current flowing through pull-down resistor _Rpd , and is the upper limit current value for maintaining the signal level of bus line 6 at L level. The pull-down resistor _Rpd shown in Fig. 2 has a value such that _Rh >> _Rpd >> _Rb and the relationship _Ib >> _Ipd >> _Ih holds. In other words, a value is selected for pull-down resistor _Rpd that allows a current to flow that cancels the holding current _Ih of bus hold unit 5 and is not affected by drive current _Ib of three-state buffer 4.

Current _Ipa is a current flowing through pull-up resistor _Rpa , and is the lower limit current value for maintaining the signal level of bus line 6 at H level. The pull-up resistor _Rpa shown in Fig. 3 has a value such that _Rh >> _Rpa >> _Rb and the relationship _Ib >> _Ipa >> _Ih holds. In other words, a value is selected for pull-up resistor _Rpa that allows a current to flow that cancels the holding current _Ih of bus hold unit 5 and is not affected by drive current _Ib of three-state buffer 4. Furthermore, at open end 12 shown in Fig. 4, the relationship _Rh >> _Rb holds.

The logic state determination method according to the first embodiment is as follows.
Fig. 5 is a flowchart showing a logic state determination method according to the embodiment 1. Fig. 6 is a timing diagram showing a logic state determination (example 1) according to the embodiment 1. The determination level supplying unit 3 outputs an H-level output signal (OUT) and an H-level output enable signal (OE) to the three-state buffer 4 in the period (1) of Fig. 6 according to the control of the timing control unit 2 (step ST1).

Next, the evaluation level supplying section 3 sets an L-level output enable signal (OE) to the three-state buffer 4 during the period (2) in Fig. 6 under the control of the timing control section 2 (step ST2). Note that the output signal (OUT) is not specified as being at an H or L level. This disables the output of the three-state buffer 4, and puts it in an open state ( _Ib ≈ 0). Next, under the control of the timing control section 2, the comparing section 7 determines whether the input signal (IN) is at an H or L level (step ST3).

At the timing A when the state of the bus line 6 is determined, if the result that the input signal (IN) is at L level is obtained (step ST3; Low), the judgment unit 8 judges that the measurement point M is in a pull-down connection (step ST4). When the measurement point M is at L level, a current of I _pd or more cannot be passed through the bus hold unit 5, and the H level of the bus line 6 cannot be maintained, so it is judged that the state of the bus line 6 has become L level. Since the current I _b flowing through the resistor R _b of the three-state buffer 4 is almost 0 (I _b ≈ 0), the current that makes the bus line 6 at L level is a current of a value equal to or less than I _pd .

Figure 7 is a timing diagram showing a logic state determination (example 2) according to the first embodiment. If the signal (IN) is at H level during the period (2) in Figure 7 (step ST3; High), the bus hold unit 5 is able to maintain the H level state of the bus line 6 (timing B). In other words, the bus line 6 is not pulled down. If the bus line 6 is not pulled down, it is in an open state (Hi-Z) or in a pulled-up state.

In accordance with the control of the timing control unit 2, the evaluation level supply unit 3 outputs an L-level output signal (OUT) to the three-state buffer 4 during the period (3) in FIG. 7, and sets an H-level output enable signal (OE) to the three-state buffer 4 (step ST5). When the H-level output enable signal (OE) is set, the three-state buffer 4 becomes output-enabled, but since the output signal (OUT) is at an L level, an L-level state opposite to that immediately before is applied to the bus line 6.

Next, the evaluation level supplying section 3 sets an L-level output enable signal (OE) to the three-state buffer 4 during the period (4) in Fig. 7 under the control of the timing control section 2 (step ST6). The output signal (OUT) is not specified as being at an H or L level. This disables the output of the three-state buffer 4, and it is in an open state ( _Ib ≈ 0). Next, under the control of the timing control section 2, the comparing section 7 determines whether the input signal (IN) is at an H or L level (step ST7).

At the timing C when the state of the bus line 6 is determined, if the result that the input signal (IN) is H level is obtained (step ST7; High), the judgment unit 8 judges that the measurement point M is in a pull-up connection (step ST8). If the measurement point M is H level, the L level of the bus line 6 cannot be maintained in the bus hold unit 5, so it is judged that the state of the bus line 6 has been set to H level by a current equal to or greater than _Ih and equal to or less than _Ipa . The current _Ib flowing through the resistor _Rb of the three-state buffer 4 is almost 0 ( _Ib ≈ 0), and the current that has set the bus line 6 to H level is a current with a value equal to or greater than _Ih and equal to or less than _Ipa .

8 is a timing diagram showing a logic state judgment (example 3) according to the first embodiment. In the period (4) of FIG. 8, when the input signal (IN) is at L level, the L level of the bus line 6 can be maintained in the bus hold unit 5. That is, since the bus line 6 is not at H level due to the pull-up current _Ipa , it can be judged that it is not pulled up. Since the bus line 6 is judged to be in an open state (Hi-Z) or in a pull-up state in step ST3, if it is not in a pull-up state, it can be judged to be in an open state (Hi-Z).

At timing D, if the judgment unit 8 obtains the result that the input signal (IN) is at L level (step ST7; Low), it judges that the measurement point M is in an open state (Hi-Z) (step ST9).

During period (1) of FIG. 6, period (1) of FIG. 7, and period (1) of FIG. 8, the judgment level supply unit 3 may set an H-level output enable signal (OE) to the three-state buffer 4 and cause the three-state buffer 4 to input an L-level output signal (OUT), or during period (3) of FIG. 7 and period (3) of FIG. 8, the judgment unit 8 may set an H-level output enable signal (OE) to the three-state buffer 4 and cause the three-state buffer 4 to input an H-level output signal (OUT). In this case, the judgment unit 8 judges the logic state of the measurement point M during period (2) of FIG. 6, period (4) of FIG. 7, or period (4) of FIG. 8.

Figure 9 is a circuit diagram showing a circuit (example 4) whose logic state is to be determined by the logic state determination circuit 1. In Figure 9, switch 13 is measurement point M, and switches to either a circuit that pulls down bus line 6 to ground 10, a circuit that pulls up bus line 6 to the potential of power supply 11, or an open end 12 that puts bus line 6 in an open state. The logic state of the circuit switched by switch 13 is determined by the series of processes shown in Figure 5.

Figure 10 is a circuit diagram showing a circuit (example 5) whose logic state is to be judged by the logic state judgment circuit 1. In Figure 10, jumper switch 14a, when turned on, connects to bus line 6 a circuit that pulls up bus line 6 to the potential of power supply 11, and when turned off, disconnects the pull-up connection from bus line 6. Jumper switch 14b, when turned on, connects to bus line 6 a circuit that pulls down bus line 6 to ground 10, and when turned off, disconnects the pull-down connection from bus line 6.

When both jumper switches 14a and 14b are off, the end of the bus line 6 becomes an open end 12. The logic state of the circuit switched by the jumper switches 14a and 14b is determined by the series of processes shown in Figure 5.

As described above, the logic state determination method according to the first embodiment applies a signal to the bus line 6, releases the signal application to the bus line 6, and determines the signal level of the bus line 6 held in the bus hold unit 5 to determine whether the state of the measurement point M is in a pull-up state, a pull-down state, or an open state (Hi-Z). As a result, the logic state determination method according to the first embodiment can determine the logic state without adding a measurement current limiting circuit.

In addition, any of the components of the embodiments may be modified or omitted.

1 logic state determination circuit, 2 timing control section, 3 determination level supply section, 4 three-state buffer, 5 bus hold section, 6 bus line, 7 comparison section, 8 determination section, 9 buffer, 10 ground, 11 power supply, 12 open end, 13 switch, 14a, 14b jumper switches.

Claims (4)

applying a signal to a bus line;
releasing the application of a signal to the bus line;
a step of determining that the state of the bus line is an open state or a pull-up state when it is determined that the signal level of the bus line is a high level if the current signal level of the bus line is held in a bus hold unit and is the same as the signal level applied in the step of applying a signal to the bus line;
a step of applying a signal to the bus line at a level different from the signal level applied in the step of applying a signal to the bus line, thereby causing the signal level of the bus line to be reversed from that immediately before;
releasing the application of a signal to the bus line;
a step of determining that the state of the bus line is a pull-down state or a pull-up state according to the signal level applied to the bus line when the signal level in the step of changing the signal level of the bus line to a level opposite to that immediately before is different from the current signal level of the bus line;
determining that the bus line is in an open state when the signal level in the step of changing the signal level of the bus line to a level opposite to that immediately before is the same as the current signal level of the bus line;
A method for determining a logic state comprising: a bus hold section for holding a signal level applied to a bus line;
a three-state buffer that receives a first signal and a second signal, and applies a signal having a level according to values of the first signal and the second signal to the bus line;
a decision level supply unit that outputs the first signal to the three-state buffer and sets the second signal;
a determination unit that determines whether the logic state of the bus line is a pull-down state, a pull-up state, or an open state ;
Equipped with
The three-state buffer is
performing a step of applying a signal to the bus line;
Next, a step of releasing the application of signals to the bus line is performed ;
The determination unit is
execute a step of determining that the state of the bus line is an open state or a pull-up state when it is determined that the signal level of the bus line is a high level if the current signal level of the bus line is held in the bus hold unit and is the same as the signal level applied in the step of applying a signal to the bus line;
The three-state buffer is
Next, a step of applying a signal to the bus line at a level different from the signal level applied in the step of applying a signal to the bus line, and changing the signal level of the bus line to a level opposite to that immediately before is executed ;
performing a step of releasing the application of a signal to the bus line;
The determination unit is
execute a step of determining that the state of the bus line is a pull-down state or a pull-up state according to the signal level applied to the bus line, when the signal level in the step of changing the signal level of the bus line executed by the three-state buffer to a level opposite to that immediately before is different from the current signal level of the bus line;
If the signal level of the step of changing the signal level of the bus line by the three-state buffer to a level opposite to that immediately before is the same as the current signal level of the bus line, a step of determining that the bus line is in an open state is performed.
A logic state determination circuit comprising: 3. The logic state determination circuit according to claim 2, wherein a switch for switching between the presence or absence of a pull-up resistor or a pull-down resistor is connected to said bus line. 3. The logic state determination circuit according to claim 2, wherein a jumper switch for switching between the presence or absence of a pull-up resistor or a pull-down resistor is connected to the bus line.

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