JP7668461B2 - Communication terminal and communication system - Google Patents

Description

This disclosure relates to a communication terminal and a communication system.

Conventionally, communication systems that perform load control using two-wire signal lines have been in widespread use. These communication systems are configured by interconnecting a transmitting terminal, which is a parent device acting as a central control device, with communication terminals such as switches via two-wire signal lines. This communication system has the characteristic that the two-wire signal lines can be freely connected and branched, and the communication terminals can be freely positioned (called free topology), allowing for a flexible system configuration. With this communication system, a communication system can be realized with a small amount of wiring in a large building. Patent Document 1 discloses an example of a communication system.

JP 2019-204638 A

In communication systems, there is a demand for an increase in the number of communication terminals and high-speed, large-capacity communication. One possible solution to this is to increase the frequency of the signal sent from the transmitting terminal. However, when the signal frequency increases, the effects of reflected waves cannot be ignored due to impedance mismatch between the signal line and the transmitting terminal or communication terminal. The effects of reflected waves can cause signal reading errors at the communication terminal.

Impedance matching is usually used to suppress reflected waves in high-frequency signals. However, because this communication system is free topology, changes to the signal line or communication terminal layout change the characteristic impedance of the signal line, making it difficult to address this issue through impedance matching. As the transmission signals of this communication system become higher frequency, signal reading errors due to reflected waves become an issue.

The objective of this disclosure is to provide a communication terminal and a communication system that are less susceptible to the effects of reflected waves and are less susceptible to signal reading errors.

The communication terminal according to the present disclosure is a communication terminal that receives a voltage signal in which a signal voltage is superimposed on a predetermined reference voltage via a signal line, and includes a signal receiving unit having a receiving end and receiving the voltage signal, and a voltage clamp circuit that clamps the receiving end when the voltage at the receiving end exceeds a first predetermined voltage that is a voltage within a predetermined range from the reference voltage. The voltage clamp circuit is characterized by having a reference voltage holding unit that holds the first predetermined voltage, and a voltage detection unit that makes the receiving end conductive with the reference voltage holding unit when the voltage at the receiving end exceeds the first predetermined voltage.

This disclosure makes it possible to realize a communication terminal and a communication system that are less susceptible to the effects of reflected waves and are less susceptible to signal reading errors.

FIG. 1 is a configuration diagram of a communication system according to an embodiment. FIG. 1 is an equivalent circuit diagram of a communication system according to an embodiment of the present invention. 1A and 1B are diagrams for explaining the principle of reflected waves in a transmission line. 2 is a waveform diagram showing a transmission signal and its reflected wave on a transmission line. 1 is a configuration diagram of a communication system including a communication terminal according to an embodiment. 6A to 6C are waveform diagrams illustrating suppression of reflected waves in the communication terminal of the embodiment. FIG. 2 is a circuit diagram of a communication terminal according to an embodiment. FIG. 11 is a circuit diagram of a communication terminal according to another embodiment. FIG. 11 is a circuit diagram of a communication terminal according to another embodiment. FIG. 11 is a circuit diagram of a communication terminal according to another embodiment.

Embodiments of the present disclosure will be described in detail below with reference to the drawings. In the following description, specific shapes, materials, directions, values, etc. are merely examples to facilitate understanding of the present disclosure, and may be modified as appropriate according to the application, purpose, specifications, etc. In addition, it is anticipated from the beginning that the components of the embodiments and modified examples described below will be selectively combined.

First, we will explain the overall configuration and general operation of a communication system in which the communication terminal disclosed herein is used.

[Communication system]
FIG. 1 is a configuration diagram of a communication system 10. The communication system 10 includes a transmission terminal 20, a switch 31 and a terminal unit 32 as a communication terminal 30, relays 40a to 40d, and lighting fixtures 50a to 50d. The lighting fixtures 50a to 50d are objects of control in the communication system 10. In addition to these devices, other switches, other terminal units, other objects of control, etc. may be connected to the communication system 10, but are not shown. The communication system 10 is a system in which the transmission terminal 20 plays a central role and can control the lighting fixtures 50a to 50d, etc., which are objects of control in the communication system 10. The control of the lighting fixtures includes on/off control, dimming control, scene control, and monitoring control of the lighting fixtures. The scene control is to control the dimming and color adjustment of the lighting fixtures depending on the installation location of the lighting fixtures (Japanese-style room, Western-style room, bedroom, study, etc.) and the situation in which the lighting fixtures are used (morning, noon, night, mealtime, family time, etc.). The monitoring control is to monitor the control state of the lighting fixtures. These controls can be performed by operating the switch 31.

The communication system 10 employs, for example, a time division multiplex transmission method, and the signal line 60 is configured as a two-wire wire. In the signal line 60, a signal (information) is transmitted by a pulse signal due to the potential difference between the two lines. In addition, the communication system 10 employs, for example, a cyclic transmission method, and a signal transmitted from the transmitting terminal 20 passes through all the devices connected to the signal line 60. Each device checks the contents of the signal, and the device that requires the signal according to the contents receives the signal. For example, each device receives the signal if it contains its own address information, and ignores the signal if it does not contain its own address information. In this way, the devices connected to the signal line 60 can check the contents of the signal even if it is transmitted from the transmitting terminal 20 and is not addressed to the device itself.

The transmitting terminal 20 is a parent controller that operates centrally in the communication system 10. The transmitting terminal 20 transmits a signal from the switch 31 connected to the signal line 60 to the terminal unit 32. The switch 31 and the terminal unit 32 in FIG. 1 are the communication terminal 30 in this disclosure.

The switch 31 is a wall switch or the like that is provided to allow the user to control (turn on, turn off, dim, etc.) the lighting devices 50a to 50d. For example, as shown in FIG. 1, the switch 31 has four operating units 31a to 31d. Each operating unit has, for example, two states, an on state and an off state, and the user can operate the operating unit to turn on or off the lighting device corresponding to the operating unit.

For example, address information is assigned to each operation unit, and the address information and lighting fixtures are associated in a one-to-one correspondence.

The terminal unit 32 is a device that transmits signals sent from the transmitting terminal 20 to the relays 40a to 40d. The terminal unit 32 has multiple terminals to which the relays 40a to 40d are connected.

The relays 40a to 40d are switches that switch the power supply to the lighting fixtures 50a to 50d connected to them on and off. For example, when a relay receives an instruction from the terminal unit 32 to turn on the power supply, it turns on the power supply to the lighting fixture connected to it, and when a relay receives an instruction to turn off the power supply, it turns off the power supply to the lighting fixture connected to it. The terminal unit 32 and the relays 40a to 40d may be formed integrally.

Lighting fixtures 50a to 50d are installed, for example, on the ceiling of a floor in a facility. Each lighting fixture can be switched on and off and its dimming rate (brightness) can be changed, for example, by a signal from transmission terminal 20. The light source of the lighting fixture can be, but is not limited to, an LED, a fluorescent lamp, etc.

With such a communication system 10, wiring for one-to-one connection between the control target and the switch 31 is not required. With the communication system 10, only a signal line 60 consisting of two wires is required. This allows the amount of wiring in the communication system 10 to be reduced, for example, in a large building.

The above describes an example in which the control target of the communication system 10 is a lighting fixture, but the control target is not limited to a lighting fixture. The communication system 10 may be configured to control other devices, such as air conditioning equipment.

When the number of connected terminals in the communication system 10 is increased or the amount of signal information between terminals is increased, measures are taken to increase the signal frequency in order to maintain the system response. When the control signal transmitted over the signal line is increased in frequency, the effects of reflected waves become apparent. The communication terminal in this disclosure has a configuration that suppresses signal reading errors without being affected by reflected waves.

The communication system 10 disclosed herein is free topology, so impedance matching is not essential. If impedance matching is not achieved, reflected waves will occur. Next, the principle of how reflected waves occur will be explained.

[Principle behind reflected wave generation]
The principle of generation of a reflected wave will be described with reference to FIGS.

Figure 2 is an equivalent circuit diagram of the minimum unit system of the communication system 10 disclosed herein, which is composed of a transmitting terminal 20, a signal line 60, and a communication terminal 30.

Vi is a voltage signal transmitted from the transmitting terminal 20. Point A is the transmitting end of the transmitting terminal 20. Z _A is the output impedance of the transmitting terminal 20. Connected between points A and B is a signal line 60, and Z _AB is the characteristic impedance of the signal line 60. Point B is the receiving end of the communication terminal 30. Z _B is the input impedance of the communication terminal 30.

ρ _A represents the reflection coefficient of the transmitting end A, and ρ _B represents the reflection coefficient of the receiving end B, which are defined by the following equations.
ρ _A = (Z _A - Z _AB )/(Z _A + Z _AB ) (Formula 1)
ρ _B = (Z _B - Z _AB )/(Z _B + Z _AB ) (Formula 2)
The signal delay time in the signal line 60 (the time it takes for a signal to propagate from point A to point B) is defined as Td.

The output impedance Z _A of the transmitting terminal 20 is set to a low impedance, Z _A < Z _AB , in order to suppress a voltage drop due to the output current. Therefore, the sign of the numerator in Equation 1 is negative, and the reflection coefficient ρ _A of the transmitting end is negative. The input impedance Z _B of the communication terminal 30 is set to a high impedance, Z _B > Z _AB , in order to maintain the voltage signal amplitude at the receiving end. Therefore, the sign of the numerator in Equation 2 is positive, and the reflection coefficient ρ _B of the receiving end is positive. In the communication system 10 of the present disclosure, unless otherwise specified, the following description will be given assuming that the above conditions are met.

Figure 3 is a conceptual diagram showing a reflected wave generated between the transmitting end A and the receiving end B. Figure 4 shows the voltage Vi of the transmitting terminal 20 and the receiving end voltage Vo at the receiving end B. The transmitting terminal 20 of the present disclosure outputs a voltage signal in which a negative voltage is superimposed on a constant DC voltage (reference voltage V10) as a voltage signal. The voltage Vi in Figure 4 represents the voltage of a single voltage signal transmitted from the transmitting terminal 20. The receiving end voltage Vo in Figure 4 is the voltage observed at the receiving end B, and represents a waveform influenced by the reflected wave.

[Reflected wave at the receiving end at time Td]
At time 0, voltage Vi transmitted from transmitting terminal 20 is dropped by output impedance _ZA to produce voltage V(t), which propagates through signal line 60 and arrives at receiving terminal B after delay time Td. The receiving terminal voltage received at receiving terminal B is delayed by time Td from V(t) and can be expressed as V(t-Td). Since impedance matching is not achieved at receiving terminal B, a reflected wave is generated in response to the arriving voltage V(t-Td), which propagates through signal line 60 and proceeds to the transmitting terminal.

At the receiving end B, the reflected wave is ρ _B V(t-Td) obtained by multiplying the arriving voltage V(t-Td) by the reflection coefficient ρ _B. Since the reflection coefficient ρ _B at the receiving end B is positive, the reflected wave ρ _B V(t-Td) is a voltage in phase with the voltage V(t). The reflected wave ρ _B V(t-Td) propagates toward the transmitting end after time Td. At the receiving end B, a composite voltage of the arriving voltage V(t-Td) and the reflected wave ρ _B V(t-Td) is observed. This voltage appears as a voltage that swings significantly in the negative direction after time Td in FIG. 4. In this disclosure, the signal that first swings to the negative side at the receiving end B is called the main wave (first wave).

The voltage generated at the receiving end B from time Td is expressed by the following equation.
V(t-Td)+ρ _B V(t-Td)=(1+ρ _B )V(t-Td) (Formula 3)

[Reflected wave at the transmitting end at time 2Td]
The reflected wave ρ _B V(t-Td) at the receiving end B reaches the transmitting end at time 2Td (the time when twice the delay time has elapsed). Since the transmitting end is also delayed by time Td, the reflected wave that arrives is ρ _B V(t-2Td). Since impedance matching is not performed at the transmitting end A, a reflected wave is also generated. The reflected wave at the transmitting end A for ρ _B V(t-2Td) is ρ _A ρ _B V(t-2Td). Since the reflection coefficient at the transmitting end A is negative, the reflected wave ρ _A ρ _B V(t-2Td) is a voltage of opposite phase to the arriving voltage ρ _B V(t-2Td). This voltage ρ _A ρ _B V(t-2Td) propagates through the signal line and reaches the receiving end B at time 3Td.

[Reflected wave at the receiving end after time 3Td]
When the reflected wave ρ _A ρ _B V (t-2Td) from the transmitting end A reaches the receiving end B at time 3Td, there is a delay of time Td, so the voltage that arrives is ρ _A ρ _B V (t-3Td). A reflected wave is generated for this arriving voltage. The reflected wave for the arriving voltage ρ _A ρ _B V (t-3Td) is ρ _A ρ _B ² V (t-3Td). The reflected wave ρ _A ρ _B ² V (t-3Td) propagates from the receiving end B to the transmitting side. The combined voltage of the voltage that arrives at time 3Td and its reflected wave is expressed by the following equation.
ρ _A ρ _B V (t-3Td) + ρ _A ρ _B ² V (t-3Td) = ρ _A ρ _B (1+ρ _B )V (t-3Td) (Formula 4)

On the other hand, at the receiving end B, the voltage of Equation 3, which is the voltage generated at time Td, still exists. Therefore, what is observed at the receiving end B is the composite voltage of the voltages expressed by Equations 3 and 4.

The voltage component represented by Equation 4 has the opposite sign to the voltage component represented by Equation 3. The voltage component represented by Equation 4 is shown in FIG. 4 as a voltage that swings to the positive side. In this disclosure, the signal that first swings to the positive side is called the second wave.

Similarly, at time 5Td, the combined voltage of the voltage arriving at the receiving end B and the reflected wave is expressed by the following equation.
ρ _A ² ρ _B ² V (t-5Td) + ρ _A ² ρ _B ³ V (t-5Td) = ρ _A ² ρ _B ² (1+ρ _B )V (t-5Td) (Formula 5)
It becomes.

The voltage component represented by Equation 5 has the same positive sign as the voltage component in Equation 3. This voltage component appears in FIG. 4 as a voltage that swings negative for the second time. In this disclosure, this signal is referred to as the third wave.

After that, reflection is repeated at receiving end B and transmitting end A every time Td in the same manner. At receiving end B, the reflected wave arrives every delay time 2Td, generating the Mth wave (M is an integer).

[Effects of reflected waves in communication systems]
The amplitude directions of the third wave, fifth wave, and Nth wave (N is an odd number) in Fig. 4 are the same negative voltage superimposed on the main wave. When a transmission method is adopted in which a reference voltage V10 is used as the base state and a negative voltage is superimposed to generate a data signal, the Nth wave such as the third wave, the fifth wave, etc. may be erroneously read as a data signal. The third wave, which has a small attenuation, is particularly problematic.

Next, we will explain the details of how the communication terminal in this disclosure suppresses reflected waves.

[Mechanism for suppressing reflected waves]
5 is a block diagram showing the configuration of a communication terminal 30 connected to the communication system 10. The communication terminal 30 is connected to a signal line 60 at a receiving end B. A voltage clamp circuit 320, a bypass circuit 330, and a trigger circuit 340 are connected to the receiving end B. _ZB is the input impedance of the communication terminal 30 including the signal receiving unit 310.

The signal receiving unit 310 reads the signal from the receiving end voltage Vo_ and decodes the information contained in the signal transmitted from the transmitting terminal 20. The communication terminal 30 performs various operations based on the signal, but details will be omitted.

The voltage clamp circuit 320 inputs the receiving end voltage Vo_ received at the receiving end B. The voltage clamp circuit 320 receives the receiving end voltage Vo_ and holds a first predetermined voltage V1 (hereinafter also referred to as a held voltage V1). When the receiving end voltage Vo_ is equal to or higher than the first predetermined voltage V1, the voltage clamp circuit 320 clamps the receiving end voltage Vo_ to the first predetermined voltage V1. The first predetermined voltage V1 is set to a voltage within a predetermined range of the reference voltage V10 of the transmission signal of the communication system 10, for example, in the range of 0.3 V to 1.4 V.

The bypass circuit 330 is connected to the receiving end B, and when the receiving end voltage Vo_ exceeds the first predetermined voltage V1, it bypasses the receiving end B with low impedance to suppress an increase in the receiving end voltage Vo_. The bypass circuit 330 operates upon receiving a trigger signal from the trigger circuit 340.

The trigger circuit 340 generates a trigger signal for operating the bypass circuit 330. The trigger circuit 340 is configured to generate a trigger signal when the receiving end voltage Vo_ exceeds a first predetermined voltage V1.

In the communication terminal 30 of this embodiment, a voltage clamp circuit 320 is provided at the receiving end B, so that when the second wave of the reflected wave shown in FIG. 4 occurs, the receiving end voltage Vo_ is clamped to a first predetermined voltage V1. Specifically, the voltage of the second wave in FIG. 4 and above V1 are cut off. Since the second wave disappears, the subsequent reflected waves from the third wave onwards also disappear. This suppresses the reflected waves that cause the communication terminal 30 to read the signal erroneously.

In this embodiment, the reflected wave (main wave in FIG. 4) that occurs at the receiving end B when the receiving signal transmitted from the transmitting terminal 20 first arrives is not suppressed. The reason for this is that the polarity of the receiving signal at the receiving end B and the reflected wave corresponding to it are the same, so the amplitude only increases and there is no error in reading the signal.

Figure 6 shows the receiving end voltage Vo_, the transmitting end transmission voltage Vi, and the receiving end voltage Vo when reflected waves are not suppressed for the communication terminal 30 of this embodiment.

As described above, the voltage clamp circuit 320 has the effect of cutting the portion of the receiving end voltage Vo that exceeds the first predetermined voltage V1 (shown by diagonal lines in the figure) when the reflected wave is not suppressed. In reality, the voltage clamp circuit 320 clamps the first positive polarity voltage (second wave) of the receiving end voltage Vo to the first predetermined voltage V1. This effectively suppresses reflection from the receiving end B to the transmitting end A. This also eliminates reflection from the transmitting end A, and high-order reflected waves are eliminated. It can be seen that the receiving end voltage Vo_ of the communication terminal 30 of this embodiment has voltages above the first predetermined voltage V1 cut off. By cutting the second wave in the receiving end voltage Vo_, the subsequent reflected waves from the third wave onwards are suppressed. The above operation suppresses reflected waves and eliminates the risk of signal reading errors.

Further explanation will be given below with specific examples.

[First embodiment]
7A shows a circuit diagram of a first embodiment of the communication terminal 30. The signal receiving unit 310 is not shown. In the first embodiment, a voltage clamp circuit 320 and a bypass circuit 330 are connected in parallel to the receiving end B.

The voltage clamp circuit 320 is composed of a series circuit of a diode D1, a resistor R3, and a capacitor C1, and a resistor R1 in parallel with the capacitor C1. The bypass circuit 330 is composed of a series circuit of the emitter-collector of a PNP transistor Q1 and a resistor R2. The diode D1, resistors R3 and R4, and the emitter-base of the transistor Q1 form a trigger circuit 340.

The capacitor C1 and resistor R1 of the voltage clamp circuit 320 constitute the reference voltage holding section 321. The capacitor C1 receives the receiving end voltage Vo_ received at the receiving end B and acts to hold the first predetermined voltage V1. The capacitor C1 is set to a capacitance large enough to hold the voltage almost constant with respect to the frequency of the signal contained in the receiving end voltage Vo_ (i.e., the frequency contained in the transmission signal). The resistor R1 is a discharge resistor for the capacitor C1 and prevents the holding voltage of the capacitor C1 from excessively rising from the first predetermined voltage V1. The resistor R1 is set to a relatively high resistance. The diode D1 constitutes the voltage detection section 322. The diode D1 turns on when the receiving end voltage Vo_ becomes higher than the sum of the holding voltage of the capacitor C1 and the forward voltage of the diode D1, and flows a current to the capacitor C1 through the resistor R3. Since the capacitance of the capacitor C1 is set to a sufficiently large capacitance as described above, the voltage hardly changes due to the current through the resistor R3. Resistor R3 is selected to have a smaller resistance value than resistor R1. The voltage V1 held by capacitor C1 is held at the reference voltage minus the forward voltage of diode D1 (approximately 0.3 to 0.7 V).

The above-described action of the voltage clamp circuit 320 can prevent the receiving end voltage Vo_ received at the receiving end B from rising above the first predetermined voltage V1. This suppresses reflected waves and eliminates the risk of signal reading errors.

In this embodiment, the bypass circuit 330 is connected in parallel to the voltage clamp circuit 320. The bypass circuit 330 connects a resistor R2 to the receiving end B via a transistor Q1, bypassing the current and assisting the voltage holding function of the voltage clamp circuit 320.

In the bypass circuit 330, the emitter of a PNP transistor Q1 is connected to the receiving end B, and the collector is connected to one end of a resistor R2. The other end of the resistor R2 is connected to the circuit ground. It is preferable that the resistor R2 is selected to have a low resistance. The base of the transistor Q1 is connected to the connection point of the resistor R3 and the capacitor C1 via a resistor R4.

When the receiving end voltage Vo_ rises above the holding voltage of the capacitor C1, as described above, the diode D1 turns on and a current flows through the path of the diode D1, resistor R3, and capacitor C1. At this time, due to the forward voltage of the diode D1 and the voltage drop of the resistor R3, the base potential becomes lower than the emitter potential of the transistor Q1, and a current flows from the emitter to the base of the transistor Q1. This causes conduction between the emitter and collector of the transistor Q1, and a path is formed that bypasses the receiving end B through the emitter-collector of the transistor Q1 and resistor R2. The resistor R2 has a low resistance, and even if the transistor Q1 turns on and the receiving end voltage Vo_ tries to rise, it bypasses the current and suppresses the rise in the receiving end voltage Vo_. The bypass circuit 330 can suppress a sudden rise in the receiving end voltage.

As described above, the diode D1, resistors R3 and R4, and the emitter-base of the transistor Q1 function as the trigger circuit 340 of the bypass circuit 330. In addition, the diode D1 functions as a voltage detection unit 322 that turns on when the receiving end voltage Vo_ becomes equal to or greater than the first predetermined voltage V1 of the capacitor C1, activating the trigger circuit 340.

When the receiving end voltage Vo_ becomes equal to or less than the sum of the holding voltage V1 of the capacitor C1 and the forward voltage of the diode D1 (second predetermined voltage), the diode D1 turns off, the emitter potential of the transistor Q1 becomes equal to or less than the base potential of Q1, the transistor Q1 turns off, and the bypass circuit 330 stops.

That is, in this embodiment, when the receiving end voltage Vo_ exceeds a first predetermined voltage, a bypass circuit that bypasses the receiving end operates, and then when the receiving end voltage Vo_ falls below a second predetermined voltage that is equal to or greater than the first predetermined voltage, the operation of the bypass circuit is stopped. Note that the relationship between the first and second predetermined voltages is not limited to that in this embodiment. The second predetermined voltage may be set to the same as the first predetermined voltage.

The operation described in the first embodiment prevents the receiving end voltage Vo_ from generating a voltage higher than the voltage V1 held by the capacitor C1, and suppresses the effects of reflected waves. This makes it possible to prevent erroneous reading of the signal.

Figure 7(b) is a modified example of the first embodiment. The configurations of the voltage clamp circuit 320 and the trigger circuit 340 are the same as those of the first embodiment in Figure 7(a), except that the connection position of the bypass circuit 330 has been changed from the receiving end B to the cathode of the diode D1.

When the receiving end voltage Vo_ rises above the holding voltage of capacitor C1 and diode D1 turns on, the base potential becomes lower than the emitter potential of transistor Q1 due to a voltage drop caused by current flowing through resistor R3, and current flows from the emitter to the base. Compared to the embodiment in Figure 7(a), the voltage applied between the emitter and base of transistor Q1 is lower by the forward voltage of diode D1, but the operation of bypass circuit 330 is the same. The holding voltage V1 of capacitor C1 is held at a voltage obtained by subtracting the sum of the forward voltage of diode D1 and the emitter-base voltage of transistor Q1 (approximately 1.4 V) from the reference voltage.

When a signal voltage is received at receiving end B, i.e., when the main wave arrives in FIG. 6, the voltage at receiving end B is lower than the reference voltage V10. Capacitor C1 of voltage clamp circuit 320 maintains the holding voltage V1, so voltage V3 is generated from the non-ground terminal of capacitor C1 toward receiving end B. In the configuration of FIG. 7(a), voltage V3 is applied from the cathode to the anode of diode D1 and simultaneously from the base to the emitter of transistor Q1. When the amplitude of the signal voltage is large, i.e., when voltage V3 is large, it is necessary to select an element with a high withstand voltage between the terminals of transistor Q1.

In the configuration of FIG. 7(b), voltage V3 is generated only from the cathode to the anode of diode D1, so there is an advantage in that an element with a low breakdown voltage between the terminals of transistor Q1 can be selected. The operation of suppressing reflected waves has the same effect as in FIG. 7(a).

[Second embodiment]
8 shows a circuit diagram of a second embodiment of the communication terminal 30. In this embodiment, a voltage clamp circuit 320 is connected in parallel to the receiving end B, and a bypass circuit and a trigger circuit are not provided.

The voltage clamp circuit 320 is composed of a series circuit of a diode D1 and a capacitor C1, and a resistor R1 in parallel with the capacitor C1. The capacitor C1 is a capacitor for holding a reference voltage, and the resistor R1 is a discharge resistor for the capacitor C1. The diode D1 turns on and charges the capacitor C1 when the receiving end voltage Vo_ exceeds the holding voltage V1 of the capacitor C1. The capacitance of the capacitor C1 is set appropriately, and the voltage hardly changes due to this charging current. Therefore, the receiving end voltage Vo_ is clamped to the holding voltage V1 of the capacitor C1.

The second embodiment does not include a bypass circuit. If there is only a discharge resistor R1 in parallel with the capacitor C1, the voltage of the capacitor C1 may gradually increase due to the voltage rise of the reflected wave. Specifically, when a signal voltage is repeatedly transmitted from the transmitting terminal 20 and a reflected wave in a positive direction relative to the reference voltage V10 is continuously generated, depending on the resistance value of resistor R1, the capacitor C1 may not be able to discharge sufficiently. If the holding voltage of the capacitor C1 increases, the clamp voltage will increase, and there is a risk that the reflected wave will not be sufficiently suppressed. As a countermeasure to this, the second embodiment provides a discharge circuit for the capacitor C1 using a PNP transistor Q2 and resistors R5 and R6.

When the holding voltage V1 of capacitor C1 is higher than the receiving end voltage Vo_, the emitter potential of transistor Q2 becomes higher than the base potential, so that transistor Q2 turns on and the charge of capacitor C1 can be discharged through resistor R5. Resistor R5 has a smaller resistance value than resistor R1 and is set to rapidly discharge the charge of capacitor C1. The discharge circuit of capacitor C1 is not limited to this configuration. It may be configured to monitor the voltage of capacitor C1 and connect a discharge resistor when the voltage is above a predetermined voltage.

The operation of the voltage clamp circuit 320 is the same as in the above-described embodiment, so the effect of suppressing reflected waves and preventing signal reading errors is the same as in the above-described embodiment.

[Third Example]
9 shows a circuit diagram of the third embodiment of the communication terminal 30. The same circuit symbols are used for elements having the same functions as those in the first embodiment. In the third embodiment, a voltage clamp circuit 320 and a bypass circuit 330 are also connected in parallel to the receiving end B.

In the third embodiment, the voltage clamp circuit 320 is composed of a series circuit of a diode D1, a resistor R8, and a capacitor C1, and a resistor R7 connected to both ends of the series circuit of the resistor R8 and the capacitor C1. The bypass circuit 330 is composed of a series circuit of the collector-emitter of the NPN transistor Q1 and a resistor R2. The trigger circuit 340 is composed of a comparator CP.

As in the first embodiment, the capacitor C1 of the voltage clamp circuit 320 receives the receiving end voltage Vo_ received at the receiving end B and holds the first predetermined voltage V1. The capacitance of the capacitor C1 is set to a sufficiently large capacity so as to hold the voltage almost constant with respect to the frequency of the voltage signal. In the third embodiment, the capacitor C1 is discharged through resistors R8 and R7. The resistor R7 is set to a relatively high resistance. The resistor R8 is set to a smaller resistance than the resistor R7. As in the first embodiment, the diode D1 turns on when the receiving end voltage Vo_ becomes higher than the sum of the holding voltage of the capacitor C1 and the forward voltage of the diode D1, and a current flows through the capacitor C1 through the resistor R8. Since the capacitance of the capacitor C1 is set to a sufficiently large capacity as described above, the voltage hardly changes due to the current through the resistor R8.

The bypass circuit 330 is composed of a series circuit of a transistor Q1 and a resistor R2, similar to the first embodiment. The difference from the first embodiment is that the transistor Q1 has been changed to an NPN transistor. By passing a current through the base of the transistor Q1, the transistor Q1 is turned on and a resistor R2 is connected to the receiving end B. The bypass circuit 330 of this embodiment also connects a resistor R2 to the receiving end B to bypass the current and assist the voltage holding function of the voltage clamp circuit 320.

The trigger circuit 340 of the third embodiment is composed of a comparator CP. The + input terminal of the comparator CP is connected to the connection point between the diode D1 and resistor R8. The - input terminal of the comparator CP is connected to the connection point between the resistor R8 and capacitor C1. The output terminal of the comparator CP is connected to the base of the transistor Q1. The output terminal of the comparator CP is, for example, an open collector configuration, and a pull-up resistor is connected to the control power supply (not shown).

When the receiving end voltage Vo_ rises above the holding voltage V1 of the capacitor C1, the diode D1 turns on, and a current flows through the path of the diode D1, resistor R8, and capacitor C1. At this time, the voltage drop across the resistor R8 causes an upward voltage in FIG. 9 to be generated across the resistor R8. As a result, the voltage at the + input terminal of the comparator CP becomes higher than the - input terminal voltage, and the output terminal of the comparator CP outputs a Hi level. When the output terminal of the comparator CP becomes a Hi level, a current flows through the base of the transistor Q1, and the transistor Q1 turns on. This forms a path that bypasses the receiving end B between the collector and emitter of the transistor Q1 and the resistor R2. The resistor R2 has a low resistance, and even if the transistor Q1 turns on and the voltage of the receiving end voltage Vo_ tries to rise, the current is bypassed to suppress the rise of the receiving end voltage Vo_. The bypass circuit 330 can suppress a sudden rise in the receiving end voltage Vo_.

In the third embodiment, the comparator CP functions as the trigger circuit 340 of the bypass circuit 330. The diode D1 is the same as in the first embodiment in that it functions as the voltage detection unit 322 that turns on when the receiving end voltage Vo_ becomes equal to or higher than the holding voltage V1 of the capacitor C1, and operates the trigger circuit 340.

When the receiving end voltage Vo_ falls below the holding voltage V1 of capacitor C1, diode D1 turns off and the current flowing from diode D1 to resistor R8 stops. Capacitor C1 then gradually discharges through resistors R8 and R7. This discharge current biases resistor R8 in the opposite direction to before, and the voltage at the - input terminal of comparator CP becomes higher than the voltage at the + input terminal, causing the output terminal of comparator CP to go to low level. This stops the base current of transistor Q1, transistor Q1 turns off, and the bypass circuit stops operating.

The above operation prevents the receiving end voltage Vo_ from becoming higher than the voltage V1 held by the capacitor C1, and suppresses the effects of reflected waves. This prevents erroneous signal reading.

[Fourth embodiment]
In the fourth embodiment, the comparator CP of the trigger circuit 340 in the third embodiment is replaced with an operational amplifier OP as shown in Fig. 10. A power supply circuit consisting of a series circuit of a diode D2 and a capacitor C2 is connected to the receiving end B. The voltage of the capacitor C2 is used as the operating power supply for the operational amplifier OP.

The configurations of the voltage clamp circuit 320 and the bypass circuit 330 are the same as those in the third embodiment, and the operation of the trigger circuit 340 is also the same as in the third embodiment, so detailed explanations are omitted.

The fourth embodiment also prevents the receiving end voltage Vo_ from being higher than the voltage V1 held by the capacitor C1, and suppresses the effects of reflected waves. This makes it possible to prevent errors in reading the signal.

[Other Modifications]
The circuit configuration for suppressing the reflected wave of the communication terminal 30 is not limited to the above embodiment. For example, the trigger circuit 340 can be realized by using a microcomputer having an analog input terminal. The voltage clamp circuit 320 has a configuration similar to that of FIG. 8. A series circuit of a transistor and a resistor is connected in parallel to the receiving end B to form a bypass circuit. The receiving end voltage Vo_ is input to the analog input terminal of the microcomputer, the receiving end voltage Vo_ is monitored, and when the voltage of the analog input terminal exceeds a predetermined value (the holding voltage V1 of the capacitor C1), the transistor is turned on to bypass the receiving end B with a resistor. By using a microcomputer with a program that performs the above operation and the above trigger circuit, it is possible to cut off the generation of reflected waves in the positive direction from the reference voltage and prevent erroneous reading of signals due to reflected waves.

The communication system 10 of the present disclosure is not only capable of transmitting a signal from the transmitting terminal 20 and receiving it at the communication terminal 30, but also of transmitting a signal from the communication terminal 30 and receiving it at the transmitting terminal 20. Therefore, it is preferable that the transmitting terminal 20 of the communication system 10 also has a configuration for suppressing the reflected waves described above. Furthermore, it may be configured to communicate between multiple communication terminals 30.

In the above embodiment, it has been explained on the assumption that impedance matching is not achieved at both the transmitting end and the receiving end, but an impedance matching unit for impedance matching may be provided in either the transmitting terminal or the communication terminal. Specifically, the output impedance of the transmitting terminal 20 is made equal to the characteristic impedance of the signal line 60, or the input impedance of the communication terminal 30 is made equal to the characteristic impedance of the signal line 60. In a communication system, if impedance matching is achieved, the influence of reflected waves is basically eliminated, but by providing the configuration of the communication terminal disclosed herein, it is possible to suppress the influence of unexpected reflections and noise.

The present invention is not limited to the above-described embodiment and its variations, and various modifications and improvements are possible within the scope of the claims of this application.

REFERENCE SIGNS LIST 10 Communication system, 20 Transmission terminal, 30 Communication terminal, 31 Switch, 32 Terminal unit, 40 Relay, 50 Load (lighting fixture), 60 Signal line, 310 Signal receiving unit, 320 Voltage clamp circuit, 321 Reference voltage holding unit, 322 Voltage detection unit, 330 Bypass circuit, 340 Trigger circuit

Claims (7)

A communication terminal that receives a voltage signal in which a signal voltage is superimposed on a predetermined reference voltage via a signal line,
a signal receiving unit having a receiving end and receiving the voltage signal;
a voltage clamp circuit that clamps the receiving end when the voltage at the receiving end exceeds a first predetermined voltage that is within a predetermined range from the reference voltage;
The voltage clamp circuit includes:
a reference voltage holding unit that holds the first predetermined voltage;
a voltage detection unit that, when a voltage at the receiving end exceeds the first predetermined voltage, causes the receiving end to be electrically connected to the reference voltage holding unit;
a bypass circuit for bypassing the receiving end;
a trigger circuit that triggers the bypass circuit when the voltage detection unit detects that the voltage at the receiving end exceeds the first predetermined voltage.
Communications terminal. A communication system including a transmitting terminal that transmits the voltage signal and a signal line that transmits the voltage signal,
The signal is used in connection with a communication system in which the sign of the reflection coefficient at the transmitting end of the transmitting terminal is different from the sign of the reflection coefficient at the receiving end of the communication terminal.
The communication terminal according to claim 1 . a reflection coefficient at the transmitting end is negative and a reflection coefficient at the receiving end is positive;
The communication terminal according to claim 2 . When the voltage at the receiving end exceeds the first predetermined voltage and then falls below a second predetermined voltage, the operation of the bypass circuit is stopped.
A communication terminal according to any one of claims 1 to 3 . The second predetermined voltage is equal to or greater than the first predetermined voltage.
The communication terminal according to claim 4 . the reference voltage holding unit includes a series circuit of a diode and a capacitor,
the voltage detection unit detects, based on the on/off of the diode, that the voltage at the receiving end has exceeded the first predetermined voltage;
The bypass circuit includes a series circuit of a switch and a resistor that is triggered by the voltage detection unit.
A communication terminal according to any one of claims 1 to 5 . A communication terminal according to any one of claims 1 to 6 ;
A transmitting terminal for transmitting the voltage signal;
A signal line for transmitting the voltage signal;
A communication system comprising:

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